CN115729274A

CN115729274A - Speed governor and control method of speed governor

Info

Publication number: CN115729274A
Application number: CN202211463523.0A
Authority: CN
Inventors: 吕跃跃; 方郁; 熊国华; 杜洋洋; 郭伟; 王绪霄; 石波; 李硕楠
Original assignee: China General Nuclear Power Corp; China Nuclear Power Technology Research Institute Co Ltd; CGN Power Co Ltd
Current assignee: China General Nuclear Power Corp; China Nuclear Power Technology Research Institute Co Ltd; CGN Power Co Ltd
Priority date: 2022-11-22
Filing date: 2022-11-22
Publication date: 2023-03-03
Also published as: WO2024108891A1

Abstract

The present application relates to a speed governor and a control method of the speed governor. The speed governor includes: the two control circuits comprise two processors, the four processors are connected with each other, and the two processors in the same control circuit are different in type; when a processor in a master control circuit fails, the failure processor in the master control circuit sends synchronization information to a first target processor in a slave control circuit, so that the first target processor and a second target processor are connected to form a target data transmission path to realize data transmission; wherein the first target processor is a processor in the slave control circuit of the same type as the failing processor, and the second target processor is of a different type from the first target processor. By adopting the speed regulator, the condition that single-point faults cause system faults can be avoided.

Description

Speed governor and control method of speed governor

Technical Field

The application relates to the technical field of control of rotating speed equipment of a nuclear power plant, in particular to a speed regulator and a control method of the speed regulator.

Background

In the design of a nuclear power plant process system, a feed water flow control system controls the water demand of a secondary loop of the whole nuclear power plant. The water supply flow control system changes the water supply flow and pressure based on the rotation speed adjustment of the steam-driven main water supply pump, realizes water supply to three steam generators, and simultaneously eliminates the water supply coupling phenomenon among the three steam generators, so as to ensure that the pressure difference between the water supply main pipe and the steam main pipe of the steam generators is equal to a setting value which changes along with the load of a set, therefore, the rotation speed adjustment of the steam-driven main water supply pump plays a crucial role in maintaining the water level stability of the steam generators and ensuring the safety of the set.

The speed regulator of the existing steam turbine is mostly controlled by an electronic speed regulator or a single set of control system, the reliability of the system is low, and the shutdown is often caused by single-point faults.

Disclosure of Invention

In view of the above, it is necessary to provide a governor and a control method of the governor, which have a high degree of redundancy and can avoid a single point failure, in view of the above technical problems.

To achieve the above and other objects, an aspect of the present application provides a governor including: the two control circuits comprise two processors, the four processors are connected with each other, and the two processors in the same control circuit are different in type;

when a processor in a master control circuit fails, the failure processor in the master control circuit sends synchronization information to a first target processor in a slave control circuit, so that the first target processor and a second target processor are connected to form a target data transmission path to realize data transmission;

wherein the first target processor is a processor of the same type as the failure processor in the slave control circuit, the second target processor is of a different type from the first target processor, the master control circuit is one of the two control circuits, and the slave control circuit is the other of the two control circuits.

In one embodiment, when one processor in the main control circuit fails, the second target processor is a normal processor in the main control circuit; when both processors in the master control circuit fail, the second target processor is a processor in the slave control circuit.

In one embodiment, a processor to be diagnosed in the main control circuit sends examination information to three other processors respectively, so that the three other processors generate diagnosis information according to the examination information;

the speed governor further includes:

the arbitration module is respectively connected with the four processors and is used for determining whether the processor to be diagnosed has a fault according to the diagnosis information output by the other three processors and outputting the diagnosis result of the processor to be diagnosed to the other three processors, wherein the processor to be diagnosed is each processor in the main control circuit;

and when the diagnosis result is that the processor to be diagnosed is a fault processor, the fault processor sends the synchronization information to the first target processor.

In one embodiment, the arbitration module includes four arbitration circuits, each of the processors to be diagnosed is configured with one of the arbitration circuits, each of the arbitration circuits is respectively connected with the other three processors, and the other three processors are processors other than the processors to be diagnosed configured with the arbitration circuit; the arbitration circuit includes: three arbitration units, two input ends of each arbitration unit are respectively connected with two processors in the other three processors correspondingly, an output end of each arbitration unit is respectively connected with the other three processors, and one input end of each two arbitration units is connected with the same processor, each arbitration unit respectively comprises: a nand gate and an inverter, wherein,

two input ends of the NAND gate are respectively and correspondingly connected with two processors in the other three processors, and the output end of the NAND gate is connected with the input end of the inverter;

and the output end of the phase inverter is respectively connected with the other three processors.

In one embodiment, the speed regulator further comprises a first isolation circuit, and two processors in the master control circuit are correspondingly connected with two processors in the slave control circuit through the first isolation circuit respectively; the first isolation circuit includes:

the first isolation unit is respectively connected with the first processor of the master control circuit and the first processor of the slave control circuit;

the second isolation unit is respectively connected with the first processor of the master control circuit and the second processor of the slave control circuit;

the third isolation unit is respectively connected with the second processor of the master control circuit and the first processor of the slave control circuit;

the fourth isolation unit is respectively connected with the second processor of the master control circuit and the second processor of the slave control circuit; wherein the first processor of the master control circuit is of the same type as the first processor of the slave control circuit;

and when the diagnosis result indicates that the processor to be diagnosed is a fault processor, the other three processors respectively control an isolation unit connected with the fault processor according to the diagnosis result so as to respectively disconnect a data transmission path connected with the fault processor.

In one embodiment, the speed governor further comprises:

the first input acquisition circuit is respectively connected with the master control circuit and the slave control circuit and is used for acquiring and processing the received analog input signal and transmitting the processed analog input signal to the target control circuit;

the first output processing circuit is respectively connected with the master control circuit and the slave control circuit and is used for receiving and processing the analog output signal from the target control circuit;

the second input acquisition circuit is respectively connected with the master control circuit and the slave control circuit and is used for acquiring and processing the received switching value input signal and transmitting the processed switching value input signal to the target control circuit;

the second output processing circuit is respectively connected with the master control circuit and the slave control circuit and is used for receiving and processing the switching value output signal from the target control circuit; wherein the target control circuit is one of the two control circuits.

In one embodiment, the governor further comprises:

the second isolating circuit is respectively connected with the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit and a second processor of the main control circuit;

the third isolating circuit is respectively connected with the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit and the second processor of the slave control circuit; wherein the second processor of the master control circuit is of the same type as the second processor of the slave control circuit;

when a processor in the main control circuit has no fault, the main control circuit controls the third isolation circuit to be in a locking state;

when the second processor in the main control circuit fails, the main control circuit controls the second isolation circuit to be in a locking state.

In one embodiment, the second input acquisition circuit comprises a first photoelectric isolator for isolating the acquired switching value input signal; the second output processing circuit comprises a second photoelectric isolator and is used for isolating the received switching value output signal; the second isolation circuit includes:

the first magnetic isolator is respectively connected with the first input acquisition circuit and the second processor of the main control circuit;

the second magnetic isolator is respectively connected with the first output processing circuit and a second processor of the main control circuit;

the third magnetic isolator is respectively connected with the first photoelectric isolator, the second photoelectric isolator and the second processor of the main control circuit;

the third isolation circuit includes:

the fourth magnetic isolator is respectively connected with the first input acquisition circuit and the second processor of the slave control circuit;

the fifth magnetic isolator is respectively connected with the first output processing circuit and the second processor of the slave control circuit;

and the sixth magnetic isolator is respectively connected with the first photoelectric isolator, the second photoelectric isolator and the second processor of the slave control circuit.

In one embodiment, the governor further comprises:

the power module is respectively connected with the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit and each control circuit and is used for providing power supply voltage;

wherein the power module includes:

the inverter unit is used for receiving external power supply voltage and performing voltage drop processing on the power supply voltage to obtain voltage drop voltage;

the first system power supply unit is connected with the inverter unit and used for rectifying, regulating and filtering the voltage drop voltage to obtain a first power supply voltage and outputting the first power supply voltage to the main control circuit;

the second system power supply unit is connected with the inversion unit, and is used for rectifying, regulating and filtering the voltage drop to obtain a second power supply voltage and outputting the second power supply voltage to the slave control circuit;

and the interface power supply unit is connected with the inversion unit and used for rectifying, regulating and filtering the voltage drop voltage to obtain a third power supply voltage and outputting the third power supply voltage to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit and the second output processing circuit.

In one embodiment, when one processor in the master control circuit fails, the failing processor in the master control circuit sends synchronization information to a first target processor in the slave control circuit, so that the first target processor is connected with a second target processor in the master control circuit through another processor in the slave control circuit to form a target data transmission path, and data transmission is realized.

In one embodiment, the governor further comprises:

the checking module is respectively connected with the four processors and is used for judging whether the processor to be diagnosed has a fault or not and outputting a diagnosis result of the processor to be diagnosed to other three processors, wherein the processor to be diagnosed is each processor in the main control circuit;

Another aspect of the present application provides a control method of a speed governor, applied to the speed governor according to any one of the above embodiments, the method including:

acquiring a temperature value according to a signal to be started to judge a starting state;

if the hot start state exists, controlling the rotating speed of the steam turbine to increase according to a first preset speed until the real-time rotating speed of the steam turbine is greater than or equal to the first preset rotating speed;

if the cold start state is achieved, controlling the rotating speed of the steam turbine to increase according to a second preset speed until the real-time rotating speed of the steam turbine is larger than or equal to the second preset speed, entering a warm state, controlling the rotating speed of the steam turbine to continue to increase according to the second preset speed after preset time, and controlling the rotating speed of the steam turbine to increase according to a first preset speed until the real-time rotating speed of the steam turbine is larger than or equal to a third preset speed until the real-time rotating speed of the steam turbine is larger than or equal to the first preset speed;

and regulating the rotating speed of the steam turbine according to the starting completion signal and the set rotating speed.

According to the speed regulator and the speed regulator control method, two processors of different types in the main control circuit realize data transmission, through the arrangement of the slave control circuit, when the processor in the main control circuit fails, the processor of the slave control circuit with the same type as the failed processor is adopted for substitution, the data to be processed by the failed processor is continuously processed, the data transmission is realized through the processor without failure in the main control circuit, and if the processors in the main control circuit fail, the data processing and transmission are carried out through the two processors in the slave control circuit. The situation that a single point of failure causes system failure is avoided through the design of the dual control circuit.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a block diagram of a governor provided in a first embodiment of the present application;

fig. 2 is a block diagram of a governor provided in a second embodiment of the present application;

fig. 3 is a schematic structural diagram of a first arbitration circuit according to an embodiment of the present application;

fig. 4 is a block diagram of a speed governor provided in a third embodiment of the present application;

fig. 5 is a block diagram showing a structure of a speed governor provided in a fourth embodiment of the present application;

FIG. 6 is a schematic diagram of a first input acquisition circuit provided in an embodiment of the present application;

FIG. 7 is a schematic diagram of a first output processing circuit provided in an embodiment of the present application;

FIG. 8 is a schematic diagram of a second input acquisition circuit provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of a second output processing circuit provided in an embodiment of the present application;

fig. 10 is a block diagram showing a structure of a speed governor provided in a fifth embodiment of the present application;

fig. 11 is a block diagram of a power module provided in an embodiment of the present application;

FIG. 12 is a block diagram showing a governor according to a sixth embodiment of the present application

Fig. 13 is a schematic flow chart of a control method of a speed governor provided in an embodiment of the present application.

Description of reference numerals:

10. a speed governor; 11. a main control circuit; 111. a first processor; 112. a second processor; 12. a slave control circuit; 121. a third processor; 122. a fourth processor; 13. an arbitration module; 131. an arbitration circuit; 1311. a first arbitration unit; 1312. a second arbitration unit; 1313. a third arbitration unit; 132. a NAND gate; 133. an inverter; 14. a first isolation circuit; 141. a first isolation unit; 142. a second isolation unit; 143. a third isolation unit; 144. a fourth isolation unit; 15. a first input acquisition circuit; 151. an analog-to-digital converter; 152. a first field effect transistor; 153. a voltage dividing circuit; 154. a first operational amplifier; 155. a voltage follower; 16. a first output processing circuit; 161. a digital-to-analog converter; 162. a second operational amplifier; 163. a third operational amplifier; 164. a fourth operational amplifier; 165. a fifth operational amplifier; 166. a second field effect transistor; 167. a third field effect transistor; 17. a second input acquisition circuit; 171. a first opto-isolator; 18. a second output processing circuit; 181. a second opto-isolator; 19. a second isolation circuit; 191. a first magnetic isolator; 192. a second magnetic isolator; 193. a third magnetic isolator; 20. a third isolation circuit; 201. a fourth magnetic isolator; 202. a fifth magnetic isolator; 203. a sixth magnetic isolator; 21. a power supply module; 211. an inversion unit; 212. a first system power supply unit; 213. a second system power supply unit; 214. and an interface power supply unit.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments is understood to mean "electrical connection", "communication connection", or the like, if there is a transfer of electrical signals or data between the connected objects.

Referring to fig. 1, in one embodiment, a governor 10 is provided, the governor 10 including two control circuits, each of the control circuits including two processors, four of the processors being connected to each other, the two processors in the same control circuit being of different types.

The two processors in the master control circuit 11 are of different types, the two processors in the slave control circuit 12 are of different types, and the two processors in the slave control circuit 12 are respectively of the same type as the two processors in the master control circuit 11. For example, a first processor in the master control circuit 11 is of the same type as a first processor in the slave control circuit 12, and a second processor in the master control circuit 11 is of the same type as a second processor in the slave control circuit 12. The processor at least comprises a Central Processing Unit (CPU) and a Field Programmable Gate Array (FPGA).

For example, two processors in the master control circuit 11 may be used as the first processor 111 and the second processor 112 of the speed governor 10, and two processors in the slave control circuit 12 may be used as the third processor 121 and the fourth processor 122 of the speed governor 10. The first processor 111 may be a first CPU, and the second processor 112 may be a first FPGA; the third processor 121 may be a second CPU and the fourth processor 122 may be a second FPGA. The first CPU is respectively connected with the first FPGA, the second CPU and the second FPGA; the first FPGA is respectively connected with the second CPU and the second FPGA; and the second CPU is connected with the second FPGA.

When the system starts to operate, the main control circuit 11 includes a target data transmission path, that is, the first CPU is connected with the first FPGA to form the target data transmission path, so as to implement data transmission. The control circuit 12 may also include a target data transmission path, that is, the second CPU and the second FPGA are connected to form the target data transmission path, so as to implement data transmission.

Optionally, when one processor in the master control circuit 11 fails, the failing processor in the master control circuit 11 sends synchronization information to a first target processor in the slave control circuit 12, so that the first target processor is connected to a second target processor in the master control circuit 11 via another processor in the slave control circuit 12 to form a target data transmission path, thereby implementing data transmission.

Taking the master control circuit 11 as an example of a target data transmission path, when a processor in the master control circuit 11 fails, the failing processor in the master control circuit 11 sends synchronization information to a first target processor in the slave control circuit 12, so that the first target processor and a second target processor are connected to form the target data transmission path, thereby realizing data transmission.

Wherein the first target processor is a processor in the slave control circuit 12 of the same type as the failing processor, and the second target processor is of a different type from the first target processor. The synchronization information is information that can characterize the fault pre-processing or transmission data of the fault processor. In the four processors, because only synchronous information needs to be transmitted between two processors in the same type, the two processors adopt a serial communication mode for communication; because the two processors of different types need to realize data transmission and the transmitted data volume is large, in order to ensure the data transmission efficiency, a parallel communication mode is adopted for communication.

Optionally, when one processor in the main control circuit 11 fails, the second target processor is a normal processor in the main control circuit 11. For example, when the first CPU fails, the first target processor is the second CPU, the second target processor is the first FPGA, and the first CPU sends synchronization information to the second CPU in the slave control circuit 12, so that the second CPU and the first FPGA are connected to form a target data transmission path to implement data transmission; when the first FPGA fails, the first target processor is a second FPGA, the second target processor is a first CPU, and the first FPGA sends synchronization information to the second FPGA in the slave control circuit 12, so that the first CPU and the second FPGA are connected to form a target data transmission path to implement data transmission.

Alternatively, when both processors in the master control circuit 11 fail, the second target processor is the processor in the slave control circuit 12. For example, when both the first CPU and the first FPGA fail, the first CPU sends synchronization information to the second CPU, and the first FPGA sends synchronization information to the second FPGA, so that the second CPU and the second FPGA are connected to form a target data transmission path, thereby implementing data transmission.

In the speed governor 10, two processors of different types in the master control circuit 11 perform data transmission through parallel port communication, and through the configuration of the slave control circuit 12, when a processor in the master control circuit 11 fails, the failed processor transmits synchronization information to a processor of the same type as the failed processor in the slave control circuit 12 through serial communication, and replaces the processor of the same type as the failed processor in the slave control circuit 12, continues to process data to be processed by the failed processor, performs data transmission with a processor having no failure in the master control circuit 11, and performs data processing and transmission through the two processors of the slave control circuit 12 if both processors in the master control circuit 11 fail. The condition that a single-point fault causes system failure is avoided through the design of the double-control circuit.

In one embodiment, as shown in fig. 2, the governor 10 further includes an arbitration module 13, which is connected to each of the four processors. The blanking module comprises four arbitration circuits, each processor to be diagnosed is provided with one arbitration circuit, each arbitration circuit is respectively connected with the other three processors, and the other three processors are processors except the processors to be diagnosed, which are configured by the arbitration circuits. The arbitration circuit comprises three arbitration units, two input ends of each arbitration unit are respectively and correspondingly connected with two processors in the other three processors, the output end of each arbitration unit is respectively connected with the other three processors, one input end of each two arbitration units is connected with the same processor, and each arbitration unit respectively comprises a NAND gate 132 and an inverter 133.

To explain with the first processor 111 as the processor to be diagnosed, the first processor 111 in the main control circuit 11 sends the check information to the second processor 112, the third processor 121, and the fourth processor 122, respectively, and the second processor 112, the third processor 121, and the fourth processor 122 generate the diagnosis information according to the check information. As shown in fig. 3, the arbitration circuit 131 of the first processor 111 outputs a high level if the diagnosis result of the first processor 111 by the other three processors is a failure, the nand gate 132 of the first arbitration unit 1311 is connected to the second processor 112 and the fourth processor 122, the nand gate 132 of the second arbitration unit 1312 is connected to the second processor 112 and the third processor 121, the nand gate 132 of the third arbitration unit 1313 is connected to the third processor 121 and the fourth processor 122, and the three arbitration circuits 131 determine whether the first processor 111 fails by using two-out-of-three method. For example, if the second processor 112, the third processor 121, and the fourth processor 122 all determine to be normal and output low level, the nand gate 132 outputs high level, the inverter 133 outputs low level, and finally the first arbiter 131 outputs low level, the first processor 111 has no fault in the first arbiter 131, the second arbiter 131, and the third arbiter 131; if the second processor 112 and the third processor 121 determine normal and output low level, and the fourth processor 122 determines failure and output high level, the nand gate 132 outputs high level, the inverter 133 outputs low level, and finally the first arbiter 131 outputs low level, and the first processor 111 has no failure in the first arbiter 131, the second arbiter 131, and the third arbiter 131; if the second processor 112 and the third processor 121 determine that the fault occurs and output a high level, and the fourth processor 122 determines that the fault occurs and outputs a low level, the nand gate 132 of the first arbitration circuit 131 and the third arbitration circuit 131 outputs a high level, the inverter 133 outputs a low level, but the nand gate 132 of the second arbitration circuit 131 outputs a low level and the inverter 133 outputs a high level, and finally the first arbitration circuit 131 outputs a high level, and the first processor 111 fails. That is, if two of the three processors except the processor to be diagnosed determine that the processor to be diagnosed has a fault, the processor to be diagnosed has a fault.

After the failure detection, the arbitration module 13 outputs the diagnosis result of the first processor 111 to the second processor 112, the third processor 121, and the fourth processor 122. If the diagnosis result is that the first processor 111 is faulty, the third processor 121 is a first target processor, the second processor 112 is a second target processor, the first processor 111 sends synchronization information to the third processor 121, and the third processor 121 is connected with the second processor 112 according to the synchronization information to form a target data transmission path, so as to implement data transmission.

When the main control circuit 11 includes the target data transmission path, both the first processor 111 and the second processor 112 may be processors to be diagnosed; when the slave control circuit 12 includes the target data transmission path, both the third processor 121 and the fourth processor 122 can be processors to be diagnosed.

Optionally, the speed regulator 10 further includes a check module, configured to determine whether the processor to be diagnosed is faulty, and output a diagnosis result of the processor to be diagnosed to the other three processors, where the processor to be diagnosed is each processor in the main control circuit 11; and when the diagnosis result is that the processor to be diagnosed is a fault processor, the fault processor sends the synchronization information to the first target processor.

In the speed regulator 10, the processor to be diagnosed sends the verification information to the other three processors, and the other three processors judge whether the processor to be diagnosed is faulty according to the verification information, and transmit the diagnosis information to the arbitration module 13 to generate the diagnosis result according to the method of taking two out of three, so that the processor originally having the fault in the other three processors can be prevented from confusing the diagnosis result of the processor to be diagnosed. If the processor to be diagnosed fails, the synchronization information is sent to the processors of the same type in the slave control circuit 12, so that the first target processor and the second target processor form a new target data transmission path, thereby avoiding the occurrence of the situation that the system cannot operate due to the single point failure of the processor to be diagnosed.

Referring to fig. 4, in an embodiment, the speed regulator 10 further includes a first isolation circuit 14, and two processors in the master control circuit 11 are respectively connected to two processors in the slave control circuit 12 through the first isolation circuit 14. The first isolation circuit 14 includes a first isolation unit 141, a second isolation unit 142, a third isolation unit 143, and a fourth isolation unit 144. A first isolation unit 141 connected to the first processor of the master control circuit 11 and the first processor of the slave control circuit 12, respectively; a second isolation unit 142 connected to the first processor of the master control circuit 11 and the second processor of the slave control circuit 12, respectively; a third isolation unit 143 connected to the second processor of the master control circuit 11 and the first processor of the slave control circuit 12, respectively; a fourth isolation unit 144 connected to the second processor of the master control circuit 11 and the second processor of the slave control circuit 12, respectively; wherein the first processor of the master control circuit 11 is of the same type as the first processor of the slave control circuit 12. The first isolation unit 141, the second isolation unit 142, the third isolation unit 143, and the fourth isolation unit 144 respectively include at least one magnetic isolator.

Illustratively, the first processor 111 is connected to the third processor 121 via a first isolation unit 141, the first processor 111 is connected to the fourth processor 122 via a second isolation unit 142, the second processor 112 is connected to the third processor 121 via a third isolation unit 143, and the second processor 112 is connected to the fourth processor 122 via a fourth isolation unit 144. For example, when the first processor 111 is a processor to be diagnosed, if the diagnosis result indicates that the first processor 111 fails, the third processor 121 receives the synchronization information and then controls the first isolation unit 141 to be disconnected according to the diagnosis result, and the fourth processor 122 controls the second isolation unit 142 to be disconnected according to the diagnosis result; when the second processor 112 is a processor to be diagnosed, if the diagnosis result is that the second processor 112 is faulty, the fourth processor 122 controls the fourth isolating unit 144 to be disconnected according to the diagnosis result after receiving the synchronization information, and the third processor 121 controls the third isolating unit 143 to be disconnected according to the diagnosis result.

Optionally, the connection path between the first processor 111 and the fourth processor 122, and the connection path between the second processor 112 and the third processor 121 may include the same magnetic isolator; the magnetic isolators in the connection path between the first processor 111 and the fourth processor 122, and the magnetic isolators in the connection path between the second processor 112 and the third processor 121 may be different, and are not limited herein.

The speed governor 10 prevents the system from being confused by erroneous information output from a faulty processor by cutting off the outputs of the isolation units connected between the other three processors and the faulty processor to be diagnosed.

As shown in fig. 5, in one embodiment, the speed governor 10 further includes a first input acquisition circuit 15, a first output processing circuit 16, a second input acquisition circuit 17, a second output processing circuit 18, a second isolation circuit 19, and a third isolation circuit 20.

The first input acquisition circuit 15 is connected with the master control unit through a first magnetic isolator 191 in the second isolation circuit 19, and is connected with the slave control unit through a fourth magnetic isolator 201 in the third isolation circuit 20, and is configured to acquire and process the received analog input signal, and transmit the processed analog input signal to the target control circuit. The circuit schematic of the first input acquisition circuit 15 is shown in fig. 6. The first input acquisition circuit 15 includes an analog-to-digital converter 151, and the analog input signal includes a current signal. After passing through the first field effect transistor 152, a current signal input from the printed circuit board forms a voltage signal through the voltage dividing circuit 153, the voltage signal is conditioned by the first operational amplifier 154, the robustness and the load capacity of the voltage signal are improved through the voltage follower 155, subsequent sampling is facilitated, and finally the voltage signal enters the analog-to-digital converter 151 to be subjected to analog-to-digital conversion to generate a digital signal, and the digital signal is transmitted to the target control circuit through the SPI interface of the analog-to-digital converter 151.

For example, when the main control circuit 11 is a target data transmission path, if the first processor 111 and the second processor 112 are not faulty, the first magnetic isolator 191 is not locked, the fourth magnetic isolator 201 is in a locked state, and the digital signal output by the first input acquisition circuit 15 is transmitted to the second processor 112 through the SPI bus for processing; if only the first processor 111 fails, the third processor 121 serves as a first target processor, and the second processor 112 serves as a second target processor, then the first magnetic isolator 191 is not locked, the fourth magnetic isolator 201 is in a locked state, and the digital signal output by the first input acquisition circuit 15 is transmitted to the second processor 112 through the SPI bus for processing; if only the second processor 112 fails, the fourth processor 122 serves as a first target processor, and the first processor 111 serves as a second target processor, the fourth magnetic isolator 201 is not locked, the first magnetic isolator 191 is locked, and the digital signal output by the first input acquisition circuit 15 is transmitted to the fourth processor 122 through the SPI bus for processing; if both the first processor 111 and the second processor 112 fail, the fourth magnetic isolator 201 is not locked, the first magnetic isolator 191 is locked, and the digital signal output by the first input acquisition circuit 15 is transmitted to the fourth processor 122 through the SPI bus for processing.

The first output processing circuit 16 is connected to the master control unit via the second magnetic isolator 192 in the second isolation circuit 19, and is connected to the slave control unit via the fifth magnetic isolator 202 in the third isolation circuit 20, for receiving and processing the analog output signal from the target control circuit. The circuit schematic of the first output processing circuit 16 is shown in fig. 7, and the first output circuit includes a digital-to-analog converter 161. The digital-to-analog conversion command generated by the second processor 112 of the target control circuit is issued to the digital-to-analog converter 161 via the SPI bus to form an initial signal of digital-to-analog conversion, the initial signal is processed by the second operational amplifier 162 to generate a common voltage for outputting current and voltage, a part of the common voltage is processed by the fourth operational amplifier 164, the fifth operational amplifier 165, the second field-effect transistor 166 and the third field-effect transistor 167 to generate a standard current signal, another part of the common voltage is processed by the third operational amplifier 163 to generate a standard voltage signal, and the standard current signal and the standard voltage signal are output from the connection terminal of the printed circuit board as an analog output signal output by the first output processing circuit 16.

For example, when the main control circuit 11 is the target data transmission path, if the first processor 111 and the second processor 112 are not faulty, the second magnetic isolator 192 is not locked, the fifth magnetic isolator 202 is in a locked state, and the digital-to-analog conversion command output by the second processor 112 is input to the first output processing circuit 16 via the SPI bus; if only the first processor 111 fails, the third processor 121 serves as a first target processor, and the second processor 112 serves as a second target processor, then the second magnetic isolator 192 is not locked, the fifth magnetic isolator 202 is in a locked state, and a digital-to-analog conversion command output by the second processor 112 is input to the first output processing circuit 16 through the SPI bus; if only the second processor 112 fails, the fourth processor 122 serves as a first target processor, and the first processor 111 serves as a second target processor, the fifth magnetic isolator 202 is not locked, the second magnetic isolator 192 is locked, and a digital-to-analog conversion command output by the fourth processor 122 is input to the first output processing circuit 16 through the SPI bus; if both the first processor 111 and the second processor 112 fail, the fifth magnetic isolator 202 is not locked, the second magnetic isolator 192 is locked, and the digital-to-analog conversion command output by the fourth processor 122 is input to the first output processing circuit 16 through the SPI bus.

The second input acquisition circuit 17 is connected to the master control unit via a third magnetic isolator 193 in the second isolation circuit 19, and is connected to the slave control circuit 12 via a sixth magnetic isolator 203 in the third isolation circuit 20, and is configured to acquire and process the received switching value input signal, and transmit the processed switching value input signal to the target control circuit. The schematic circuit diagram of the second input acquisition circuit 17 is shown in fig. 8, and the second input acquisition circuit 17 includes a first opto-isolator 171.

The second output processing circuit 18 is connected with the master control unit through a third magnetic isolator 193 in the second isolation circuit 19 and connected with the slave control circuit 12 through a sixth magnetic isolator 203 in the third isolation circuit 20, and is used for receiving and processing the switching value output signal from the target control circuit; wherein the target control circuit is one of the two control circuits. The circuit schematic of the second output processing circuit 18 is shown in fig. 9, and the second input acquisition circuit 17 includes a second opto-isolator 181.

In the speed regulator 10, when the first processor 111 and the second processor 112 are used as a target data transmission path, the first processor 111 outputs a low level to control the third isolation unit 143 to be locked, so that the magnetic isolator in the third isolation unit 143 cannot output, and the first input acquisition circuit 15, the first output processing circuit 16 and the second processor 112 perform information interaction; when the first processor 111 and the fourth processor 122 are used as a target data transmission path, the first processor 111 outputs a low level to control the latching of the second isolation unit 142, so that the magnetic isolator in the second isolation unit 142 cannot output, and the first input acquisition circuit 15, the first output processing circuit 16 and the fourth processor 122 perform information interaction. The SPI bus authority conflict is avoided by controlling the second isolation unit 142 and the third isolation unit 143.

As shown in fig. 10 and 11, in one embodiment, the speed governor 10 further includes a power module 21, and the power module 21 includes an inverter unit 211, a first system power unit 212, a second system power unit 213, and an interface power unit 214. As shown in fig. 11, the power module 21 is a schematic diagram, and the inverter unit 211 is configured to receive an external power voltage and perform voltage drop processing on the power voltage to obtain a voltage drop voltage; the first system power supply unit 212 is connected to the inverter unit 211, and configured to rectify, regulate, and filter the voltage drop voltage to obtain a first supply voltage, and output the first supply voltage to the main control circuit 11; the second system power supply unit 213 is connected to the inverter unit 211, and configured to perform rectification, voltage regulation, and filtering on the voltage drop voltage to obtain a second supply voltage, and output the second supply voltage to the slave control circuit 12; and the interface power supply unit 214 is connected with the inverter unit 211, and is used for rectifying, regulating and filtering the voltage drop voltage to obtain a third power supply voltage, and outputting the third power supply voltage to the first input acquisition circuit 15, the first output processing circuit 16, the second input acquisition circuit 17 and the second output processing circuit 18.

In the speed regulator 10, the first system power supply is arranged to supply power to the main control circuit 11, the second system power supply is arranged to supply power to the slave control circuit 12, and the interface power supply unit 214 supplies power to the first input acquisition circuit 15, the first output processing circuit 16, the second input acquisition circuit 17 and the second output processing circuit 18, so that redundancy of a system working power supply and an interface power supply is realized.

As shown in fig. 12, in one embodiment, the governor 10 further includes a Human Machine Interface (HMI), the master control circuit 11 includes a first CPU and a first FPGA, and the slave control circuit 12 includes a second CPU and a second FPGA. The first input acquisition circuit 15 includes an analog-to-digital converter (ADC) 151, and the first output processing circuit 16 includes a digital-to-analog converter (DAC) 161. The second input acquisition circuitry 17 comprises a first opto-isolator 171 for primary isolation and the second output processing circuitry 18 comprises a second opto-isolator 181 for primary isolation. The first system power supply unit 212 supplies power to the first CPU and the first FPGA, the second system power supply unit 213 supplies power to the second CPU and the second FPGA, and the interface power supply unit 214 supplies power to the first input acquisition circuit 15, the first output processing circuit 16, the second input acquisition circuit 17, and the second output processing circuit 18. Because different system power supplies are adopted among the first CPU, the second CPU and the second FPGA, the first CPU is connected with the second CPU and the first FPGA through the magnetic isolator; the first FPGA is connected with the second CPU and the second FPGA through the magnetic isolators because the first FPGA and the second CPU and the second FPGA adopt different system power supplies; because the first CPU and the first FPGA as well as the second CPU and the second FPGA adopt the same system power supply, the first CPU is directly connected with the first FPGA, and the second CPU is directly connected with the second FPGA.

The system is powered on, the main control circuit 11 is selected as a target control circuit for explanation, the first CPU sends check information to the second CPU, the first FPGA and the second FPGA, and the arbitration circuit conducts two-out-of-three diagnosis through other three generated diagnosis information to diagnose whether the first CPU is in fault or not; the first FPGA sends check information to the first CPU, the second CPU and the second FPGA, and the arbitration circuit carries out two out on three through the other three generated diagnosis information to diagnose whether the first FPGA has faults or not.

If the first CPU fails, the first CPU sends synchronous information to the second CPU through serial communication so that the second CPU performs target data transmission with the first FPGA through parallel port communication; if the first FPGA fails, the first FPGA sends synchronous information to a second FPGA through serial communication so that the second FPGA can perform target data transmission with a first CPU through parallel port communication; if neither the first CPU nor the first FPGA has a fault, the first CPU outputs a low level to control the third isolation circuit 20 to be locked, so that the conflict of bus operation authority is avoided, and target data is transmitted between the first CPU and the first FPGA; and if the first CPU and the first FPGA both have faults, the first CPU sends the synchronous information to the second CPU through serial communication, and the first FPGA sends the synchronous information to the second FPGA through serial communication, so that the second CPU performs target data transmission with the second FPGA through parallel port communication.

In the speed governor 10, two different types of processors in the master control circuit 11 implement data transmission, and through the setting of the slave control circuit 12, when a processor in the master control circuit 11 fails, a processor in the slave control circuit 12, which is the same type as the failed processor, is used for substitution, data to be processed by the failed processor is continuously processed, data transmission is implemented with a processor in the master control circuit 11, which does not have a failure, and if both processors in the master control circuit 11 fail, data processing and transmission are performed through the two processors in the slave control circuit 12. The situation that a single point of failure causes system failure is avoided through the design of the dual-control circuit.

In one embodiment, as shown in fig. 13, there is provided a control method of a speed regulator, applied to the speed regulator in any of the above embodiments, the method including:

step S100: and acquiring a temperature value according to the signal to be started to judge the starting state.

The starting state comprises a hot starting state and a cold starting state. When the temperature value is greater than or equal to the preset temperature value, the state is a hot start state; and when the temperature value is less than the preset temperature value, the state is a cold start state.

After the speed regulator is electrified, firstly, self-checking is carried out, whether the current state meets the state requirement is judged, and if the current state meets the state requirement, a temperature value is obtained according to a signal to be started so as to judge the starting state of the speed regulator.

Step S210: and if the hot start state exists, controlling the rotating speed of the steam turbine to increase according to a first preset speed until the real-time rotating speed of the steam turbine is greater than or equal to the first preset rotating speed.

Wherein the first preset speed may be 500rpm/min, and the first preset rotation speed may be 4440rpm.

And when the thermal starting state is judged, the speed regulator outputs an opening signal to control the opening of the regulating valve of the steam turbine so as to control the rotating speed of the steam turbine, the rotating speed of the steam turbine is controlled to be increased by 500rpm per minute until the rotating speed of the steam turbine reaches 4440rpm, and the starting is finished.

Step S220: and if the cold start state is achieved, controlling the rotating speed of the steam turbine to increase according to a second preset speed, entering a warm-up state after the real-time rotating speed of the steam turbine is larger than or equal to the second preset speed, controlling the rotating speed of the steam turbine to continue to increase according to a third preset speed after a preset time, and controlling the rotating speed of the steam turbine to increase according to a first preset speed until the real-time rotating speed of the steam turbine is larger than or equal to the third preset speed.

The second preset speed may be 125rpm/min, the second preset rotation speed may be 700rpm, the third preset rotation speed may be 3100rpm, and the preset time may be 10min.

And when the cold start state is judged, the speed regulator outputs an opening signal to control the opening of the regulating valve of the steam turbine so as to control the rotating speed of the steam turbine, the rotating speed of the steam turbine is controlled to be increased at 125rpm per minute, the speed regulator enters a warm-up state after the rotating speed of the steam turbine reaches 700rpm, the speed regulator continues to control the rotating speed of the steam turbine to be increased at 125rpm per minute after 10 minutes, the rotating speed of the steam turbine is controlled to be increased at 500rpm per minute until the rotating speed of the steam turbine reaches 300rpm, and the starting is finished.

Step S300: and regulating the rotating speed of the steam turbine according to the starting completion signal and the set rotating speed.

Wherein, the set rotating speed is an artificially set rotating speed.

According to the control method of the speed regulator, two processors of different types in the master control circuit realize data transmission, through the arrangement of the slave control circuit, when the processors in the master control circuit have faults, the processors in the slave control circuit, which have the same type as the fault processors, are adopted for substitution, the data to be processed by the fault processors are continuously processed, the data transmission is realized through the processors without faults in the master control circuit, and if the processors in the master control circuit have faults, the data processing and transmission are carried out through the two processors in the slave control circuit. The situation that a single point of failure causes system failure is avoided through the design of the dual-control circuit. The speed regulator can normally input and output signals to control the speed regulation of the steam turbine, and the speed regulation method is changed according to the temperature so as to better control the rotation speed regulation of the steam turbine.

It should be understood that, although the steps in the flowchart are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps of the flow chart may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or in alternation with other steps or at least a portion of the steps or stages of other steps.

In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.

Claims

1. A governor, comprising: the two control circuits each comprise two processors, the four processors are connected with each other, and the two processors in the same control circuit are different in type;

2. The governor of claim 1, wherein when one processor in a primary control circuit fails, the second target processor is a normal processor in the primary control circuit; when both processors in the master control circuit fail, the second target processor is a processor in the slave control circuit.

3. The speed regulator according to claim 1, wherein the processor to be diagnosed in the main control circuit sends test information to the other three processors, respectively, so that the other three processors generate diagnosis information according to the test information;

the speed governor further includes:

4. A speed regulator according to claim 3, wherein the arbitration module comprises four arbitration circuits, each of the processors to be diagnosed is configured with one of the arbitration circuits, each of the arbitration circuits is respectively connected with the other three processors, and the other three processors are processors other than the processors to be diagnosed configured with the arbitration circuit; the arbitration circuit includes: three arbitration units, two input ends of each arbitration unit are respectively connected with two processors in the other three processors correspondingly, an output end of each arbitration unit is respectively connected with the other three processors, and one input end of each two arbitration units is connected with the same processor, each arbitration unit respectively comprises: a nand gate and an inverter, wherein,

two input ends of the NAND gate are respectively and correspondingly connected with two processors in the other three processors, and the output end of the NAND gate is connected with the input end of the phase inverter;

5. The speed governor of claim 3, further comprising a first isolation circuit, wherein two processors in the master control circuit are respectively connected with two processors in the slave control circuit through the first isolation circuit; the first isolation circuit includes:

6. A governor according to claim 1, further comprising:

the first output processing circuit is respectively connected with the master control circuit and the slave control circuit and is used for receiving and processing the analog quantity output signal from the target control circuit;

7. The governor of claim 6, further comprising:

the third isolation circuit is respectively connected with the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit and the second processor of the slave control circuit; wherein the second processor of the master control circuit is of the same type as the second processor of the slave control circuit;

8. The speed regulator of claim 7, wherein the second input acquisition circuit comprises a first photoelectric isolator for isolating the acquired switching value input signal; the second output processing circuit comprises a second photoelectric isolator and is used for isolating the received switching value output signal; the second isolation circuit includes:

the third isolation circuit includes:

9. The governor of claim 6, further comprising:

wherein the power module includes:

the second system power supply unit is connected with the inverter unit and used for rectifying, regulating and filtering the voltage drop voltage to obtain a second power supply voltage and outputting the second power supply voltage to the slave control circuit;

and the interface power supply unit is connected with the inversion unit and used for rectifying, regulating and filtering the voltage drop to obtain a third power supply voltage and outputting the third power supply voltage to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit and the second output processing circuit.

10. A speed regulator according to claim 1, wherein when one processor in the master control circuit fails, the failure processor in the master control circuit sends synchronization information to a first target processor in the slave control circuit, so that the first target processor is connected with a second target processor in the master control circuit through another processor in the slave control circuit to form a target data transmission path, and data transmission is realized.

11. The governor of claim 1, further comprising:

the checking module is respectively connected with the four processors and used for judging whether the processor to be diagnosed has a fault or not and outputting the diagnosis result of the processor to be diagnosed to other three processors, wherein the processor to be diagnosed is each processor in the main control circuit;

12. A control method of a governor, applied to a governor according to any one of claims 1 to 11, the method comprising:

if the cold start state is achieved, controlling the rotating speed of the steam turbine to increase according to a second preset speed, entering a warm-up state after the real-time rotating speed of the steam turbine is greater than or equal to the second preset speed, controlling the rotating speed of the steam turbine to continue to increase according to the second preset speed after preset time, and controlling the rotating speed of the steam turbine to increase according to a first preset speed until the real-time rotating speed of the steam turbine is greater than or equal to a third preset speed;