WO2024106980A1 - Circuit intégré de pilote pour affichage - Google Patents

Circuit intégré de pilote pour affichage Download PDF

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Publication number
WO2024106980A1
WO2024106980A1 PCT/KR2023/018474 KR2023018474W WO2024106980A1 WO 2024106980 A1 WO2024106980 A1 WO 2024106980A1 KR 2023018474 W KR2023018474 W KR 2023018474W WO 2024106980 A1 WO2024106980 A1 WO 2024106980A1
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WO
WIPO (PCT)
Prior art keywords
sensing
circuit
channel
sensing channel
display
Prior art date
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PCT/KR2023/018474
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English (en)
Korean (ko)
Inventor
김성근
김원
신영호
허준석
황지현
Original Assignee
주식회사 엘엑스세미콘
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 주식회사 엘엑스세미콘 filed Critical 주식회사 엘엑스세미콘
Priority claimed from KR1020230159201A external-priority patent/KR20240073788A/ko
Publication of WO2024106980A1 publication Critical patent/WO2024106980A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present invention relates to a driving integrated circuit for a display, and more specifically, to an improved arrangement of a sensing channel circuit that receives a sensing signal through a sensing pad and a readout circuit that converts the sensing signal of the sensing channel circuit into sensing data. It relates to a driving integrated circuit for a display.
  • An organic light emitting diode (OLED) panel displays a screen in response to driving signals provided from a driving integrated circuit, and the driving integrated circuit may be configured to provide driving signals corresponding to display data.
  • Pixels of an OLED panel may have characteristic differences.
  • the above-mentioned characteristic deviation can be understood as being caused by factors such as differences in the lifespan of the pixel and the driving ability of the driving transistor, and needs to be compensated for to improve image quality.
  • the driving integrated circuit may be configured to sense the above characteristic deviation and generate sensing data corresponding to the sensing.
  • Sensing data may be transmitted to a timing controller, and the timing controller may compensate display data using the sensing data to compensate for characteristic deviations.
  • the driving integrated circuit may be equipped with a sensing channel circuit and a read-out circuit (ROIC) to sense the above-described characteristic deviation and generate sensing data.
  • ROIC read-out circuit
  • the sensing channel circuit may include a plurality of sensing channels that receive sensing signals for pixels through sensing pads.
  • the readout circuit may be configured to receive analog sensing signals and generate sensing data corresponding to the sensing signals.
  • the driving integrated circuit may include sensing pads for receiving sensing signals and driving pads for providing driving signals to pixels to drive the OLED panel.
  • the sensing pads and driving pads may be arranged on one side of the chip area of the driving integrated circuit facing the OLED panel.
  • the sensing pads may be formed in separate areas on the left and right sides of one side. Sensing signals may have deviations depending on the distance between the sensing pads and the sensing channels.
  • the sensing channel circuit must be arranged to minimize the occurrence of deviation due to internal routing, and the lead-out circuit must be placed close to the sensing channel circuit.
  • the driving integrated circuit needs to improve its internal layout to solve the above problems.
  • the purpose of the present invention is to provide a driving integrated circuit for a display in which a sensing channel circuit including sensing channels can be laid out as one group, and a readout circuit can be arranged adjacent to the sensing channel circuit laid out as a group. do.
  • Another object of the present invention is to provide a driving integrated circuit for a display in which sensing channel circuits are separated and arranged around a readout circuit, and the separated sensing channel circuits can have uniform performance.
  • Another purpose of the present invention is to reduce the area of the chip and resolve performance differences between sensing channels by improving the layout of the readout circuit and the sensing channel circuit.
  • a driving integrated circuit for a display of the present invention includes a first sensing pad and a second sensing pad formed on one side of a chip area and formed at the same distance in opposite directions with respect to the first center of the one side; a sensing channel circuit having a layout area asymmetrical with respect to the first center and including a first sensing channel and a second sensing channel that are symmetrical with respect to a second center of the layout area; a first sensing line connecting the first sensing pad and the first sensing channel; a second sensing line connecting the second sensing pad and the second sensing channel and being longer than the first sensing line; and a channel characteristic adjustment circuit configured in the first sensing line and providing resistance to compensate for the difference in length between the first sensing line and the second sensing line.
  • the driving integrated circuit for a display of the present invention includes a first sensing pad and a second sensing pad formed on one side of the chip area and formed at the same distance in opposite directions with respect to the center of the one side; a readout circuit having a layout area symmetrical with respect to the center of one side; a first sensing channel circuit including a first sensing channel and disposed adjacent to the readout circuit in a first direction where the first sensing pad is located; A second sensing channel circuit comprising a second sensing channel and disposed adjacent to the lead-out circuit in a second direction in which the second sensing pad is located symmetrically with the first sensing channel circuit with respect to the center of the side. ; a first sensing line connecting the first sensing pad and the first sensing channel; and a second sensing line connecting the second sensing pad and the second sensing channel.
  • a driving integrated circuit for a display of the present invention includes a first sensing pad formed on a first side of a chip area; a second sensing pad formed symmetrically with the first pad on a second side of the chip area facing the first side; a readout circuit having a layout area symmetrical about a center between the first side and the second side; a first sensing channel circuit including a first sensing channel and disposed adjacent to the readout circuit in a first direction where the first sensing pad is located; and a second sensing channel circuit, including a second sensing channel circuit, disposed symmetrically to the first sensing channel circuit and adjacent to the readout circuit in a second direction in which the second sensing pad is located. a first sensing line connecting the first sensing pad and the first sensing channel; and a second sensing line connecting the second sensing pad and the second sensing channel.
  • the present invention lays out a sensing channel circuit including sensing channels as one group, arranges a readout circuit adjacent to the sensing channel circuit laid out as a group, and adjusts the deviation according to the positions of the sensing channels of the sensing channel circuit. Adjustment has the effect of ensuring efficient layout of the sensing channel circuit and the readout circuit and uniform characteristics of the sensing channels of the sensing channel circuit.
  • the present invention has the effect of securing uniform performance of the separated sensing channel circuits and improving the digital conversion characteristics of the readout circuit by separately arranging the sensing channel circuits around the readout circuit.
  • the present invention can reduce the length of the sensing line between the sensing pads and the sensing channels by separately arranging the sensing channel circuit around the readout circuit, thereby improving sensing performance and reducing chip area. There is.
  • the present invention can improve the layout of the chip area by arranging the sensing channel circuit adjacent to the readout circuit, which has the effect of reducing the area of the chip and resolving the performance difference between sensing channels.
  • FIG. 1 is a block diagram showing an example of the configuration of a driving integrated circuit for a display of the present invention.
  • FIG. 2 is a layout diagram showing one embodiment of a driving integrated circuit for a display of the present invention.
  • Figure 3 is a diagram illustrating a channel characteristic adjustment circuit.
  • FIG. 4 is a layout diagram showing another embodiment of a driving integrated circuit for a display of the present invention.
  • Figure 5 is a layout diagram showing another embodiment of a driving integrated circuit for a display of the present invention.
  • FIG. 6 is a diagram illustrating an embodiment in which dummy channels are added to both ends of the sensing channel circuit in the embodiment of FIG. 4.
  • FIG. 7 is a diagram illustrating an embodiment in which dummy channels are added to both ends of the sensing channel circuit in the embodiment of FIG. 5.
  • the display may include a display panel (DP) and a driving integrated circuit (SRIC) as shown in FIG. 1 .
  • the display panel DP may be understood as an OLED panel.
  • the driving integrated circuit may receive display data from an external source, such as a timing controller (not shown), and send a driving signal corresponding to the display data to the pixels of the display panel (DP) through the driving lines (DL). It can be configured to provide to.
  • an external source such as a timing controller (not shown)
  • a driving signal corresponding to the display data to the pixels of the display panel (DP) through the driving lines (DL). It can be configured to provide to.
  • the driving integrated circuit may receive sensing signals from pixels of the display panel (DP) through the sensing lines (SL) and may be configured to generate sensing data corresponding to the sensing signals.
  • the driving integrated circuit may include output pads corresponding to channels for driving signals and sensing pads corresponding to channels for sensing signals.
  • the output pads and sensing pads may be separately arranged left and right on one side of the driving integrated circuit (SRIC) facing the display panel (DP).
  • the present invention is implemented as shown in FIG. 2, so that within the driving integrated circuit (SRIC), the sensing channel circuit (SC) is arranged to minimize the occurrence of deviation due to internal routing, and the readout circuit (ROIC) is positioned in the sensing channel circuit. It can be placed close to .
  • SRIC driving integrated circuit
  • ROIC readout circuit
  • the sensing channel circuit (SC) including the sensing channels is laid out as one group, and the readout circuit (ROIC) is placed adjacent to the sensing channel circuit (SC).
  • the driving integrated circuit has a sensing channel circuit (SC), a readout circuit (ROIC), a peripheral circuit (PC), and driving circuits (DIC1 and DIC2) laid out inside.
  • the sensing channel circuit (SC), readout circuit (ROIC), peripheral circuit (PC), and driving circuits (DIC1 and DIC2) shown in FIG. 2 can be understood as representing the layout area within the driving integrated circuit (SRIC). there is.
  • sensing pads are formed on one side of the chip area of the driving integrated circuit (SRIC).
  • the sensing pads (SPL, SPR) may be arranged separately to the left and right on one side of the chip area.
  • the sensing pads (SPL) arranged on the left are called left sensing pads
  • the sensing pads (SPR) arranged on the right are called right sensing pads.
  • illustration of output pads is omitted.
  • the left sensing pads (SPL) and the right sensing pads (SPR) may be formed at the same distance in opposite directions based on the center of one side of the chip area (hereinafter referred to as the first center (CP)).
  • the left sensing pads (SPL) and the right sensing pads (SPR) may have the same number of pads and may be understood as being arranged symmetrically with respect to the first center (CP). As an example, it may be understood that one pad each at the same distance from the first center CP is included in the left sensing pads SPL and one right sensing pad SPR.
  • the sensing channel circuit has sensing channels corresponding to the number of pads of the left sensing pads (SPL) and the right sensing pads (SPR), and is laid out as one group. Layout as one group means that all sensing channels are placed in a single layout area.
  • Sensing channels of the sensing channel circuit (SC) laid out as one group may be expressed as SCa and SCb in FIG. 2.
  • the sensing channel SCa corresponds to the sensing pad of the left sensing pads SPL
  • the sensing channel SCb corresponds to the sensing pad of the right sensing pads SPR.
  • the sensing channel circuit (SC) may be laid out to have an asymmetric layout area with respect to the first center (CP).
  • the sensing channel circuit (SC) has an asymmetrical layout area biased to the right with respect to the first center (CP).
  • the sensing channel circuit may include sensing channels that are symmetrical with respect to the center of its layout area (hereinafter referred to as the second center (LP)).
  • the sensing channels arranged to the left of the second center are called left sensing channels
  • the sensing channels arranged to the right of the second center are called right sensing channels.
  • the sensing channel (SCa) corresponds to the left channel
  • the sensing channel (SCb) corresponds to the right channel.
  • the left sensing channel (SCa) and the right sensing channel (SCb) can be understood as being symmetrically arranged at the same distance from the second center (LP).
  • the left sensing channels are connected through left sensing pads (SPL) and sensing lines (SLL).
  • the sensing line (SLL) can be referred to as the left sensing line.
  • the right sensing channels are connected through right sensing pads (SPR) and sensing lines (SLR).
  • the sensing line (SLR) can be referred to as the right sensing line.
  • the sensing channel circuit (SC) is laid out asymmetrically with respect to the first center (CP), the left sensing line (SLL) is longer than the right sensing line (SLR).
  • the peripheral circuit may be laid out between the sensing channel circuit (SC) and one side where the sensing pads (SPL and SPR) are arranged.
  • the peripheral circuit may include a circuit for transmitting sensing data, a circuit for receiving display data, and a circuit for restoring pixel data and clock from display data transmitted in packets.
  • PC peripheral circuit
  • the readout circuit (ROIC) may be laid out on one side of the sensing channel circuit (SC) described above.
  • the sensing channel circuit (SC) may be laid out on the left side of the first center (CP) where a free space is formed by being biased to the right with respect to the first center (CP). That is, the readout circuit (ROIC) can be understood as being disposed adjacent to the sensing channel circuit (SC) in a direction opposite to the direction in which the sensing channel circuit (SC) is biased with respect to the first center (CP).
  • the read-out circuit may be configured to read out analog sensing signals provided from sensing channels included in the sensing channel circuit (SC) and generate sensing data corresponding to the read-out sensing signals.
  • the readout circuit may include an amplifier for amplifying the sensing signal and an analog-to-digital converter (ADC) for converting the analog sensing signal into digital sensing data.
  • ADC analog-to-digital converter
  • the readout circuit can receive a sensing signal in analog form from a sample and hold circuit.
  • the sample and hold circuit can sample an analog sensing signal and hold it for a certain period of time before providing the analog sensing signal to the ADC. Through this, the sample and hold circuit allows the ADC to stably provide analog sensing signals to the ADC.
  • the amplifier can amplify the analog sensing signal provided by the sample and hold circuit.
  • ADC can convert an amplified analog sensing signal into digital sensing data.
  • Sensing signals may be transmitted through readout lines (RL) configured between the readout circuit (ROIC) and the sensing channel circuit (SC). Since the internal configuration of the read-out circuit (ROIC) can be implemented in various ways, detailed description thereof will be omitted.
  • the driving circuits DIC1 and DIC2 may include channels for outputting driving signals corresponding to display data.
  • the driving circuits DIC1 and DIC2 may be configured to be separated from the sensing channel circuit SC and the readout circuit ROIC. That is, the driving circuit (DIC1) may be laid out in the left area of the first center (CP1) adjacent to the readout circuit (ROIC), and the driving circuit (DIC2) may be laid out in the area to the left of the first center (CP1) adjacent to the sensing channel circuit (SC). It can be laid out in the right area of (CP1).
  • the driving circuits DIC1 and DIC2 may include a latch circuit for latching display data, a digital-to-analog conversion circuit for converting the latched display data into analog, and an output circuit for outputting an analog driving signal. Since the layout of the driving circuits (DIC and DIC2) and the configuration of the internal circuit can be designed in various ways according to the convenience of the manufacturer, detailed description thereof will be omitted.
  • the sensing channel circuit SC is not placed in the center of the chip, resulting in a length discrepancy between the left sensing line (SLL) and the right sensing line (SLR).
  • SLL left sensing line
  • SLR right sensing line
  • the readout circuit (ROIC) is disposed on the left side of the sensing channel circuit (SC)
  • the lengths of the readout lines (RL) connecting the readout circuit (ROIC) and the sensing channels vary.
  • a difference in performance occurs between a sensing channel located close to the read-out circuit (ROIC) and a sensing channel located far from the read-out circuit (ROIC).
  • the thickness of the lead-out line (RL) becomes thicker.
  • the present invention may include a channel characteristic adjustment circuit (AR) as shown in FIG. 3 to resolve the resistance difference between the left sensing line (SLL) and the right sensing line (SLR).
  • AR channel characteristic adjustment circuit
  • the channel characteristic adjustment circuit (AR) may include a resistance component (R) configured in each of the short right sensing lines (SLR).
  • the resistance component (R) described above may be implemented in various ways depending on the manufacturer's intention.
  • an additional resistance component is used for the right sensing line (SLR) to have a resistance value equal to that of the left sensing line (SLL). It can be configured to include (R).
  • the right sensing line (SLR) may be formed to have a curved extension pattern in some sections.
  • the curved extension pattern may act as a resistance component (R).
  • the channel characteristic adjustment circuit (AR) of FIG. 3 can resolve the resistance deviation due to the difference in length between the left sensing line (SLL) and the right sensing line (SLR).
  • the embodiment of the present invention can have the advantage of being able to sense the characteristics of pixels without deviation even though the sensing channel circuit (SC) is asymmetrically laid out with respect to the first center (CP).
  • the present invention can be implemented as shown in FIG. 4 in order to arrange the sensing channel circuit within the driving integrated circuit to minimize the occurrence of deviation due to internal routing and arrange the readout circuit close to the sensing channel circuit.
  • the readout circuit is placed at the center of the chip area, and the sensing channel circuit is arranged separately around the readout circuit (ROIC). That is, for uniform characteristic sensing of pixels, the sensing channel circuit may be understood as including separate sensing channel circuits SC1 and SC2.
  • the sensing channel circuit (SC1) disposed on the left of the first center (CP) is referred to as the left sensing channel circuit
  • the sensing channel circuit (SC2) disposed on the right axis of the first center (CP) is referred to as the right sensing channel circuit. It is called a sensing channel circuit.
  • the driving integrated circuit may include the same left sensing pads (SPL) and right sensing pads (SPR) as in FIG. 2 .
  • the driving integrated circuit described above includes a readout circuit (ROIC), left sensing channel circuit (SC1), right sensing channel circuit (SC2), left sensing line (SLL) and right sensing line (SLR), left peripheral circuit (PC1), It may include a right peripheral circuit (PC2), a left driving circuit (DIC1), and a right driving circuit (DIC2).
  • ROIC readout circuit
  • SC1 left sensing channel circuit
  • SC2 right sensing channel circuit
  • SLL left sensing line
  • SLR right sensing line
  • PC1 left peripheral circuit
  • PC2 right peripheral circuit
  • DI1 left driving circuit
  • DIC2 right driving circuit
  • the readout circuit (ROIC) in FIG. 4 has a layout area that is symmetrical with respect to the center of one side of the chip area.
  • the internal configuration and operation of the read-out circuit (ROIC) can be understood as the same as in FIG. 2, and detailed description thereof will be omitted.
  • the sensing channel circuit is separated into the left and right sides of the readout circuit (ROIC), and the left sensing channel circuit (SC1) and the right sensing channel circuit (SC2) have the same layout area. Includes.
  • the left sensing channel circuit (SC1) includes left sensing channels (SCa1, SCa2) corresponding to the left sensing pads (SPL), and is adjacent to the readout circuit (ROIC) in the direction in which the left sensing pads (SPL) are located. are placed accordingly.
  • the left sensing channel circuit (SC1) can provide a sensing signal to the readout circuit (ROIC) through the readout line (RLL).
  • the right sensing channel circuit (SC1) includes right sensing channels (SCb1, SCb2) corresponding to the right sensing pads (SPR), and is adjacent to the readout circuit (ROIC) in the direction where the right sensing pads (SPR) are located. are placed accordingly.
  • the right sensing channel circuit (SC2) can provide a sensing signal to the readout circuit (ROIC) through the readout line (RLR).
  • the left sensing channel circuit (SC1) and the right sensing channel circuit (SC2) are arranged symmetrically with respect to the first center (CP), and can be understood as having the same number of sensing channels in a symmetrical pattern.
  • the left sensing channel (SCa1) and the right sensing channel (SCb2), which are furthest from the first center (CP) may be understood as being symmetrically disposed at the same distance with respect to the first center (CP)
  • the left sensing channel (SCa2) and the right sensing channel (SCb1) closest to the first center (CP) may be understood as being symmetrically arranged at the same distance from the first center (CP).
  • the left sensing channel circuit (SC1) and the right sensing channel circuit (SC2) are arranged symmetrically with respect to the first center (CP), and may be understood as having an unequal number of sensing channels in a symmetrical pattern. You can.
  • the left sensing channels (SCa1, SCa2) are connected through left sensing pads (SPL) and left sensing lines (SLL).
  • the right sensing channels (SCb1, SCb2) are connected through right sensing pads (SPR) and right sensing lines (SLR).
  • the left sensing lines (SLL) and the right sensing lines (SLR) are preferably formed to have a pattern that is symmetrical with respect to the first center (CP).
  • the left sensing channel circuit (SC1) and the right sensing channel circuit (SC2) are laid out symmetrically with respect to the first center (CP). Therefore, the left and right sensing channels in symmetrical positions with respect to the first center (CP) are connected to the left sensing pad (SPL) and the right sensing pad through the left sensing line (SLL) and right sensing line (SLR) of the same length. Can be connected to pad (SPR). That is, the resistance acting on the left sensing channels (SCa1, SCa2) of the left sensing channel circuit (SC1) and the right sensing channels (SCb1, SCb2) of the right sensing channel circuit (SC2) can be understood to be the same.
  • the embodiment of the present invention can have the advantage that the sensing channel circuit (SC), which is separately arranged into the left sensing channel circuit (SC1) and the right sensing channel circuit (SC2), can sense the characteristics of pixels without deviation. there is.
  • SC sensing channel circuit
  • the peripheral circuits (PC1, PC2) can be arranged separately on the left and right sides, corresponding to the fact that the sensing channel circuit (SC) is arranged separately into the left sensing channel circuit (SC1) and the right sensing channel circuit (SC2). there is. Additionally, the peripheral circuit (PC1) may be laid out between the left sensing channel circuit (SC1) and one side where the sensing pads (SPL) are arranged, and the peripheral circuit (PC2) may be laid out between the right sensing channel circuit (SC2) and the sensing pads. It can be laid out between one side where fields (SPRs) are placed.
  • peripheral circuits PC1 and PC2 Since the internal circuit configuration of the peripheral circuits PC1 and PC2 can be understood with reference to FIG. 2, detailed description thereof will be omitted.
  • the driving circuits DIC1 and DIC2 may include channels for outputting driving signals corresponding to display data.
  • the driving circuits DIC1 and DIC2 may be configured to be separated from the sensing channel circuit SC and the readout circuit ROIC. Since the configuration of the internal circuits of the above-described driving circuits DIC1 and DIC2 can be understood with reference to FIG. 2, detailed description thereof will be omitted.
  • the present invention can be implemented as shown in FIG. 5 to improve the routing path between sensing pads and sensing channel circuits.
  • Figure 5 illustrates a case where sensing pads are formed on both sides of the chip area facing each other.
  • the sensing channel circuit can be placed separately to minimize deviation due to internal routing, and the lead-out circuit can be placed in the center to be close to the sensing channel circuit.
  • FIG. 5 is different from the embodiment of FIG. 4 in the arrangement positions of the left sensing pads (SPL) and right sensing pads (SPR), the configuration of the driving circuits, and the routing of the sensing lines.
  • SPL left sensing pads
  • SPR right sensing pads
  • the left sensing pads (SPL) may be formed on the left side of the chip area, and the right sensing pads (SPR) may be formed on the right side of the chip area facing the left side. You can. That is, the left sensing pads (SPL) and right sensing pads (SPR) may be formed to have a symmetrical pattern with respect to the first center (CP).
  • the readout circuit (ROIC) is formed to have a layout area symmetrical to the center between the left side and the right side. That is, the readout circuit (ROIC) is formed to have a layout area that is symmetrical with respect to the first center (CP).
  • the sensing channel circuit includes a left sensing channel circuit (SC1) and a right sensing channel circuit (SC2) separately arranged on both sides of the readout circuit (ROIC).
  • the left sensing channel circuit (SC1) is placed adjacent to the readout circuit (ROIC) in the direction where the left sensing pad (SPL) is located
  • the right sensing channel circuit (SC2) is placed adjacent to the readout circuit (ROIC) in the direction where the right sensing pad (SPR) is located. It is arranged symmetrically to the channel circuit (SC1) and adjacent to the readout circuit (ROIC).
  • the left sensing channel circuit (SC1) and the right sensing channel circuit (SC2) are arranged symmetrically with respect to the first center (CP), and can be understood as having the same number of sensing channels in a symmetrical pattern.
  • first sensing lines (SLL) are configured to connect the left sensing pads (SPL) and the left sensing channels (SCa1 and SCa2) of the left sensing channel circuit (SC1)
  • second sensing lines (SLR) is configured to connect the right sensing pads (SPR) and the right sensing channels (SCb1, SCb2) of the right sensing channel circuit (SC2).
  • the first sensing lines SLL and the second sensing lines SLR may be formed to have symmetrical patterns.
  • the driving circuit is disposed separately on both sides of the left sensing channel circuit (SC1) and the right sensing channel circuit (SC2).
  • the arrangement of the driving circuit in FIG. 5 is illustrated as an example, and may be implemented in various ways depending on the manufacturer's intention.
  • the present invention can reduce the length of the sensing line between the sensing pads and the sensing channels by separately arranging the sensing channel circuit around the readout circuit (ROIC), thereby improving sensing performance. This has the effect of reducing chip area while improving .
  • ROIC readout circuit
  • the present invention can improve the layout of the chip area by arranging the sensing channel circuit adjacent to the readout circuit as in the embodiments, and as a result, the chip area can be reduced and the performance difference between sensing channels can be resolved. It works.
  • FIG. 6 is a diagram illustrating an embodiment in which dummy channels are added to both ends of the sensing channel circuit in the embodiment of FIG. 4.
  • a first dummy channel (DCa1) may be disposed on the left side of the first left sensing channel (SCa1) disposed at the left end of the left sensing channel circuit (SC1), and the left sensing channel circuit (SC1)
  • a second dummy channel (DCa2) may be disposed on the right side of the second left sensing channel (SCa2) disposed at the right end of .
  • Each of the first dummy channel DCa1 and the second dummy channel DCa2 may have the same configuration as the sensing channel.
  • the first dummy channel DCa1 and the second dummy channel DCa2 may be arranged to ensure operational stability of the first left sensing channel SCa1 and the second left sensing channel SCa2, respectively.
  • a first dummy channel (DCa1) and a second dummy channel (DCa2) that do not actually collect sensing signals may be provided.
  • the first left sensing channel (SCa1) and the second left sensing channel (SCa2) also have the same environment as other sensing channels, so that the operation Stability can be secured.
  • a third dummy channel (DCb1) may be disposed on the left side of the first right sensing channel (SCb1) disposed at the left end of the right sensing channel circuit (SC2), and may be disposed at the right end of the right sensing channel circuit (SC2).
  • a fourth dummy channel (DCb2) may be disposed on the right side of the second right sensing channel (SCb2).
  • the first right sensing channel (SCb1) and the second right sensing channel (SCb2) also have the same environment as other sensing channels, thereby improving operational stability. can be secured.
  • the same voltage as that applied to the sensing channel may be applied to each dummy channel to create the same environment.
  • the applied voltage may be a reference voltage.
  • FIG. 7 is a diagram illustrating an embodiment in which dummy channels are added to both ends of the sensing channel circuit in the embodiment of FIG. 5.
  • a first dummy channel (DCa1) may be disposed on the left side of the first left sensing channel (SCa1) disposed at the left end of the left sensing channel circuit (SC1), and the left sensing channel circuit (SC1)
  • a second dummy channel (DCa2) may be disposed on the right side of the second left sensing channel (SCa2) disposed at the right end of .
  • a third dummy channel (DCb1) may be disposed on the left side of the first right sensing channel (Scb1) disposed at the left end of the right sensing channel circuit (SC2), and may be disposed at the right end of the right sensing channel circuit (SC2).
  • a fourth dummy channel (DCb2) may be disposed on the right side of the second right sensing channel (SCb2).
  • the same voltage as that applied to the sensing channel may be applied to each dummy channel to create the same environment.
  • the applied voltage may be a reference voltage.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un circuit intégré de pilote pour un affichage, le circuit intégré de pilote ayant un agencement amélioré d'un circuit de canal de détection, pour recevoir un signal de détection par l'intermédiaire d'un élément de détection, et un circuit de lecture, pour convertir un signal de détection du circuit de canal de détection en données de détection, ce qui permet de réduire la zone d'une puce et de résoudre une différence de performance entre des canaux de détection.
PCT/KR2023/018474 2022-11-18 2023-11-16 Circuit intégré de pilote pour affichage WO2024106980A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20220155382 2022-11-18
KR10-2022-0155382 2022-11-18
KR10-2023-0159201 2023-11-16
KR1020230159201A KR20240073788A (ko) 2022-11-18 2023-11-16 디스플레이를 위한 구동 집적 회로

Publications (1)

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WO2024106980A1 true WO2024106980A1 (fr) 2024-05-23

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WO (1) WO2024106980A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170124150A (ko) * 2016-04-29 2017-11-10 엘지디스플레이 주식회사 드라이버 집적회로, 컨트롤러 및 표시 장치
KR20180041281A (ko) * 2016-10-13 2018-04-24 삼성디스플레이 주식회사 유기 발광 표시 장치
KR20180128548A (ko) * 2017-05-23 2018-12-04 삼성디스플레이 주식회사 표시 장치 및 그 검사 방법
KR20200129471A (ko) * 2019-05-08 2020-11-18 삼성전자주식회사 데이터 드라이버 및 이를 포함하는 디스플레이 구동 회로
KR20210109738A (ko) * 2020-02-28 2021-09-07 주식회사 실리콘웍스 화소센싱회로 및 패널구동장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170124150A (ko) * 2016-04-29 2017-11-10 엘지디스플레이 주식회사 드라이버 집적회로, 컨트롤러 및 표시 장치
KR20180041281A (ko) * 2016-10-13 2018-04-24 삼성디스플레이 주식회사 유기 발광 표시 장치
KR20180128548A (ko) * 2017-05-23 2018-12-04 삼성디스플레이 주식회사 표시 장치 및 그 검사 방법
KR20200129471A (ko) * 2019-05-08 2020-11-18 삼성전자주식회사 데이터 드라이버 및 이를 포함하는 디스플레이 구동 회로
KR20210109738A (ko) * 2020-02-28 2021-09-07 주식회사 실리콘웍스 화소센싱회로 및 패널구동장치

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