WO2024106011A1 - Semiconductor package, electronic device, and method for controlling semiconductor package - Google Patents

Semiconductor package, electronic device, and method for controlling semiconductor package Download PDF

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Publication number
WO2024106011A1
WO2024106011A1 PCT/JP2023/034401 JP2023034401W WO2024106011A1 WO 2024106011 A1 WO2024106011 A1 WO 2024106011A1 JP 2023034401 W JP2023034401 W JP 2023034401W WO 2024106011 A1 WO2024106011 A1 WO 2024106011A1
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WIPO (PCT)
Prior art keywords
substrate
semiconductor package
peltier module
mounting
peltier
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PCT/JP2023/034401
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French (fr)
Japanese (ja)
Inventor
剛 渡部
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2024106011A1 publication Critical patent/WO2024106011A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/38Cooling arrangements using the Peltier effect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
    • H10N10/13Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the heat-exchanging means at the junction
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
    • H10N10/17Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device

Definitions

  • This technology relates to semiconductor packages. In more detail, it relates to semiconductor packages that use Peltier elements, electronic devices, and methods for controlling semiconductor packages.
  • the Peltier module and heat sink are used to dissipate heat generated by the semiconductor chip.
  • the arrangement of the Peltier module makes it difficult to secure space on the underside of the board to mount components. This requires a larger board area, but this increases the size of the semiconductor package. Reducing the Peltier module and heat sink would allow for a smaller package, but this is not desirable as it would reduce heat dissipation performance.
  • the above-mentioned semiconductor package has the problem that it is difficult to reduce the size.
  • This technology was developed in light of these circumstances, and aims to make it easier to miniaturize semiconductor packages equipped with Peltier modules.
  • This technology has been made to solve the above-mentioned problems, and its first aspect is a semiconductor package including a mounting substrate, a semiconductor chip mounted in an attachment area on the substrate plane of the mounting substrate, and a Peltier module connected to the periphery of the attachment area on the substrate plane, and a control method for the same. This has the effect of facilitating miniaturization.
  • the Peltier module may include a heat dissipation side substrate, a heat absorption side substrate connected to the mounting substrate, and a Peltier element disposed between the heat dissipation side substrate and the heat absorption side substrate. This provides the effect of cooling the semiconductor chip.
  • both the heat dissipation side substrate and the heat absorption side substrate may be flexible substrates having openings. This has the effect of enabling the semiconductor package to be made thinner.
  • the heat absorption side substrate may be a ceramic substrate having an opening. This provides the effect of absorbing heat via the ceramic substrate.
  • the heat dissipation substrate may be a ceramic substrate having an opening. This provides the effect of dissipating heat via the ceramic substrate.
  • the heat dissipation substrate may be a transparent substrate. This eliminates the need for glass.
  • the Peltier module may include a metal plate having an opening, a heat dissipation side substrate connected to the metal plate, a heat absorption side substrate connected to the mounting substrate, and a Peltier element disposed between the heat dissipation side substrate and the heat absorption side substrate. This provides the effect of dissipating heat via the metal plate.
  • the metal plate is fixed to the mounting portion, and the linear expansion coefficient and thermal conductivity of the metal plate may be greater than those of the heat dissipation side substrate and less than those of the mounting portion. This provides the effect of suppressing thermal deformation of the metal plate while ensuring the thermal conductivity of the metal plate.
  • the Peltier module may further include a sealing resin that seals the heat dissipation substrate and each side of the Peltier element. This provides the effect of sealing the space within the semiconductor package.
  • the semiconductor chip may perform photoelectric conversion of incident light to generate image data. This provides the effect of capturing an image of the image data.
  • glass may be further provided to seal the space formed by the Peltier module and the mounting substrate. This provides the effect of sealing the space within the semiconductor package.
  • a first application area along the outer periphery of the mounting board, a mounting land to which the Peltier module is connected, and a second application area between the application area and the mounting land are arranged on the substrate plane, and the mounting land and the first application area may be bonded to the Peltier module by a conductive adhesive, and the second application area may be bonded to the Peltier module by a non-conductive adhesive. This provides the effect of insulating the first application area from the mounting land.
  • the second aspect of the present technology is an electronic device that includes a mounting substrate, a semiconductor chip mounted in an attachment region of a substrate plane of the mounting substrate, a Peltier module connected to the periphery of the attachment region of the substrate plane, and a control unit that supplies current to the Peltier module. This provides the effect of miniaturizing the electronic device.
  • 1 is a block diagram showing an example of a configuration of an imaging device according to a first embodiment of the present technology
  • 1 is a cross-sectional view showing a configuration example of a semiconductor package according to a first embodiment of the present technology
  • 1A and 1B are a top view and a bottom view of a semiconductor package according to a first embodiment of the present technology.
  • 1A to 1C are diagrams for explaining a mounting example of a semiconductor package according to a first embodiment of the present technology
  • 1A to 1C are an example of a top view, a cross-sectional view, and a bottom view of a Peltier module according to a first embodiment of the present technology.
  • 3A to 3C are diagrams for explaining an arrangement of Peltier elements according to the first embodiment of the present technology.
  • 1A and 1B are an example of a top view and a cross-sectional view of an interposer substrate according to a first embodiment of the present technology
  • 5A to 5C are diagrams illustrating a process of forming an electrode on the ceramic substrate on the heat dissipation side in the first embodiment of the present technology.
  • 5A to 5C are diagrams illustrating a process of applying solder to a ceramic substrate on a heat dissipation side in the first embodiment of the present technology.
  • 5A to 5C are diagrams illustrating a process of forming an electrode on the heat absorption side ceramic substrate in the first embodiment of the present technology.
  • 5A to 5C are diagrams illustrating a process of applying solder to a ceramic substrate on a heat absorption side in the first embodiment of the present technology.
  • 1A to 1C are diagrams illustrating a process of arranging a Peltier element according to the first embodiment of the present technology.
  • 3A to 3C are diagrams illustrating a process of soldering the ceramic substrate according to the first embodiment of the present technology.
  • 5A to 5C are diagrams illustrating a process of applying a sealing resin in the first embodiment of the present technology.
  • 4A and 4B are an example of a cross-sectional view and a top view of a Peltier module after application of a sealing resin according to a first embodiment of the present technology
  • 4A to 4C are diagrams showing a process of bonding a metal plate in the first embodiment of the present technology
  • 1A and 1B are an example of a cross-sectional view and a bottom view of an organic substrate according to a first embodiment of the present technology.
  • 1A to 1C are diagrams illustrating a process of mounting components on an organic substrate according to a first embodiment of the present technology.
  • 3A to 3C are diagrams illustrating a process of dividing an organic substrate into individual pieces according to the first embodiment of the present technology.
  • 3A to 3C are diagrams illustrating a die bonding process according to the first embodiment of the present technology.
  • 1A to 1C are diagrams illustrating a wire bonding process according to a first embodiment of the present technology.
  • 5A to 5C are diagrams illustrating a step of applying a non-conductive adhesive in the first embodiment of the present technology.
  • 5A to 5C are diagrams illustrating a process of applying a conductive adhesive in the first embodiment of the present technology.
  • 1A to 1C are diagrams showing a process of adhering a Peltier module according to the first embodiment of the present technology;
  • 1A to 1C are diagrams illustrating a step of applying an adhesive in the first embodiment of the present technology.
  • 4A to 4C are diagrams illustrating a process of mounting glass in the first embodiment of the present technology.
  • 4 is a flowchart showing an example of a control method for a semiconductor package according to the first embodiment of the present technology.
  • 13A to 13C are an example of a top view, a cross-sectional view, and a bottom view of a Peltier module according to a second embodiment of the present technology.
  • 13A to 13C are an example of a top view, a cross-sectional view, and a bottom view of a Peltier module according to a third embodiment of the present technology.
  • 1 is a block diagram showing a schematic configuration example of a vehicle control system;
  • FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit.
  • First embodiment (example in which a Peltier module is connected to the upper surface of an interposer substrate) 2.
  • Second embodiment an example in which a Peltier module including a sapphire substrate is connected to the upper surface of an interposer substrate) 3.
  • Third embodiment an example in which a Peltier module including a flexible substrate is connected to the upper surface of an interposer substrate) 4. Examples of applications to moving objects
  • First embodiment [Configuration example of imaging device] 1 is a block diagram showing a configuration example of an imaging device 100 according to a first embodiment of the present technology.
  • the imaging device 100 is an electronic device that captures image data, and includes a control unit 110, a battery remaining capacity measurement unit 120, a battery 130, a semiconductor package 200, an image processing unit 140, and a storage unit 150.
  • the imaging device 100 a mirrorless camera, a smartphone, a notebook computer having an imaging function, and the like are assumed.
  • the semiconductor package 200 includes a Peltier module 300, a sensor chip 220, and a temperature sensor 411.
  • the imaging device 100 is an example of an electronic device described in the claims.
  • the control unit 110 controls the entire imaging device 100.
  • the control unit 110 acquires the temperature measured by the temperature sensor 411 during imaging, and judges whether the temperature is higher than a predetermined upper limit. If the temperature is higher than the upper limit, the control unit 110 supplies a current to the Peltier module 300 to drive it. Then, while the Peltier module 300 is being driven, the control unit 110 acquires the temperature measured by the temperature sensor 411, and judges again whether the temperature is higher than the upper limit. If the temperature is higher than the upper limit, the control unit 110 acquires the remaining battery capacity measured by the battery remaining capacity measurement unit 120. If the remaining battery capacity is equal to or lower than a predetermined lower limit, the control unit 110 controls the Peltier module 300 and the sensor chip 220 to stop their operation.
  • the battery remaining capacity measuring unit 120 measures the remaining capacity of the battery 130. This battery remaining capacity measuring unit 120 supplies the measured battery remaining capacity to the control unit 110.
  • the battery 130 supplies power to the circuits and elements within the imaging device 100.
  • a secondary battery is used as the battery 130.
  • the Peltier module 300 dissipates heat generated by the sensor chip 220 through the Peltier effect.
  • the sensor chip 220 photoelectrically converts incident light to generate image data.
  • a CIS CMOS Image Sensor
  • This sensor chip 220 generates image data according to the control of the control unit 110, and supplies the data to the image processing unit 140.
  • the temperature sensor 411 measures the temperature of the sensor chip 220. This temperature sensor 411 supplies the measured temperature to the control unit 110.
  • the image processing unit 140 performs various image processing such as demosaic processing on the image data.
  • This image processing unit 140 stores the processed image data in the storage unit 150.
  • the storage unit 150 stores image data.
  • the image processing unit 140 and the memory unit 150 are provided outside the semiconductor package 200, some or all of them can be provided within the sensor chip 220.
  • the sensor chip 220 can have a stacked structure in which multiple chips are stacked, and the image processing unit 140 and the memory unit 150 can be located on one of these chips.
  • the temperature sensor 411 is disposed inside the semiconductor package 200, this sensor can also be disposed outside the semiconductor package 200.
  • control unit 110 is disposed outside the semiconductor package 200, some or all of the functions of this control unit 110 can be realized by circuits within the semiconductor package 200.
  • Example of semiconductor package configuration is a cross-sectional view showing an example of a configuration of a semiconductor package 200 according to the first embodiment of the present technology.
  • the semiconductor package 200 includes a glass 210, a Peltier module 300, a sensor chip 220, and an interposer substrate 400.
  • X-axis a specific axis parallel to the substrate plane of the interposer substrate 400
  • Z-axis an axis perpendicular to the substrate plane
  • Y-axis An axis perpendicular to the X-axis and Z-axis. This figure is a cross-sectional view seen from the Y-axis direction.
  • the direction from the interposer substrate 400 to the sensor chip 220 will be referred to as the "up" direction.
  • the sensor chip 220 is mounted on the attachment area of the upper surface of the interposer substrate 400 and is electrically connected by wire bonding.
  • a predetermined number of peripheral components 412 and a connector 413 are arranged on the lower surface of the interposer substrate 400.
  • a flexible cable 230 is connected to the connector 413.
  • wiring is formed within the interposer substrate 400 to electrically connect the sensor chip 220 and the Peltier module 300 to the connector 413.
  • a circuit outside the semiconductor package 200 such as the control unit 110
  • a temperature sensor 411 (not shown) is disposed, for example, within the interposer substrate 400, and the temperature measured by the temperature sensor 411 is transmitted to the control unit 110, etc., via the connector 413.
  • the sensor chip 220 is an example of a semiconductor chip as described in the claims
  • the interposer substrate 400 is an example of a mounting substrate as described in the claims.
  • the Peltier module 300 is connected to the periphery of the attachment area on the top surface of the interposer substrate 400 where the sensor chip 220 is mounted. This Peltier module 300 surrounds the sides of the sensor chip 220, and a space (in other words, a cavity) is formed by the interposer substrate 400 and the Peltier module 300. The top of the cavity is sealed with glass 210.
  • the sensor chip 220 has many pixels and operates at high speed, power consumption increases, and the heat generated during operation adversely affects imaging characteristics and reliability. For this reason, it is necessary to forcibly dissipate heat from the sensor chip 220, and the volume and weight of the semiconductor package 200 and imaging device 100 tend to increase due to the need for cooling and heat dissipation members for this purpose.
  • a configuration in which the sensor chip 220 and Peltier module 300 are connected to the upper surface of the interposer substrate 400 makes it easier to mount components on the lower surface of the interposer substrate 400.
  • This allows the substrate area to be narrower than in the comparative example, making the semiconductor package 200 more compact.
  • warping of the imaging surface of the sensor chip 220 due to temperature changes when controlling the temperature of the sensor chip 220 is also reduced, preventing degradation of image quality.
  • FIG. 3 is a top view and a bottom view of a semiconductor package 200 according to a first embodiment of the present technology.
  • a is an example of a top view of the semiconductor package 200
  • b is an example of a bottom view of the semiconductor package 200.
  • a screw hole 312 is provided at each of the four corners of the Peltier module 300.
  • various peripheral components 412 can be arranged on the underside of the interposer board 400.
  • FIG. 4 is a diagram for explaining an example of mounting the semiconductor package 200 in the first embodiment of the present technology.
  • An attachment portion 161 and a thermally conductive sheet 162 are provided within the imaging device 100.
  • the semiconductor package 200 is fixed to the mounting portion 161 with screws 163, sandwiching the thermally conductive sheet 162 between them.
  • Example of Peltier module configuration 5A and 5B are an example of a top view, a cross-sectional view, and a bottom view of the Peltier module 300 according to the first embodiment of the present technology.
  • a is an example of a top view of the Peltier module 300
  • b is an example of a cross-sectional view of the Peltier module 300 as viewed from the Y-axis direction.
  • C is an example of a bottom view of the Peltier module 300.
  • the Peltier module 300 includes a metal plate 310, a ceramic substrate 320, a Peltier element 330, and a ceramic substrate 340.
  • the ceramic substrate 340 is a frame-shaped ceramic substrate with an opening, and is disposed on the lower side (in other words, the heat absorption side) of the ceramic substrate 320.
  • the ceramic substrate 320 is a frame-shaped ceramic substrate with an opening, and is disposed on the upper side (in other words, the heat dissipation side) of the ceramic substrate 340.
  • the area of the upper ceramic substrate 320 is made smaller than that of the lower ceramic substrate 340 so that the sealing resin 350 can be applied.
  • the thickness of the lower ceramic substrate 340 is made approximately 30% greater than that of the upper ceramic substrate 320 so that the ceramic substrate 320 does not follow deformation caused by a temperature rise during heat dissipation.
  • the ceramic substrate 320 is an example of a heat dissipation side substrate as described in the claims
  • the ceramic substrate 340 is an example of a heat absorption side substrate as described in the claims.
  • the Peltier element 330 is disposed between the ceramic substrate 320 and the ceramic substrate 340, and its size in the Z-axis direction (i.e., its height) is 1 millimeter (mm) or less.
  • a number of semiconductors (not shown) constituting the Peltier element 330 are arranged along the outer periphery of the opening of the ceramic substrate 320.
  • the respective sides of the ceramic substrate 320 and the Peltier element 330 are sealed with non-conductive sealing resin 350 to prevent foreign matter or moisture from entering the cavity through the gaps between these semiconductors.
  • the sealing resin 350 for example, a silicone-based or epoxy-based thermosetting resin with a viscosity of 30 Pascal seconds (Pa ⁇ s) or more, high thixotropy, and low outgassing is used.
  • the metal plate 310 is a black-plated metal substrate, and is bonded to the top surface of the ceramic substrate 320 by sealing resin 350.
  • the material used for the metal plate 310 has a linear expansion coefficient and thermal conductivity greater than those of the ceramic substrate 320 and smaller than those of the mounting portion 161 illustrated in FIG. 4. This ensures the thermal conductivity of the metal plate 310 while suppressing its thermal deformation.
  • thermal stress occurs due to the difference in thermal expansion coefficient between the glass 210 (not shown) on the top surface of the metal plate 310 and the metal plate 310. For this reason, the glass 210 used is one that can sufficiently relieve this thermal stress (such as heat-resistant glass).
  • the metal plate 310 has an opening 311 in the center when viewed in the Z-axis direction, and screw holes 312 at the four corners.
  • the ceramic substrate 340 has an opening 341 in the center when viewed from the Z-axis direction, and has terminals 342 and 343 on the bottom surface.
  • the thick line in Fig. 3c indicates the outer periphery of the opening 341.
  • FIG. 6 is a diagram for explaining the arrangement of Peltier elements 330 in the first embodiment of the present technology.
  • a is an example of a top view of a ceramic substrate 340 on which Peltier elements 330 are arranged
  • b is an example of a cross-sectional view of the Peltier elements 330 and the ceramic substrate 340 when cut along the dashed line in a of the figure.
  • c is an example of a bottom view of the ceramic substrate 340.
  • d is an example of an enlarged view of the Peltier element 330.
  • e is a cross-sectional view of the unit structure of the Peltier element 330.
  • the unit structure of Peltier element 330 includes gold-plated electrodes 331, 332, and 335, p-type semiconductor 333, and n-type semiconductor 334. This unit structure is called a ⁇ -type thermoelectric conversion element.
  • Electrode 335 is formed on the lower (heat absorption side) ceramic substrate 340. Electrodes 332 and 335 are formed on the upper (heat dissipation side) ceramic substrate 320. P-type semiconductor 333 and n-type semiconductor 334 are connected to electrode 335 with solder. Furthermore, p-type semiconductor 333 and an adjacent n-type semiconductor (not shown) are connected to electrode 331. N-type semiconductor 334 and an adjacent p-type semiconductor (not shown) are connected to electrode 332.
  • a plurality of electrodes 335, a plurality of p-type semiconductors 333, and a plurality of n-type semiconductors 334 are arranged on the ceramic substrate 320 along the outer periphery of the opening 341. These semiconductors and electrodes form a plurality of units of ⁇ -type thermoelectric conversion elements, which are connected in series.
  • the two upper left electrodes 335 are provided with only n-type semiconductors 334, and these electrodes 335 are commonly connected to the terminal 342 in the figure c.
  • the two lower right electrodes 335 are provided with only p-type semiconductors 333, and these electrodes 335 are commonly connected to the terminal 343 in the figure c.
  • [Example of interposer board configuration] 7 is an example of a top view and a cross-sectional view of the interposer substrate 400 according to the first embodiment of the present technology.
  • peripheral components 412 and connectors 413 are omitted.
  • a is an example of a top view of the interposer substrate 400.
  • b is an example of a cross-sectional view taken along line A1-A2 in the figure.
  • c is an example of a cross-sectional view taken along line B1-B2 in the figure.
  • a rectangular attachment area 421 is disposed in the center of the upper surface of the interposer substrate 400.
  • This attachment area 421 is an area for mounting the sensor chip 220, and is gold plated.
  • multiple bumps 422 are arranged along the outer periphery of the attachment region 421. During wire bonding, one end of a wire is connected to the bumps 422.
  • a mounting land 423 is formed at the upper left and a mounting land 424 is formed at the lower right.
  • These mounting lands 423 and 424 are gold plated and are connected to terminals 342 and 343 of the ceramic substrate 340 in FIG. 6.
  • L-shaped application areas 425 and 426 are formed along the outer periphery of the interposer substrate 400. These application areas 425 and 426 are areas for applying a conductive adhesive, and are gold plated. Application area 427 for applying a non-conductive adhesive is provided between mounting lands 423 and 424 and application areas 425 and 426. This application area 427 is not gold plated. Furthermore, adhesive is applied to the area indicated by the dotted line a in the figure.
  • application areas 425 and 426 are an example of a first application area described in the claims, and application area 427 is an example of a second application area described in the claims.
  • the coating areas 425 and 426 and the attachment area 421 are commonly connected by copper foil 431 in the interposer substrate 400. This allows heat generated by the sensor chip 220 mounted in the attachment area 421 to be conducted to the coating areas 425 and 426 and released to the Peltier module 300 (not shown) on the upper surface.
  • the mounting lands 423 and 424 are connected to one end of signal lines 432 and 433, and the other ends of these signal lines are connected to the connector 413 (not shown).
  • a current is supplied from the control unit 110 to the Peltier module 300 via the signal lines 432 and 433.
  • FIG. 8a electrodes such as electrodes 331 and 332 are formed along the outer periphery of opening 321 on the upper surface of ceramic substrate 320 on the upper side (heat dissipation side).
  • FIG. 8b is a cross-sectional view of ceramic substrate 320 taken along the dashed line in FIG. 8a.
  • FIG. 8c is a bottom view of ceramic substrate 320. At this point, the surface facing ceramic substrate 340 is the upper side, and compared to FIG. 5b, the top and bottom are reversed.
  • FIG. 9A solder 336 is applied to each of the electrodes on the upper surface of the ceramic substrate 320.
  • FIG. 9B is a cross-sectional view of the ceramic substrate 320 taken along the dashed line in FIG. 9A.
  • FIG. 9C is a bottom view of the ceramic substrate 320. At this point, the surface facing the ceramic substrate 340 is the upper side, and the top and bottom are reversed compared to FIG. 5B.
  • FIG. 10A a plurality of electrodes 335 are formed along the outer periphery of the opening 341 on the upper surface of the lower (heat absorbing) ceramic substrate 340.
  • FIG. 10B is a cross-sectional view of the ceramic substrate 340 taken along the dashed line in FIG. 10A.
  • FIG. 10C is a bottom view of the ceramic substrate 340.
  • FIG. 11A solder 337 is applied to each of the electrodes on the upper surface of the ceramic substrate 340.
  • FIG. 11B is a cross-sectional view of the ceramic substrate 340 taken along the dashed line in FIG. 11A.
  • FIG. 11C is a bottom view of the ceramic substrate 340.
  • FIG. 12a is a cross-sectional view of ceramic substrate 340 taken along the dashed line in FIG. 12a.
  • FIG. 12c is a bottom view of ceramic substrate 340.
  • steps from FIG. 8 to FIG. 9 and the steps from FIG. 10 to FIG. 12 may be performed in parallel or in sequence.
  • FIG. 13A the ceramic substrate 320 is turned upside down and soldered to the Peltier element 330 on the top surface of the ceramic substrate 340.
  • FIG. 13B shows the state after soldering is completed.
  • sealing resin 350 is applied to the periphery of the ceramic substrate 340.
  • FIG. 15a shows a top view of the state after application of the sealing resin 350 has been completed
  • FIG. 15b shows a cross-sectional view. As shown in FIG. 15b, the sealing resin 350 is applied so that it is higher than the ceramic substrate 320.
  • FIG. 16A the metal plate 310 is attached with good precision and close contact.
  • FIG. 16B shows the state after attachment.
  • the sealing resin 350 is hardened by heating.
  • an organic substrate 500 including multiple interposer substrates is created.
  • a is a cross-sectional view of the organic substrate 500
  • b is a bottom view of the organic substrate 500.
  • peripheral components 412 and connectors 413 are mounted on the bottom surface of the organic substrate 500 by soldering.
  • a is a cross-sectional view of the organic substrate 500
  • b is a bottom view of the organic substrate 500.
  • a plurality of interposer substrates 400 are obtained by dicing.
  • a is a cross-sectional view of the interposer substrate 400
  • b is a bottom view of the interposer substrate 400.
  • FIG. 20A is a bottom view of the interposer substrate 400.
  • FIG. 21A is a bottom view of the sensor chip 220.
  • non-conductive adhesive 441 is applied to application area 427 between mounting lands 423 and 424 and gold-plated application areas 425 and 426.
  • conductive adhesive 442 is applied to each of the mounting lands 423 and 424 and the gold-plated application areas 425 and 426.
  • the volume resistivity of the conductive adhesive 442 is, for example, 8 ⁇ 10 ⁇ 4 ohm-centimeters ( ⁇ cm).
  • the diameter of the coating region 427 is greater than the width and diameter of the mounting lands 423 and 424 and the coating regions 425 and 426. Therefore, the non-conductive adhesive 441 in the coating region 427 insulates the mounting lands 423 and 424 from the coating regions 425 and 426.
  • the non-conductive adhesive 441 and the conductive adhesive 442 are, for example, silicone-based or epoxy-based thermosetting resins that have a viscosity of 30 Pascal seconds (Pa ⁇ s) or more, are highly thixotropic, and have little outgassing.
  • the Peltier module 300 is precisely placed on the interposer substrate 400 and pressurized. Then, as shown in FIG. 24B, the Peltier module 300 and the interposer substrate 400 are heated with no gaps in the adhesive between them, causing the adhesive to harden.
  • adhesive 313 is applied around the opening 311 on the top surface of the Peltier module 300.
  • an ultraviolet curable resin is used as the adhesive 313.
  • B is a cross-sectional view of the semiconductor package 200 before the glass 210 is mounted.
  • thermosetting resin can also be used as adhesive 313 and hardened by heating.
  • Example of semiconductor package control 1 is a flowchart showing an example of a control method for a semiconductor package according to a first embodiment of the present technology. This control is started by a control unit 110 when a predetermined application for capturing image data is executed, for example.
  • the control unit 110 acquires the temperature of the sensor chip 220 at a predetermined timing (e.g., periodically) (step S901) and determines whether the temperature is higher than a predetermined upper limit (step S902). If the temperature is equal to or lower than the upper limit (step S902: No), the control unit 110 repeats step S901.
  • step S902 if the temperature is higher than the upper limit (step S902: Yes), the control unit 110 starts supplying current to the Peltier module 300 (step S903). While the Peltier module 300 is in operation, the control unit 110 acquires the temperature of the sensor chip 220 at a predetermined timing (e.g., periodically) (step S904) and determines whether the temperature is higher than the predetermined upper limit (step S905).
  • a predetermined timing e.g., periodically
  • step S905 if the temperature is higher than the upper limit (step S905: Yes), the control unit 110 acquires the remaining battery charge (step S906) and determines whether the remaining battery charge exceeds a predetermined lower limit (step S907). If the remaining battery charge exceeds the lower limit (step S907: Yes), the control unit 110 repeats steps S904 and onward.
  • step S907 if the remaining battery charge is equal to or lower than the lower limit (step S907: No), the control unit 110 instructs the sensor chip 220 to stop the imaging operation (step S908) and ends the control. Note that in step S908, the control unit 110 can also output a specified alarm regarding a temperature rise to the outside.
  • power can be saved by controlling the Peltier module 300 to perform cooling only when necessary.
  • the Peltier module 300 is connected together with the sensor chip 220 to the upper surface of the interposer substrate 400, making it easier to mount components on the lower surface of the interposer substrate 400. This makes it possible to reduce the substrate area compared to the comparative example, thereby making the semiconductor package 200 smaller.
  • a ceramic substrate is used as the substrate of the Peltier module 300, but a substrate other than a ceramic substrate may also be used.
  • the Peltier module 300 in this second embodiment differs from the first embodiment in that a sapphire substrate is used.
  • FIG. 28 shows an example of a top view, a cross-sectional view, and a bottom view of a Peltier module 300 in the second embodiment of the present technology.
  • a is a top view of the Peltier module 300
  • b is a cross-sectional view of the Peltier module 300
  • c is a bottom view of the Peltier module 300.
  • the Peltier module 300 in the second embodiment differs from the first embodiment in that a transparent sapphire substrate 360 without any openings is placed on the upper side (heat dissipation side) instead of the ceramic substrate 320.
  • the sapphire substrate 360 is an example of a transparent substrate as described in the claims.
  • the glass 210 is no longer necessary, making it possible to reduce the height of the semiconductor package 200.
  • the sapphire substrate 360 is disposed within the Peltier module 300, eliminating the need to provide glass 210.
  • a ceramic substrate is used as the substrate of the Peltier module 300, but a substrate other than a ceramic substrate may also be used.
  • the Peltier module 300 in this third embodiment differs from the first embodiment in that a flexible substrate is used.
  • FIG. 29 shows an example of a top view, a cross-sectional view, and a bottom view of a Peltier module 300 in the third embodiment of the present technology.
  • a is a top view of the Peltier module 300
  • b is a cross-sectional view of the Peltier module 300
  • c is a bottom view of the Peltier module 300.
  • the Peltier module 300 in the third embodiment differs from the first embodiment in that flexible substrates 371 and 372 are arranged instead of the ceramic substrates 320 and 340.
  • the flexible substrates 371 and 372 have openings, just like the ceramic substrates 320 and 340.
  • the substrates can be made thinner than in the first embodiment, making the semiconductor package 200 even lighter.
  • the second embodiment can also be applied to the third embodiment.
  • the upper flexible substrate 371 is replaced with a sapphire substrate 360.
  • the flexible substrates 371 and 372 are disposed inside the Peltier module 300, thereby making it possible to further reduce the weight of the semiconductor package 200.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.
  • FIG. 30 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
  • the body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps.
  • radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020.
  • the body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
  • the outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030.
  • the outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle and receives the captured images.
  • the outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received.
  • the imaging unit 12031 can output the electrical signal as an image, or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects information inside the vehicle.
  • a driver state detection unit 12041 that detects the state of the driver is connected.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
  • the microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output control commands to the drive system control unit 12010.
  • the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 can also control the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby performing cooperative control aimed at automatic driving, which allows the vehicle to travel autonomously without relying on the driver's operation.
  • the microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching high beams to low beams.
  • the audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • FIG. 31 shows an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 12100.
  • the imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100.
  • the imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100.
  • the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
  • FIG. 31 shows an example of the imaging ranges of the imaging units 12101 to 12104.
  • Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door.
  • an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for detecting phase differences.
  • the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles.
  • the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, it can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by forcibly decelerating or steering the vehicle to avoid a collision via the drive system control unit 12010.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian.
  • the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian.
  • the audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology of the present disclosure can be applied to, for example, the imaging unit 12031.
  • the imaging device 100 of FIG. 1 can be applied to the imaging unit 12031.
  • the technology of the present disclosure it is possible to miniaturize the imaging device 100 and provide more space for installation.
  • a mounting board a semiconductor chip mounted in an attachment region of a substrate plane of the mounting substrate; a Peltier module connected to the periphery of the attachment region on the substrate surface.
  • the Peltier module is A heat dissipation substrate; a heat absorption side substrate connected to the mounting substrate;
  • the semiconductor package according to (1) further comprising a Peltier element disposed between the heat radiation side substrate and the heat absorption side substrate.
  • the semiconductor package according to (2), wherein both the heat radiation side substrate and the heat absorption side substrate are flexible substrates having openings.
  • the heat absorption side substrate is a ceramic substrate having an opening.
  • the semiconductor package according to (4), wherein the heat dissipation side substrate is a ceramic substrate having an opening.
  • the Peltier module is A metal plate having an opening; a heat dissipation side substrate connected to the metal plate; a heat absorption side substrate connected to the mounting substrate;
  • the metal plate is fixed to a mounting portion, The semiconductor package according to (7), wherein the linear expansion coefficient and thermal conductivity of the metal plate are greater than those of the heat dissipation side substrate and smaller than those of the mounting portion.
  • the Peltier module further includes a sealing resin that seals each side surface of the heat dissipation substrate and the Peltier element.
  • a first application area along an outer periphery of the mounting board, a mounting land to which the Peltier module is connected, and a second application area between the first application area and the mounting land are arranged on the substrate plane; the mounting land and the first application area are adhered to the Peltier module by a conductive adhesive;
  • control unit acquires the temperature of the semiconductor chip and supplies the current when the temperature is higher than a predetermined upper limit value.
  • Imaging device 110 Control unit 120 Battery remaining capacity measuring unit 130 Battery 140 Image processing unit 150 Memory unit 161 Mounting unit 162 Thermally conductive sheet 163 Screw 200 Semiconductor package 210 Glass 220 Sensor chip 230 Flexible cable 300 Peltier module 310 Metal plate 311, 321, 341 Opening 312 Screw hole 313 Adhesive 320, 340 Ceramic substrate 330 Peltier element 331, 332, 335 Electrode 333 p-type semiconductor 334 n-type semiconductor 336, 337 Solder 342, 343 Terminal 350 Sealing resin 360 Sapphire substrate 371, 372 Flexible substrate 400 Interposer substrate 411 Temperature sensor 412 Peripheral parts 413 Connector 421 Attachment area 422 Bump 423, 424 Mounting land 425, 426, 427 Coating area 431 Copper foil 432, 433 Signal line 441 Non-conductive adhesive 442 Conductive adhesive 500 Organic substrate 12031 Imaging unit

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Abstract

The present invention makes it easy to downsize a semiconductor package provided with a Peltier module. This semiconductor package is equipped with a mounting substrate, a semiconductor chip, and a Peltier module. In the semiconductor package equipped with the mounting substrate, the semiconductor chip, and the Peltier module, the semiconductor chip is loaded in an attachment region in a substrate surface of the mounting substrate. Also, in the semiconductor package equipped with the mounting substrate, the semiconductor chip, and the Peltier module, the Peltier module is connected to the periphery of the attachment region in the substrate surface of the mounting substrate.

Description

半導体パッケージ、電子装置、および、半導体パッケージの制御方法SEMICONDUCTOR PACKAGE, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING SEMICONDUCTOR PACKAGE
 本技術は、半導体パッケージに関する。詳しくは、ペルチェ素子を用いる半導体パッケージ、電子装置、および、半導体パッケージの制御方法に関する。 This technology relates to semiconductor packages. In more detail, it relates to semiconductor packages that use Peltier elements, electronic devices, and methods for controlling semiconductor packages.
 従来より、イメージセンサなどの消費電力の大きな半導体チップでは、動作時の熱が性能に悪影響を及ぼすため、熱管理が必要になる。例えば、上面に半導体チップを搭載した基板の下面に、ペルチェ素子を用いたペルチェモジュールを接続し、その下部にヒートシンクを配置した半導体パッケージが提案されている(例えば、特許文献1参照。)。 Conventionally, semiconductor chips that consume a lot of power, such as image sensors, require thermal management because heat generated during operation adversely affects performance. For example, a semiconductor package has been proposed in which a Peltier module using a Peltier element is connected to the underside of a substrate that has a semiconductor chip mounted on its upper surface, and a heat sink is placed underneath (see, for example, Patent Document 1).
特開2006-222776号公報JP 2006-222776 A
 上述の従来技術では、ペルチェモジュールおよびヒートシンクにより、半導体チップで生じた熱の放熱を図っている。しかしながら、上述の半導体パッケージでは、ペルチェモジュールの配置により、基板の下面において、部品を実装するスペースの確保が困難になる。このため、基板面積を広くする必要があるが、その分、半導体パッケージのサイズが大きくなってしまう。ペルチェモジュールやヒートシンクを削減すれば、小型化することができるが、放熱性能が低下するため、好ましくない。このように、上述の半導体パッケージでは、小型化が困難になるという問題がある。 In the above-mentioned conventional technology, the Peltier module and heat sink are used to dissipate heat generated by the semiconductor chip. However, in the above-mentioned semiconductor package, the arrangement of the Peltier module makes it difficult to secure space on the underside of the board to mount components. This requires a larger board area, but this increases the size of the semiconductor package. Reducing the Peltier module and heat sink would allow for a smaller package, but this is not desirable as it would reduce heat dissipation performance. Thus, the above-mentioned semiconductor package has the problem that it is difficult to reduce the size.
 本技術はこのような状況に鑑みて生み出されたものであり、ペルチェモジュールを設けた半導体パッケージにおいて、小型化を容易にすることを目的とする。 This technology was developed in light of these circumstances, and aims to make it easier to miniaturize semiconductor packages equipped with Peltier modules.
 本技術は、上述の問題点を解消するためになされたものであり、その第1の側面は、実装基板と、上記実装基板の基板平面のうちアタッチ領域に搭載された半導体チップと、上記基板平面のうち上記アタッチ領域の周囲に接続されたペルチェモジュールとを具備する半導体パッケージ、および、その制御方法である。これにより、小型化が容易になるという作用をもたらす。 This technology has been made to solve the above-mentioned problems, and its first aspect is a semiconductor package including a mounting substrate, a semiconductor chip mounted in an attachment area on the substrate plane of the mounting substrate, and a Peltier module connected to the periphery of the attachment area on the substrate plane, and a control method for the same. This has the effect of facilitating miniaturization.
 また、この第1の側面において、上記ペルチェモジュールは、放熱側基板と、上記実装基板に接続された吸熱側基板と、上記放熱側基板および上記吸熱側基板の間に配置されたペルチェ素子とを備えてもよい。これにより、半導体チップが冷却されるという作用をもたらす。 In addition, in this first aspect, the Peltier module may include a heat dissipation side substrate, a heat absorption side substrate connected to the mounting substrate, and a Peltier element disposed between the heat dissipation side substrate and the heat absorption side substrate. This provides the effect of cooling the semiconductor chip.
 また、この第1の側面において、上記放熱側基板および上記吸熱側基板の両方は、開口部を有するフレキシブル基板であってもよい。これにより、半導体パッケージの低背化が可能になるという作用をもたらす。 Furthermore, in this first aspect, both the heat dissipation side substrate and the heat absorption side substrate may be flexible substrates having openings. This has the effect of enabling the semiconductor package to be made thinner.
 また、この第1の側面において、上記吸熱側基板は、開口部を有するセラミック基板であってもよい。これにより、セラミック基板を介して吸熱されるという作用をもたらす。 In addition, in this first aspect, the heat absorption side substrate may be a ceramic substrate having an opening. This provides the effect of absorbing heat via the ceramic substrate.
 また、この第1の側面において、上記放熱側基板は、開口部を有するセラミック基板であってもよい。これにより、セラミック基板を介して放熱されるという作用をもたらす。 In addition, in this first aspect, the heat dissipation substrate may be a ceramic substrate having an opening. This provides the effect of dissipating heat via the ceramic substrate.
 また、この第1の側面において、上記放熱側基板は、透明基板であってもよい。これにより、ガラスが不要になるという作用をもたらす。 In addition, in this first aspect, the heat dissipation substrate may be a transparent substrate. This eliminates the need for glass.
 また、この第1の側面において、上記ペルチェモジュールは、開口部を有する金属板と、上記金属板に接続された放熱側基板と、上記実装基板に接続された吸熱側基板と、上記放熱側基板および上記吸熱側基板の間に配置されたペルチェ素子とを備えてもよい。これにより、金属板を介して放熱されるという作用をもたらす。 In addition, in this first aspect, the Peltier module may include a metal plate having an opening, a heat dissipation side substrate connected to the metal plate, a heat absorption side substrate connected to the mounting substrate, and a Peltier element disposed between the heat dissipation side substrate and the heat absorption side substrate. This provides the effect of dissipating heat via the metal plate.
 また、この第1の側面において、上記金属板は、取り付け部に固定され、上記金属板の線膨張係数および熱伝導率は、上記放熱側基板より大きく、上記取付け部よりも小さくてもよい。これにより、金属板の熱伝導性を確保しつつ、その熱変形が抑制されるという作用をもたらす。 Furthermore, in this first aspect, the metal plate is fixed to the mounting portion, and the linear expansion coefficient and thermal conductivity of the metal plate may be greater than those of the heat dissipation side substrate and less than those of the mounting portion. This provides the effect of suppressing thermal deformation of the metal plate while ensuring the thermal conductivity of the metal plate.
 また、この第1の側面において、上記ペルチェモジュールは、上記放熱側基板および上記ペルチェ素子のそれぞれの側面を封止する封止樹脂をさらに備えてもよい。これにより、半導体パッケージ内の空間が密閉されるという作用をもたらす。 In addition, in this first aspect, the Peltier module may further include a sealing resin that seals the heat dissipation substrate and each side of the Peltier element. This provides the effect of sealing the space within the semiconductor package.
 また、この第1の側面において、上記半導体チップは、入射光を光電変換して画像データを生成してもよい。これにより、画像データが撮像されるという作用をもたらす。 In addition, in this first aspect, the semiconductor chip may perform photoelectric conversion of incident light to generate image data. This provides the effect of capturing an image of the image data.
 また、この第1の側面において、上記ペルチェモジュールおよび上記実装基板により形成された空間を封止するガラスをさらに具備してもよい。これにより、半導体パッケージ内の空間が密閉されるという作用をもたらす。 In addition, in this first aspect, glass may be further provided to seal the space formed by the Peltier module and the mounting substrate. This provides the effect of sealing the space within the semiconductor package.
 また、この第1の側面において、上記基板平面には、上記実装基板の外周に沿った第1塗布領域と上記ペルチェモジュールが接続される実装ランドと上記塗布領域および上記実装ランドの間の第2塗布領域とが配置され、上記実装ランドおよび上記第1塗布領域は、導電性接着剤により上記ペルチェモジュールに接着され、上記第2塗布領域は、非導電性接着剤により上記ペルチェモジュールに接着されてもよい。これにより、第1塗布領域と実装ランドとが絶縁されるという作用をもたらす。 Furthermore, in this first aspect, a first application area along the outer periphery of the mounting board, a mounting land to which the Peltier module is connected, and a second application area between the application area and the mounting land are arranged on the substrate plane, and the mounting land and the first application area may be bonded to the Peltier module by a conductive adhesive, and the second application area may be bonded to the Peltier module by a non-conductive adhesive. This provides the effect of insulating the first application area from the mounting land.
 また、本技術の第2の側面は、実装基板と、上記実装基板の基板平面のうちアタッチ領域に搭載された半導体チップと、上記基板平面のうち上記アタッチ領域の周囲に接続されたペルチェモジュールと、上記ペルチェモジュールに電流を供給する制御部とを具備する電子装置である。これにより、電子装置が小型化されるという作用をもたらす。 The second aspect of the present technology is an electronic device that includes a mounting substrate, a semiconductor chip mounted in an attachment region of a substrate plane of the mounting substrate, a Peltier module connected to the periphery of the attachment region of the substrate plane, and a control unit that supplies current to the Peltier module. This provides the effect of miniaturizing the electronic device.
本技術の第1の実施の形態における撮像装置の一構成例を示すブロック図である。1 is a block diagram showing an example of a configuration of an imaging device according to a first embodiment of the present technology; 本技術の第1の実施の形態における半導体パッケージの一構成例を示す断面図である。1 is a cross-sectional view showing a configuration example of a semiconductor package according to a first embodiment of the present technology; 本技術の第1の実施の形態における半導体パッケージの上面図および下面図である。1A and 1B are a top view and a bottom view of a semiconductor package according to a first embodiment of the present technology. 本技術の第1の実施の形態における半導体パッケージの実装例を説明するための図である。1A to 1C are diagrams for explaining a mounting example of a semiconductor package according to a first embodiment of the present technology; 本技術の第1の実施の形態におけるペルチェモジュールの上面図、断面図および下面図の一例である。1A to 1C are an example of a top view, a cross-sectional view, and a bottom view of a Peltier module according to a first embodiment of the present technology. 本技術の第1の実施の形態におけるペルチェ素子の配列を説明するための図である。3A to 3C are diagrams for explaining an arrangement of Peltier elements according to the first embodiment of the present technology. 本技術の第1の実施の形態におけるインタポーザ基板の上面図および断面図の一例である。1A and 1B are an example of a top view and a cross-sectional view of an interposer substrate according to a first embodiment of the present technology; 本技術の第1の実施の形態における放熱側のセラミック基板に電極を形成する工程を示す図である。5A to 5C are diagrams illustrating a process of forming an electrode on the ceramic substrate on the heat dissipation side in the first embodiment of the present technology. 本技術の第1の実施の形態における放熱側のセラミック基板に、はんだを塗布する工程を示す図である。5A to 5C are diagrams illustrating a process of applying solder to a ceramic substrate on a heat dissipation side in the first embodiment of the present technology. 本技術の第1の実施の形態における吸熱側のセラミック基板に電極を形成する工程を示す図である。5A to 5C are diagrams illustrating a process of forming an electrode on the heat absorption side ceramic substrate in the first embodiment of the present technology. 本技術の第1の実施の形態における吸熱側のセラミック基板に、はんだを塗布する工程を示す図である。5A to 5C are diagrams illustrating a process of applying solder to a ceramic substrate on a heat absorption side in the first embodiment of the present technology. 本技術の第1の実施の形態におけるペルチェ素子を配置する工程を示す図である。1A to 1C are diagrams illustrating a process of arranging a Peltier element according to the first embodiment of the present technology. 本技術の第1の実施の形態におけるセラミック基板を、はんだ付けする工程を示す図である。3A to 3C are diagrams illustrating a process of soldering the ceramic substrate according to the first embodiment of the present technology. 本技術の第1の実施の形態における封止樹脂を塗布する工程を示す図である。5A to 5C are diagrams illustrating a process of applying a sealing resin in the first embodiment of the present technology. 本技術の第1の実施の形態における封止樹脂の塗布が完了したペルチェモジュールの断面図および上面図の一例である。4A and 4B are an example of a cross-sectional view and a top view of a Peltier module after application of a sealing resin according to a first embodiment of the present technology; 本技術の第1の実施の形態における金属板を接着する工程を示す図である。4A to 4C are diagrams showing a process of bonding a metal plate in the first embodiment of the present technology; 本技術の第1の実施の形態における有機基板の断面図および下面図の一例である。1A and 1B are an example of a cross-sectional view and a bottom view of an organic substrate according to a first embodiment of the present technology. 本技術の第1の実施の形態における有機基板に部品を実装する工程を示す図である。1A to 1C are diagrams illustrating a process of mounting components on an organic substrate according to a first embodiment of the present technology. 本技術の第1の実施の形態における有機基板を個片化する工程を示す図である。3A to 3C are diagrams illustrating a process of dividing an organic substrate into individual pieces according to the first embodiment of the present technology. 本技術の第1の実施の形態におけるダイボンドの工程を示す図である。3A to 3C are diagrams illustrating a die bonding process according to the first embodiment of the present technology. 本技術の第1の実施の形態におけるワイヤボンディングの工程を示す図である。1A to 1C are diagrams illustrating a wire bonding process according to a first embodiment of the present technology. 本技術の第1の実施の形態における非導電性接着剤を塗布する工程を示す図である。5A to 5C are diagrams illustrating a step of applying a non-conductive adhesive in the first embodiment of the present technology. 本技術の第1の実施の形態における導電性接着剤を塗布する工程を示す図である。5A to 5C are diagrams illustrating a process of applying a conductive adhesive in the first embodiment of the present technology. 本技術の第1の実施の形態におけるペルチェモジュールを接着する工程を示す図である。1A to 1C are diagrams showing a process of adhering a Peltier module according to the first embodiment of the present technology; 本技術の第1の実施の形態における接着剤を塗布する工程を示す図である。1A to 1C are diagrams illustrating a step of applying an adhesive in the first embodiment of the present technology. 本技術の第1の実施の形態におけるガラスを搭載する工程を示す図である。4A to 4C are diagrams illustrating a process of mounting glass in the first embodiment of the present technology. 本技術の第1の実施の形態における半導体パッケージの制御方法の一例を示すフローチャートである。4 is a flowchart showing an example of a control method for a semiconductor package according to the first embodiment of the present technology. 本技術の第2の実施の形態におけるペルチェモジュールの上面図、断面図および下面図の一例である。13A to 13C are an example of a top view, a cross-sectional view, and a bottom view of a Peltier module according to a second embodiment of the present technology. 本技術の第3の実施の形態におけるペルチェモジュールの上面図、断面図および下面図の一例である。13A to 13C are an example of a top view, a cross-sectional view, and a bottom view of a Peltier module according to a third embodiment of the present technology. 車両制御システムの概略的な構成例を示すブロック図である。1 is a block diagram showing a schematic configuration example of a vehicle control system; 撮像部の設置位置の一例を示す説明図である。FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit.
 以下、本技術を実施するための形態(以下、実施の形態と称する)について説明する。説明は以下の順序により行う。
 1.第1の実施の形態(ペルチェモジュールをインタポーザ基板の上面に接続した例)
 2.第2の実施の形態(サファイヤ基板を含むペルチェモジュールをインタポーザ基板の上面に接続した例)
 3.第3の実施の形態(フレキシブル基板を含むペルチェモジュールをインタポーザ基板の上面に接続した例)
 4.移動体への応用例
Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described in the following order.
1. First embodiment (example in which a Peltier module is connected to the upper surface of an interposer substrate)
2. Second embodiment (an example in which a Peltier module including a sapphire substrate is connected to the upper surface of an interposer substrate)
3. Third embodiment (an example in which a Peltier module including a flexible substrate is connected to the upper surface of an interposer substrate)
4. Examples of applications to moving objects
 <1.第1の実施の形態>
 [撮像装置の構成例]
 図1は、本技術の第1の実施の形態における撮像装置100の一構成例を示すブロック図である。この撮像装置100は、画像データを撮像する電子装置であり、制御部110、バッテリ残量測定部120、バッテリ130、半導体パッケージ200、画像処理部140および記憶部150を備える。撮像装置100としては、ミラーレスカメラ、スマートフォンや、撮像機能を有するノートパソコンなどが想定される。また、半導体パッケージ200は、ペルチェモジュール300、センサーチップ220および温度センサー411を備える。なお、撮像装置100は、特許請求の範囲に記載の電子装置の一例である。
1. First embodiment
[Configuration example of imaging device]
1 is a block diagram showing a configuration example of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is an electronic device that captures image data, and includes a control unit 110, a battery remaining capacity measurement unit 120, a battery 130, a semiconductor package 200, an image processing unit 140, and a storage unit 150. As the imaging device 100, a mirrorless camera, a smartphone, a notebook computer having an imaging function, and the like are assumed. In addition, the semiconductor package 200 includes a Peltier module 300, a sensor chip 220, and a temperature sensor 411. The imaging device 100 is an example of an electronic device described in the claims.
 制御部110は、撮像装置100全体を制御するものである。この制御部110は、撮像中に温度センサー411の測定した温度を取得し、その温度が所定の上限値より高いか否かを判断する。温度が上限値より高い場合、制御部110は、ペルチェモジュール300に電流を供給して駆動する。そして、ペルチェモジュール300の駆動中に、制御部110は、温度センサー411の測定した温度を取得し、その温度が上限値より高いか否かを再度判断する。温度が上限値より高い場合、制御部110は、バッテリ残量測定部120の測定したバッテリ残量を取得する。バッテリ残量が所定の下限値以下である場合に制御部110は、ペルチェモジュール300やセンサーチップ220を制御して、その動作を停止させる。 The control unit 110 controls the entire imaging device 100. The control unit 110 acquires the temperature measured by the temperature sensor 411 during imaging, and judges whether the temperature is higher than a predetermined upper limit. If the temperature is higher than the upper limit, the control unit 110 supplies a current to the Peltier module 300 to drive it. Then, while the Peltier module 300 is being driven, the control unit 110 acquires the temperature measured by the temperature sensor 411, and judges again whether the temperature is higher than the upper limit. If the temperature is higher than the upper limit, the control unit 110 acquires the remaining battery capacity measured by the battery remaining capacity measurement unit 120. If the remaining battery capacity is equal to or lower than a predetermined lower limit, the control unit 110 controls the Peltier module 300 and the sensor chip 220 to stop their operation.
 バッテリ残量測定部120は、バッテリ130の残量を測定するものである。このバッテリ残量測定部120は、測定したバッテリ残量を制御部110に供給する。 The battery remaining capacity measuring unit 120 measures the remaining capacity of the battery 130. This battery remaining capacity measuring unit 120 supplies the measured battery remaining capacity to the control unit 110.
 バッテリ130は、撮像装置100内の回路や素子に電力を供給するものである。バッテリ130として、例えば、二次電池が用いられる。 The battery 130 supplies power to the circuits and elements within the imaging device 100. For example, a secondary battery is used as the battery 130.
 ペルチェモジュール300は、ペルチェ効果により、センサーチップ220で生じた熱を放出するものである。 The Peltier module 300 dissipates heat generated by the sensor chip 220 through the Peltier effect.
 センサーチップ220は、入射光を光電変換して画像データを生成するものである。センサーチップ220として、例えば、CIS(CMOS Image Sensor)が用いられる。このセンサーチップ220は、制御部110の制御に従って、画像データを生成し、そのデータを画像処理部140に供給する。 The sensor chip 220 photoelectrically converts incident light to generate image data. For example, a CIS (CMOS Image Sensor) is used as the sensor chip 220. This sensor chip 220 generates image data according to the control of the control unit 110, and supplies the data to the image processing unit 140.
 温度センサー411は、センサーチップ220の温度を測定するものである。この温度センサー411は、測定した温度を制御部110に供給する。 The temperature sensor 411 measures the temperature of the sensor chip 220. This temperature sensor 411 supplies the measured temperature to the control unit 110.
 画像処理部140は、画像データに対して、デモザイク処理などの各種の画像処理を行うものである。この画像処理部140は、処理後の画像データを記憶部150に記憶させる。 The image processing unit 140 performs various image processing such as demosaic processing on the image data. This image processing unit 140 stores the processed image data in the storage unit 150.
 記憶部150は、画像データを記憶するものである。 The storage unit 150 stores image data.
 なお、画像処理部140および記憶部150を半導体パッケージ200の外部に設けているが、これらの一部または全てをセンサーチップ220内に設けることもできる。例えば、センサーチップ220を、複数のチップを積層した積層構造とし、それらのチップのいずれかに画像処理部140や記憶部150を配置することができる。 Note that while the image processing unit 140 and the memory unit 150 are provided outside the semiconductor package 200, some or all of them can be provided within the sensor chip 220. For example, the sensor chip 220 can have a stacked structure in which multiple chips are stacked, and the image processing unit 140 and the memory unit 150 can be located on one of these chips.
 また、温度センサー411を半導体パッケージ200内に配置しているが、このセンサーを半導体パッケージ200の外部に配置することもできる。 In addition, although the temperature sensor 411 is disposed inside the semiconductor package 200, this sensor can also be disposed outside the semiconductor package 200.
 また、制御部110を半導体パッケージ200の外部に配置しているが、この制御部110の機能の一部または全てを半導体パッケージ200内の回路で実現することもできる。 In addition, although the control unit 110 is disposed outside the semiconductor package 200, some or all of the functions of this control unit 110 can be realized by circuits within the semiconductor package 200.
 [半導体パッケージの構成例]
 図2は、本技術の第1の実施の形態における半導体パッケージ200の一構成例を示す断面図である。この半導体パッケージ200は、ガラス210、ペルチェモジュール300、センサーチップ220およびインタポーザ基板400を備える。
[Example of semiconductor package configuration]
2 is a cross-sectional view showing an example of a configuration of a semiconductor package 200 according to the first embodiment of the present technology. The semiconductor package 200 includes a glass 210, a Peltier module 300, a sensor chip 220, and an interposer substrate 400.
 以下、インタポーザ基板400の基板平面に平行な所定の軸を「X軸」とし、その基板平面に垂直な軸を「Z軸」とする。X軸およびZ軸に垂直な軸を「Y軸」とする。同図は、Y軸方向から見た断面図である。 Hereinafter, a specific axis parallel to the substrate plane of the interposer substrate 400 is referred to as the "X-axis", and an axis perpendicular to the substrate plane is referred to as the "Z-axis". An axis perpendicular to the X-axis and Z-axis is referred to as the "Y-axis". This figure is a cross-sectional view seen from the Y-axis direction.
 また、以下、インタポーザ基板400からセンサーチップ220への方向を「上」の方向とする。 Furthermore, below, the direction from the interposer substrate 400 to the sensor chip 220 will be referred to as the "up" direction.
 インタポーザ基板400の上面のうちアタッチ領域にセンサーチップ220が搭載され、ワイヤボンディングにより電気的に接続される。また、インタポーザ基板400の下面には、所定数の周辺部品412と、コネクタ413とが配置される。コネクタ413には、フレキシブルケーブル230が接続される。 The sensor chip 220 is mounted on the attachment area of the upper surface of the interposer substrate 400 and is electrically connected by wire bonding. In addition, a predetermined number of peripheral components 412 and a connector 413 are arranged on the lower surface of the interposer substrate 400. A flexible cable 230 is connected to the connector 413.
 また、インタポーザ基板400内には、センサーチップ220およびペルチェモジュール300のそれぞれと、コネクタ413とを電気的に接続する配線が形成されている。このため、半導体パッケージ200の外部の回路(制御部110など)は、フレキシブルケーブル230を介して、センサーチップ220との間で画像データや制御信号を送受信するとともにペルチェモジュール300に電流を供給することができる。また、温度センサー411(不図示)は、例えば、インタポーザ基板400内に配置され、温度センサー411の測定した温度は、コネクタ413を介して制御部110などに送信される。 In addition, wiring is formed within the interposer substrate 400 to electrically connect the sensor chip 220 and the Peltier module 300 to the connector 413. This allows a circuit outside the semiconductor package 200 (such as the control unit 110) to transmit and receive image data and control signals to and from the sensor chip 220 via the flexible cable 230, and to supply current to the Peltier module 300. In addition, a temperature sensor 411 (not shown) is disposed, for example, within the interposer substrate 400, and the temperature measured by the temperature sensor 411 is transmitted to the control unit 110, etc., via the connector 413.
 なお、センサーチップ220は、特許請求の範囲に記載の半導体チップの一例であり、インタポーザ基板400は、特許請求の範囲に記載の実装基板の一例である。 The sensor chip 220 is an example of a semiconductor chip as described in the claims, and the interposer substrate 400 is an example of a mounting substrate as described in the claims.
 ペルチェモジュール300は、インタポーザ基板400の上面のうち、センサーチップ220を搭載したアタッチ領域の周囲に接続される。このペルチェモジュール300は、センサーチップ220の側面を囲み、インタポーザ基板400とペルチェモジュール300とにより、空間(言い換えれば、キャビティ)が形成される。そのキャビティの上部は、ガラス210により封止される。 The Peltier module 300 is connected to the periphery of the attachment area on the top surface of the interposer substrate 400 where the sensor chip 220 is mounted. This Peltier module 300 surrounds the sides of the sensor chip 220, and a space (in other words, a cavity) is formed by the interposer substrate 400 and the Peltier module 300. The top of the cavity is sealed with glass 210.
 センサーチップ220が、多画素で高速に動作するものである場合、消費電力が大きくなり、動作時の熱が、撮像特性や信頼性に悪影響を及ぼす。このため、強制的にセンサーチップ220を放熱させる必要があり、そのための冷却部材や放熱部材により半導体パッケージ200や撮像装置100の容積や重量が大きくなる傾向にある。 If the sensor chip 220 has many pixels and operates at high speed, power consumption increases, and the heat generated during operation adversely affects imaging characteristics and reliability. For this reason, it is necessary to forcibly dissipate heat from the sensor chip 220, and the volume and weight of the semiconductor package 200 and imaging device 100 tend to increase due to the need for cooling and heat dissipation members for this purpose.
 ここで、インタポーザ基板400の上面にセンサーチップ220を配置し、その下面にペルチェモジュールを接続し、その下部にヒートシンクを配置した半導体パッケージを比較例として想定する。ミラーレスカメラなどでは、軽量化や省スペース化のために、インタポーザ基板400の裏面にも部品の実装が必要になることがある。しかし、比較例では、インタポーザ基板400の下面にペルチェモジュールを配置するため、その下面において部品を実装するスペースの確保が困難になる。このため、基板面積を広くする必要があるが、その分、半導体パッケージのサイズが大きくなってしまう。ペルチェモジュールやヒートシンクを削減すれば、小型化することができるが、放熱性能が低下するため、好ましくない。 Here, consider a comparative example of a semiconductor package in which the sensor chip 220 is placed on the upper surface of the interposer substrate 400, a Peltier module is connected to its underside, and a heat sink is placed underneath. In mirrorless cameras and the like, it may be necessary to mount components on the underside of the interposer substrate 400 as well in order to reduce weight and save space. However, in the comparative example, since the Peltier module is placed on the underside of the interposer substrate 400, it becomes difficult to secure space to mount components on that underside. This requires a larger substrate area, but this results in a corresponding increase in the size of the semiconductor package. Reducing the Peltier module and heat sink would enable the package to be made smaller, but this is not desirable as it would reduce heat dissipation performance.
 これに対して、同図のように、インタポーザ基板400の上面にセンサーチップ220およびペルチェモジュール300を接続する構成によれば、インタポーザ基板400の下面に部品を実装しやすくなる。このため、基板面積を比較例よりも狭くして、半導体パッケージ200を小型化することができる。また、センサーチップ220の温度をコントロールする際の温度変化によるセンサーチップ220の撮像面の反りも小さくなり、画質を劣化させることもない。このような特徴から、画角サイズの大きい動画撮像を行うセンサーチップ220を実装する撮像装置100の小型化が可能となり、携帯性が向上する。 In contrast, as shown in the figure, a configuration in which the sensor chip 220 and Peltier module 300 are connected to the upper surface of the interposer substrate 400 makes it easier to mount components on the lower surface of the interposer substrate 400. This allows the substrate area to be narrower than in the comparative example, making the semiconductor package 200 more compact. In addition, warping of the imaging surface of the sensor chip 220 due to temperature changes when controlling the temperature of the sensor chip 220 is also reduced, preventing degradation of image quality. These characteristics make it possible to miniaturize the imaging device 100 that incorporates the sensor chip 220 that captures video with a large angle of view, improving portability.
 図3は、本技術の第1の実施の形態における半導体パッケージ200の上面図および下面図である。同図におけるaは、半導体パッケージ200の上面図の一例であり、同図におけるbは、半導体パッケージ200の下面図の一例である。 FIG. 3 is a top view and a bottom view of a semiconductor package 200 according to a first embodiment of the present technology. In the figure, a is an example of a top view of the semiconductor package 200, and b is an example of a bottom view of the semiconductor package 200.
 同図におけるaに例示するように、ペルチェモジュール300の4隅のそれぞれに、ネジ穴312が設けられている。また、同図におけるbに例示するように、インタポーザ基板400の下面に、各種の周辺部品412を配置することができる。 As shown in FIG. 1A, a screw hole 312 is provided at each of the four corners of the Peltier module 300. Also, as shown in FIG. 1B, various peripheral components 412 can be arranged on the underside of the interposer board 400.
 図4は、本技術の第1の実施の形態における半導体パッケージ200の実装例を説明するための図である。撮像装置100内には、取り付け部161および熱伝導シート162が設けられる。 FIG. 4 is a diagram for explaining an example of mounting the semiconductor package 200 in the first embodiment of the present technology. An attachment portion 161 and a thermally conductive sheet 162 are provided within the imaging device 100.
 半導体パッケージ200は、熱伝導シート162を挟んで、取り付け部161にネジ163により固定される。 The semiconductor package 200 is fixed to the mounting portion 161 with screws 163, sandwiching the thermally conductive sheet 162 between them.
 図2から図4に例示した構成により、図3のコネクタ413を介してペルチェモジュール300に電流が供給されると、インタポーザ基板400の上面から放熱され、その基板を介してセンサーチップ220が冷却される。放出された熱は、ペルチェモジュール300から、図4の熱伝導シート162および取り付け部161を経由して撮像装置100の筐体に放出される。 When a current is supplied to the Peltier module 300 via the connector 413 in FIG. 3 in the configuration illustrated in FIG. 2 to FIG. 4, heat is dissipated from the upper surface of the interposer substrate 400, and the sensor chip 220 is cooled via the substrate. The released heat is dissipated from the Peltier module 300 via the thermal conduction sheet 162 and the mounting portion 161 in FIG. 4 to the housing of the imaging device 100.
 [ペルチェモジュールの構成例]
 図5は、本技術の第1の実施の形態におけるペルチェモジュール300の上面図、断面図および下面図の一例である。同図におけるaは、ペルチェモジュール300の上面図の一例であり、同図におけるbは、Y軸方向から見たペルチェモジュール300の断面図の一例である。同図におけるcは、ペルチェモジュール300の下面図の一例である。
[Example of Peltier module configuration]
5A and 5B are an example of a top view, a cross-sectional view, and a bottom view of the Peltier module 300 according to the first embodiment of the present technology. In the figure, a is an example of a top view of the Peltier module 300, and b is an example of a cross-sectional view of the Peltier module 300 as viewed from the Y-axis direction. C is an example of a bottom view of the Peltier module 300.
 同図におけるbに例示するように、ペルチェモジュール300は、金属板310、セラミック基板320、ペルチェ素子330およびセラミック基板340を備える。 As shown in FIG. 3B, the Peltier module 300 includes a metal plate 310, a ceramic substrate 320, a Peltier element 330, and a ceramic substrate 340.
 セラミック基板340は、開口部を有する枠状のセラミック製の基板であり、セラミック基板320の下側(言い換えれば、吸熱側)に配置される。セラミック基板320は、開口部を有する枠状のセラミック製の基板であり、セラミック基板340の上側(言い換えれば、放熱側)に配置される。また、封止樹脂350を塗布可能なように、上側のセラミック基板320の面積は、下側のセラミック基板340よりも狭いものとする。さらに、セラミック基板320が放熱時の温度上昇で変形した際に追従しないように、下側のセラミック基板340の厚みは、上側のセラミック基板320よりも3割程度大きいものとする。 The ceramic substrate 340 is a frame-shaped ceramic substrate with an opening, and is disposed on the lower side (in other words, the heat absorption side) of the ceramic substrate 320. The ceramic substrate 320 is a frame-shaped ceramic substrate with an opening, and is disposed on the upper side (in other words, the heat dissipation side) of the ceramic substrate 340. The area of the upper ceramic substrate 320 is made smaller than that of the lower ceramic substrate 340 so that the sealing resin 350 can be applied. Furthermore, the thickness of the lower ceramic substrate 340 is made approximately 30% greater than that of the upper ceramic substrate 320 so that the ceramic substrate 320 does not follow deformation caused by a temperature rise during heat dissipation.
 なお、セラミック基板320は、特許請求の範囲に記載の放熱側基板の一例であり、セラミック基板340は、特許請求の範囲に記載の吸熱側基板の一例である。 The ceramic substrate 320 is an example of a heat dissipation side substrate as described in the claims, and the ceramic substrate 340 is an example of a heat absorption side substrate as described in the claims.
 ペルチェ素子330は、セラミック基板320とセラミック基板340との間に配置され、Z軸方向におけるサイズ(すなわち、高さ)は、1ミリメートル(mm)以下である。セラミック基板320の開口部の外周に沿って、ペルチェ素子330を構成する複数の半導体(不図示)が配列される。また、これらの半導体の隙間からキャビティ内に異物や水分が侵入しないように、セラミック基板320およびペルチェ素子330のそれぞれの側面が、非導電性の封止樹脂350により封止されている。封止樹脂350として、例えば、粘度が30パスカル秒(Pa・s)以上で、チキソ性の高い、シリコーン系やエポキシ系の熱硬化樹脂で、アウトガスの少ないものが用いられる。 The Peltier element 330 is disposed between the ceramic substrate 320 and the ceramic substrate 340, and its size in the Z-axis direction (i.e., its height) is 1 millimeter (mm) or less. A number of semiconductors (not shown) constituting the Peltier element 330 are arranged along the outer periphery of the opening of the ceramic substrate 320. In addition, the respective sides of the ceramic substrate 320 and the Peltier element 330 are sealed with non-conductive sealing resin 350 to prevent foreign matter or moisture from entering the cavity through the gaps between these semiconductors. As the sealing resin 350, for example, a silicone-based or epoxy-based thermosetting resin with a viscosity of 30 Pascal seconds (Pa·s) or more, high thixotropy, and low outgassing is used.
 金属板310は、黒メッキが施された金属製の基板であり、封止樹脂350によりセラミック基板320の上面と接するように接着される。この金属板310の材料として、線膨張係数および熱伝導率がセラミック基板320より大きく、図4に例示した取り付け部161よりも小さいものが用いられる。これにより、金属板310の熱伝導性を確保しつつ、その熱変形を抑制することができる。また、金属板310の上面のガラス210(不図示)と、金属板310との間の熱膨張係数の相違により熱応力が発生する。このため、ガラス210として、その熱応力を十分に緩和することができるもの(耐熱ガラスなど)が用いられる。 The metal plate 310 is a black-plated metal substrate, and is bonded to the top surface of the ceramic substrate 320 by sealing resin 350. The material used for the metal plate 310 has a linear expansion coefficient and thermal conductivity greater than those of the ceramic substrate 320 and smaller than those of the mounting portion 161 illustrated in FIG. 4. This ensures the thermal conductivity of the metal plate 310 while suppressing its thermal deformation. In addition, thermal stress occurs due to the difference in thermal expansion coefficient between the glass 210 (not shown) on the top surface of the metal plate 310 and the metal plate 310. For this reason, the glass 210 used is one that can sufficiently relieve this thermal stress (such as heat-resistant glass).
 図5におけるaに例示するように、金属板310は、Z軸方向から見て中央部に開口部311を有し、4隅にネジ穴312を有する。 As shown in FIG. 5A, the metal plate 310 has an opening 311 in the center when viewed in the Z-axis direction, and screw holes 312 at the four corners.
 また、同図におけるcに例示するように、セラミック基板340は、Z軸方向から見て中央部に開口部341を有し、下面に端子342および343を有する。同図におけるcの太線は、開口部341の外周を示す。 As shown in Fig. 3c, the ceramic substrate 340 has an opening 341 in the center when viewed from the Z-axis direction, and has terminals 342 and 343 on the bottom surface. The thick line in Fig. 3c indicates the outer periphery of the opening 341.
 図6は、本技術の第1の実施の形態におけるペルチェ素子330の配列を説明するための図である。同図におけるaは、ペルチェ素子330を配列したセラミック基板340の上面図の一例であり、同図におけるbは、同図におけるaの一点鎖線で切断した際のペルチェ素子330およびセラミック基板340の断面図の一例である。同図におけるcは、セラミック基板340の下面図の一例である。同図におけるdは、ペルチェ素子330の拡大図の一例である。同図におけるeは、ペルチェ素子330の単位構造の断面図である。 FIG. 6 is a diagram for explaining the arrangement of Peltier elements 330 in the first embodiment of the present technology. In the figure, a is an example of a top view of a ceramic substrate 340 on which Peltier elements 330 are arranged, and b is an example of a cross-sectional view of the Peltier elements 330 and the ceramic substrate 340 when cut along the dashed line in a of the figure. c is an example of a bottom view of the ceramic substrate 340. d is an example of an enlarged view of the Peltier element 330. e is a cross-sectional view of the unit structure of the Peltier element 330.
 同図におけるeに例示するように、ペルチェ素子330の単位構造は、金メッキの施された電極331、332および335と、p型半導体333およびn型半導体334とを含む。この単位構造は、π型の熱電変換素子と呼ばれる。 As shown in FIG. 1E, the unit structure of Peltier element 330 includes gold-plated electrodes 331, 332, and 335, p-type semiconductor 333, and n-type semiconductor 334. This unit structure is called a π-type thermoelectric conversion element.
 電極335は、下側(吸熱側)のセラミック基板340に形成される。電極332および335は、上側(放熱側)のセラミック基板320に形成される。電極335にp型半導体333およびn型半導体334が、はんだにより接続される。また、電極331に、p型半導体333と、隣のn型半導体(不図示)とが接続される。電極332に、n型半導体334と、隣のp型半導体(不図示)とが接続される。 Electrode 335 is formed on the lower (heat absorption side) ceramic substrate 340. Electrodes 332 and 335 are formed on the upper (heat dissipation side) ceramic substrate 320. P-type semiconductor 333 and n-type semiconductor 334 are connected to electrode 335 with solder. Furthermore, p-type semiconductor 333 and an adjacent n-type semiconductor (not shown) are connected to electrode 331. N-type semiconductor 334 and an adjacent p-type semiconductor (not shown) are connected to electrode 332.
 また、同図におけるaに例示するように、セラミック基板320には、複数の電極335と、複数のp型半導体333と、複数のn型半導体334とが、開口部341の外周に沿って配列される。これらの半導体および電極により、複数単位のπ型熱電変換素子が形成され、直列に接続される。また、左上の2つの電極335には、n型半導体334のみが設けられ、これらの電極335は、同図におけるcの端子342に共通に接続される。また、同図におけるaの右下の2つの電極335には、p型半導体333のみが設けられ、これらの電極335は、同図におけるcの端子343に共通に接続される。この構成により、制御部110がペルチェモジュール300を駆動した際には、端子342から、ペルチェ素子330内の複数のπ型の熱電交換素子を経由して、端子343へ電流が流れる。 Also, as shown in a in the figure, a plurality of electrodes 335, a plurality of p-type semiconductors 333, and a plurality of n-type semiconductors 334 are arranged on the ceramic substrate 320 along the outer periphery of the opening 341. These semiconductors and electrodes form a plurality of units of π-type thermoelectric conversion elements, which are connected in series. The two upper left electrodes 335 are provided with only n-type semiconductors 334, and these electrodes 335 are commonly connected to the terminal 342 in the figure c. The two lower right electrodes 335 are provided with only p-type semiconductors 333, and these electrodes 335 are commonly connected to the terminal 343 in the figure c. With this configuration, when the control unit 110 drives the Peltier module 300, a current flows from the terminal 342 to the terminal 343 via the plurality of π-type thermoelectric conversion elements in the Peltier element 330.
 [インタポーザ基板の構成例]
 図7は、本技術の第1の実施の形態におけるインタポーザ基板400の上面図および断面図の一例である。同図において、周辺部品412やコネクタ413は省略されている。同図におけるaは、インタポーザ基板400の上面図の一例である。同図におけるbは、同図におけるaの線分A1-A2に沿って切断した際の断面図の一例である。同図におけるcは、同図におけるaの線分B1-B2に沿って切断した際の断面図の一例である。
[Example of interposer board configuration]
7 is an example of a top view and a cross-sectional view of the interposer substrate 400 according to the first embodiment of the present technology. In the figure, peripheral components 412 and connectors 413 are omitted. In the figure, a is an example of a top view of the interposer substrate 400. In the figure, b is an example of a cross-sectional view taken along line A1-A2 in the figure. In the figure, c is an example of a cross-sectional view taken along line B1-B2 in the figure.
 同図におけるaに例示するように、インタポーザ基板400の上面の中央部に矩形のアタッチ領域421が配置される。このアタッチ領域421は、センサーチップ220を搭載するための領域であり、金メッキが施されている。 As shown in FIG. 1A, a rectangular attachment area 421 is disposed in the center of the upper surface of the interposer substrate 400. This attachment area 421 is an area for mounting the sensor chip 220, and is gold plated.
 また、アタッチ領域421の外周に沿って、複数のバンプ422が配列される。ワイヤボンディングの際に、バンプ422にワイヤの一端が接続される。 In addition, multiple bumps 422 are arranged along the outer periphery of the attachment region 421. During wire bonding, one end of a wire is connected to the bumps 422.
 また、インタポーザ基板400の4隅のうち、左上に実装ランド423が形成され、右下に実装ランド424が形成される。これらの実装ランド423および424は、金メッキが施されており、図6のセラミック基板340の端子342および343に接続される。 Furthermore, of the four corners of the interposer substrate 400, a mounting land 423 is formed at the upper left and a mounting land 424 is formed at the lower right. These mounting lands 423 and 424 are gold plated and are connected to terminals 342 and 343 of the ceramic substrate 340 in FIG. 6.
 また、インタポーザ基板400の外周に沿ってL字型の塗布領域425および426が形成される。これらの塗布領域425および426は、導電性接着剤を塗布するための領域であり、金メッキが施されている。実装ランド423および424と、塗布領域425および426との間には、非導電性接着剤を塗布するための塗布領域427が設けられる。この塗布領域427には、金メッキが施されていない。また、同図におけるaの点線の領域に接着剤が塗布される。 Also, L-shaped application areas 425 and 426 are formed along the outer periphery of the interposer substrate 400. These application areas 425 and 426 are areas for applying a conductive adhesive, and are gold plated. Application area 427 for applying a non-conductive adhesive is provided between mounting lands 423 and 424 and application areas 425 and 426. This application area 427 is not gold plated. Furthermore, adhesive is applied to the area indicated by the dotted line a in the figure.
 なお、塗布領域425および426は、特許請求の範囲に記載の第1塗布領域の一例であり、塗布領域427は、特許請求の範囲に記載の第2塗布領域の一例である。 Note that application areas 425 and 426 are an example of a first application area described in the claims, and application area 427 is an example of a second application area described in the claims.
 同図におけるbに例示するように、塗布領域425および426と、アタッチ領域421とは、インタポーザ基板400内の銅箔431により共通に接続されている。これにより、アタッチ領域421に搭載されたセンサーチップ220で生じた熱が塗布領域425および426に伝導され、上面のペルチェモジュール300(不図示)に放出される。 As shown in FIG. 1B, the coating areas 425 and 426 and the attachment area 421 are commonly connected by copper foil 431 in the interposer substrate 400. This allows heat generated by the sensor chip 220 mounted in the attachment area 421 to be conducted to the coating areas 425 and 426 and released to the Peltier module 300 (not shown) on the upper surface.
 また、同図におけるcに例示するように、実装ランド423および424は、信号線432および433の一端に接続され、これらの信号線の他端は、コネクタ413(不図示)に接続される。信号線432および433を介して、制御部110からペルチェモジュール300へ電流が供給される。 As shown in FIG. 3c, the mounting lands 423 and 424 are connected to one end of signal lines 432 and 433, and the other ends of these signal lines are connected to the connector 413 (not shown). A current is supplied from the control unit 110 to the Peltier module 300 via the signal lines 432 and 433.
 [ペルチェモジュールの製造方法]
 次に、図8から図16を参照して、ペルチェモジュール300の製造方法について説明する。
[Manufacturing method of Peltier module]
Next, a method for manufacturing the Peltier module 300 will be described with reference to FIGS.
 図8におけるaに例示するように、上側(放熱側)のセラミック基板320の上面において、開口部321の外周に沿って電極331や332などの電極が形成される。同図におけるbは、同図におけるaの一点鎖線で切断した際のセラミック基板320の断面図である。同図におけるcは、セラミック基板320の下面図である。この時点において、セラミック基板340に対向する面が上側であり、図5におけるbと比較して、上下が逆になっている。 As illustrated in FIG. 8a, electrodes such as electrodes 331 and 332 are formed along the outer periphery of opening 321 on the upper surface of ceramic substrate 320 on the upper side (heat dissipation side). FIG. 8b is a cross-sectional view of ceramic substrate 320 taken along the dashed line in FIG. 8a. FIG. 8c is a bottom view of ceramic substrate 320. At this point, the surface facing ceramic substrate 340 is the upper side, and compared to FIG. 5b, the top and bottom are reversed.
 そして、図9におけるaに例示するように、セラミック基板320の上面において、電極のそれぞれに、はんだ336が塗布される。同図におけるbは、同図におけるaの一点鎖線で切断した際のセラミック基板320の断面図である。同図におけるcは、セラミック基板320の下面図である。この時点において、セラミック基板340に対向する面が上側であり、図5におけるbと比較して、上下が逆になっている。 Then, as illustrated in FIG. 9A, solder 336 is applied to each of the electrodes on the upper surface of the ceramic substrate 320. FIG. 9B is a cross-sectional view of the ceramic substrate 320 taken along the dashed line in FIG. 9A. FIG. 9C is a bottom view of the ceramic substrate 320. At this point, the surface facing the ceramic substrate 340 is the upper side, and the top and bottom are reversed compared to FIG. 5B.
 また、図10におけるaに例示するように、下側(吸熱側)のセラミック基板340の上面において、開口部341の外周に沿って複数の電極335が形成される。同図におけるbは、同図におけるaの一点鎖線で切断した際のセラミック基板340の断面図である。同図におけるcは、セラミック基板340の下面図である。 Also, as illustrated in FIG. 10A, a plurality of electrodes 335 are formed along the outer periphery of the opening 341 on the upper surface of the lower (heat absorbing) ceramic substrate 340. FIG. 10B is a cross-sectional view of the ceramic substrate 340 taken along the dashed line in FIG. 10A. FIG. 10C is a bottom view of the ceramic substrate 340.
 そして、図11におけるaに例示するように、セラミック基板340の上面において、電極のそれぞれに、はんだ337が塗布される。同図におけるbは、同図におけるaの一点鎖線で切断した際のセラミック基板340の断面図である。同図におけるcは、セラミック基板340の下面図である。 Then, as shown in FIG. 11A, solder 337 is applied to each of the electrodes on the upper surface of the ceramic substrate 340. FIG. 11B is a cross-sectional view of the ceramic substrate 340 taken along the dashed line in FIG. 11A. FIG. 11C is a bottom view of the ceramic substrate 340.
 次に、図12におけるaに例示するように、セラミック基板340の上面において、電極のそれぞれに、p型半導体333およびn型半導体334が、はんだ付けされる。これらのp型半導体333およびn型半導体334は、開口部341の外周に沿って交互に配列される。同図におけるbは、同図におけるaの一点鎖線で切断した際のセラミック基板340の断面図である。同図におけるcは、セラミック基板340の下面図である。 Next, as illustrated in FIG. 12a, p-type semiconductors 333 and n-type semiconductors 334 are soldered to the electrodes on the upper surface of ceramic substrate 340. These p-type semiconductors 333 and n-type semiconductors 334 are arranged alternately along the outer periphery of opening 341. FIG. 12b is a cross-sectional view of ceramic substrate 340 taken along the dashed line in FIG. 12a. FIG. 12c is a bottom view of ceramic substrate 340.
 図8から図9までの工程と、図10から図12までの工程とは、並列に行ってもよいし、順に行ってもよい。 The steps from FIG. 8 to FIG. 9 and the steps from FIG. 10 to FIG. 12 may be performed in parallel or in sequence.
 そして、図13におけるaに例示するように、セラミック基板320が上下反転されて、セラミック基板340の上面のペルチェ素子330に、はんだ付けされる。同図におけるbは、はんだ付けが完了した状態を示す。 Then, as shown in FIG. 13A, the ceramic substrate 320 is turned upside down and soldered to the Peltier element 330 on the top surface of the ceramic substrate 340. FIG. 13B shows the state after soldering is completed.
 続いて、図14に例示するように、セラミック基板340の周縁に、封止樹脂350が塗布される。 Next, as shown in FIG. 14, sealing resin 350 is applied to the periphery of the ceramic substrate 340.
 図15におけるaは、封止樹脂350の塗布が完了した状態の上面図を示し、同図におけるbは断面図を示す。同図におけるbに例示するように、封止樹脂350は、セラミック基板320よりも高くなるように塗布される。 15a shows a top view of the state after application of the sealing resin 350 has been completed, and FIG. 15b shows a cross-sectional view. As shown in FIG. 15b, the sealing resin 350 is applied so that it is higher than the ceramic substrate 320.
 そして、図16におけるaに例示するように、金属板310が精度よく密着して貼り付けられる。同図におけるbは、貼り付け後の状態を示す。そして、同図におけるcに例示するように加熱により封止樹脂350が硬化される。 Then, as shown in FIG. 16A, the metal plate 310 is attached with good precision and close contact. FIG. 16B shows the state after attachment. Then, as shown in FIG. 16C, the sealing resin 350 is hardened by heating.
 [半導体パッケージの製造方法]
 次に、図8から図16までの工程により得られたペルチェモジュール300を用いて半導体パッケージ200を製造する工程について、図17から図26を参照して説明する。
[Method of manufacturing semiconductor package]
Next, a process for manufacturing the semiconductor package 200 using the Peltier module 300 obtained by the process shown in FIGS. 8 to 16 will be described with reference to FIGS. 17 to 26. FIG.
 図17に例示するように、複数のインタポーザ基板を含む有機基板500が作成される。同図におけるaは、有機基板500の断面図であり、同図におけるbは、有機基板500の下面図である。 As shown in FIG. 17, an organic substrate 500 including multiple interposer substrates is created. In the figure, a is a cross-sectional view of the organic substrate 500, and b is a bottom view of the organic substrate 500.
 次に、図18に例示するように、有機基板500の下面に周辺部品412やコネクタ413が、はんだ付けにより実装される。同図におけるaは、有機基板500の断面図であり、同図におけるbは、有機基板500の下面図である。 Next, as shown in FIG. 18, peripheral components 412 and connectors 413 are mounted on the bottom surface of the organic substrate 500 by soldering. In the figure, a is a cross-sectional view of the organic substrate 500, and b is a bottom view of the organic substrate 500.
 次に、図19に例示するように、ダイシングにより、複数のインタポーザ基板400が得られる。同図におけるaは、インタポーザ基板400の断面図であり、同図におけるbは、インタポーザ基板400の下面図である。 Next, as shown in FIG. 19, a plurality of interposer substrates 400 are obtained by dicing. In the figure, a is a cross-sectional view of the interposer substrate 400, and b is a bottom view of the interposer substrate 400.
 次に、図20におけるaに例示するように、インタポーザ基板400の上面にセンサーチップ220がダイボンドされる。同図におけるbは、インタポーザ基板400の下面図である。 Next, as shown in FIG. 20A, the sensor chip 220 is die-bonded to the upper surface of the interposer substrate 400. FIG. 20B is a bottom view of the interposer substrate 400.
 次に、図21におけるaに例示するように、センサーチップ220がワイヤによりインタポーザ基板400に電気的に接続される。同図におけるbは、インタポーザ基板400の下面図である。 Next, as shown in FIG. 21A, the sensor chip 220 is electrically connected to the interposer substrate 400 by wires. FIG. 21B is a bottom view of the interposer substrate 400.
 次に、図22におけるaおよびbに例示するように、実装ランド423および424と、金メッキの塗布領域425および426との間の塗布領域427に、非導電性接着剤441が塗布される。 Next, as illustrated in FIG. 22a and 22b, non-conductive adhesive 441 is applied to application area 427 between mounting lands 423 and 424 and gold-plated application areas 425 and 426.
 また、図23におけるaおよびbに例示するように、実装ランド423および424と、金メッキの塗布領域425および426とのそれぞれに、導電性接着剤442が塗布される。 Furthermore, as illustrated in FIG. 23A and FIG. 23B, conductive adhesive 442 is applied to each of the mounting lands 423 and 424 and the gold-plated application areas 425 and 426.
 導電性接着剤442の体積抵抗率は、例えば、8×10-4オームセンチメートル(Ω・cm)である。また、塗布領域427の直径は、実装ランド423および424と塗布領域425および426とのそれぞれの幅や直径よりも大きい。このため、塗布領域427の非導電性接着剤441により、実装ランド423および424と塗布領域425および426とは絶縁される。 The volume resistivity of the conductive adhesive 442 is, for example, 8×10 −4 ohm-centimeters (Ω·cm). The diameter of the coating region 427 is greater than the width and diameter of the mounting lands 423 and 424 and the coating regions 425 and 426. Therefore, the non-conductive adhesive 441 in the coating region 427 insulates the mounting lands 423 and 424 from the coating regions 425 and 426.
 また、非導電性接着剤441および導電性接着剤442として、例えば、粘度が30パスカル秒(Pa・s)以上で、チキソ性の高い、シリコーン系やエポキシ系の熱硬化樹脂で、アウトガスの少ないものが用いられる。 The non-conductive adhesive 441 and the conductive adhesive 442 are, for example, silicone-based or epoxy-based thermosetting resins that have a viscosity of 30 Pascal seconds (Pa·s) or more, are highly thixotropic, and have little outgassing.
 次に、図24におけるaに例示するように、ペルチェモジュール300が、インタポーザ基板400に精度よく載置されて、加圧される。そして、同図におけるbに例示するように、ペルチェモジュール300とインタポーザ基板400との間の接着剤の隙間を無くした状態で加熱され、接着剤が硬化する。 Next, as shown in FIG. 24A, the Peltier module 300 is precisely placed on the interposer substrate 400 and pressurized. Then, as shown in FIG. 24B, the Peltier module 300 and the interposer substrate 400 are heated with no gaps in the adhesive between them, causing the adhesive to harden.
 続いて、図25におけるaに例示するように、ペルチェモジュール300の上面において、開口部311の周囲に接着剤313が塗布される。接着剤313として、例えば、紫外線硬化樹脂が用いられる。同図におけるbは、ガラス210搭載前の半導体パッケージ200の断面図である。 Next, as shown in FIG. 25A, adhesive 313 is applied around the opening 311 on the top surface of the Peltier module 300. For example, an ultraviolet curable resin is used as the adhesive 313. In the same figure, B is a cross-sectional view of the semiconductor package 200 before the glass 210 is mounted.
 そして、図26におけるaに例示するようにガラス210が搭載され、同図におけるbに例示するように紫外線が照射されて、接着剤313が硬化する。これにより、キャビティが封止される。なお、接着剤313として、熱硬化樹脂を用い、加熱により硬化させることもできる。 Then, glass 210 is mounted as shown in FIG. 26A, and ultraviolet light is applied as shown in FIG. 26B to harden adhesive 313. This seals the cavity. Note that thermosetting resin can also be used as adhesive 313 and hardened by heating.
 [半導体パッケージの制御例]
 本技術の第1の実施の形態における半導体パッケージの制御方法の一例を示すフローチャートである。この制御は、例えば、画像データを撮像するための所定のアプリケーションが実行されたときに、制御部110により開始される。
[Example of semiconductor package control]
1 is a flowchart showing an example of a control method for a semiconductor package according to a first embodiment of the present technology. This control is started by a control unit 110 when a predetermined application for capturing image data is executed, for example.
 制御部110は、センサーチップ220の温度を所定のタイミングで(例えば、定期的に)取得し(ステップS901)、その温度が所定の上限値より高いか否かを判断する(ステップS902)。温度が上限値以下である場合(ステップS902:No)、制御部110は、ステップS901を繰り返す。 The control unit 110 acquires the temperature of the sensor chip 220 at a predetermined timing (e.g., periodically) (step S901) and determines whether the temperature is higher than a predetermined upper limit (step S902). If the temperature is equal to or lower than the upper limit (step S902: No), the control unit 110 repeats step S901.
 一方、温度が上限値より高い場合(ステップS902:Yes)、制御部110は、ペルチェモジュール300への電流供給を開始する(ステップS903)。ペルチェモジュール300の動作中に制御部110は、センサーチップ220の温度を所定のタイミングで(例えば、定期的に)取得し(ステップS904)、温度が所定の上限値より高いか否かを判断する(ステップS905)。 On the other hand, if the temperature is higher than the upper limit (step S902: Yes), the control unit 110 starts supplying current to the Peltier module 300 (step S903). While the Peltier module 300 is in operation, the control unit 110 acquires the temperature of the sensor chip 220 at a predetermined timing (e.g., periodically) (step S904) and determines whether the temperature is higher than the predetermined upper limit (step S905).
 温度が上限値以下である場合(ステップS905:No)、制御部110は、ペルチェモジュール300への電流供給を停止し(ステップS909)、ステップS901以降を繰り返す。 If the temperature is equal to or lower than the upper limit (step S905: No), the control unit 110 stops the current supply to the Peltier module 300 (step S909) and repeats steps S901 and onward.
 一方、温度が上限値より高い場合(ステップS905:Yes)、制御部110は、バッテリ残量を取得し(ステップS906)、そのバッテリ残量が所定の下限値を超えるか否かを判断する(ステップS907)。バッテリ残量が下限値を超える場合(ステップS907:Yes)、制御部110は、ステップS904以降を繰り返す。 On the other hand, if the temperature is higher than the upper limit (step S905: Yes), the control unit 110 acquires the remaining battery charge (step S906) and determines whether the remaining battery charge exceeds a predetermined lower limit (step S907). If the remaining battery charge exceeds the lower limit (step S907: Yes), the control unit 110 repeats steps S904 and onward.
 一方、バッテリ残量が下限値以下である場合(ステップS907:No)、制御部110は、センサーチップ220に撮像動作の停止を指示し(ステップS908)、制御を終了する。なお、ステップS908において、制御部110は、温度上昇に関する所定のアラームを外部出力することもできる。 On the other hand, if the remaining battery charge is equal to or lower than the lower limit (step S907: No), the control unit 110 instructs the sensor chip 220 to stop the imaging operation (step S908) and ends the control. Note that in step S908, the control unit 110 can also output a specified alarm regarding a temperature rise to the outside.
 同図に例示したように、ペルチェモジュール300を制御して必要な場合にのみ冷却を行うことにより、電力を節約することができる。 As shown in the figure, power can be saved by controlling the Peltier module 300 to perform cooling only when necessary.
 このように、本技術の第1の実施の形態によれば、インタポーザ基板400の上面にセンサーチップ220とともにペルチェモジュール300を接続したため、インタポーザ基板400の下面に部品を実装しやすくなる。これにより、基板面積を比較例よりも狭くして、半導体パッケージ200を小型化することができる。 In this way, according to the first embodiment of the present technology, the Peltier module 300 is connected together with the sensor chip 220 to the upper surface of the interposer substrate 400, making it easier to mount components on the lower surface of the interposer substrate 400. This makes it possible to reduce the substrate area compared to the comparative example, thereby making the semiconductor package 200 smaller.
 <2.第2の実施の形態>
 上述の第1の実施の形態では、ペルチェモジュール300の基板としてセラミック基板を用いていたが、セラミック基板以外の基板を用いることもできる。この第2の実施の形態におけるペルチェモジュール300は、サファイヤ基板を用いた点において第1の実施の形態と異なる。
2. Second embodiment
In the above-described first embodiment, a ceramic substrate is used as the substrate of the Peltier module 300, but a substrate other than a ceramic substrate may also be used. The Peltier module 300 in this second embodiment differs from the first embodiment in that a sapphire substrate is used.
 図28は、本技術の第2の実施の形態におけるペルチェモジュール300の上面図、断面図および下面図の一例である。同図におけるaは、ペルチェモジュール300の上面図であり、同図におけるbは、ペルチェモジュール300の断面図である。同図におけるcは、ペルチェモジュール300の下面図である。 FIG. 28 shows an example of a top view, a cross-sectional view, and a bottom view of a Peltier module 300 in the second embodiment of the present technology. In the figure, a is a top view of the Peltier module 300, and b is a cross-sectional view of the Peltier module 300. c is a bottom view of the Peltier module 300.
 第2の実施の形態におけるペルチェモジュール300は、セラミック基板320の代わりに、開口部の無い、透明なサファイヤ基板360を上側(放熱側)に配置した点において第1の実施の形態と異なる。なお、サファイヤ基板360は、特許請求の範囲に記載の透明基板の一例である。 The Peltier module 300 in the second embodiment differs from the first embodiment in that a transparent sapphire substrate 360 without any openings is placed on the upper side (heat dissipation side) instead of the ceramic substrate 320. The sapphire substrate 360 is an example of a transparent substrate as described in the claims.
 同図に例示したように、サファイヤ基板360を用いることにより、ガラス210が不要となり、半導体パッケージ200の低背化が可能となる。 As shown in the figure, by using a sapphire substrate 360, the glass 210 is no longer necessary, making it possible to reduce the height of the semiconductor package 200.
 このように、本技術の第2の実施の形態によれば、サファイヤ基板360をペルチェモジュール300内に配置したため、ガラス210を設ける必要が無くなる。 In this way, according to the second embodiment of the present technology, the sapphire substrate 360 is disposed within the Peltier module 300, eliminating the need to provide glass 210.
 <3.第3の実施の形態>
 上述の第1の実施の形態では、ペルチェモジュール300の基板としてセラミック基板を用いていたが、セラミック基板以外の基板を用いることもできる。この第3の実施の形態におけるペルチェモジュール300は、フレキシブル基板を用いた点において第1の実施の形態と異なる。
3. Third embodiment
In the above-described first embodiment, a ceramic substrate is used as the substrate of the Peltier module 300, but a substrate other than a ceramic substrate may also be used. The Peltier module 300 in this third embodiment differs from the first embodiment in that a flexible substrate is used.
 図29は、本技術の第3の実施の形態におけるペルチェモジュール300の上面図、断面図および下面図の一例である。同図におけるaは、ペルチェモジュール300の上面図であり、同図におけるbは、ペルチェモジュール300の断面図である。同図におけるcは、ペルチェモジュール300の下面図である。 FIG. 29 shows an example of a top view, a cross-sectional view, and a bottom view of a Peltier module 300 in the third embodiment of the present technology. In the figure, a is a top view of the Peltier module 300, and b is a cross-sectional view of the Peltier module 300. c is a bottom view of the Peltier module 300.
 第3の実施の形態におけるペルチェモジュール300は、セラミック基板320および340の代わりに、フレキシブル基板371および372を配置した点において第1の実施の形態と異なる。フレキシブル基板371および372は、セラミック基板320および340と同様に開口部を有する。 The Peltier module 300 in the third embodiment differs from the first embodiment in that flexible substrates 371 and 372 are arranged instead of the ceramic substrates 320 and 340. The flexible substrates 371 and 372 have openings, just like the ceramic substrates 320 and 340.
 同図に例示したように、フレキシブル基板371および372を用いることにより、第1の実施の形態よりも基板を薄くして半導体パッケージ200をさらに軽量化することができる。 As shown in the figure, by using flexible substrates 371 and 372, the substrates can be made thinner than in the first embodiment, making the semiconductor package 200 even lighter.
 なお、第3の実施の形態に、第2の実施の形態を適用することもできる。この場合には、上側のフレキシブル基板371がサファイヤ基板360に置き換えられる。 The second embodiment can also be applied to the third embodiment. In this case, the upper flexible substrate 371 is replaced with a sapphire substrate 360.
 このように、本技術の第3の実施の形態によれば、フレキシブル基板371および372をペルチェモジュール300内に配置したため、半導体パッケージ200をさらに軽量化することができる。 In this way, according to the third embodiment of the present technology, the flexible substrates 371 and 372 are disposed inside the Peltier module 300, thereby making it possible to further reduce the weight of the semiconductor package 200.
 <4.移動体への応用例>
 本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。
<4. Examples of applications to moving objects>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.
 図30は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。 FIG. 30 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
 車両制御システム12000は、通信ネットワーク12001を介して接続された複数の電子制御ユニットを備える。図30に示した例では、車両制御システム12000は、駆動系制御ユニット12010、ボディ系制御ユニット12020、車外情報検出ユニット12030、車内情報検出ユニット12040、及び統合制御ユニット12050を備える。また、統合制御ユニット12050の機能構成として、マイクロコンピュータ12051、音声画像出力部12052、及び車載ネットワークI/F(interface)12053が図示されている。 The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 30, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
 駆動系制御ユニット12010は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット12010は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。 The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
 ボディ系制御ユニット12020は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット12020は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット12020には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット12020は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。 The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020. The body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
 車外情報検出ユニット12030は、車両制御システム12000を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット12030には、撮像部12031が接続される。車外情報検出ユニット12030は、撮像部12031に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット12030は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。 The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.
 撮像部12031は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部12031は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部12031が受光する光は、可視光であっても良いし、赤外線等の非可視光であっても良い。 The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
 車内情報検出ユニット12040は、車内の情報を検出する。車内情報検出ユニット12040には、例えば、運転者の状態を検出する運転者状態検出部12041が接続される。運転者状態検出部12041は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット12040は、運転者状態検出部12041から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。 The in-vehicle information detection unit 12040 detects information inside the vehicle. To the in-vehicle information detection unit 12040, for example, a driver state detection unit 12041 that detects the state of the driver is connected. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
 マイクロコンピュータ12051は、車外情報検出ユニット12030又は車内情報検出ユニット12040で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット12010に対して制御指令を出力することができる。例えば、マイクロコンピュータ12051は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むADAS(Advanced Driver Assistance System)の機能実現を目的とした協調制御を行うことができる。 The microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
 また、マイクロコンピュータ12051は、車外情報検出ユニット12030又は車内情報検出ユニット12040で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 The microcomputer 12051 can also control the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby performing cooperative control aimed at automatic driving, which allows the vehicle to travel autonomously without relying on the driver's operation.
 また、マイクロコンピュータ12051は、車外情報検出ユニット12030で取得される車外の情報に基づいて、ボディ系制御ユニット12020に対して制御指令を出力することができる。例えば、マイクロコンピュータ12051は、車外情報検出ユニット12030で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。 The microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching high beams to low beams.
 音声画像出力部12052は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図30の例では、出力装置として、オーディオスピーカ12061、表示部12062及びインストルメントパネル12063が例示されている。表示部12062は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。 The audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information. In the example of FIG. 30, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
 図31は、撮像部12031の設置位置の例を示す図である。 FIG. 31 shows an example of the installation position of the imaging unit 12031.
 図31では、撮像部12031として、撮像部12101,12102,12103,12104,12105を有する。 In FIG. 31, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
 撮像部12101,12102,12103,12104,12105は、例えば、車両12100のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部12101及び車室内のフロントガラスの上部に備えられる撮像部12105は、主として車両12100の前方の画像を取得する。サイドミラーに備えられる撮像部12102,12103は、主として車両12100の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部12104は、主として車両12100の後方の画像を取得する。車室内のフロントガラスの上部に備えられる撮像部12105は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。 The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
 なお、図31には、撮像部12101ないし12104の撮影範囲の一例が示されている。撮像範囲12111は、フロントノーズに設けられた撮像部12101の撮像範囲を示し、撮像範囲12112,12113は、それぞれサイドミラーに設けられた撮像部12102,12103の撮像範囲を示し、撮像範囲12114は、リアバンパ又はバックドアに設けられた撮像部12104の撮像範囲を示す。例えば、撮像部12101ないし12104で撮像された画像データが重ね合わせられることにより、車両12100を上方から見た俯瞰画像が得られる。 Note that FIG. 31 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.
 撮像部12101ないし12104の少なくとも1つは、距離情報を取得する機能を有していてもよい。例えば、撮像部12101ないし12104の少なくとも1つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。 At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for detecting phase differences.
 例えば、マイクロコンピュータ12051は、撮像部12101ないし12104から得られた距離情報を基に、撮像範囲12111ないし12114内における各立体物までの距離と、この距離の時間的変化(車両12100に対する相対速度)を求めることにより、特に車両12100の進行路上にある最も近い立体物で、車両12100と略同じ方向に所定の速度(例えば、0km/h以上)で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ12051は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御(追従停止制御も含む)や自動加速制御(追従発進制御も含む)等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 For example, the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
 例えば、マイクロコンピュータ12051は、撮像部12101ないし12104から得られた距離情報を元に、立体物に関する立体物データを、2輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ12051は、車両12100の周辺の障害物を、車両12100のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ12051は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ12061や表示部12062を介してドライバに警報を出力することや、駆動系制御ユニット12010を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。 For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, it can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by forcibly decelerating or steering the vehicle to avoid a collision via the drive system control unit 12010.
 撮像部12101ないし12104の少なくとも1つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ12051は、撮像部12101ないし12104の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部12101ないし12104の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ12051が、撮像部12101ないし12104の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部12052は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部12062を制御する。また、音声画像出力部12052は、歩行者を示すアイコン等を所望の位置に表示するように表示部12062を制御してもよい。 At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured image of the imaging units 12101 to 12104 and recognizes a pedestrian, the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
 以上、本開示に係る技術が適用され得る車両制御システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、例えば、撮像部12031に適用され得る。具体的には、図1の撮像装置100は、撮像部12031に適用することができる。撮像部12031に本開示に係る技術を適用することにより、撮像装置100を小型化して、設置スペースに余裕を持たせることが可能になる。 Above, an example of a vehicle control system to which the technology of the present disclosure can be applied has been described. Of the configurations described above, the technology of the present disclosure can be applied to, for example, the imaging unit 12031. Specifically, the imaging device 100 of FIG. 1 can be applied to the imaging unit 12031. By applying the technology of the present disclosure to the imaging unit 12031, it is possible to miniaturize the imaging device 100 and provide more space for installation.
 なお、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。 Note that the above-described embodiment shows an example for realizing the present technology, and there is a corresponding relationship between the matters in the embodiment and the matters specifying the invention in the claims. Similarly, there is a corresponding relationship between the matters specifying the invention in the claims and the matters in the embodiment of the present technology that have the same name. However, the present technology is not limited to the embodiment, and can be realized by making various modifications to the embodiment without departing from the gist of the technology.
 なお、本明細書に記載された効果はあくまで例示であって、限定されるものではなく、また、他の効果があってもよい。
(1)実装基板と、
 前記実装基板の基板平面のうちアタッチ領域に搭載された半導体チップと、
 前記基板平面のうち前記アタッチ領域の周囲に接続されたペルチェモジュールと
を具備する半導体パッケージ。
(2)前記ペルチェモジュールは、
 放熱側基板と、
 前記実装基板に接続された吸熱側基板と、
 前記放熱側基板および前記吸熱側基板の間に配置されたペルチェ素子と
を備える前記(1)記載の半導体パッケージ。
(3)前記放熱側基板および前記吸熱側基板の両方は、開口部を有するフレキシブル基板である
前記(2)記載の半導体パッケージ。
(4)前記吸熱側基板は、開口部を有するセラミック基板である
前記(2)記載の半導体パッケージ。
(5)前記放熱側基板は、開口部を有するセラミック基板である
前記(4)記載の半導体パッケージ。
(6)前記放熱側基板は、透明基板である
前記(4)記載の半導体パッケージ。
(7)前記ペルチェモジュールは、
 開口部を有する金属板と、
 前記金属板に接続された放熱側基板と、
 前記実装基板に接続された吸熱側基板と、
 前記放熱側基板および前記吸熱側基板の間に配置されたペルチェ素子と
を備える前記(1)から(6)のいずれかに記載の半導体パッケージ。
(8)前記金属板は、取り付け部に固定され、
 前記金属板の線膨張係数および熱伝導率は、前記放熱側基板より大きく、前記取付け部よりも小さい
前記(7)記載の半導体パッケージ。
(9)前記ペルチェモジュールは、前記放熱側基板および前記ペルチェ素子のそれぞれの側面を封止する封止樹脂をさらに備える
前記(7)または(8)記載の半導体パッケージ。
(10)前記半導体チップは、入射光を光電変換して画像データを生成する
前記(1)から(9)のいずれかに記載の半導体パッケージ。
(11)前記ペルチェモジュールおよび前記実装基板により形成された空間を封止するガラスをさらに具備する
前記(1)から(10)のいずれかに記載の半導体パッケージ。
(12)前記基板平面には、前記実装基板の外周に沿った第1塗布領域と前記ペルチェモジュールが接続される実装ランドと前記塗布領域および前記実装ランドの間の第2塗布領域とが配置され、
 前記実装ランドおよび前記第1塗布領域は、導電性接着剤により前記ペルチェモジュールに接着され、
 前記第2塗布領域は、非導電性接着剤により前記ペルチェモジュールに接着される
前記(1)から(12)のいずれかに記載の半導体パッケージ。
(13)実装基板と、
 前記実装基板の基板平面のうちアタッチ領域に搭載された半導体チップと、
 前記基板平面のうち前記アタッチ領域の周囲に接続されたペルチェモジュールと、
 前記ペルチェモジュールに電流を供給する制御部と
を具備する電子装置。
(14)前記制御部は、前記半導体チップの温度を取得し、前記温度が所定の上限値より高い場合には前記電流を供給する
前記(13)記載の電子装置。
(15)実装基板の基板平面のうちアタッチ領域に半導体チップを搭載するチップ搭載手順と、
 前記基板平面のうち前記アタッチ領域の周囲にペルチェモジュールを接続する接続手順と
を具備する半導体パッケージの製造方法。
It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.
(1) a mounting board;
a semiconductor chip mounted in an attachment region of a substrate plane of the mounting substrate;
a Peltier module connected to the periphery of the attachment region on the substrate surface.
(2) The Peltier module is
A heat dissipation substrate;
a heat absorption side substrate connected to the mounting substrate;
The semiconductor package according to (1), further comprising a Peltier element disposed between the heat radiation side substrate and the heat absorption side substrate.
(3) The semiconductor package according to (2), wherein both the heat radiation side substrate and the heat absorption side substrate are flexible substrates having openings.
(4) The semiconductor package according to (2), wherein the heat absorption side substrate is a ceramic substrate having an opening.
(5) The semiconductor package according to (4), wherein the heat dissipation side substrate is a ceramic substrate having an opening.
(6) The semiconductor package according to (4), wherein the heat dissipation side substrate is a transparent substrate.
(7) The Peltier module is
A metal plate having an opening;
a heat dissipation side substrate connected to the metal plate;
a heat absorption side substrate connected to the mounting substrate;
The semiconductor package according to any one of (1) to (6), further comprising a Peltier element disposed between the heat radiation side substrate and the heat absorption side substrate.
(8) The metal plate is fixed to a mounting portion,
The semiconductor package according to (7), wherein the linear expansion coefficient and thermal conductivity of the metal plate are greater than those of the heat dissipation side substrate and smaller than those of the mounting portion.
(9) The semiconductor package according to (7) or (8), wherein the Peltier module further includes a sealing resin that seals each side surface of the heat dissipation substrate and the Peltier element.
(10) The semiconductor package according to any one of (1) to (9), wherein the semiconductor chip performs photoelectric conversion of incident light to generate image data.
(11) The semiconductor package according to any one of (1) to (10), further comprising glass for sealing a space formed by the Peltier module and the mounting substrate.
(12) A first application area along an outer periphery of the mounting board, a mounting land to which the Peltier module is connected, and a second application area between the first application area and the mounting land are arranged on the substrate plane;
the mounting land and the first application area are adhered to the Peltier module by a conductive adhesive;
The semiconductor package according to any one of (1) to (12), wherein the second coating area is attached to the Peltier module by a non-conductive adhesive.
(13) a mounting board;
a semiconductor chip mounted in an attachment region of a substrate plane of the mounting substrate;
a Peltier module connected to a periphery of the attachment area of the substrate plane;
and a control unit that supplies a current to the Peltier module.
(14) The electronic device according to (13), wherein the control unit acquires the temperature of the semiconductor chip and supplies the current when the temperature is higher than a predetermined upper limit value.
(15) a chip mounting step of mounting a semiconductor chip on an attachment area of a substrate plane of a mounting substrate;
and a connection step of connecting a Peltier module to a periphery of the attachment area on the substrate surface.
 100 撮像装置
 110 制御部
 120 バッテリ残量測定部
 130 バッテリ
 140 画像処理部
 150 記憶部
 161 取り付け部
 162 熱伝導シート
 163 ネジ
 200 半導体パッケージ
 210 ガラス
 220 センサーチップ
 230 フレキシブルケーブル
 300 ペルチェモジュール
 310 金属板
 311、321、341 開口部
 312 ネジ穴
 313 接着剤
 320、340 セラミック基板
 330 ペルチェ素子
 331、332、335 電極
 333 p型半導体
 334 n型半導体
 336、337 はんだ
 342、343 端子
 350 封止樹脂
 360 サファイヤ基板
 371、372 フレキシブル基板
 400 インタポーザ基板
 411 温度センサー
 412 周辺部品
 413 コネクタ
 421 アタッチ領域
 422 バンプ
 423、424 実装ランド
 425、426、427 塗布領域
 431 銅箔
 432、433 信号線
 441 非導電性接着剤
 442 導電性接着剤
 500 有機基板
 12031 撮像部
REFERENCE SIGNS LIST 100 Imaging device 110 Control unit 120 Battery remaining capacity measuring unit 130 Battery 140 Image processing unit 150 Memory unit 161 Mounting unit 162 Thermally conductive sheet 163 Screw 200 Semiconductor package 210 Glass 220 Sensor chip 230 Flexible cable 300 Peltier module 310 Metal plate 311, 321, 341 Opening 312 Screw hole 313 Adhesive 320, 340 Ceramic substrate 330 Peltier element 331, 332, 335 Electrode 333 p-type semiconductor 334 n- type semiconductor 336, 337 Solder 342, 343 Terminal 350 Sealing resin 360 Sapphire substrate 371, 372 Flexible substrate 400 Interposer substrate 411 Temperature sensor 412 Peripheral parts 413 Connector 421 Attachment area 422 Bump 423, 424 Mounting land 425, 426, 427 Coating area 431 Copper foil 432, 433 Signal line 441 Non-conductive adhesive 442 Conductive adhesive 500 Organic substrate 12031 Imaging unit

Claims (15)

  1.  実装基板と、
     前記実装基板の基板平面のうちアタッチ領域に搭載された半導体チップと、
     前記基板平面のうち前記アタッチ領域の周囲に接続されたペルチェモジュールと
    を具備する半導体パッケージ。
    A mounting board;
    a semiconductor chip mounted in an attachment region of a substrate plane of the mounting substrate;
    a Peltier module connected to the periphery of the attachment region on the substrate surface.
  2.  前記ペルチェモジュールは、
     放熱側基板と、
     前記実装基板に接続された吸熱側基板と、
     前記放熱側基板および前記吸熱側基板の間に配置されたペルチェ素子と
    を備える請求項1記載の半導体パッケージ。
    The Peltier module is
    A heat dissipation substrate;
    a heat absorption side substrate connected to the mounting substrate;
    2. The semiconductor package according to claim 1, further comprising a Peltier element disposed between the heat radiation side substrate and the heat absorption side substrate.
  3.  前記放熱側基板および前記吸熱側基板の両方は、開口部を有するフレキシブル基板である
    請求項2記載の半導体パッケージ。
    3. The semiconductor package according to claim 2, wherein both the heat radiation side substrate and the heat absorption side substrate are flexible substrates having openings.
  4.  前記吸熱側基板は、開口部を有するセラミック基板である
    請求項2記載の半導体パッケージ。
    3. The semiconductor package according to claim 2, wherein the heat absorption side substrate is a ceramic substrate having an opening.
  5.  前記放熱側基板は、開口部を有するセラミック基板である
    請求項4記載の半導体パッケージ。
    5. The semiconductor package according to claim 4, wherein the heat dissipation side substrate is a ceramic substrate having an opening.
  6.  前記放熱側基板は、透明基板である
    請求項4記載の半導体パッケージ。
    5. The semiconductor package according to claim 4, wherein the heat dissipation side substrate is a transparent substrate.
  7.  前記ペルチェモジュールは、
     開口部を有する金属板と、
     前記金属板に接続された放熱側基板と、
     前記実装基板に接続された吸熱側基板と、
     前記放熱側基板および前記吸熱側基板の間に配置されたペルチェ素子と
    を備える請求項1記載の半導体パッケージ。
    The Peltier module is
    A metal plate having an opening;
    a heat dissipation side substrate connected to the metal plate;
    a heat absorption side substrate connected to the mounting substrate;
    2. The semiconductor package according to claim 1, further comprising a Peltier element disposed between the heat radiation side substrate and the heat absorption side substrate.
  8.  前記金属板は、取り付け部に固定され、
     前記金属板の線膨張係数および熱伝導率は、前記放熱側基板より大きく、前記取付け部よりも小さい
    請求項7記載の半導体パッケージ。
    The metal plate is fixed to a mounting portion,
    8. The semiconductor package according to claim 7, wherein the metal plate has a linear expansion coefficient and a thermal conductivity greater than those of the heat dissipation side substrate and smaller than those of the attachment portion.
  9.  前記ペルチェモジュールは、前記放熱側基板および前記ペルチェ素子のそれぞれの側面を封止する封止樹脂をさらに備える
    請求項7記載の半導体パッケージ。
    The semiconductor package according to claim 7 , wherein the Peltier module further comprises a sealing resin that seals each of the side surfaces of the heat dissipation substrate and the Peltier element.
  10.  前記半導体チップは、入射光を光電変換して画像データを生成する
    請求項1記載の半導体パッケージ。
    2. The semiconductor package according to claim 1, wherein the semiconductor chip performs photoelectric conversion of incident light to generate image data.
  11.  前記ペルチェモジュールおよび前記実装基板により形成された空間を封止するガラスをさらに具備する
    請求項1記載の半導体パッケージ。
    2. The semiconductor package according to claim 1, further comprising glass for sealing a space formed by the Peltier module and the mounting substrate.
  12.  前記基板平面には、前記実装基板の外周に沿った第1塗布領域と前記ペルチェモジュールが接続される実装ランドと前記塗布領域および前記実装ランドの間の第2塗布領域とが配置され、
     前記実装ランドおよび前記第1塗布領域は、導電性接着剤により前記ペルチェモジュールに接着され、
     前記第2塗布領域は、非導電性接着剤により前記ペルチェモジュールに接着される
    請求項1記載の半導体パッケージ。
    a first application area along an outer periphery of the mounting board, a mounting land to which the Peltier module is connected, and a second application area between the first application area and the mounting land are arranged on the board plane;
    the mounting land and the first application area are adhered to the Peltier module by a conductive adhesive;
    2. The semiconductor package of claim 1, wherein the second coating area is attached to the Peltier module by a non-conductive adhesive.
  13.  実装基板と、
     前記実装基板の基板平面のうちアタッチ領域に搭載された半導体チップと、
     前記基板平面のうち前記アタッチ領域の周囲に接続されたペルチェモジュールと、
     前記ペルチェモジュールに電流を供給する制御部と
    を具備する電子装置。
    A mounting board;
    a semiconductor chip mounted in an attachment region of a substrate plane of the mounting substrate;
    a Peltier module connected to a periphery of the attachment area of the substrate plane;
    and a control unit that supplies a current to the Peltier module.
  14.  前記制御部は、前記半導体チップの温度を取得し、前記温度が所定の上限値より高い場合には前記電流を供給する
    請求項13記載の電子装置。
    The electronic device according to claim 13 , wherein the control unit acquires a temperature of the semiconductor chip, and supplies the current when the temperature is higher than a predetermined upper limit value.
  15.  実装基板の基板平面のうちアタッチ領域に半導体チップを搭載するチップ搭載手順と、
     前記基板平面のうち前記アタッチ領域の周囲にペルチェモジュールを接続する接続手順と
    を具備する半導体パッケージの製造方法。
    a chip mounting step of mounting a semiconductor chip on an attachment area of a substrate surface of a mounting substrate;
    and a connection step of connecting a Peltier module to a periphery of the attachment area on the substrate surface.
PCT/JP2023/034401 2022-11-17 2023-09-22 Semiconductor package, electronic device, and method for controlling semiconductor package WO2024106011A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123462A (en) * 1990-09-14 1992-04-23 Toshiba Corp Semiconductor mounting device
JP2008211026A (en) * 2007-02-27 2008-09-11 Yamaha Corp Thermoelectric device
JP2010205818A (en) * 2009-03-02 2010-09-16 Oki Semiconductor Co Ltd Semiconductor device
JP2013243341A (en) * 2012-04-27 2013-12-05 Canon Inc Electronic component and electronic apparatus
WO2021140920A1 (en) * 2020-01-08 2021-07-15 ソニーセミコンダクタソリューションズ株式会社 Solid-state imaging device, imaging device, and imaging system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123462A (en) * 1990-09-14 1992-04-23 Toshiba Corp Semiconductor mounting device
JP2008211026A (en) * 2007-02-27 2008-09-11 Yamaha Corp Thermoelectric device
JP2010205818A (en) * 2009-03-02 2010-09-16 Oki Semiconductor Co Ltd Semiconductor device
JP2013243341A (en) * 2012-04-27 2013-12-05 Canon Inc Electronic component and electronic apparatus
WO2021140920A1 (en) * 2020-01-08 2021-07-15 ソニーセミコンダクタソリューションズ株式会社 Solid-state imaging device, imaging device, and imaging system

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