WO2024103851A1 - Semiconductor structure and forming method therefor, and memory - Google Patents

Abstract

The present invention relates to a semiconductor structure and a forming method therefor, and a memory. The forming method comprises: forming a plurality of bitline structures (2) and first contact windows (101) on a substrate (1); forming a conductive contact layer (3) and a first conductive layer (4) in each first contact window (101); forming a first conductive material layer (5) on the surface of the first conductive layer (4), the top of the first conductive material layer (5) being flush with the end of the first conductive layer (4) away from the conductive contact layer (3); removing the first conductive layer (4) located on the side of the side wall of each bitline structure (2) away from the conductive contact layer (3); forming a second conductive material layer (6) at the top of a structure jointly formed by the first conductive material layer (5) and the bitline structure (2); and etching the first conductive material layer (5) and the second conductive material layer (6) to form an opening (403).

Description

Semiconductor structure and method for forming the same, and memory

cross reference

This disclosure claims priority to Chinese patent application No. 202211429708.X, filed on November 15, 2022, and entitled “Semiconductor structure, method for forming the same, and memory”, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same, and a memory.

Background technique

Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration and fast transmission speed. Storage node contact plugs are important components of DRAM, and their performance directly affects the storage function of capacitors. However, during the manufacturing process, due to the influence of the manufacturing process, short circuits are prone to occur between adjacent storage node contact plugs, resulting in low product yield.

It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

Summary of the invention

In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, and a memory, which can reduce the risk of short circuits and improve product yield.

According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:

providing a substrate;

forming a plurality of spaced-apart bit line structures on the substrate, wherein a first contact window is formed between two adjacent bit line structures;

forming a conductive contact layer and a first conductive layer in the first contact window, wherein a top of the conductive contact layer is lower than a top of the bit line structure, and the first conductive layer covers the top of the conductive contact layer and a side wall of the bit line structure not covered by the conductive contact layer;

forming a first conductive material layer on the surface of the first conductive layer, wherein the first conductive material layer fills the first contact window, and a top of the first conductive material layer is flush with an end of the first conductive layer away from the conductive contact layer;

removing the first conductive layer located on a side of the sidewall of the bit line structure away from the conductive contact layer;

forming a second conductive material layer on top of the structure formed by the first conductive material layer and the bit line structure;

The first conductive material layer and the second conductive material layer are etched to disconnect the second conductive material layers corresponding to adjacent first contact windows from each other and to form an opening between the first conductive material layer and the bit line structure on one side thereof.

In an exemplary embodiment of the present disclosure, the conductive contact layer includes a first contact layer and a second contact layer, and forming the conductive contact layer in the first contact window includes:

forming a first contact layer in the first contact window;

A second contact layer is formed on the surface of the first contact layer, wherein the surface of the second contact layer is lower than the top of the bit line structure, and a portion of the first contact window not filled by the first contact layer and the second contact layer serves as a second contact window.

In an exemplary embodiment of the present disclosure, forming the first conductive layer and the first conductive material layer includes:

forming the first conductive layer on a surface of a structure formed by the second contact layer and the bit line structure;

forming the first conductive material layer on the surface of the first conductive layer, wherein the first conductive material layer at least fills the second contact window;

The first conductive layer and the first conductive material layer are planarized so that the top of the remaining first conductive layer and the top of the remaining first conductive material layer are flush with the top of the bit line structure.

In an exemplary embodiment of the present disclosure, the bit line structure includes a bit line conductive structure, an insulating cover layer and an isolation layer, and forming the bit line structure includes:

forming the bit line conductive structure and the insulating cover layer located on the top of the bit line conductive structure on the surface of the substrate;

forming an isolation material layer on the sidewalls of the bit line conductive structure and the insulating cover layer;

The isolation material layer is etched back to form an isolation layer, wherein a top of the isolation layer is lower than a top of the insulating cover layer and higher than a top of the conductive contact layer and a top of the bit line conductive structure.

In an exemplary embodiment of the present disclosure, the first conductive layer conformally covers the surface of the structure formed by the insulating cover layer, the isolation layer and the conductive contact layer, and the removing of the first conductive layer located on a side of the sidewall of the bit line structure away from the conductive contact layer includes:

The first conductive layer on the sidewall of the insulating cover layer is removed to form a first gap and a second gap on both sides of the first conductive material layer respectively.

In an exemplary embodiment of the present disclosure, a second conductive material layer is formed on top of a structure formed by the first conductive material layer and the bit line structure, including:

A second conductive material layer is formed on the top of the structure formed by the first conductive material layer and the insulating cover layer, and the second conductive material layer at least seals the first gap.

In an exemplary embodiment of the present disclosure, the first conductive material layer and the second conductive material layer are etched so that the second conductive material layers corresponding to adjacent first contact windows are disconnected from each other, and the first conductive material layer and the bit line junction on one side thereof are connected. The openings are formed between the structures, including:

forming a mask layer on a surface of the second conductive material layer;

forming a photoresist layer on a surface of the mask layer;

Exposing and developing the photoresist layer to form a development area, wherein an orthographic projection of the second gap on the substrate is within an orthographic projection of the development area on the substrate;

The mask layer, the second conductive material layer, the first conductive material layer, and the insulating cover layer are etched in the developing area to form the opening.

In an exemplary embodiment of the present disclosure, a material of the first conductive material layer is the same as a material of the second conductive material layer.

In an exemplary embodiment of the present disclosure, the material of the first conductive material layer and the material of the second conductive material layer are both tungsten, and etching the mask layer, the second conductive material layer, the first conductive material layer and the insulating cover layer in the developing area includes:

The second conductive material layer, the first conductive material layer and the insulating cover layer are selectively etched using nitrogen trifluoride and chlorine gas.

According to one aspect of the present disclosure, there is provided a semiconductor structure, comprising:

substrate;

A plurality of bit line structures are distributed on the substrate at intervals, the bit line structures comprising a bit line conductive structure, an insulating cover layer and an isolation layer, the bit line conductive structure is located on the surface of the substrate, the insulating cover layer is located on the top of the bit line conductive structure, the isolation layer covers the side walls of the bit line conductive structure and the insulating cover layer, and the top of the isolation layer is lower than the top of the insulating cover layer; a first contact window is formed between adjacent bit line structures;

A conductive contact layer, located in the first contact window, wherein a top of the conductive contact layer is lower than a top of the isolation layer;

A first conductive layer at least conformally covers the surfaces of the conductive contact layer and the isolation layer;

A first conductive material layer, located on a surface of the first conductive layer, having a first gap between the first conductive material layer and the bit line structure on one side thereof, and having an opening between the first conductive material layer and the bit line structure on the other side thereof;

The second conductive material layer covers the surface of the first conductive material layer and seals the first gap, and extends to the surface of the insulating cover layer adjacent to the first gap.

In an exemplary embodiment of the present disclosure, the conductive contact layer includes:

A first contact layer, located in the first contact window, wherein a top of the first contact layer is higher than a top of the bit line conductive structure;

The second contact layer is located on the surface of the first contact layer, and the surface of the second contact layer is lower than the top of the isolation layer.

In an exemplary embodiment of the present disclosure, the material of the first contact layer is polysilicon, and the material of the second contact layer is cobalt silicide.

In an exemplary embodiment of the present disclosure, a material of the first conductive material layer is the same as a material of the second conductive material layer.

In an exemplary embodiment of the present disclosure, the material of the first conductive material layer is The material of the second conductive material layer is tungsten.

According to one aspect of the present disclosure, a memory is provided, comprising any one of the semiconductor structures described above.

In the method for forming a semiconductor structure disclosed in the present invention, since the top of the first conductive material layer is flush with the end of the first conductive layer away from the conductive contact layer, the end of the first conductive layer can be exposed, and then after the first conductive material layer is formed, the first conductive layer on the side of the sidewall of the bit line structure away from the conductive contact layer can be selectively removed, so as to avoid the second conductive material layer formed in different first contact windows being connected through the first conductive layer on the sidewall of the bit line structure, thereby reducing the risk of short circuit and improving the product yield. At the same time, since the second conductive material layer has not been formed before etching the first conductive layer, the etching process of the first conductive layer will not be affected by the pattern and alignment deviation of the second conductive material layer, and it is relatively easy to control the etching depth. In the above process, only the first conductive layer on the side away from the conductive contact layer is removed, and part of the first conductive layer is still retained on the side close to the conductive contact layer, that is, the surface of the conductive contact layer is still covered with the first conductive layer. When the surface of the conductive contact layer is covered by the first conductive layer, it will not be etched into the conductive contact layer, thereby reducing the probability of structural defects and improving the product yield.

The semiconductor structure and memory disclosed in the present invention, on the one hand, because the isolation layer is located between the conductive contact layer and the bit line conductive layer, and the top of the isolation layer is higher than the top of the bit line conductive structure and the conductive contact layer, a higher insulating barrier can be formed between the bit line conductive structure and the conductive contact layer to ensure the insulation effect, which can reduce the risk of short circuit between the bit line conductive structure and the conductive contact layer adjacent to it, and help to improve product yield; on the other hand, the first gap between the first conductive material layer and the bit line structure is sealed by the second conductive material layer, and the first gap is retained between the first conductive material layer and the bit line structure. Since the dielectric constant of the air in the first gap is relatively small, the parasitic capacitance between adjacent first conductive material layers can be reduced to a certain extent, thereby reducing RC delay, so as to increase the signal transmission speed.

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

FIG1 is a schematic diagram of a semiconductor structure in the related art;

FIG2 is a flow chart of a method for forming a semiconductor structure in an embodiment of the present disclosure;

FIG3 is a schematic diagram of a first contact window in an embodiment of the present disclosure;

FIG4 is a schematic diagram of a first conductive layer and a first conductive material layer in the first example of the present disclosure;

FIG5 is a schematic diagram of a structure after completing step S420 in an embodiment of the present disclosure;

FIG6 is a schematic diagram of the structure after completing step S150 in the embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a structure after completing step S160 in the embodiment of the present disclosure;

FIG8 is a schematic diagram of the structure after completing step S170 in the embodiment of the present disclosure;

FIG. 9 is a schematic diagram of the structure after completing step S530 in the embodiment of the present disclosure.

Description of reference numerals:
100, contact layer; 200, first conductive layer; 300, second conductive layer; 1, substrate; 11,
Shallow trench isolation structure; 12, active area; 101, first contact window; 102, second contact window; 2, bit line structure; 21, bit line conductive structure; 211, first conductive part; 212, second conductive part; 213, third conductive part; 22, insulating covering layer; 23, isolation layer; 230, isolation material layer; 231, first isolation layer; 232, second isolation layer; 233, third isolation layer; 3, conductive contact layer; 31, first contact layer; 32, second contact layer; 4, first conductive layer; 41, first sub-film layer; 42, second sub-film layer; 401, first gap; 402, second gap; 403, opening; 5, first conductive material layer; 6, second conductive material layer; 7, mask layer; 8, photoresist layer; 801, developing area.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements/components/etc. may exist in addition to the listed elements/components/etc.; the terms "first" and "second" etc. are used merely as labels and are not intended to limit the quantity of their objects.

A dynamic random access memory (DRAM) includes a plurality of storage cells, each of which includes a word line, a bit line 100 and a capacitor, wherein the word line structure has a first doping region and a second doping region on both sides, the bit line 100 is electrically connected to the first doping region, and the capacitor is electrically connected to the second doping region through a storage node contact plug. The storage node contact plug includes a contact layer 200, a first conductive layer 300 and a second conductive layer 400. The process of forming the storage node contact plug generally includes: forming contact windows on both sides of the bit line 100, forming a first conductive layer 300 and a second conductive layer 400; and forming a second conductive layer 400 on the contact plug. A contact layer 200 is formed in the window (the surface of the contact layer 200 is lower than the top surface of the contact window), a first conductive layer 300 is formed on the surface of the structure formed by the contact layer 200 and the bit line 100, and a second conductive layer 400 is formed on the surface of the first conductive layer 300. During this process, the second conductive layer 400 can fill the contact window, and then partial areas of the first conductive layer 300 and the second conductive layer 400 are etched back to form conductive contact structures in each contact window. The conductive contact structures can form storage node contact plugs together with the contact layer 200.

However, in the process of back-etching the first conductive layer 300 and the second conductive layer 400, most of the time is used to etch the second conductive layer 400. Since the etching rate of the first conductive layer 300 by the etching gas or etching solution used when etching the second conductive layer 400 is relatively slow, the first conductive layer 300 between adjacent conductive contact structures is easily not completely removed, resulting in residue (as shown in area a in Figure 1), which in turn causes the adjacent conductive contact structures to be connected through the residual first conductive layer 300 therebetween, thereby causing a short circuit.

At present, in order to completely remove the remaining first conductive layer 300 and thus avoid a short circuit, after partial areas of the first conductive layer 300 and the second conductive layer 400 are etched back, an additional etching process may be used to etch the remaining first conductive layer 300 between adjacent conductive contact structures. The etching process is easily affected by the size and alignment accuracy of the conductive contact structure on one side thereof, and the etching depth is difficult to control. In order to ensure that the remaining first conductive layer 300 can be completely removed, sufficient etching time must be provided. During this process, it is easy to etch into the contact layer 200 thereunder, thereby causing structural defects (as shown in area b in FIG1 ), and the product yield is low.

Based on this, an embodiment of the present disclosure provides a method for forming a semiconductor structure. FIG. 2 shows a schematic diagram of the method for forming a semiconductor structure of the present disclosure. Referring to FIG. 2 , the forming method may include steps S110 to S170, wherein:

Step S110, providing a substrate;

Step S120, forming a plurality of spaced-apart bit line structures on the substrate, wherein a first contact window is formed between two adjacent bit line structures;

Step S130, forming a conductive contact layer and a first conductive layer in the first contact window, wherein a top of the conductive contact layer is lower than a top of the bit line structure, and the first conductive layer covers the top of the conductive contact layer and a side wall of the bit line structure not covered by the conductive contact layer;

Step S140, forming a first conductive material layer on the surface of the first conductive layer, wherein the first conductive material layer fills the first contact window, and a top of the first conductive material layer is flush with an end of the first conductive layer away from the conductive contact layer;

Step S150, removing the first conductive layer located on a side of the sidewall of the bit line structure away from the conductive contact layer;

Step S160, forming a second conductive material layer on the top of the structure formed by the first conductive material layer and the bit line structure;

Step S170, etching the first conductive material layer and the second conductive material layer to disconnect the second conductive material layers corresponding to adjacent first contact windows from each other and to form an opening between the first conductive material layer and the bit line structure on one side thereof.

The method for forming a semiconductor structure disclosed in the present invention is that the top of the first conductive material layer is connected to the The end of a conductive layer away from the conductive contact layer is flush, and the end of the first conductive layer can be exposed. After the first conductive material layer is formed, the first conductive layer on the side of the side wall of the bit line structure away from the conductive contact layer can be selectively removed to prevent the second conductive material layer formed in different first contact windows from being connected through the first conductive layer on the side wall of the bit line structure, thereby reducing the risk of short circuit and improving the product yield. At the same time, since the second conductive material layer has not yet been formed before etching the first conductive layer, the etching process of the first conductive layer will not be affected by the pattern and alignment deviation of the second conductive material layer, and it is easier to control the etching depth. In the above process, only the first conductive layer on the side away from the conductive contact layer is removed, and part of the first conductive layer is still retained on the side close to the conductive contact layer, that is, the surface of the conductive contact layer is still covered with the first conductive layer. When the surface of the conductive contact layer is covered by the first conductive layer, it will not be etched into the conductive contact layer, which can reduce the probability of structural defects and improve the product yield.

The steps and specific details of the method for forming a semiconductor structure disclosed in the present invention are described in detail below:

As shown in FIG. 2 , in step S110 , a substrate 1 is provided.

As shown in FIG3 , the substrate 1 may be plate-shaped, for example, it may be a flat plate structure, and its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is made to the shape and material of the substrate 1 herein.

In some embodiments of the present disclosure, the substrate 1 may be a silicon substrate 1, and a shallow trench isolation structure 11 may be formed therein. The material of the shallow trench isolation structure 11 may include silicon oxide or silicon nitride, etc., which is not particularly limited here. The shallow trench isolation structure 11 can separate a plurality of active areas 12 on the substrate 1, and the active area 12 may include a first doped area and a second doped area distributed at intervals. A plurality of word line structures (not shown in the figure) may also be formed in the substrate 1, and each word line structure may be distributed at intervals, and each word line structure may pass through a plurality of active areas 12, and the first doped area and the second doped area in each active area 12 passed through by it may be located on both sides of the word line structure, respectively.

As shown in FIG. 2 , in step S120 , a plurality of spaced-apart bit line structures 2 are formed on the substrate 1 , and a first contact window 101 is formed between two adjacent bit line structures 2 .

Continuing to refer to FIG. 3 , a plurality of bit line structures 2 may be formed on the surface of the substrate 1. Each bit line structure 2 may be distributed at intervals, and the space between adjacent bit line structures 2 may serve as a first contact window 101. Each bit line structure 2 may include a bit line conductive structure 21, an insulating cover layer 22, and an isolation layer 23, wherein:

The bit line conductive structure 21 may be in contact with the first doped region, and may include a first conductive portion 211, a second conductive portion 212, and a third conductive portion 213 that are sequentially stacked and distributed in a direction perpendicular to the substrate 1. In a direction parallel to the substrate 1, the first conductive portion 211, the second conductive portion 212, and the third conductive portion 213 may be aligned at both ends. In some embodiments of the present disclosure, the material of the first conductive portion 211 may be polysilicon, and the polysilicon in the first conductive portion 211 may be doped to improve the conductivity of the first conductive portion 211; the material of the second conductive portion 212 may be titanium nitride, and the material of the third conductive portion 213 may be tungsten, and titanium nitride may be used to prevent tungsten from diffusing into the polysilicon and the substrate 1 to ensure the stability of the bit line conductive structure 21.

The insulating capping layer 22 may be located on the surface of the bit line conductive structure 21 , and the material of the insulating capping layer 22 may be silicon nitride. The isolation layer 23 can cover the side walls of the bit line conductive structure 21 and the insulating covering layer 22 close to the substrate 1. The top of the isolation layer 23 can be higher than the top of the conductive contact layer. Two adjacent insulating covering layers 22, the isolation layer 23 between two adjacent insulating covering layers 22, and the conductive contact layer between two adjacent insulating covering layers 22 can together constitute an inverted convex space.

In some embodiments of the present disclosure, the isolation layer 23 may include a first isolation layer 231, a second isolation layer 232, and a third isolation layer 233, wherein:

The first isolation layer 231 can be attached to the sidewall of the bit line conductive structure 21 and the insulating cover layer 22 on the side close to the bit line conductive structure 21. The thickness of the first isolation layer 231 can be 2nm to 4nm, for example, it can be 2nm, 3nm or 4nm. The second isolation layer 232 covers the surface of the first isolation layer 231, and its thickness can be 1nm to 3nm, for example, it can be 1nm, 2nm or 3nm. The third isolation layer 233 covers the surface of the second isolation layer 232, and its thickness can be 4nm to 6nm, for example, it can be 4nm, 5nm or 6nm. Of course, the first isolation layer 231, the second isolation layer 232 and the third isolation layer 233 can also have other thicknesses, and the thicknesses of the first isolation layer 231, the second isolation layer 232 and the third isolation layer 233 are not specifically limited here.

In an exemplary embodiment of the present disclosure, the material of the first isolation layer 231 is the same as the material of the third isolation layer 233, and the material of the third isolation layer 233 is different from the material of the second isolation layer 232. For example, the materials of the first isolation layer 231 and the third isolation layer 233 may both be silicon nitride, the material of the second isolation layer 232 may be silicon oxide, and the first isolation layer 231, the second isolation layer 232 and the third isolation layer 233 may be a "sandwich" structure consisting of silicon nitride-silicon oxide-silicon nitride.

In an exemplary embodiment of the present disclosure, forming each bit line structure 2 may include steps S210 to S230, wherein:

Step S210 , forming the bit line conductive structure 21 and the insulating cover layer 22 located on the top of the bit line conductive structure 21 on the surface of the substrate 1 .

The first material layer, the second material layer, the third material layer and the insulating material layer can be sequentially formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation, etc. The first material layer, the second material layer, the third material layer and the insulating material layer can be etched by anisotropic etching to remove the first material layer, the second material layer, the third material layer and the insulating material layer in the area outside the first doping region, and only the first material layer, the second material layer, the third material layer and the insulating material layer in the first doping region are retained. At this time, the first material layer is in contact with the surface of the first doping region. The first material layer, the second material layer and the third material layer remaining after etching can jointly constitute the bit line conductive structure 21, and at the same time, the insulating material layer remaining after etching can be defined as the insulating cover layer 22.

In step S220 , an isolation material layer 230 is formed on the sidewalls of the bit line conductive structure 21 and the insulating cover layer 22 .

The isolation material layer 230 may be formed on the surface of the bit line conductive structure 21 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. The isolation material layer 230 may include a first isolation material layer, a second isolation material layer and a third isolation material layer, wherein the first isolation material layer is located on the sidewall and top of the bit line conductive structure 21, and the second isolation material layer is located on the first isolation material layer. The third isolation material layer is located on the surface of the second isolation material layer.

Step S230 , etching back the isolation material layer 230 to form an isolation layer 23 , wherein the top of the isolation layer 23 is lower than the top of the insulating cover layer 22 and higher than the tops of the conductive contact layer 3 and the bit line conductive structure 21 .

The isolation material layer 230 can be etched back by a dry etching process to form an isolation layer 23. In this process, the space of the first contact window 101 can be expanded to prepare for the subsequent formation of a storage node contact plug, thereby avoiding the possibility of increased resistance of the storage node contact plug formed subsequently due to its too small width, which helps to improve the conductive performance of the storage node contact plug formed subsequently. In the above process, part of the insulating layer (for example, silicon oxide) in the isolation layer 23 is removed, which can also reduce the resistance to a certain extent and further improve the conductive performance of the device.

For example, the first isolation material layer remaining after the back etching is used as the first isolation layer 231, the second isolation material layer remaining after the back etching is used as the second isolation layer 232, and the third isolation material layer remaining after the back etching is used as the third isolation layer 233. The first isolation layer 231, the second isolation layer 232 and the third isolation layer 233 together constitute the isolation layer 23. The height of the isolation layer 23 remaining after etching can be higher than the top of the bit line conductive structure 21 and the conductive contact layer 3 subsequently formed on one side thereof. A higher insulation barrier can be formed between the bit line conductive structure 21 and the conductive contact layer 3 adjacent thereto through the isolation layer 23 to ensure the insulation effect, reduce the risk of short circuit between the bit line conductive structure 21 and the conductive contact layer 3 adjacent thereto, and help improve the product yield.

As shown in Figure 2, in step S130, a conductive contact layer 3 and a first conductive layer 4 are formed in the first contact window 101, the top of the conductive contact layer 3 is lower than the top of the bit line structure 2, and the first conductive layer 4 covers the top of the conductive contact layer 3 and the side walls of the bit line structure 2 not covered by the conductive contact layer 3.

As shown in FIG4 , the conductive contact layer 3 may be located in the first contact window 101, the first contact window 101 may expose the second doped region, and the conductive contact layer 3 may be in contact with and connected to the second doped region at the bottom of the first contact window 101. It should be noted that the conductive contact layer 3 does not fill the first contact window 101, and its top may be lower than the top of the isolation layer 23 in the bit line structure 2.

In an exemplary embodiment of the present disclosure, the conductive contact layer 3 may include a first contact layer 31 and a second contact layer 32, wherein the first contact layer 31 may be in contact with the surface of the second doping region, and its top is higher than the top of the bit line conductive structure 21, and the material of the first contact layer 31 may be polysilicon; the second contact layer 32 is located on the surface of the first contact layer 31, and the material of the second contact layer 32 may be cobalt silicide.

In some embodiments of the present disclosure, forming the conductive contact layer 3 may include step S310 and step S320, wherein:

Step S310 , forming a first contact layer 31 in the first contact window 101 .

The first contact material may be deposited in the first contact window 101 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In order to ensure that the thickness of the first contact layer 31 to be formed can be accurately controlled later, the first contact material may at least fill the first contact window 101, that is, the deposition may be stopped after the first contact material fills the first contact window 101. In some embodiments of the present disclosure, the first contact material may be polysilicon.

Subsequently, the first contact material may be selectively etched by a dry etching process, thereby removing the first contact material located on the top of the bit line structure 2, and etching a portion of the first contact material located in the first contact window 101. When the first contact material is polysilicon, the etching gas of the dry etching may be a non-fluorocarbon gas, for example, the etching gas may be HCl or Br ₂ , etc.

It should be noted that step S230 (etching back the isolation material layer 230 to form the isolation layer 23) can be completed at the same time during the process of etching back the first contact material, that is, during the process of etching back the first contact material, the portion of the third isolation material layer exposed on the side wall of the insulating cover layer 22 can be etched away at the same time, and then the etching gas (carbon fluoride gas, such as _CF4 or _CHF3 , etc.) can be switched to remove the second isolation material layer exposed on the side wall of the insulating cover layer 22. Finally, the etching gas can be switched again to continue etching the first contact material until the remaining first contact material reaches a preset height, and the remaining first contact material after etching back can be defined as the first contact layer 31.

Step S320, forming a second contact layer 32 on the surface of the first contact layer 31, wherein the surface of the second contact layer 32 is lower than the top of the bit line structure 2, and the portion of the first contact window 101 not filled by the first contact layer 31 and the second contact layer 32 serves as the second contact window 102.

The second contact layer 32 may be formed on the surface of the first contact layer 31 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In some embodiments of the present disclosure, during the deposition of the second contact layer 32, the deposited material may be cobalt. Under high temperature, the cobalt may react with the polysilicon thereunder to form cobalt silicide. In other words, the material of the second contact layer 32 ultimately formed is cobalt silicide, which may effectively form an ohmic contact with the polysilicon at its bottom, thereby helping to reduce resistance.

It should be noted that the second contact layer 32 can be a thin film conformally attached to the surface of the first contact layer 31, and its top can be lower than the top of the isolation layer 23. The second contact layer 32, the isolation layer 23 and the adjacent bit line structure 2 can form an inverted convex window, which can serve as the second contact window 102.

The first conductive layer 4 can be conformally attached to the inner wall and bottom of the second contact window 102 , that is, the first conductive layer 4 can conformally cover the surface of the inverted convex structure formed by the insulating cover layer 22 , the isolation layer 23 and the conductive contact layer 3 .

In an exemplary embodiment of the present disclosure, the first conductive layer 4 may be a single-layer film layer or a multi-layer film layer, which is not particularly limited herein. Taking the multi-layer film layer as an example, the first conductive layer 4 may include a first sub-film layer 41 and a second sub-film layer 42, wherein the first sub-film layer 41 may be conformally attached to the inner wall and the bottom of the second contact window 102, and the second sub-film layer 42 may be located on the surface of the first sub-film layer 41. The material of the first sub-film layer 41 is different from that of the second sub-film layer 42. For example, the material of the first sub-film layer 41 may be titanium, and the material of the second sub-film layer 42 may be titanium nitride. Titanium may be used to balance the adhesion and tension between titanium nitride and the inner wall of the second contact window 102. At the same time, the arrangement of titanium nitride may reduce the probability of metal atoms in the storage node contact plug formed subsequently diffusing into the conductive contact layer 3 and the bit line structure 2, which helps to improve the stability of the device.

As shown in FIG. 2 , in step S140, a first conductive layer 4 is formed on the surface of the first conductive layer 4. The conductive material layer 5 fills up the first contact window 101 , and the top of the first conductive material layer 5 is flush with the end of the first conductive layer 4 away from the conductive contact layer 3 .

A first conductive material layer 5 can be formed on the surface of the first conductive layer 4. The first conductive material layer 5 can fill the second contact window 102 (i.e., the remaining space in the first contact window 101). The material of the first conductive material layer 5 can be a metal material or a non-metallic material with good conductive properties. For example, the material of the first conductive material layer 5 can be tungsten. Of course, it can also be other materials, which are not listed here one by one.

In an exemplary embodiment of the present disclosure, forming the first conductive layer 4 and the first conductive material layer 5 may include steps S410 to S430, wherein:

Step S410 , forming the first conductive layer 4 on the surface of the structure formed by the second contact layer 32 and the bit line structure 2 .

The first conductive layer 4 can be formed on the surface of the structure formed by the second contact layer 32 and the bit line structure 2 (i.e., the inner wall and bottom of the second contact window 102) by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation. Of course, the first conductive layer 4 can also be formed by other methods, and the formation method of the first conductive layer 4 is not particularly limited herein.

It should be noted that when the first conductive layer 4 is a multi-layer film, for example, including a first sub-layer 41 and a second sub-layer 42 , the first sub-layer 41 and the second sub-layer 42 can be sequentially deposited in the second contact window 102 .

Step S420 , forming the first conductive material layer 5 on the surface of the first conductive layer 4 , wherein the first conductive material layer 5 at least fills the second contact window 102 .

The first conductive material layer 5 can be formed on the surface of the first conductive layer 4 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation. Of course, the first conductive material layer 5 can also be formed by other methods, and the formation method of the first conductive material layer 5 is not particularly limited here. It should be noted that the first conductive material layer 5 can at least fill the second contact window 102, that is, the deposition can be stopped after the material used to form the first conductive material layer 5 fills the second contact window 102. In the embodiment of the present disclosure, the structure after completing step S420 is shown in Figure 5.

Step S430 , planarizing the first conductive layer 4 and the first conductive material layer 5 , so that the top of the remaining first conductive layer 4 and the top of the remaining first conductive material layer 5 are flush with the top of the bit line structure 2 .

The first conductive layer 4 and the first conductive material layer 5 can be ground by a grinding process, thereby removing the first conductive layer 4 and the first conductive material layer 5 located on the top of the bit line structure 2, and making the ends of the first conductive layer 4 and the first conductive material layer 5 located in the second contact window 102 away from the substrate 1 flush with the top of the bit line structure 2, thereby reducing the probability of the first conductive material layer 5 in the adjacent second contact windows 102 being connected through the first conductive material layer 5 on the top of the bit line, thereby reducing the probability of the first conductive material layer 5 in the adjacent second contact windows 102 being short-circuited, thereby improving the product yield.

As shown in FIG. 2 , in step S150 , the first conductive layer 4 located on a side of the sidewall of the bit line structure 2 away from the conductive contact layer 3 is removed.

A portion of the first conductive layer 4 can be removed by a selective etching process to prevent the second conductive material layer 6 formed in different first contact windows 101 from being connected through the first conductive layer 4 on the sidewall of the bit line structure 2, thereby reducing the risk of short circuits and improving product yield. In the embodiment of the present disclosure, the structure after completing step S150 is shown in FIG6 .

For example, the first conductive layer 4 can be selectively etched by a wet etching process or a dry etching process. During the etching process, the etching solution or gas used has a high etching rate for the first conductive layer 4, and at the same time, a low etching rate for the first conductive material layer 5. For example, during the etching process, the etching selectivity ratio of the first conductive layer 4 and the first conductive material layer 5 can be greater than 20.

It should be noted that the type of etching solution or etching gas during the etching process can be set according to the specific materials of the first conductive layer 4 and the first conductive material layer 5, and the etching solution or etching gas is not specifically limited here. Taking wet etching as an example, when the material of the first conductive layer 4 is titanium nitride and/or titanium, and the material of the first conductive material layer 5 is tungsten, the etching solution can be a mixture of an ammonium salt solution and dilute sulfuric acid, and during the wet etching process, the etching rate of the first conductive layer 4 can be 3nm/10s.

In an exemplary embodiment of the present disclosure, the first conductive layer 4 located on the sidewalls of the insulating cover layer 22 may be removed to form a first gap 401 and a second gap 402 on both sides of the first conductive material layer 5. That is, when the second contact window 102 is an inverted convex shape, the first conductive layer 4 on the sidewalls of the portion of the inverted convex shape with a larger cross-sectional area in a direction parallel to the substrate 1 may be removed, thereby forming gaps on both sides of the first conductive material layer 5. The gaps may be located between the first conductive material layer 5 and the insulating cover layer 22 of the bit line structure 2. For the sake of distinction, the two gaps may be defined as a first gap 401 and a second gap 402, respectively.

It should be noted that, in the above process, the first conductive layer 4 on the side wall of the inverted convex shape with a smaller cross-sectional area in a direction parallel to the substrate 1 and the surface of the inverted convex shape close to the substrate 1 is not removed, that is, the surface of the conductive contact layer 3 is not exposed. Therefore, the conductive contact layer 3 will not be etched into the interior during the etching process, and the structure of the conductive contact layer 3 will not be destroyed, which can reduce the probability of structural defects and improve product yield.

As shown in FIG. 2 , in step S160 , a second conductive material layer 6 is formed on the top of the structure formed by the first conductive material layer 5 and the bit line structure 2 .

The second conductive material layer 6 can be formed on the top of the structure formed by the first conductive material layer 5 and the bit line structure 2 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation. Of course, the second conductive material layer 6 can also be formed by other methods, and the formation method of the second conductive material layer 6 is not particularly limited herein.

In some embodiments of the present disclosure, the material of the second conductive material layer 6 may be a metal material or a non-metal material with good conductivity. The material of the second conductive material layer 6 may be the same as or different from the material of the first conductive material layer 5, and is not particularly limited here.

Optionally, the material of the second conductive material layer 6 is the same as that of the first conductive material layer 5. For example, the material of the second conductive material layer 6 and the material of the first conductive material layer 5 can both be tungsten. Of course, they can also be other materials, which will not be listed here one by one.

In some exemplary embodiments of the present disclosure, during the process of forming the second conductive material layer 6 on the top of the structure jointly formed by the first conductive material layer 5 and the insulating covering layer 22, the first conductive material layer 5 may fill the first gap 401 and the second gap 402, or may seal the first gap 401 and/or the second gap 402 inside.

Optionally, in the process of forming the second conductive material layer 6 on the top of the structure formed by the first conductive material layer 5 and the insulating cover layer 22, at least the first gap 401 can be sealed, thereby retaining the first gap 401 between the first conductive material layer 5 and the bit line structure 2. In this process, since the dielectric constant of the air in the first gap 401 is relatively small, the parasitic capacitance between adjacent first conductive material layers 5 can be reduced to a certain extent, thereby reducing the RC delay, so as to improve the transmission speed of the signal. In the embodiment of the present disclosure, the structure after completing step S160 is shown in FIG. 7.

As shown in FIG. 2 , in step S170 , the first conductive material layer 5 and the second conductive material layer 6 are etched to disconnect the second conductive material layers 6 corresponding to adjacent first contact windows 101 from each other and form an opening 403 between the first conductive material layer 5 and the bit line structure 2 on one side thereof.

The first conductive material layer 5 and the second conductive material layer 6 can be selectively etched so that the second conductive material layers 6 corresponding to adjacent second contact windows 102 are disconnected from each other and do not interfere with each other, thereby reducing the risk of short circuit between the second conductive material layers 6 in adjacent second contact windows 102 and helping to improve product yield.

In the process of etching the first conductive material layer 5 and the second conductive material layer 6, in order to ensure that the second conductive material layers 6 in adjacent second contact windows 102 are completely disconnected, an opening 403 may be formed between the first conductive material layer 5 and the bit line structure 2 on one side thereof, and the opening 403 may be located on the side of the first conductive material layer 5 away from the first void 401, that is, in the process of forming the opening 403, the first conductive material layer 5 adjacent to the second void 402 and the first conductive material layer 5 on the top of the second void 402 may be removed, and in this process, the second void 402 is included in the opening 403. In the embodiment of the present disclosure, the structure after completing step S170 is shown in FIG8 .

In an exemplary embodiment of the present disclosure, etching the first conductive material layer 5 and the second conductive material layer 6 to disconnect the second conductive material layers 6 corresponding to adjacent first contact windows 101 from each other and forming an opening 403 between the first conductive material layer 5 and the bit line structure 2 on one side thereof (i.e., step S170) may include steps S510 to S540, wherein:

Step S510 , forming a mask layer 7 on the surface of the second conductive material layer 6 .

A mask layer 7 can be formed on the surface of the second conductive material layer 6 by chemical vapor deposition, physical vapor deposition, vacuum evaporation, magnetron sputtering, atomic layer deposition or other methods. The mask layer 7 can be a multi-layer film structure or a single-layer film structure. Its material can be at least one of polymer, SiO2, SiN, SiON, polysilicon and SiCN. Of course, it can also be other materials, which are not listed here one by one.

Step S520 , forming a photoresist layer 8 on the surface of the mask layer 7 .

The photoresist layer 8 may be formed on the surface of the mask layer 7 facing away from the substrate 1 by spin coating or other methods. The material of the photoresist layer 8 may be positive photoresist or negative photoresist, which is not particularly limited herein.

Step S530 , exposing and developing the photoresist layer 8 to form a development area 801 , wherein the orthographic projection of the second gap 402 on the substrate 1 is within the orthographic projection of the development area 801 on the substrate 1 .

The photoresist layer 8 may be exposed using a mask, and the pattern of the mask may match the pattern required for the opening 403. Subsequently, the exposed photoresist layer 8 may be developed to form a plurality of spaced development areas 801, each of which may expose the surface of the mask layer 7, and the pattern of the development area 801 may be the same as the pattern required for the opening 403, and the size of the development area 801 may be the same as the size required for the opening 403. In the embodiment of the present disclosure, the structure after completing step S530 is shown in FIG9 .

In step S540 , the mask layer 7 , the second conductive material layer 6 , the first conductive material layer 5 , and the insulating cover layer 22 are etched in the developing area 801 to form the opening 403 .

The mask layer 7, the second conductive material layer 6, the first conductive material layer 5 and the insulating cover layer 22 may be anisotropically etched in each developing area 801 by an anisotropic etching process, thereby forming an opening 403. After the above etching process is completed, the photoresist layer 8 and the mask layer 7 may be removed, so that the surface of the etched second conductive material layer 6 is exposed.

In some embodiments of the present disclosure, the mask layer 7, the second conductive material layer 6, the first conductive material layer 5 and the insulating cover layer 22 may be anisotropically etched in each developing area 801 by dry etching or wet etching, and the etching method is not particularly limited herein.

It should be noted that the type of etching solution or etching gas during the etching process can be set according to the specific materials of the first conductive material layer 5, the second conductive material layer 6 and the insulating cover layer 22, and the etching solution or etching gas is not specifically limited here. Taking dry etching as an example, when the material of the first conductive layer 4 and the material of the second conductive material layer 6 are both tungsten, and the material of the insulating cover layer 22 is silicon nitride, the etching gas can be a mixed gas of nitrogen trifluoride and chlorine, that is, nitrogen trifluoride and chlorine can be used to selectively etch the second conductive material layer 6, the first conductive material layer 5 and the insulating cover layer 22.

The first conductive material layer 5 and the second conductive material layer 6 remaining after etching may together constitute a storage node contact plug, which may serve as a contact structure of a capacitor to store charges collected in the capacitor.

It should be noted that, although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and/or one step may be decomposed into multiple steps, etc.

The present disclosure also provides a semiconductor structure. FIG8 shows a schematic diagram of the semiconductor structure of the present disclosure. Referring to FIG8, the semiconductor structure may include a substrate 1, a plurality of bit line structures 2, a conductive contact layer 3, a first conductive layer 4, a first conductive material layer 5, and a second conductive layer 6. An electrical material layer 6, wherein:

A plurality of bit line structures 2 may be distributed on the substrate 1 at intervals, the bit line structures 2 comprising a bit line conductive structure 21, an insulating cover layer 22 and an isolation layer 23, the bit line conductive structure 21 being located on the surface of the substrate 1, the insulating cover layer 22 being located on the top of the bit line conductive structure 21, the isolation layer 23 covering the sidewalls of the bit line conductive structure 21 and the insulating cover layer 22, and the top of the isolation layer 23 being lower than the top of the insulating cover layer 22; adjacent bit line structures 2 enclose a first contact window 101;

The conductive contact layer 3 may be located in the first contact window 101 , and the top of the conductive contact layer 3 is lower than the top of the isolation layer 23 ;

The first conductive layer 4 may at least conformally cover the surface of the conductive contact layer 3 and the isolation layer 23;

The first conductive material layer 5 may be located on the surface of the first conductive layer 4 and have a first gap 401 between it and the bit line structure 2 on one side and an opening 403 between it and the bit line structure 2 on the other side;

The second conductive material layer 6 may cover the surface of the first conductive material layer 5 and seal the first gap 401 , and extend to the surface of the insulating cover layer 22 adjacent to the first gap 401 .

The semiconductor structure disclosed in the present invention, on the one hand, because the isolation layer 23 is located between the conductive contact layer 3 and the bit line conductive layer, and the top of the isolation layer 23 is higher than the top of the bit line conductive structure 21 and the conductive contact layer 3, a higher insulating barrier can be formed between the bit line conductive structure 21 and the conductive contact layer 3 to ensure the insulating effect, which can reduce the risk of short circuit between the bit line conductive structure 21 and the conductive contact layer 3 adjacent thereto, and help to improve the product yield; on the other hand, the first gap 401 between the first conductive material layer 5 and the bit line structure 2 is sealed by the second conductive material layer 6, and the first gap 401 is retained between the first conductive material layer 5 and the bit line structure 2. Since the dielectric constant of the air in the first gap 401 is relatively small, the parasitic capacitance between the adjacent first conductive material layers 5 can be reduced to a certain extent, thereby reducing the RC delay, so as to increase the signal transmission speed.

The specific details and formation processes of other parts of the semiconductor structure disclosed in the present invention have been described in detail in the corresponding semiconductor structure formation method, and therefore, they will not be repeated here.

The embodiments of the present disclosure also provide a memory, which may include the semiconductor structure in any of the above-mentioned embodiments. The specific details, formation process and beneficial effects have been described in detail in the corresponding semiconductor structure and the method for forming the semiconductor structure, and will not be repeated here.

For example, the memory may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. Of course, it may also be other storage devices, which are not listed here one by one.

Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims (15)

1. A method for forming a semiconductor structure, comprising:

   Providing a substrate (1);

   A plurality of spaced-apart bit line structures (2) are formed on the substrate (1), wherein a first contact window (101) is formed between two adjacent bit line structures (2);

   A conductive contact layer (3) and a first conductive layer (4) are formed in the first contact window (101), wherein the top of the conductive contact layer (3) is lower than the top of the bit line structure (2), and the first conductive layer (4) covers the top of the conductive contact layer (3) and the side walls of the bit line structure (2) not covered by the conductive contact layer (3);

   A first conductive material layer (5) is formed on the surface of the first conductive layer (4), wherein the first conductive material layer (5) fills the first contact window (101), and the top of the first conductive material layer (5) is flush with the end of the first conductive layer (4) away from the conductive contact layer (3);

   Removing the first conductive layer (4) located on a side of the side wall of the bit line structure (2) away from the conductive contact layer (3);

   forming a second conductive material layer (6) on the top of the structure formed by the first conductive material layer (5) and the bit line structure (2);

   The first conductive material layer (5) and the second conductive material layer (6) are etched so that the second conductive material layers (6) corresponding to adjacent first contact windows (101) are disconnected from each other, and an opening (403) is formed between the first conductive material layer (5) and the bit line structure (2) on one side thereof.
2. The forming method according to claim 1, wherein the conductive contact layer (3) comprises a first contact layer (31) and a second contact layer (32), and the forming of the conductive contact layer (3) in the first contact window (101) comprises:

   forming a first contact layer (31) in the first contact window (101);

   A second contact layer (32) is formed on the surface of the first contact layer (31), the surface of the second contact layer (32) is lower than the top of the bit line structure (2), and the portion of the first contact window (101) not filled by the first contact layer (31) and the second contact layer (32) serves as a second contact window (102).
3. The forming method according to claim 2, wherein forming the first conductive layer (4) and the first conductive material layer (5) comprises:

   forming the first conductive layer (4) on the surface of a structure formed by the second contact layer (32) and the bit line structure (2);

   forming the first conductive material layer (5) on the surface of the first conductive layer (4), wherein the first conductive material layer (5) at least fills the second contact window (102);

   The first conductive layer (4) and the first conductive material layer (5) are planarized so that the top of the remaining first conductive layer (4) and the top of the remaining first conductive material layer (5) are flush with the top of the bit line structure (2).
4. The forming method according to any one of claims 1 to 3, wherein the bit line structure (2) includes a bit line conductive structure (21), an insulating cover layer (22) and an isolation layer 23, and the bit line structure (2) includes:

   Forming the bit line conductive structure (21) and the insulating cover layer (22) located on the top of the bit line conductive structure (21) on the surface of the substrate (1);

   forming an isolation material layer (230) on the side walls of the bit line conductive structure (21) and the insulating cover layer (22);

   The isolation material layer (230) is etched back to form an isolation layer 23, wherein the top of the isolation layer 23 is lower than the top of the insulating cover layer (22) and higher than the top of the conductive contact layer (3) and the bit line conductive structure (21).
5. The formation method according to claim 4, wherein the first conductive layer (4) conformally covers the surface of the structure formed by the insulating cover layer (22), the isolation layer 23 and the conductive contact layer (3), and the removing of the first conductive layer (4) located on a side of the sidewall of the bit line structure (2) away from the conductive contact layer (3) comprises:

   The first conductive layer (4) located on the side wall of the insulating cover layer (22) is removed to form a first gap (401) and a second gap (402) on both sides of the first conductive material layer (5), respectively.
6. The forming method according to claim 5, wherein forming a second conductive material layer (6) on top of a structure formed by the first conductive material layer (5) and the bit line structure (2) comprises:

   A second conductive material layer (6) is formed on the top of the structure formed by the first conductive material layer (5) and the insulating cover layer (22), and the second conductive material layer (6) at least seals the first gap (401).
7. The forming method according to claim 6, wherein the first conductive material layer (5) and the second conductive material layer (6) are etched so that the second conductive material layers (6) corresponding to adjacent first contact windows (101) are disconnected from each other and an opening (403) is formed between the first conductive material layer (5) and the bit line structure (2) on one side thereof, comprising:

   forming a mask layer (7) on the surface of the second conductive material layer (6);

   forming a photoresist layer (8) on the surface of the mask layer (7);

   Exposing and developing the photoresist layer (8) to form a development area (801), wherein the orthographic projection of the second gap (402) on the substrate (1) is within the orthographic projection of the development area (801) on the substrate (1);

   The mask layer (7), the second conductive material layer (6), the first conductive material layer (5) and the insulating cover layer (22) are etched in the developing area (801) to form the opening (403).
8. The forming method according to claim 7, wherein the material of the first conductive material layer (5) is the same as the material of the second conductive material layer (6).
9. The forming method according to claim 8, wherein the material of the first conductive material layer (5) and the material of the second conductive material layer (6) are both tungsten, and in the developing area (801) Etching the mask layer (7), the second conductive material layer (6), the first conductive material layer (5) and the insulating cover layer (22), comprising:

   The second conductive material layer (6), the first conductive material layer (5) and the insulating cover layer (22) are selectively etched using nitrogen trifluoride and chlorine gas.
10. A semiconductor structure, comprising:

    Substrate (1);

    A plurality of bit line structures (2) are distributed at intervals on the substrate (1), the bit line structures (2) comprising a bit line conductive structure (21), an insulating covering layer (22) and an isolation layer 23, the bit line conductive structure (21) being located on the surface of the substrate (1), the insulating covering layer (22) being located on the top of the bit line conductive structure (21), the isolation layer 23 covering the side walls of the bit line conductive structure (21) and the insulating covering layer (22), and the top of the isolation layer 23 being lower than the top of the insulating covering layer (22); a first contact window (101) is formed between adjacent bit line structures (2);

    A conductive contact layer (3) is located in the first contact window (101), and the top of the conductive contact layer (3) is lower than the top of the isolation layer 23;

    A first conductive layer (4), at least conformally covering the surfaces of the conductive contact layer (3) and the isolation layer 23;

    A first conductive material layer (5), located on a surface of the first conductive layer (4), having a first gap (401) between it and the bit line structure (2) on one side, and having an opening (403) between it and the bit line structure (2) on the other side;

    The second conductive material layer (6) covers the surface of the first conductive material layer (5) and seals the first gap (401), and extends to the surface of the insulating cover layer (22) adjacent to the first gap (401).
11. The semiconductor structure according to claim 10, wherein the conductive contact layer (3) comprises:

    A first contact layer (31), located in the first contact window (101), the top of the first contact layer (31) being higher than the top of the bit line conductive structure (21);

    The second contact layer (32) is located on the surface of the first contact layer (31), and the surface of the second contact layer (32) is lower than the top of the isolation layer 23.
12. The semiconductor structure according to claim 11, wherein the material of the first contact layer (31) is polysilicon, and the material of the second contact layer (32) is cobalt silicide.
13. The semiconductor structure according to any one of claims 10 to 12, wherein the material of the first conductive material layer (5) is the same as the material of the second conductive material layer (6).
14. The semiconductor structure according to claim 13, wherein the material of the first conductive material layer (5) and the material of the second conductive material layer (6) are both tungsten.
15. A memory, comprising the semiconductor structure according to any one of claims 10 to 14.