WO2024103666A1 - 一种多核处理器动态缓存分区隔离系统及其控制方法 - Google Patents

一种多核处理器动态缓存分区隔离系统及其控制方法 Download PDF

Info

Publication number
WO2024103666A1
WO2024103666A1 PCT/CN2023/095559 CN2023095559W WO2024103666A1 WO 2024103666 A1 WO2024103666 A1 WO 2024103666A1 CN 2023095559 W CN2023095559 W CN 2023095559W WO 2024103666 A1 WO2024103666 A1 WO 2024103666A1
Authority
WO
WIPO (PCT)
Prior art keywords
cache
core
way
core processor
queue
Prior art date
Application number
PCT/CN2023/095559
Other languages
English (en)
French (fr)
Inventor
陈刚
张余
黄凯
Original Assignee
中山大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中山大学 filed Critical 中山大学
Publication of WO2024103666A1 publication Critical patent/WO2024103666A1/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the technical field of multi-core processors, and in particular to a multi-core processor dynamic cache partition isolation system and a control method thereof.
  • multi-core processor system-on-chip (MPSoC) architectures are usually equipped with hierarchical cache subsystems.
  • This complex cache hierarchy makes the behavior of shared caches difficult to predict and analyze. For example, a task running on one core may evict useful L2 cache space, which may be in use by another task in another core.
  • inter-core cache interferences will lead to an increase in miss rates, resulting in corresponding performance degradation.
  • inter-core cache interference is difficult to analyze accurately, making it difficult to estimate the worst-case execution time of applications.
  • page coloring technology that is, a software cache partitioning method at the operating system level, which partitions the cache according to settings.
  • page coloring technology a software cache partitioning method at the operating system level, which partitions the cache according to settings.
  • the problem with page coloring technology is that the coloring time overhead is large. This time overhead prohibits frequent changes in page color on the one hand, and makes the color change of tasks whose execution time is less than the page change overhead uneconomical on the other hand, which in turn affects the performance of multi-core processor systems.
  • the present invention proposes a multi-core processor dynamic cache partition isolation system and a control method thereof, which avoids cache interference between cores and improves system performance.
  • a multi-core processor dynamic cache partition isolation system comprising:
  • a multi-core processor wherein the multi-core processor includes multiple cores, each of which is independent of each other and has a corresponding first-level cache;
  • a shared timer interrupt module the shared timer interrupt module is used to synchronize and trigger tasks on each of the cores;
  • a shared secondary cache wherein the shared secondary cache includes a cache way management unit, a cache control unit, a cache way switching unit, and a cache way pool, wherein the cache way pool includes a plurality of cache ways, and the cache way management unit is used to reconfigure the cache ways occupied by the cores according to the cache instructions sent by the cores, and to send corresponding cache control signals.
  • the cache way switching unit is used to dynamically connect each of the cores and the corresponding cache way according to the cache control signal
  • the cache control unit is used to control the access of each of the cores to the corresponding cache way according to the cache control signal.
  • the shared timer interrupt module includes a global timer and a decrementer corresponding to each of the cores.
  • the global timer is used to generate a trigger signal at a preset time interval, and the trigger signal causes each of the decrementers to decrement once in sequence.
  • each of the cores is connected to the cache way management unit, each of the cores is provided with a corresponding code, the cache instruction includes the code and an instruction type, the cache way management unit identifies the corresponding core according to the code, and determines the corresponding cache way configuration operation according to the instruction type.
  • the cache control unit includes a plurality of cache controllers, and the cache controllers correspond to the cores one by one.
  • the cache path is composed of memory blocks and is provided with a plurality of cache partitions, and each of the cache partitions can be occupied by a different core respectively.
  • the multi-core processor dynamic cache partition isolation system also includes a cache way replacement module, which is used to select an occupied cache way for cache replacement when the core needs to store data in the shared secondary cache and all the cache ways are occupied.
  • the cache way replacement module includes a memory and a selector, the memory is used to store a reference way queue, the reference way queue is a queue of cache ways to be replaced formed based on a first-in-first-out replacement strategy, the selector is used to select a corresponding cache way for cache replacement according to the reference way queue and an enable signal queue, the enable signal queue is generated by the cache way management unit, and the enable signal queue includes a plurality of enable signals corresponding one-to-one to the cache ways to be replaced.
  • a control method for a multi-core processor dynamic cache partition isolation system is implemented by the multi-core processor dynamic cache partition isolation system, comprising the following steps:
  • the cache control signal is received through a cache way switching unit, and each of the cores and the corresponding cache way is dynamically connected according to the cache control signal, and then the connection state is returned to the cache control unit;
  • the cache control unit receives the cache control signal and the connection status, and opens or interrupts the access of each core to the corresponding cache path according to the cache control signal and the connection status.
  • the multi-core processor dynamic cache partition isolation system further includes a cache way replacement module, the cache way replacement module includes a memory and a selector, and the control method further includes the following steps:
  • the cache way management unit selects a plurality of cache ways with earlier occupancy times as cache ways to be replaced, generates a reference way queue according to the cache ways to be replaced, and then stores the reference way queue in the memory;
  • the cache way management unit When the cache way management unit receives a cache instruction from the core, it generates a corresponding enable signal queue according to the cache instruction, and sends the enable signal queue to the selector, wherein the enable signal queue includes a plurality of enable signals corresponding to the cache ways to be replaced;
  • the selector selects a corresponding cache path for cache replacement according to the enable signal queue and the reference path queue.
  • the present invention provides a multi-core processor dynamic cache partition isolation system and a control method thereof, which dynamically partitions cache channels through a cache path management unit, a cache control unit, and a cache path switching unit, and provides a dynamically configurable shared secondary cache for a multi-core processor, so that the shared secondary cache can be efficiently used by each core, avoiding cache interference between cores, ensuring the correct operation of processor tasks to a certain extent, and improving system performance.
  • FIG1 is a schematic diagram of the structure of a multi-core processor dynamic cache partition isolation system provided by an embodiment of the present invention
  • FIG2 is a schematic diagram of the structure of a shared secondary cache provided by an embodiment of the present invention.
  • FIG3 is a schematic diagram of partitioning of cache channels provided by an embodiment of the present invention.
  • FIG4 is a flowchart of the steps of a control method of a multi-core processor dynamic cache partition isolation system provided by an embodiment of the present invention.
  • an embodiment of the present invention provides a multi-core processor dynamic cache partition isolation system, including:
  • Multi-core processors include multiple cores, each of which is independent of the others and has its own corresponding L1 cache.
  • Shared timer interrupt module which is used to synchronize and trigger tasks on each core
  • the shared secondary cache includes a cache way management unit, a cache control unit, a cache way switching unit and a cache way pool.
  • the cache way pool includes multiple cache ways.
  • the cache way management unit is used to reconfigure the cache ways occupied by each core according to the cache instructions sent by each core, and send down corresponding cache control signals.
  • the cache way switching unit is used to dynamically connect each core and the corresponding cache way according to the cache control signal.
  • the cache control unit is used to control the access of each core to the corresponding cache way according to the cache control signal.
  • different cores of a multi-core processor have exclusive first-level cache and are independent of each other; a shared timer interrupt module is used to synchronize and trigger tasks on different processors; a shared second-level cache is shared by multiple cores and is allocated and used by multiple cores in a configurable dynamic cache partitioning manner.
  • the shared timer interrupt module includes a global timer and a decrementer corresponding to each core one by one, the global timer is used to generate a trigger signal at a preset time interval, and the trigger signal causes each decrementer to decrement once in turn.
  • the shared timer interrupt module provides a dedicated decrementer for each core, which is decremented based on a shared global timer.
  • the shared global timer generates a trigger signal at a fixed time interval, so that each decrementer is decremented once.
  • each core is connected to a cache way management unit, each core is provided with a corresponding code, a cache instruction includes a code and an instruction type, the cache way management unit identifies the corresponding core according to the code, and determines the corresponding cache way configuration operation according to the instruction type.
  • the cache way management unit is used to centrally manage cache ways. Through the cache way management unit, each core can send commands to reconfigure the cache ways it occupies.
  • the cache way management unit is connected to N cores, can identify the encoding of different cores, and operate the corresponding cache ways in the cache way pool according to different instruction types. Based on this unified scheduling scheme, the core no longer needs to query the status of the cache way before allocating memory, and also avoids interference between the cores of the multi-core processor.
  • the cache control unit includes a plurality of cache controllers, and the cache controllers correspond to the cores one by one.
  • the cache control unit includes a plurality of cache controllers, which are arranged in one-to-one correspondence with the plurality of cores to ensure that each core has access to the shared secondary cache.
  • the cache path is composed of memory blocks and has multiple cache partitions. Each cache partition can be occupied by different cores.
  • FIG. 3 a partition diagram of a cache channel provided by an embodiment of the present invention, different fillings in the figure indicate that the memory of the corresponding cache partition is occupied by different cores.
  • the dynamic partition cache management of the embodiment of the present invention is implemented based on this cache partitioning method.
  • the multi-core processor dynamic cache partition isolation system also includes a cache way replacement module, which is used to select an occupied cache way for cache replacement when the core needs to store data in the shared secondary cache and all cache ways are occupied.
  • an occupied cache way needs to be selected for replacement.
  • the embodiment of the present invention adopts a first-in-first-out replacement strategy, that is, the cache way that was occupied the earliest is replaced first.
  • the embodiment of the present invention deploys a cache way replacement module.
  • the cache way replacement module includes a memory and a selector
  • the memory is used to store a reference way queue
  • the reference way queue is a queue of cache ways to be replaced formed based on a first-in-first-out replacement strategy
  • the selector is used to select a corresponding cache way for cache replacement according to the reference way queue and an enable signal queue
  • the enable signal queue is generated by a cache way management unit
  • the enable signal queue includes a plurality of enable signals corresponding one-to-one to the cache ways to be replaced.
  • the embodiment of the present invention stores the cache paths to be replaced in the form of a queue in a dual-port memory based on a first-in-first-out replacement strategy to form a reference path queue.
  • a cache path When a cache path is released, the information in the reference path queue should be cleared to the initial reference path within one clock.
  • the embodiment of the present invention adopts an enable signal control method to construct a 1-bit enable signal for each reference path in the reference path queue and store it in the form of a queue to control the output of the selector, thereby achieving the purpose of resetting the reference path queue in one clock cycle.
  • the cache channel is dynamically partitioned and managed through the cache path management unit, the cache control unit and the cache path switching unit, and a dynamically configurable shared secondary cache is provided for the multi-core processor, so that the shared secondary cache can be efficiently used by each core, avoiding cache interference between cores, ensuring the correct operation of the processor task to a certain extent, and improving the system performance.
  • an embodiment of the present invention provides a control method for a multi-core processor dynamic cache partition isolation system, which is implemented by the multi-core processor dynamic cache partition isolation system, and includes the following steps:
  • the multi-core processor dynamic cache partition isolation system further includes a cache way replacement module, the cache way replacement module includes a memory and a selector, and the control method further includes the following steps:
  • a cache way management unit selects multiple cache ways with earlier occupancy times as cache ways to be replaced, generates a reference way queue according to the cache ways to be replaced, and then stores the reference way queue in a memory;
  • the cache way management unit when the cache way management unit receives the cache instruction of the core, it generates a corresponding enable signal queue according to the cache instruction, and sends the enable signal queue to the selector, where the enable signal queue includes a plurality of enable signals corresponding one to one to the cache ways to be replaced;
  • embodiments of the present invention may be implemented or enforced by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory.
  • the above methods may be implemented in a computer program using standard programming techniques, including a non-transitory computer-readable storage medium configured with a computer program, wherein the storage medium so configured causes the computer to operate in a specific and predefined manner, according to the methods and drawings described in the specific embodiments.
  • Each program may be implemented in a high-level procedural or object-oriented programming language to communicate with a computer system. However, if desired, the program may be implemented in an assembly or machine language. In any case, the language may be a compiled or interpreted language. In addition, the program may be run on a programmed dedicated integrated circuit for this purpose.
  • the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context.
  • the processes described herein may be performed under the control of one or more computer systems configured with executable instructions, and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed collectively on one or more processors, by hardware, or a combination thereof.
  • the computer programs described above include a plurality of instructions that may be executed by one or more processors.
  • the above method can be implemented in any type of computing platform operably connected to a suitable computer, including but not limited to a personal computer, a minicomputer, a mainframe, a workstation, a network or distributed computing environment, a stand-alone or integrated computer, or a computer system. computer platform, or communicate with charged particle tools or other imaging devices, etc.
  • Various aspects of the present invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and/or write storage medium, RAM, ROM, etc., so that it can be read by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the process described herein.
  • the machine-readable code, or parts thereof can be transmitted via a wired or wireless network.
  • the invention described herein includes these and other different types of non-transitory computer-readable storage media.
  • the present invention also includes the computer itself.
  • the computer program can be applied to input data to perform the functions described herein, thereby converting the input data to generate output data stored in a non-volatile memory.
  • the output information can also be applied to one or more output devices such as a display.
  • the converted data represents physical and tangible objects, including specific visual depictions of physical and tangible objects produced on the display.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

一种多核处理器动态缓存分区隔离系统及其控制方法，系统包括多核处理器、共享定时器中断模块以及共享二级缓存，共享二级缓存包括缓存通路管理单元、缓存控制单元、缓存通路切换单元以及缓存通路池，通过缓存通路管理单元、缓存控制单元以及缓存通路切换单元对缓存通道进行动态分区管理，为多核处理器提供动态可配置的共享二级缓存，使得共享二级缓存可以高效地供各个核心使用，避免了核间缓存干扰，一定程度上保证了处理器任务的正确运行，提高了系统性能。

Description

一种动态划分缓存模块设计方法 技术领域
本发明涉及多核处理器技术领域，尤其涉及一种多核处理器动态缓存分区隔离系统及其控制方法。
背景技术
随着摩尔定律的终结，计算机处理器单核瓶颈的性能提升受到了限制，当前的处理器设计正在越来越多地转向多核平台。为了减轻片外内存的高延迟，多核处理器片上系统(MPSoC)架构通常配备了分层的高速缓存子系统。这种复杂缓存层次结构会导致共享缓存的行为难以被预测和分析。例如，在一个核心上运行的任务可能会驱逐有用的L2缓存空间，而该空间可能正在被另一个核心中的另一个任务使用。这些核间缓存干扰将导致错过率的增加，从而导致相应的性能下降。同时，核间缓存干扰很难准确地分析，因此导致难以估计应用程序的最坏情况执行时间。当前，在实时系统的多核缓存管理上的大多使用页面着色技术，即操作系统级的软件缓存分区方法，根据设置对缓存进行分区。然而，页面着色技术的问题在于着色时间开销很大，这种时间开销一方面禁止了页面颜色的频繁更改，另一方面则使执行时间小于页面更改开销的任务的颜色更改不划算，进而影响了多核处理器系统性能。
发明内容
为了解决上述技术问题，本发明的目的在于：本发明提出一种多核处理器动态缓存分区隔离系统及其控制方法，避免了核间缓存干扰，提高了系统性能。
本发明所采用的第一技术方案是：
一种多核处理器动态缓存分区隔离系统，包括：
多核处理器，所述多核处理器包括多个核心，各所述核心相互独立且均享有相应的一级缓存；
共享定时器中断模块，所述共享定时器中断模块用于同步和触发各所述核心上的任务；
共享二级缓存，所述共享二级缓存包括缓存通路管理单元、缓存控制单元、缓存通路切换单元以及缓存通路池，所述缓存通路池包括多个缓存通路，所述缓存通路管理单元用于根据各所述核心发送的缓存指令重新配置其占用的缓存通路，并下发相应的缓存控制信号，所 述缓存通路切换单元用于根据所述缓存控制信号对各所述核心和相应的缓存通路进行动态连接，所述缓存控制单元用于根据所述缓存控制信号控制各所述核心对相应的缓存通路的访问。
进一步，所述共享定时器中断模块包括全局计时器以及与各所述核心一一对应的递减器，所述全局计时器用于以预设的时间间隔产生触发信号，所述触发信号使得各所述递减器依次递减一次。
进一步，各所述核心均与所述缓存通路管理单元连接，各所述核心均设有相应的编码，所述缓存指令包括所述编码和指令类型，所述缓存通路管理单元根据所述编码识别对应的核心，并根据所述指令类型确定对应的缓存通路配置操作。
进一步，所述缓存控制单元包括多个缓存控制器，所述缓存控制器与所述核心一一对应。
进一步，所述缓存通路由内存块组成，设有多个缓存分区，各所述缓存分区可分别被不同的核心占用。
进一步，所述多核处理器动态缓存分区隔离系统还包括缓存通路替换模块，所述缓存通路替换模块用于当所述核心需要将数据存储在所述共享二级缓存且各所述缓存通路均被占用时，选择一个被占用的缓存通路进行缓存替换。
进一步，所述缓存通路替换模块包括存储器和选择器，所述存储器用于存储参考通路队列，所述参考通路队列为基于先进先出的替换策略形成的待替换的缓存通路的队列，所述选择器用于根据所述参考通路队列和使能信号队列选择相应的缓存通路进行缓存替换，所述使能信号队列由所述缓存通路管理单元生成，所述使能信号队列包括多个与待替换的缓存通路一一对应的使能信号。
本发明所采用的第二技术方案是：
一种多核处理器动态缓存分区隔离系统的控制方法，用于通过上述多核处理器动态缓存分区隔离系统实现，包括以下步骤：
通过缓存通路管理单元接收各核心发送的缓存指令，并根据所述缓存指令对所述核心占用的缓存通路进行重新配置，进而根据重新配置的结果生成相应的缓存控制信号；
通过缓存通路切换单元接收所述缓存控制信号，并根据所述缓存控制信号对各所述核心和相应的缓存通路进行动态连接，进而返回连接状态至缓存控制单元；
通过所述缓存控制单元接收所述缓存控制信号和所述连接状态，并根据所述缓存控制信号和所述连接状态开启或中断各所述核心对相应的缓存通路的访问。
进一步，所述多核处理器动态缓存分区隔离系统还包括缓存通路替换模块，所述缓存通路替换模块包括存储器和选择器，所述控制方法还包括以下步骤：
当所述缓存通路均被占用，通过所述缓存通路管理单元选取占用时间靠前的多个缓存通路作为待替换的缓存通路，并根据待替换的缓存通路生成参考通路队列，进而将所述参考通路队列存储在所述存储器中；
当所述缓存通路管理单元接收到所述核心的缓存指令，根据所述缓存指令生成相应的使能信号队列，并将所述使能信号队列下发至所述选择器，所述使能信号队列包括多个与待替换的缓存通路一一对应的使能信号；
通过所述选择器根据所述使能信号队列和所述参考通路队列选择相应的缓存通路进行缓存替换。
本发明的有益效果是：本发明提供了一种多核处理器动态缓存分区隔离系统及其控制方法，通过缓存通路管理单元、缓存控制单元以及缓存通路切换单元对缓存通道进行动态分区管理，为多核处理器提供动态可配置的共享二级缓存，使得共享二级缓存可以高效地供各个核心使用，避免了核间缓存干扰，一定程度上保证了处理器任务的正确运行，提高了系统性能。
附图说明
图1为本发明实施例提供的一种多核处理器动态缓存分区隔离系统的结构示意图；
图2为本发明实施例提供的共享二级缓存的结构示意图；
图3为本发明实施例提供的缓存通道的分区示意图；
图4为本发明实施例提供的一种多核处理器动态缓存分区隔离系统的控制方法的步骤流程图。
具体实施方式
下面结合附图和具体实施例对本发明做进一步的详细说明。对于以下实施例中的步骤编号，其仅为了便于阐述说明而设置，对步骤之间的顺序不做任何限定，实施例中的各步骤的执行顺序均可根据本领域技术人员的理解来进行适应性调整。
在本发明的描述中，多个的含义是两个以上，如果有描述到第一、第二只是用于区分技术特征为目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量或者隐含指明所指示的技术特征的先后关系。此外，除非另有定义，本文所使用的所有的技术和科学术语与本技术领域的技术人员通常理解的含义相同。本文说明书中所使用的术语只是为了描述具体的实施例，而不是为了限制本发明。
参照图1和2，本发明实施例提供了一种多核处理器动态缓存分区隔离系统，包括：
多核处理器，多核处理器包括多个核心，各核心相互独立且均享有相应的一级缓存；
共享定时器中断模块，共享定时器中断模块用于同步和触发各核心上的任务；
共享二级缓存，共享二级缓存包括缓存通路管理单元、缓存控制单元、缓存通路切换单元以及缓存通路池，缓存通路池包括多个缓存通路，缓存通路管理单元用于根据各核心发送的缓存指令重新配置其占用的缓存通路，并下发相应的缓存控制信号，缓存通路切换单元用于根据缓存控制信号对各核心和相应的缓存通路进行动态连接，缓存控制单元用于根据缓存控制信号控制各核心对相应的缓存通路的访问。
具体地，本发明实施例中，多核处理器的不同核心独享一级缓存，并且相互独立；共享定时器中断模块用于同步和触发不同处理器上的任务；共享二级缓存被多个核心共享，并按照可配置动态缓存分区的方式被多个核心分配和使用。
进一步作为可选的实施方式，共享定时器中断模块包括全局计时器以及与各核心一一对应的递减器，全局计时器用于以预设的时间间隔产生触发信号，触发信号使得各递减器依次递减一次。
本发明实施例中，共享定时器中断模块为每个核心提供了一个专用的递减器，基于共享的全局计时器进行递减，共享的全局定时器在固定时间间隔内产生触发信号，使得每个递减器递减一次。
参照图2，进一步作为可选的实施方式，各核心均与缓存通路管理单元连接，各核心均设有相应的编码，缓存指令包括编码和指令类型，缓存通路管理单元根据编码识别对应的核心，并根据指令类型确定对应的缓存通路配置操作。
具体地，缓存通路管理单元用于集中管理缓存通路。通过缓存通路管理单元，每个核心可以发送命令来重新配置其占用的缓存通路。缓存通路管理单元连接在N个核心上，能够识别不同核心的编码，并根据不同的指令类型在缓存通路池中操作相应的缓存通路。基于这种统一调度方案，在分配内存之前核心不用再查询缓存通路的状态，同时也避免了多核处理器各个核心之间的干扰。
进一步作为可选的实施方式，缓存控制单元包括多个缓存控制器，缓存控制器与核心一一对应。
具体地，缓存控制单元中包含多个缓存控制器，与多个核心一一对应设置，以确保各个核心对共享二级缓存的访问。
参照图3，进一步作为可选的实施方式，缓存通路由内存块组成，设有多个缓存分区， 各缓存分区可分别被不同的核心占用。
具体地，如图3所示为本发明实施例提供的缓存通道的分区示意图，图中不同的填充表示对应缓存分区的内存正在被不同核心所占用。本发明实施例的动态分区缓存管理是基于此缓存分区的方式实现的。
参照图1，进一步作为可选的实施方式，多核处理器动态缓存分区隔离系统还包括缓存通路替换模块，缓存通路替换模块用于当核心需要将数据存储在共享二级缓存且各缓存通路均被占用时，选择一个被占用的缓存通路进行缓存替换。
具体地，当必须将新数据存储在共享二级缓存中而所有缓存通路都被占用时，需要选择一个已被占有的缓存通路进行替换，本发明实施例采用先进先出的替换策略，即优先替换最早开始占用的缓存通道。为了保持不连续的缓存通路分区占用模式，本发明实施例部署了缓存通路替换模块。
参照图1，进一步作为可选的实施方式，缓存通路替换模块包括存储器和选择器，存储器用于存储参考通路队列，参考通路队列为基于先进先出的替换策略形成的待替换的缓存通路的队列，选择器用于根据参考通路队列和使能信号队列选择相应的缓存通路进行缓存替换，使能信号队列由缓存通路管理单元生成，使能信号队列包括多个与待替换的缓存通路一一对应的使能信号。
具体地，本发明实施例基于先进先出的替换策略，将待替换的缓存通路以队列的形式存储在双端口存储器中，形成参考通路队列。当有缓存通路被释放的时候，参考通路队列中的信息应该在一个时钟内清除为初始参考通路。为了达到这个目的，本发明实施例采用使能信号的控制方式，为参考通路队列中的每个参考通路构建一个1位的使能信号并以队列的形式存储，用以控制选择器的输出，从而达到在一个时钟周期复位参考通路队列的目的。
以上是对本发明实施例的系统结构和工作原理进行了说明。可以理解的是，通过缓存通路管理单元、缓存控制单元以及缓存通路切换单元对缓存通道进行动态分区管理，为多核处理器提供动态可配置的共享二级缓存，使得共享二级缓存可以高效地供各个核心使用，避免了核间缓存干扰，一定程度上保证了处理器任务的正确运行，提高了系统性能。
下面结合控制方法对本发明实施例作进一步说明。
参照图4，本发明实施例提供了一种多核处理器动态缓存分区隔离系统的控制方法，用于通过上述多核处理器动态缓存分区隔离系统实现，包括以下步骤：
S101、通过缓存通路管理单元接收各核心发送的缓存指令，并根据缓存指令对核心占用的缓存通路进行重新配置，进而根据重新配置的结果生成相应的缓存控制信号；
S102、通过缓存通路切换单元接收缓存控制信号，并根据缓存控制信号对各核心和相应的缓存通路进行动态连接，进而返回连接状态至缓存控制单元；
S103、通过缓存控制单元接收缓存控制信号和连接状态，并根据缓存控制信号和连接状态开启或中断各核心对相应的缓存通路的访问。
进一步作为可选的实施方式，多核处理器动态缓存分区隔离系统还包括缓存通路替换模块，缓存通路替换模块包括存储器和选择器，控制方法还包括以下步骤：
S104、当缓存通路均被占用，通过缓存通路管理单元选取占用时间靠前的多个缓存通路作为待替换的缓存通路，并根据待替换的缓存通路生成参考通路队列，进而将参考通路队列存储在存储器中；
S105、当缓存通路管理单元接收到核心的缓存指令，根据缓存指令生成相应的使能信号队列，并将使能信号队列下发至选择器，使能信号队列包括多个与待替换的缓存通路一一对应的使能信号；
S106、通过选择器根据使能信号队列和参考通路队列选择相应的缓存通路进行缓存替换。
可以理解的是，上述系统实施例中的内容均适用于本方法实施例中，本方法实施例所具体实现的功能与上述系统实施例相同，并且达到的有益效果与上述系统实施例所达到的有益效果也相同。
应当认识到，本发明的实施例可以由计算机硬件、硬件和软件的组合、或者通过存储在非暂时性计算机可读存储器中的计算机指令来实现或实施。上述方法可以使用标准编程技术—包括配置有计算机程序的非暂时性计算机可读存储介质在计算机程序中实现，其中如此配置的存储介质使得计算机以特定和预定义的方式操作——根据在具体实施例中描述的方法和附图。每个程序可以以高级过程或面向对象的编程语言来实现以与计算机系统通信。然而，若需要，该程序可以以汇编或机器语言实现。在任何情况下，该语言可以是编译或解释的语言。此外，为此目的该程序能够在编程的专用集成电路上运行。
此外，可按任何合适的顺序来执行本文描述的过程的操作，除非本文另外指示或以其他方式明显地与上下文矛盾。本文描述的过程(或变型和/或其组合)可在配置有可执行指令的一个或多个计算机系统的控制下执行，并且可作为共同地在一个或多个处理器上执行的代码(例如，可执行指令、一个或多个计算机程序或一个或多个应用)、由硬件或其组合来实现。上述计算机程序包括可由一个或多个处理器执行的多个指令。
进一步，上述方法可以在可操作地连接至合适的任何类型的计算平台中实现，包括但不限于个人电脑、迷你计算机、主框架、工作站、网络或分布式计算环境、单独的或集成的计 算机平台、或者与带电粒子工具或其它成像装置通信等等。本发明的各方面可以以存储在非暂时性存储介质或设备上的机器可读代码来实现，无论是可移动的还是集成至计算平台，如硬盘、光学读取和/或写入存储介质、RAM、ROM等，使得其可由可编程计算机读取，当存储介质或设备由计算机读取时可用于配置和操作计算机以执行在此所描述的过程。此外，机器可读代码，或其部分可以通过有线或无线网络传输。当此类媒体包括结合微处理器或其他数据处理器实现上文所描述步骤的指令或程序时，本文所描述的发明包括这些和其他不同类型的非暂时性计算机可读存储介质。当根据本发明所描述的方法和技术编程时，本发明还包括计算机本身。
计算机程序能够应用于输入数据以执行本文所描述的功能，从而转换输入数据以生成存储至非易失性存储器的输出数据。输出信息还可以应用于一个或多个输出设备如显示器。在本发明优选的实施例中，转换的数据表示物理和有形的对象，包括显示器上产生的物理和有形对象的特定视觉描绘。
以上所述，只是本发明的较佳实施例而已，本发明并不局限于上述实施方式，只要其以相同的手段达到本发明的技术效果，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明保护的范围之内。在本发明的保护范围内其技术方案和/或实施方式可以有各种不同的修改和变化。

Claims (9)

  1. 一种多核处理器动态缓存分区隔离系统，其特征在于，包括：
    多核处理器，所述多核处理器包括多个核心，各所述核心相互独立且均享有相应的一级缓存；
    共享定时器中断模块，所述共享定时器中断模块用于同步和触发各所述核心上的任务；
    共享二级缓存，所述共享二级缓存包括缓存通路管理单元、缓存控制单元、缓存通路切换单元以及缓存通路池，所述缓存通路池包括多个缓存通路，所述缓存通路管理单元用于根据各所述核心发送的缓存指令重新配置其占用的缓存通路，并下发相应的缓存控制信号，所述缓存通路切换单元用于根据所述缓存控制信号对各所述核心和相应的缓存通路进行动态连接，所述缓存控制单元用于根据所述缓存控制信号控制各所述核心对相应的缓存通路的访问。
  2. 根据权利要求1所述的一种多核处理器动态缓存分区隔离系统，其特征在于：所述共享定时器中断模块包括全局计时器以及与各所述核心一一对应的递减器，所述全局计时器用于以预设的时间间隔产生触发信号，所述触发信号使得各所述递减器依次递减一次。
  3. 根据权利要求1所述的一种多核处理器动态缓存分区隔离系统，其特征在于：各所述核心均与所述缓存通路管理单元连接，各所述核心均设有相应的编码，所述缓存指令包括所述编码和指令类型，所述缓存通路管理单元根据所述编码识别对应的核心，并根据所述指令类型确定对应的缓存通路配置操作。
  4. 根据权利要求1所述的一种多核处理器动态缓存分区隔离系统，其特征在于：所述缓存控制单元包括多个缓存控制器，所述缓存控制器与所述核心一一对应。
  5. 根据权利要求1所述的一种多核处理器动态缓存分区隔离系统，其特征在于：所述缓存通路由内存块组成，设有多个缓存分区，各所述缓存分区可分别被不同的核心占用。
  6. 根据权利要求1至5中任一项所述的一种多核处理器动态缓存分区隔离系统，其特征在于：所述多核处理器动态缓存分区隔离系统还包括缓存通路替换模块，所述缓存通路替换模块用于当所述核心需要将数据存储在所述共享二级缓存且各所述缓存通路均被占用时，选择一个被占用的缓存通路进行缓存替换。
  7. 根据权利要求6所述的一种多核处理器动态缓存分区隔离系统，其特征在于：所述缓存通路替换模块包括存储器和选择器，所述存储器用于存储参考通路队列，所述参考通路队列为基于先进先出的替换策略形成的待替换的缓存通路的队列，所述选择器用于根据所述参考通路队列和使能信号队列选择相应的缓存通路进行缓存替换，所述使能信号队列由所述缓存通路管理单元生成，所述使能信号队列包括多个与待替换的缓存通路一一对应的使能信号。
  8. 一种多核处理器动态缓存分区隔离系统的控制方法，用于通过如权利要求1至7中任一项所述的多核处理器动态缓存分区隔离系统实现，其特征在于，包括以下步骤：
    通过缓存通路管理单元接收各核心发送的缓存指令，并根据所述缓存指令对所述核心占用的缓存通路进行重新配置，进而根据重新配置的结果生成相应的缓存控制信号；
    通过缓存通路切换单元接收所述缓存控制信号，并根据所述缓存控制信号对各所述核心和相应的缓存通路进行动态连接，进而返回连接状态至缓存控制单元；
    通过所述缓存控制单元接收所述缓存控制信号和所述连接状态，并根据所述缓存控制信号和所述连接状态开启或中断各所述核心对相应的缓存通路的访问。
  9. 根据权利要求8所述的一种多核处理器动态缓存分区隔离系统的控制方法，其特征在于，所述多核处理器动态缓存分区隔离系统还包括缓存通路替换模块，所述缓存通路替换模块包括存储器和选择器，所述控制方法还包括以下步骤：
    当所述缓存通路均被占用，通过所述缓存通路管理单元选取占用时间靠前的多个缓存通路作为待替换的缓存通路，并根据待替换的缓存通路生成参考通路队列，进而将所述参考通路队列存储在所述存储器中；
    当所述缓存通路管理单元接收到所述核心的缓存指令，根据所述缓存指令生成相应的使能信号队列，并将所述使能信号队列下发至所述选择器，所述使能信号队列包括多个与待替换的缓存通路一一对应的使能信号；
    通过所述选择器根据所述使能信号队列和所述参考通路队列选择相应的缓存通路进行缓存替换。
PCT/CN2023/095559 2022-11-16 2023-05-22 一种多核处理器动态缓存分区隔离系统及其控制方法 WO2024103666A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211438477.9 2022-11-16
CN202211438477.9A CN115827547A (zh) 2022-11-16 2022-11-16 一种多核处理器动态缓存分区隔离系统及其控制方法

Publications (1)

Publication Number Publication Date
WO2024103666A1 true WO2024103666A1 (zh) 2024-05-23

Family

ID=85528672

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/095559 WO2024103666A1 (zh) 2022-11-16 2023-05-22 一种多核处理器动态缓存分区隔离系统及其控制方法

Country Status (2)

Country Link
CN (1) CN115827547A (zh)
WO (1) WO2024103666A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115827547A (zh) * 2022-11-16 2023-03-21 中山大学 一种多核处理器动态缓存分区隔离系统及其控制方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040059875A1 (en) * 2002-09-20 2004-03-25 Vivek Garg Cache sharing for a chip multiprocessor or multiprocessing system
CN101571843A (zh) * 2008-04-29 2009-11-04 国际商业机器公司 在多核处理器中动态共享高速缓存的方法、设备和系统
US20140040556A1 (en) * 2012-08-05 2014-02-06 William L. Walker Dynamic Multithreaded Cache Allocation
CN105426319A (zh) * 2014-08-19 2016-03-23 超威半导体产品（中国）有限公司 动态缓存分区设备和方法
CN114661629A (zh) * 2020-12-22 2022-06-24 英特尔公司 用于具有大代码占用的工作负载的动态共享高速缓存分区
CN115098431A (zh) * 2022-05-27 2022-09-23 北京奕斯伟计算技术股份有限公司 处理器、共享高速缓存的分配方法及其装置
CN115827547A (zh) * 2022-11-16 2023-03-21 中山大学 一种多核处理器动态缓存分区隔离系统及其控制方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040059875A1 (en) * 2002-09-20 2004-03-25 Vivek Garg Cache sharing for a chip multiprocessor or multiprocessing system
CN101571843A (zh) * 2008-04-29 2009-11-04 国际商业机器公司 在多核处理器中动态共享高速缓存的方法、设备和系统
US20140040556A1 (en) * 2012-08-05 2014-02-06 William L. Walker Dynamic Multithreaded Cache Allocation
CN105426319A (zh) * 2014-08-19 2016-03-23 超威半导体产品（中国）有限公司 动态缓存分区设备和方法
CN114661629A (zh) * 2020-12-22 2022-06-24 英特尔公司 用于具有大代码占用的工作负载的动态共享高速缓存分区
CN115098431A (zh) * 2022-05-27 2022-09-23 北京奕斯伟计算技术股份有限公司 处理器、共享高速缓存的分配方法及其装置
CN115827547A (zh) * 2022-11-16 2023-03-21 中山大学 一种多核处理器动态缓存分区隔离系统及其控制方法

Also Published As

Publication number Publication date
CN115827547A (zh) 2023-03-21

Similar Documents

Publication Publication Date Title
CN112088355B (zh) 多线程自调度处理器在本地或远程计算元件上的线程创建
CN112088358B (zh) 具有线程优先级管理的多线程自调度处理器
CN112088357B (zh) 用户模式多线程自调度处理器中的系统调用管理
CN112106027B (zh) 多线程自调度处理器中的存储器请求大小管理
CN112088356B (zh) 自调度处理器中使用工作描述符包的线程开始
CN112088359B (zh) 多线程自调度处理器
CN112119376B (zh) 具有自调度处理器和混合线程组构的系统
KR102223840B1 (ko) 컴퓨터 이미징 파이프라인
JP5413001B2 (ja) キャッシュメモリ
JP6294586B2 (ja) 命令スレッドを組み合わせた実行の管理システムおよび管理方法
CN1327370C (zh) 资源管理装置
US8935491B2 (en) Memory architecture for dynamically allocated manycore processor
CN109997112B (zh) 数据处理
CN112106030A (zh) 具有多线程自调度处理器的系统中的线程状态监测
CN112106026A (zh) 多线程自调度处理器为管理网络拥塞而进行的加载存取大小调整
US20170083474A1 (en) Distributed memory controller
JP2009519513A (ja) 専用スレッド管理を用いたマルチコアの演算処理方法及び装置
WO2024103666A1 (zh) 一种多核处理器动态缓存分区隔离系统及其控制方法
CN1981280A (zh) 用于经由资源分配和限制的异构芯片多处理器的装置和方法
CA2463748A1 (en) Method and apparatus for dispatching tasks in a non-uniform memory access (numa) computer system
KR20170111462A (ko) 다중 코어 프로세서 및 다중 코어 프로세서를 제어하는 방법
JP2018512662A (ja) 複数の独立マイクロコントローラを伴うマイクロコントローラデバイス
WO2011161782A1 (ja) マルチコアシステムおよび外部入出力バス制御方法
CN113849296A (zh) 用于闭环动态资源分配控制框架的装置和方法
CN106250348A (zh) 一种基于gpu访存特性的异构多核架构缓存管理方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23890110

Country of ref document: EP

Kind code of ref document: A1