WO2024103587A1 - Semiconductor structure and method for manufacturing same - Google Patents

Abstract

Disclosed are a semiconductor structure and a method for manufacturing same. The semiconductor structure comprises: a substrate; and a plurality of lower electrode layers arranged at intervals in a first direction on the substrate; in a second direction, the lower electrode layers comprise a first part, a second part, a third part and a fourth part which are sequentially stacked, the first direction being parallel to the plane that the substrate occupies, and the second direction being the direction where the lower electrode layers face the substrate; and in the first direction, the minimum width of the first part is greater than the maximum width of the third part, the minimum width of the third part is greater than the maximum width of the second part, and the minimum width of the third part is greater than the maximum width of the fourth part.

Description

Semiconductor structure and method for manufacturing the same

cross reference

This application claims priority to the Chinese patent application entitled “Semiconductor Structure and Manufacturing Method Thereof” and application number 202211441587.0, filed on November 17, 2022, which is incorporated herein by reference in its entirety.

Technical Field

The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same.

Background technique

With the continuous development of semiconductor structures, their key dimensions are constantly decreasing. However, due to the limitations of photolithography machines, there is a limit to the reduction of their key dimensions. Therefore, how to make chips with higher storage density on a wafer is the research direction of many scientific researchers and semiconductor practitioners. At present, with the increasing demand for capacitor structures with large capacitance, it is difficult to control the dimensional accuracy of the capacitor structure while increasing the integration density of the capacitor structure, making it difficult to achieve a balance between the integration density of the capacitor structure and the dimensional accuracy of the capacitor structure.

Summary of the invention

The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial for increasing the spacing between adjacent lower electrode layers while ensuring a high integration density of the lower electrode layers.

According to some embodiments of the present disclosure, on one hand, the embodiments of the present disclosure provide a semiconductor structure, comprising: a substrate; a plurality of lower electrode layers, wherein the plurality of lower electrode layers are arranged on the substrate at intervals along a first direction, and in a second direction, the lower electrode layer comprises a first part, a second part, a third part and a fourth part stacked in sequence; wherein the first direction is parallel to the plane where the substrate is located, and the second direction is the direction in which the lower electrode layer points to the substrate; along the first direction, the minimum value of the width of the first part is greater than the maximum value of the width of the third part, the minimum value of the width of the third part is greater than the maximum value of the width of the second part, and the minimum value of the width of the third part is greater than the maximum value of the width of the fourth part.

In some embodiments, along the second direction, side walls of the second portion and the fourth portion are perpendicular to a plane where the substrate is located.

In some embodiments, along the first direction, a ratio of a maximum value of the width of the third portion to a minimum value of the width of the first portion ranges from 0.9 to 1.0.

In some embodiments, along the first direction, a ratio of a minimum width of the third portion to a maximum width of the second portion ranges from 1.0 to 1.05.

In some embodiments, along the first direction, a ratio of a minimum width of the third portion to a maximum width of the fourth portion ranges from 1.0 to 1.1.

In some embodiments, along the second direction, the semiconductor structure further includes: a first supporting layer, which is in contact and connected with a portion of the side wall of each of the first parts extending along the second direction; a second supporting layer, which is in contact and connected with a portion of the side wall of each of the third parts extending along the second direction; a dielectric layer, which at least covers the side walls of the second part and the fourth part extending along the second direction; and an upper electrode layer, which at least covers the surface of the dielectric layer.

In some embodiments, the base includes: a substrate and a plurality of mutually spaced contact layers located in the substrate, the contact layers being in one-to-one contact connection with the lower electrode layer; the lower electrode layer includes: a fifth part located between the fourth part and the contact layer; the semiconductor structure also includes: a third supporting layer located above the substrate and in contact connection with the side wall of the fifth part extending along the second direction.

In some embodiments, along the second direction, the height of the first portion is greater than or equal to the height of the third portion, the height of the second portion is greater than the height of the first portion, and the height of the fourth portion is greater than the height of the first portion.

In some embodiments, along the second direction, the width of the first portion in the first direction gradually decreases, and the width of the third portion in the first direction gradually decreases.

In some embodiments, the second portion and the fourth portion are inclined in a direction away from the second direction.

According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a plurality of initial lower electrode layers on the substrate, wherein the plurality of initial lower electrode layers are arranged at intervals along a first direction, and along a second direction, the width of the initial lower electrode layer in the first direction gradually decreases, and the initial lower electrode layer comprises a first part, an initial second part, a third part and an initial fourth part stacked in sequence; wherein the first direction is parallel to the plane where the substrate is located, and the second direction is the direction in which the lower electrode layer points to the substrate; etching the initial second part to form a second part, and along the first direction, the maximum value of the width of the second part is less than the minimum value of the width of the third part; etching the initial fourth part to form a fourth part, and along the first direction, the maximum value of the width of the fourth part is less than the minimum value of the width of the third part; the first part, the second part, the third part and the fourth part together form a lower electrode layer.

In some embodiments, the step of forming the initial lower electrode layer includes: forming a stacked second dielectric film, a second support film, a first dielectric film and a first support film on the substrate, wherein the second dielectric film, the second support film, the first dielectric film and the first support film each have a plurality of contact holes, and along the second direction, the opening size of the contact holes gradually decreases; and forming the initial lower electrode layer that fills the contact holes.

In some embodiments, the step of forming the second part includes: etching the first supporting film to form a first supporting layer, the first supporting layer having a first opening exposing the first dielectric film; removing the first dielectric film through the first opening to expose the side wall of the initial second part; etching the exposed side wall of the initial second part to form the second part.

In some embodiments, the step of forming the fourth portion includes: etching the second support film to form A second supporting layer, wherein the second supporting layer has a second opening exposing the second dielectric film; the second dielectric film is removed through the second opening to expose the side wall of the initial fourth portion; and the exposed side wall of the initial fourth portion is etched to form the fourth portion.

In some embodiments, a first etching process is used to remove the first dielectric film and the second dielectric film, and a second etching process is used to etch the initial second portion and the initial fourth portion, and the first etching process is different from the second etching process.

In some embodiments, the removing the first dielectric film and the second dielectric film by using a first etching process includes: wet etching the first dielectric film and the second dielectric film by using an etching solution containing hydrofluoric acid and ammonium fluoride.

In some embodiments, etching the initial second portion and the initial fourth portion using a second etching process includes: wet etching the initial second portion and the initial fourth portion using a mixture of ammonia water, hydrogen peroxide and water.

In some embodiments, the height of the initial second part in the second direction is a first height, and adjacent initial second parts have a first spacing in the first direction; after forming the initial lower electrode layer and before etching the initial second part, it also includes: detecting the size of the first spacing and/or detecting the size of the first height; determining the time to etch the initial second part based on the size of the first spacing and/or the size of the first height.

In some embodiments, the height of the initial fourth part in the second direction is a second height, and adjacent initial fourth parts have a second spacing in the first direction; after forming the initial lower electrode layer and before etching the initial fourth part, it also includes: detecting the size of the second spacing and/or detecting the size of the second height; determining the time to etch the initial fourth part based on the size of the second spacing and/or the size of the second height.

In some embodiments, the manufacturing method includes manufacturing multiple batches of the lower electrode layer; the time for etching the initial second part is a first time, and the time for etching the initial fourth part is a second time. After manufacturing the previous batch of the lower electrode layer, in the step of manufacturing the next batch of the lower electrode layer, it includes: obtaining first feedback process information and second feedback process information in the previous batch, wherein the first feedback process information includes the relationship between the first spacing and the first time, and/or the relationship between the first height and the first time; the second feedback process information includes the relationship between the second spacing and the second time, and/or the relationship between the second height and the second time; based on the first feedback process information, adjusting the relationship between the first spacing and the first time in the next batch, and/or adjusting the relationship between the first height and the first time in the next batch; based on the second feedback process information, adjusting the relationship between the second spacing and the second time in the next batch, and/or adjusting the relationship between the second height and the second time in the next batch.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are exemplarily described by the pictures in the corresponding drawings. These exemplified descriptions do not constitute limitations on the embodiments, unless otherwise stated, and the pictures in the drawings do not constitute proportional limitations. In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and a person skilled in the art can obtain other drawings based on these drawings without any creative work.

1 to 3 are schematic diagrams of three partial cross-sectional structures of a semiconductor structure provided by an embodiment of the present disclosure;

4 to 13 are schematic diagrams of partial cross-sectional structures corresponding to various steps of a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure.

Detailed ways

As can be seen from the background technology, the integration density and dimensional accuracy of capacitor structures need to be improved.

After analysis, it was found that in a semiconductor structure, if one wants to prepare a capacitor structure with large capacitance, one will mainly improve the dielectric constant of the capacitor dielectric layer in the capacitor structure and the facing area between the lower electrode layer and the upper electrode layer to increase the capacitance of the capacitor structure.

First, the capacitance of the capacitor structure is increased by increasing the dielectric constant of the capacitor dielectric layer. The means to increase the dielectric constant of the capacitor dielectric layer is usually to change the material of the capacitor dielectric layer, such as selecting a material with a larger dielectric constant. However, the cost of the material with a larger dielectric constant is generally very high, and the lattice mismatch problem between the material with a larger dielectric constant and the lower electrode layer or the upper electrode layer needs to be considered.

Secondly, the capacitance of the capacitor structure is increased by increasing the facing area between the lower electrode layer and the upper electrode layer. The means to increase the facing area between the lower electrode layer and the upper electrode layer is usually to increase the height of the lower electrode layer. However, the prepared lower electrode layer often has an inclined side wall. Increasing the height of the lower electrode layer or increasing the aspect ratio of the lower electrode layer increases the maximum width of the lower electrode layer and reduces the number of lower electrode layers that can be prepared per unit volume, which ultimately affects the integration density of the capacitor structure in the semiconductor structure.

The present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein in the semiconductor structure, along the first direction, the width of the first part in the lower electrode layer is the largest, so whether the adjacent lower electrode layers will be in contact and connected, resulting in a short circuit between the adjacent lower electrode layers, mainly depends on the spacing between the adjacent first parts in the adjacent lower electrode layers. Under the premise of ensuring a high integration density of the capacitor structure, after regulating the spacing between the adjacent first parts, by reducing the width of the second part and the fourth part in the lower electrode layer in the first direction, it is beneficial to reduce the inclination of the sidewall extending along the second direction of the lower electrode layer as a whole, thereby facilitating the contact and connection between the adjacent first parts in the adjacent lower electrode layers, increasing the spacing between the adjacent second parts in the adjacent lower electrode layers, and the spacing between the adjacent fourth parts in the adjacent lower electrode layers, so as to increase the spacing between the adjacent lower electrode layers as a whole. In addition, reducing the width of the second part and the fourth part in the lower electrode layer in the first direction is beneficial to increasing the surface area of the lower electrode layer as a whole, thereby facilitating the subsequent increase in the directly opposite area between the upper electrode layer and the lower electrode layer formed subsequently, and facilitating the increase in the capacitance of the capacitor structure including the upper electrode layer and the lower electrode layer.

The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

An embodiment of the present disclosure provides a semiconductor structure, and the semiconductor structure provided by an embodiment of the present application will be described in detail below in conjunction with the accompanying drawings. Figures 1 to 3 are schematic diagrams of three partial cross-sectional structures of a semiconductor structure provided by an embodiment of the present disclosure.

1 to 3 , the semiconductor structure includes: a substrate 100; a plurality of lower electrode layers 101, wherein the plurality of lower electrode layers 101 are arranged at intervals along a first direction X on the substrate 100, and in a second direction Y, the lower electrode layer 101 includes a first portion 111, a second portion 121, a third portion 131 and a fourth portion 141 stacked in sequence; wherein the first direction X is parallel to a plane where the substrate 100 is located, and the second direction Y is a direction in which the lower electrode layer 101 points toward the substrate 101; and along the first direction X, a minimum value a of the width of the first portion 111 is greater than a maximum value c1 of the width of the third portion 131, a minimum value c2 of the width of the third portion 131 is greater than a maximum value b of the width of the second portion 121, and a minimum value c2 of the width of the third portion 131 is greater than a maximum value d of the width of the fourth portion 141.

It can be understood that along the first direction X, the width of the first part 111 determines the maximum width of the lower electrode layer 101, and therefore whether adjacent lower electrode layers 101 will be in contact and connected, resulting in a short circuit between adjacent lower electrode layers 101 mainly depends on the spacing between adjacent first parts 111 in adjacent lower electrode layers 101.

Under the above premise, the width of the second portion 121 and the width of the fourth portion 141 are reduced so that the minimum value c2 of the width of the third portion 131 is greater than the maximum value b of the width of the second portion 121, and the minimum value c2 of the width of the third portion 131 is greater than the maximum value d of the width of the fourth portion 141. On the one hand, it is beneficial to reduce the inclination of the side wall of the lower electrode layer 101 extending along the second direction Y as a whole, so that there is no need to increase the width of the first portion 111 again under the premise of increasing the height of the lower electrode layer 101 as a whole in the second direction Y, which is beneficial to improve the integration density of the lower electrode layer 101 in the semiconductor structure; on the other hand, it is beneficial to increase the spacing between adjacent second portions 121 and the spacing between adjacent fourth portions 141, so as to increase the spacing between adjacent lower electrode layers 101 as a whole, so as to reduce the electrical interference between adjacent lower electrode layers; on the other hand, it is beneficial to increase the surface area of the lower electrode layer 101 as a whole, so as to increase the facing area between the upper electrode layer and the lower electrode layer 101 formed subsequently, and to increase the capacitance of the capacitor structure including the upper electrode layer and the lower electrode layer 101.

In this way, it is beneficial to increase the integration density of the lower electrode layer 101 in the semiconductor structure, increase the spacing between adjacent lower electrode layers 101 as a whole, and increase the surface area of the lower electrode layer 101 as a whole.

It should be noted that, in the semiconductor structure provided by an embodiment of the present disclosure, when increasing the overall height of the lower electrode layer 101 along the second direction Y, there is no need to increase the width of the first part 111, that is, there is no need to reduce the integration density of the lower electrode layer 101 in the semiconductor structure, and it is sufficient to increase the height of the second part 121 and the fourth part 141 in the second direction, which is beneficial to ensure a higher integration density of the lower electrode layer 101 in the semiconductor structure while increasing the capacitance of the subsequent capacitor structure including the upper electrode layer and the lower electrode layer 101.

In some embodiments, referring to FIG. 1 , along the first direction X, the minimum width of the second portion 121 is greater than the maximum width of the fourth portion 141, that is, the overall width of the second portion 121 is greater than the overall width of the fourth portion 141. In some embodiments, along the first direction X, the minimum width of the second portion 121 may be less than or equal to the maximum width of the fourth portion 141, that is, the overall width of the second portion 121 may be less than or equal to the overall width of the fourth portion 141. It is understandable that The semiconductor structure provided in an embodiment of the present disclosure does not limit the width relationship between the second portion 121 and the fourth portion 141 .

The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

In some embodiments, along the second direction Y, the sidewalls of the second portion 121 and the fourth portion 141 are perpendicular to the plane where the substrate 100 is located. In this way, the inclination of the sidewalls of the lower electrode layer 101 extending along the second direction Y is further reduced, which is conducive to further ensuring a higher integration density of the lower electrode layer 101 in the semiconductor structure.

It should be noted that Figures 1 to 3 all take the example that the side walls of the second part 121 and the fourth part 141 are perpendicular to the plane where the substrate 100 is located. In actual applications, due to limitations of the preparation process, the side walls of the second part 121 and the fourth part 141 may also have a very small inclination angle relative to the second direction Y, such as 0.2°, 1° or 1.1°.

In some embodiments, along the second direction Y, the width of the first portion 111 in the first direction X gradually decreases, and the width of the third portion 131 in the first direction X gradually decreases. In this way, the difference in width between the first portion 111 and the second portion 121 is reduced, the difference in width between the third portion 131 and the second portion 121 is reduced, and the difference in width between the third portion 131 and the fourth portion 141 is reduced, thereby facilitating the improvement of the stability of the structure of the lower electrode layer 101.

In some embodiments, along the first direction X, the ratio of the maximum value c1 of the width of the third portion 131 to the minimum value a of the width of the first portion 111 is in the range of 0.9 to 1.0. If the ratio of the maximum value c1 of the width of the third portion 131 to the minimum value a of the width of the first portion 111 is less than 0.9, while the minimum value a of the width of the first portion 111 is small to ensure a higher integration density of the lower electrode layer 101 in the semiconductor structure, the width of the third portion 131 is too small, thereby causing the widths of the second portion 121 and the fourth portion 141 to be too small, which is not conducive to improving the stability of the overall structure of the lower electrode layer 101, for example, it is easy to cause the collapse of the lower electrode layer 101, and it is not conducive to improving the conductivity of the lower electrode layer 101 itself. Therefore, when the ratio of the maximum value c1 of the width of the third portion 131 to the minimum value a of the width of the first portion 111 is in the range of 0.9 to 1.0, it is conducive to ensuring that the lower electrode layer 101 has good conductivity and structural stability, while ensuring a higher integration density of the lower electrode layer 101 in the semiconductor structure.

In some embodiments, along the first direction X, the ratio of the minimum value c2 of the width of the third portion 131 to the maximum value b of the width of the second portion 121 is in the range of 1.0 to 1.05. From the above analysis, it can be seen that in order to ensure a higher integration density of the lower electrode layer 101 in the semiconductor structure, the width of the third portion 131 is relatively small. If the ratio of the minimum value c2 of the width of the third portion 131 to the maximum value b of the width of the second portion 121 is greater than 1.05, the width of the second portion 121 is too small, which is not conducive to improving the stability of the overall structure of the lower electrode layer 101, and is not conducive to improving the conductivity of the lower electrode layer 101 itself.

In other words, if the second portion 121 is ensured to have an appropriate width dimension, and the ratio of the minimum value c2 of the width of the third portion 131 to the maximum value b of the width of the second portion 121 is greater than 1.05, the width of the third portion 131 is too large, resulting in an overall size of the lower electrode layer 101 being too large, which is not conducive to improving the higher integration density of the lower electrode layer 101 in the semiconductor structure. Therefore, when the ratio of the minimum value c2 of the width of the third portion 131 to the maximum value b of the width of the second portion 121 is in the range of 1.0 to 1.05, it is beneficial to ensure that the lower electrode layer 101 has good conductivity and structural stability while ensuring that the lower electrode layer 101 is Higher integration density in semiconductor structures.

In some embodiments, along the first direction X, the ratio of the minimum value c2 of the width of the third portion 131 to the maximum value d of the width of the fourth portion 141 is in the range of 1.0 to 1.1. From the above analysis, it can be seen that in order to ensure a higher integration density of the lower electrode layer 101 in the semiconductor structure, the width of the third portion 131 is relatively small. If the ratio of the minimum value c2 of the width of the third portion 131 to the maximum value d of the width of the fourth portion 141 is greater than 1.1, the width of the fourth portion 141 is too small, which is not conducive to improving the stability of the overall structure of the lower electrode layer 101, and is not conducive to improving the conductivity of the lower electrode layer 101 itself.

In other words, if the fourth portion 141 is ensured to have a suitable width dimension, and the ratio of the minimum value c2 of the width of the third portion 131 to the maximum value d of the width of the fourth portion 141 is greater than 1.1, the width of the third portion 131 is too large, resulting in an overall size of the lower electrode layer 101 being too large, which is not conducive to improving the higher integration density of the lower electrode layer 101 in the semiconductor structure. Therefore, when the ratio of the minimum value c2 of the width of the third portion 131 to the maximum value d of the width of the fourth portion 141 is in the range of 1.0 to 1.1, it is conducive to ensuring that the lower electrode layer 101 has good conductivity and structural stability, while ensuring a higher integration density of the lower electrode layer 101 in the semiconductor structure.

In some embodiments, along the first direction X, the width of the first portion 111 has a value ranging from 27 nm to 32 nm, for example, 30 nm.

In some embodiments, along the first direction X, the width of the second portion 121 has a value ranging from 23 nm to 29 nm, for example, 25 nm.

In some embodiments, along the first direction X, the width of the third portion 131 has a value ranging from 24 nm to 31 nm, for example, 27 nm.

In some embodiments, along the first direction X, the width of the fourth portion 141 has a value ranging from 23 nm to 28 nm, for example, 24 nm.

In some embodiments, referring to FIG. 2 , along the second direction Y, the semiconductor structure may further include: a first supporting layer 102, which is in contact with and connected to a portion of the sidewall of each first portion 111 extending along the second direction Y; and a second supporting layer 112, which is in contact with and connected to a portion of the sidewall of each third portion 131 extending along the second direction Y. The first supporting layer 102 and the second supporting layer 112 jointly support the lower electrode layer 101 to improve the structural stability of the lower electrode layer 101 and prevent the lower electrode layer 101 from collapsing.

In some embodiments, with continued reference to FIG. 2 , along the second direction Y, the semiconductor structure may further include: a dielectric layer 103, the dielectric layer 103 at least covers the sidewalls of the second portion 121 and the fourth portion 141 extending along the second direction Y; and an upper electrode layer 104, the upper electrode layer 104 at least covers the surface of the dielectric layer 103. Among them, the lower electrode layer 101, the dielectric layer 103 and the upper electrode layer 104 together constitute a capacitor structure. It can be understood that the semiconductor structure provided in an embodiment of the present disclosure is beneficial to improving the integration density of the lower electrode layer 101 on the one hand, thereby improving the integration density of the capacitor structure, and on the other hand, it is beneficial to increase the surface area of the lower electrode layer 101 to increase the facing area between the lower electrode layer 101 and the upper electrode layer 104, thereby improving the capacitance of the capacitor structure, and on the other hand, it is beneficial to increase the spacing between adjacent lower electrode layers 101 to reduce the electrical interference between adjacent lower electrode layers 101, thereby improving the electrical performance of the capacitor structure.

It should be noted that in FIG. 2 , the dielectric layer 103 conformally covers the lower electrode layer 101 , the first support layer 102 and The surface of the combined structure of the second support layer 112, the upper electrode layer 104 covers the surface of the dielectric layer 103, and multiple lower electrode layers 101 share one upper electrode layer 104. In practical applications, the upper electrode layer 104 can also conformally cover the surface of the dielectric layer 103, and one lower electrode layer 101 corresponds to one upper electrode layer 104, or the dielectric layer 103 only covers the exposed surface of the lower electrode layer 101.

In some embodiments, referring to Figure 3, the base 100 may include: a substrate 110 and a plurality of mutually spaced contact layers 120 located in the substrate 110, the contact layers 120 being in one-to-one contact connection with the lower electrode layer 101; the lower electrode layer 101 may also include: a fifth portion 151 located between the fourth portion 141 and the contact layer 120; the semiconductor structure may also include: a third supporting layer 122 located above the substrate 110 and in contact connection with the side wall of the fifth portion 151 extending along the second direction Y.

It can be understood that the contact layer 120 can realize electrical connection between the lower electrode layer 101 and other electrical devices (not shown in the figure) in the substrate 110 .

1 , along the second direction Y, a height h1 of the first portion 111 is greater than or equal to a height h3 of the third portion 131 , a height h2 of the second portion 121 is greater than a height h1 of the first portion 111 , and a height h4 of the fourth portion 141 is greater than a height h1 of the first portion 111 .

It can be understood that the height h2 of the second portion 121 is greater than the height h1 of the first portion 111 and the height h3 of the third portion 131, which is beneficial to increase the surface area of the lower electrode layer 101 by increasing the height h2 of the second portion 121 without increasing the width of the first portion 111 and the third portion 131 in the first direction X. Alternatively, the height h4 of the fourth portion 141 is greater than the height h1 of the first portion 111 and the height h3 of the third portion 131, which is beneficial to increase the surface area of the lower electrode layer 101 by increasing the height h4 of the fourth portion 141 without increasing the width of the first portion 111 and the third portion 131 in the first direction X.

In some embodiments, along the second direction Y, the height h2 of the second portion 121 is greater than the height h4 of the fourth portion 141. In some embodiments, along the second direction Y, the height h2 of the second portion 121 may be less than or equal to the height h4 of the fourth portion 141. It is understood that the semiconductor structure provided in an embodiment of the present disclosure does not limit the height relationship between the second portion 121 and the fourth portion 141.

In some embodiments, along the second direction Y, the height of the first support layer 102 may be 90nm-110nm, for example, 100nm; the height of the second support layer 112 may be 40nm-60nm, for example, 50nm, and the height of the third support layer 122 may be 20nm-40nm, for example, 30nm. It is understood that along the second direction Y, the height of the first portion 111 is the same as the height of the first support layer 102, the height of the third portion 131 is the same as the height of the second support layer 112, and the height of the fifth portion 151 is the same as the height of the third support layer 122.

In some embodiments, along the second direction Y, the height of the second portion 121 may be 500nm-700nm, and the height of the fourth portion 141 may be 500nm-700nm. In one example, the height of the second portion 121 may be 600nm, and the height of the fourth portion 141 may be 600nm; in another example, the height of the second portion 121 may be 500nm, and the height of the fourth portion 141 may be 700nm; in yet another example, the height of the second portion 121 may be 700nm, and the height of the fourth portion 141 may be 500nm.

In some embodiments, along the second direction Y, the overall height of the lower electrode layer 101 is 1.2 um to 1.5 um, for example, 1.4 um.

In summary, under the premise of ensuring a high integration density of the capacitor structure, after adjusting the spacing between adjacent first parts, by reducing the width of the second part 121 and the fourth part 141 in the lower electrode layer 101 in the first direction X, it is beneficial to reduce the inclination of the side wall extending along the second direction Y of the lower electrode layer 101 as a whole, so as to avoid contact and connection between adjacent first parts 111 in adjacent lower electrode layers 101, increase the spacing between adjacent second parts 121 in adjacent lower electrode layers 101, and the spacing between adjacent fourth parts 141 in adjacent lower electrode layers 101, so as to increase the spacing between adjacent lower electrode layers 101 as a whole. In addition, reducing the width of the second part 121 and the fourth part 141 in the lower electrode layer 101 in the first direction X is beneficial to increase the surface area of the lower electrode layer 101 as a whole, so as to increase the directly opposite area between the upper electrode layer 104 and the lower electrode layer 101 formed subsequently, and to increase the capacitance of the capacitor structure including the upper electrode layer 104 and the lower electrode layer 101.

Another embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, which is used to prepare the semiconductor structure provided by the aforementioned embodiment. The method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described in detail below in conjunction with Figures 1 to 13. Figures 4 to 13 are schematic diagrams of partial cross-sectional structures corresponding to each step of the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure. It should be noted that the parts that are the same or corresponding to the aforementioned embodiments are not repeated here.

The method for manufacturing a semiconductor structure comprises the following steps:

4 to 8 , a substrate 100 is provided; a plurality of initial lower electrode layers 161 are formed on the substrate 100, the plurality of initial lower electrode layers 161 are arranged at intervals along a first direction X, and along a second direction Y, the width of the initial lower electrode layer 161 in the first direction X gradually decreases, and the initial lower electrode layer 161 includes a first portion 111, an initial second portion 171, a third portion 131, and an initial fourth portion 181 stacked in sequence; wherein the first direction X is parallel to the plane where the substrate 100 is located, and the second direction Y is the direction in which the lower electrode layer 101 points to the substrate 100.

In some embodiments, referring to FIG. 4 and FIG. 5 , the base 100 may include: a substrate 110 and a plurality of contact layers 120 spaced apart from each other in the substrate 110 , wherein the contact layers 120 are in one-to-one contact connection with the initial lower electrode layers 161 .

In some embodiments, referring to Figures 4 to 8, the step of forming an initial lower electrode layer 161 may include: forming a stacked second dielectric film 132, a second support film 142, a first dielectric film 152 and a first support film 162 on the substrate 100, and the second dielectric film 132, the second support film 142, the first dielectric film 152 and the first support film 162 each have a plurality of contact holes 105, and along the second direction Y, the opening size of the contact hole 105 gradually decreases.

In some embodiments, referring to FIG6 , before forming the second dielectric film 132, the second supporting film 142, the first dielectric film 152, and the first supporting film 162, the manufacturing method may further include: forming a third supporting layer 122. It is understood that an initial third supporting layer, an initial second dielectric film, an initial second supporting film, an initial first dielectric film, and an initial first supporting film that cover the surface of the substrate 100 and are sequentially stacked may be formed, and the initial third supporting layer, the initial second dielectric film, the initial second supporting film, the initial first dielectric film, and the initial first supporting film are patterned to form the third supporting layer 122, the second dielectric film 132, the second supporting film 142, the first dielectric film 152, and the first supporting film 162.

The following description will be made using the third supporting layer 122, the second dielectric film 132, the second supporting film 142, the first dielectric film 152 and the first supporting film 162 formed on the substrate 100 as an example. It should be noted that, unless otherwise specified, the examples provided below can also be applied to the case where only the second dielectric film 132, the second supporting film 142, the first dielectric film 152 and the first supporting film 162 are formed on the substrate 100, and can also be applied to the case where the substrate 100 has a contact layer 120 or does not have a contact layer 120.

6 to 8 , a preliminary lower electrode layer 161 is formed to fully fill the contact hole 105 .

In some embodiments, the step of forming the initial lower electrode layer 161 includes: in conjunction with reference to Figures 6 and 7, forming an initial lower electrode film 191 that fills the contact hole 105 and covers the top surface of the first support film 162; in conjunction with reference to Figures 7 and 8, back-etching the initial lower electrode film 191 to remove the initial lower electrode film 191 covering the top surface of the first support film 162, and the remaining initial lower electrode film 191 serves as the initial lower electrode layer 161.

8 to 11 , the initial second portion 171 is etched to form the second portion 121 . Along the first direction X, the maximum value b of the width of the second portion 121 is smaller than the minimum value c2 of the width of the third portion 131 .

In some embodiments, the step of forming the second portion 121 may include: in conjunction with reference to Figures 8 and 9, etching the first support film 162 to form a first support layer 102, the first support layer 102 having a first opening 115 exposing the first dielectric film 152; in conjunction with reference to Figures 9 and 10, removing the first dielectric film 152 through the first opening 115 to expose the side wall of the initial second portion 171; etching the exposed side wall of the initial second portion 171 to form the second portion 121.

In some embodiments, referring to Figure 10, the height of the initial second part 171 in the second direction Y is a first height H1, and adjacent initial second parts 171 have a first spacing D1 in the first direction X; after forming the initial lower electrode layer 161 and before etching the initial second part 171, it also includes: detecting the size of the first spacing D1, and/or detecting the size of the first height H1; based on the size of the first spacing D1 and/or the size of the first height H1, determining the time to etch the initial second part 171.

It can be understood that the first spacing D1 can be the spacing between the top surfaces of adjacent initial second parts 171 along the first direction X. In practical applications, the spacing between any areas corresponding to adjacent initial second parts 171 along the first direction X can be measured as the first spacing D1 according to actual needs. Determining the time for etching the initial second part 171 based on the size of the first spacing D1 and/or the size of the first height H1 is beneficial to the dimensional accuracy of the formed second part 121, for example, it is more conducive to forming the second part 121 with a sidewall perpendicular to the surface of the substrate 100. It should be noted that in order to form the second part 121 with a sidewall perpendicular to the surface of the substrate 100, the time for etching the initial second part 171 is affected by the first spacing D1 and the first height H1. In practical applications, the time for etching the initial second part 171 can be determined based on one of the first spacing D1 and the first height H1 or based on both the first spacing D1 and the first height H1 according to needs.

10 to 13 , the initial fourth portion 181 is etched to form a fourth portion 141. In the first direction X, the maximum value d of the width of the fourth portion 141 is less than the minimum value c2 of the width of the third portion 131. The first portion 111, the second portion 121, the third portion 131 and the fourth portion 141 together form the lower electrode layer 101. It should be noted that, in some embodiments, the lower electrode layer 101 may further include a fifth portion 151.

In some embodiments, the step of forming the fourth portion 141 may include: in conjunction with reference to Figures 10 and 11, etching the second support film 142 to form a second support layer 112, the second support layer 112 having a second opening 125 exposing the second dielectric film 132; in conjunction with reference to Figures 11 and 12, removing the second dielectric film 132 through the second opening 125 to expose the side wall of the initial fourth portion 181; in conjunction with reference to Figures 12 and 13, etching the exposed side wall of the initial fourth portion 181 to form the fourth portion 141.

In some embodiments, the height of the initial fourth portion 181 in the second direction Y is a second height H2, and adjacent initial fourth portions 181 have a second spacing D2 in the first direction X; after forming the initial lower electrode layer 161 and before etching the initial fourth portion 181, it also includes: detecting the size of the second spacing D2, and/or detecting the size of the second height H2; determining the time for etching the initial fourth portion 181 based on the size of the second spacing D2 and/or the size of the second height H2.

It can be understood that the second spacing D2 can be the spacing between the top surfaces of the initial fourth portion 181 along the first direction X. In practical applications, the spacing between any regions corresponding to adjacent initial fourth portions 181 along the first direction X can be measured as the second spacing D2 according to actual needs. Determining the time for etching the initial fourth portion 181 based on the size of the second spacing D2 and/or the size of the second height H2 is beneficial to the dimensional accuracy of the formed fourth portion 141, for example, it is more beneficial to form the fourth portion 141 whose sidewall is perpendicular to the surface of the substrate 100. It should be noted that in order to form the fourth portion 141 whose sidewall is perpendicular to the surface of the substrate 100, the time for etching the initial fourth portion 181 is affected by the second spacing D2 and the second height H2. In practical applications, the time for etching the initial fourth portion 181 can be determined based on one of the second spacing D2 and the second height H2 or based on both the second spacing D2 and the second height H2 according to needs.

In the above embodiment, the first etching process is used to remove the first dielectric film 152 and the second dielectric film 132 , and the second etching process is used to etch the initial second portion 171 and the initial fourth portion 181 . The first etching process is different from the second etching process.

In some embodiments, removing the first dielectric film 152 and the second dielectric film 132 by using the first etching process includes: wet etching the first dielectric film 152 and the second dielectric film 132 by using an etching solution containing hydrofluoric acid and ammonium fluoride.

In some embodiments, etching the initial second portion 171 and the initial fourth portion 181 using the second etching process includes: wet etching the initial second portion 171 and the initial fourth portion 181 using a mixture of ammonia, hydrogen peroxide, and water.

In some embodiments, etching the initial second portion 171 and the initial fourth portion 181 using the second etching process includes: etching the initial second portion 171 and the initial fourth portion 181 using a dry etching process. In some embodiments, the etching atmosphere of the dry etching process may include at least one of a chlorine-containing gas and a fluorine-containing gas. In one example, the etching atmosphere of the dry etching process may include argon, chlorine, boron trichloride, methane, etc.

In some embodiments, the material of the initial lower electrode layer 161 is titanium nitride. Since the etching products produced by the etching of titanium nitride by chlorine-containing gas and fluorine-containing gas are volatile gases, they are easily extracted from the etching chamber. Moreover, the etching of titanium nitride by chlorine-containing gas and fluorine-containing gas has good etching selectivity and anisotropic properties, which is beneficial to improving the dimensional accuracy of the formed lower electrode layer 101.

In some embodiments, the manufacturing method includes manufacturing multiple batches of lower electrode layers 101; etching the initial second portion 171 for a first time, etching the initial fourth portion 181 for a second time, and manufacturing the previous batch of lower electrode layers. After 101, in the step of manufacturing the lower electrode layer 101 of the next batch, it includes: obtaining the first feedback process information and the second feedback process information in the previous batch, wherein the first feedback process information includes the relationship between the first spacing D1 and the first time, and/or the relationship between the first height H1 and the first time; the second feedback process information includes the relationship between the second spacing D2 and the second time, and/or the relationship between the second height H2 and the second time; based on the first feedback process information, adjusting the relationship between the first spacing D1 and the first time in the next batch, and/or adjusting the relationship between the first height H1 and the first time in the next batch; based on the second feedback process information, adjusting the relationship between the second spacing D2 and the second time in the next batch, and/or adjusting the relationship between the second height H2 and the second time in the next batch.

It can be understood that based on the relationship between the first spacing D1 and the first time obtained in the previous batch and/or the relationship between the second height H2 and the second time, the specific process parameters for forming the second part 121 and the fourth part 141 in actual production can be known, and adjusting the process parameters for forming the second part 121 and the fourth part 141 in a subsequent batch based on the specific process parameters can help to further improve the dimensional accuracy of the formed second part 121 and the fourth part 141. For example, it is helpful to further ensure that the second part 121 and the fourth part 141 are formed with side walls perpendicular to the surface of the substrate 100.

In some embodiments, with reference to FIG. 13 and FIG. 3 , the manufacturing method may further include: forming a dielectric layer 103, the dielectric layer 103 at least covering the sidewalls of the second portion 121 and the fourth portion 141 extending along the second direction Y; forming an upper electrode layer 104, the upper electrode layer 104 at least covering the surface of the dielectric layer 103. The lower electrode layer 101, the dielectric layer 103 and the upper electrode layer 104 together constitute a capacitor structure, and it can be understood that the manufacturing method provided in another embodiment of the present disclosure does not limit the specific process of forming the dielectric layer 103 and the upper electrode layer 104.

In summary, by reducing the width of the second portion 121 and the fourth portion 141 in the lower electrode layer 101 in the first direction X, it is beneficial to reduce the inclination of the side wall extending along the second direction Y of the lower electrode layer 101 as a whole, so as to avoid contact and connection between adjacent first portions 111 in adjacent lower electrode layers 101, while increasing the spacing between adjacent second portions 121 in adjacent lower electrode layers 101, and the spacing between adjacent fourth portions 141 in adjacent lower electrode layers 101, so as to increase the spacing between adjacent lower electrode layers 101 as a whole. In addition, reducing the width of the second portion 121 and the fourth portion 141 in the lower electrode layer 101 in the first direction X is beneficial to increase the surface area of the lower electrode layer 101 as a whole, so as to increase the directly opposed area between the upper electrode layer 104 and the lower electrode layer 101 formed subsequently, and to increase the capacitance of the capacitor structure including the upper electrode layer 104 and the lower electrode layer 101.

Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims (20)

1. A semiconductor structure comprising:

   Base (100);

   A plurality of lower electrode layers (101), wherein the plurality of lower electrode layers (101) are arranged at intervals along a first direction (X) on the substrate (100); in a second direction (Y), the lower electrode layer (101) comprises a first part (111), a second part (121), a third part (131) and a fourth part (141) stacked in sequence; wherein the first direction (X) is parallel to the plane where the substrate (100) is located, and the second direction (Y) is the direction in which the lower electrode layer (101) points toward the substrate (100);

   Along the first direction (X), the minimum value (a) of the width of the first part (111) is greater than the maximum value (c1) of the width of the third part (131), the minimum value (c2) of the width of the third part (131) is greater than the maximum value (b) of the width of the second part (121), and the minimum value (c2) of the width of the third part (131) is greater than the maximum value (d) of the width of the fourth part (141).
2. The semiconductor structure according to claim 1, wherein, along the second direction (Y), side walls of the second portion (121) and the fourth portion (141) are both perpendicular to a plane where the substrate (100) is located.
3. The semiconductor structure according to claim 1 or 2 is characterized in that, along the first direction (X), the ratio of the maximum value (c1) of the width of the third part (131) to the minimum value (a) of the width of the first part (111) ranges from 0.9 to 1.0.
4. The semiconductor structure according to claim 1 or 2, wherein, along the first direction (X), the ratio of the minimum value (c2) of the width of the third portion (131) to the maximum value (b) of the width of the second portion (121) ranges from 1.0 to 1.05.
5. The semiconductor structure according to claim 1 or 2, wherein, along the first direction (X), the ratio of the minimum value (c2) of the width of the third portion (131) to the maximum value (b) of the width of the fourth portion (141) ranges from 1.0 to 1.1.
6. The semiconductor structure according to claim 1, wherein along the second direction (Y), the semiconductor structure further comprises:

   A first supporting layer (102) is in contact with and connected to a portion of the side wall of each first portion (111) extending along the second direction (Y);

   A second supporting layer (112) is in contact with and connected to a portion of the side wall of each of the third portions (131) extending along the second direction (Y);

   a dielectric layer (103), the dielectric layer (103) at least covering the side walls of the second portion (121) and the fourth portion (141) extending along the second direction (Y);

   An upper electrode layer (104), wherein the upper electrode layer (104) at least covers a surface of the dielectric layer (103).
7. The semiconductor structure according to claim 6, wherein the substrate (100) comprises:

   A substrate (110) and a plurality of contact layers (120) spaced apart from each other located in the substrate (110), wherein the contact layers (120) are in one-to-one contact connection with the lower electrode layer (101);

   The lower electrode layer (101) comprises: a fifth portion (151) located between the fourth portion (141) and the contact layer (120);

   The semiconductor structure further comprises: a third supporting layer (122) located above the substrate (110) and in contact with the sidewall of the fifth portion (151) extending along the second direction (Y).
8. The semiconductor structure according to claim 1, wherein, along the second direction (Y), the height (h1) of the first portion (111) is greater than or equal to the height (h3) of the third portion (131), the height (h2) of the second portion (121) is greater than the height (h1) of the first portion (111), and the height (h4) of the fourth portion (141) is greater than the height (h1) of the first portion (111).
9. The semiconductor structure according to claim 1 or 2, wherein, along the second direction (Y), the width of the first portion (111) in the first direction (X) gradually decreases, and the width of the third portion (131) in the first direction (X) gradually decreases.
10. The semiconductor structure according to claim 1 or 2, wherein the second portion (121) and the fourth portion (141) are inclined toward a direction away from the second direction (Y).
11. A method for manufacturing a semiconductor structure, comprising:

    Providing a substrate (100);

    A plurality of initial lower electrode layers (161) are formed on the substrate (100), the plurality of initial lower electrode layers (161) are arranged at intervals along a first direction (X), and along a second direction (Y), the width of the initial lower electrode layer (161) in the first direction (X) gradually decreases, and the initial lower electrode layer (161) comprises a first part (111), an initial second part (171), a third part (131), and an initial fourth part (181) stacked in sequence; wherein the first direction (X) is parallel to the plane where the substrate (100) is located, and the second direction (Y) is the direction in which the initial lower electrode layer (161) points toward the substrate (100);

    Etching the initial second portion (171) to form a second portion (121), wherein along the first direction (X), a maximum value (b) of the width of the second portion (121) is smaller than a minimum value (c2) of the width of the third portion (131);

    The initial fourth portion (181) is etched to form a fourth portion (141); along the first direction (X), the maximum value (d) of the width of the fourth portion (141) is smaller than the minimum value (c2) of the width of the third portion (131); the first portion (111), the second portion (121), the third portion (131) and the fourth portion (141) together form a lower electrode layer (101).
12. The manufacturing method according to claim 11, wherein the step of forming the initial lower electrode layer (161) comprises:

    A stacked second dielectric film (132), a second supporting film (142), a first dielectric film (152) and a first supporting film (162) are formed on the substrate (100), wherein the second dielectric film (132), the second supporting film (142), the first dielectric film (152) and the first supporting film (162) are stacked. The first dielectric film (152) and the first supporting film (162) both have a plurality of contact holes (105), and along the second direction (Y), the opening size of the contact holes (105) gradually decreases;

    The initial lower electrode layer (161) is formed to fill the contact hole (105).
13. The manufacturing method according to claim 12, wherein the step of forming the second portion (121) comprises:

    Etching the first supporting film (162) to form a first supporting layer (102), wherein the first supporting layer (102) has a first opening (115) exposing the first dielectric film (152);

    removing the first dielectric film (152) through the first opening (115) to expose the side wall of the initial second portion (171);

    The exposed sidewall of the initial second portion (171) is etched to form the second portion (121).
14. The manufacturing method according to claim 13, wherein the step of forming the fourth portion (141) comprises:

    Etching the second supporting film (142) to form a second supporting layer (112), wherein the second supporting layer (112) has a second opening (125) exposing the second dielectric film (132);

    removing the second dielectric film (132) through the second opening (125) to expose the side wall of the initial fourth portion (181);

    The exposed sidewall of the initial fourth portion (181) is etched to form the fourth portion (141).
15. The manufacturing method according to claim 14, wherein a first etching process is used to remove the first dielectric film (152) and the second dielectric film (132), and a second etching process is used to etch the initial second portion (171) and the initial fourth portion (181), and the first etching process is different from the second etching process.
16. The manufacturing method according to claim 15, wherein the removing the first dielectric film (152) and the second dielectric film (132) by using a first etching process comprises: wet etching the first dielectric film (152) and the second dielectric film (132) by using an etching solution containing hydrofluoric acid and ammonium fluoride.
17. The manufacturing method according to claim 15, wherein the etching of the initial second part (171) and the initial fourth part (181) using a second etching process comprises: wet etching the initial second part (171) and the initial fourth part (181) using a mixture of ammonia water, hydrogen peroxide and water.
18. The manufacturing method according to claim 11, wherein the height of the initial second portion (171) in the second direction (Y) is a first height (H1), and adjacent initial second portions (171) have a first spacing (D1) in the first direction (X); after forming the initial lower electrode layer (161) and before etching the initial second portion (171), the method further comprises:

    Detecting the size of the first distance (D1), and/or detecting the size of the first height (H1);

    The time for etching the initial second portion (171) is determined based on the size of the first distance (D1) and/or the size of the first height (H1).
19. The manufacturing method according to claim 18, wherein the height of the initial fourth portion (181) in the second direction (Y) is a second height (H2), and adjacent initial fourth portions (181) have a second spacing (D2) in the first direction (X); after forming the initial lower electrode layer (161) and before etching the initial fourth portion (181), the method further comprises:

    Detecting the size of the second distance (D2), and/or detecting the size of the second height (H2);

    The time for etching the initial fourth portion (181) is determined based on the size of the second distance (D2) and/or the size of the second height (H2).
20. The manufacturing method according to claim 19, wherein the manufacturing method comprises manufacturing a plurality of batches of the lower electrode layer (101); the time for etching the initial second portion (171) is a first time, the time for etching the initial fourth portion (181) is a second time, and after manufacturing a previous batch of the lower electrode layer (101), in the step of manufacturing a subsequent batch of the lower electrode layer (101), the step comprises:

    Acquire first feedback process information and second feedback process information in the previous batch, wherein the first feedback process information includes a relationship between the first spacing (D1) and the first time, and/or a relationship between the first height (H1) and the first time; the second feedback process information includes a relationship between the second spacing (D2) and the second time, and/or a relationship between the second height (H2) and the second time;

    Based on the first feedback process information, adjusting the relationship between the first distance (D1) and the first time in the subsequent batch, and/or adjusting the relationship between the first height (H1) and the first time in the subsequent batch;

    Based on the second feedback process information, the relationship between the second spacing (D2) and the second time in the subsequent batch is adjusted, and/or the relationship between the second height (H2) and the second time in the subsequent batch is adjusted.