WO2024098705A1

WO2024098705A1 - Semiconductor structure and manufacturing method therefor

Info

Publication number: WO2024098705A1
Application number: PCT/CN2023/093691
Authority: WO
Inventors: 刘洋; 穆天蕾
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-11-10
Filing date: 2023-05-11
Publication date: 2024-05-16
Also published as: CN118055614A

Abstract

Provided in the present disclosure are a semiconductor structure and a manufacturing method therefor. The method comprises: forming a plurality of graphic units on a substrate, wherein there is a first gap or a second gap between adjacent graphic units; forming a protective layer on a side wall of each graphic unit, wherein the protective layer only fills the first gap; removing the protective layer in the second gap, and retaining the protective layer in the first gap; thinning the side wall of each exposed graphic unit; and removing the protective layer and etching the substrate, so as to form active areas.

Description

Semiconductor structure and method for manufacturing the same

This disclosure claims priority to the Chinese patent application filed with the China Patent Office on November 10, 2022, with application number 202211409924.8 and application name “Semiconductor Structure and Manufacturing Method Thereof”, the entire contents of which are incorporated by reference in this disclosure.

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof.

Background technique

With the development of semiconductor technology, semiconductor structures, especially dynamic random access memory (DRAM), are widely used in electronic products such as mobile phones, computers, and automobiles. With the development of semiconductor technology, the characteristic size of semiconductor structures continues to shrink, and its manufacturing difficulty becomes increasingly greater, and the electrical requirements become increasingly higher. In the process of manufacturing semiconductor structures, the uniformity of the single active area formed is poor, and there are defects in the active area, which affects the performance of the semiconductor structure.

Summary of the invention

The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same to ensure the performance of the semiconductor structure.

According to some embodiments, a first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

providing a substrate;

forming a first mask layer on the substrate, wherein the first mask layer comprises a plurality of discrete graphic units arranged in an array, a first gap or a second gap is provided between adjacent graphic units, a size of the first gap in a first direction is smaller than a size of the second gap in the first direction, wherein the first direction is parallel to the surface of the substrate;

forming a protection layer on the substrate, wherein the protection layer covers the sidewalls of the graphic unit exposed in the second gap and fills the first gap;

Perform a first etching to remove the side of the graphic unit that covers and contacts the second gap. The protective layer on the side wall of the graphic unit contacts the second gap, exposing the side wall of the graphic unit contacts the second gap, and retaining the protective layer covering the side wall of the graphic unit contacts the first gap;

Performing a second etching to thin the sidewalls of the graphic unit in contact with the second gap, so that the first mask layer is transformed into a second mask layer;

The protection layer is removed, and a third etching process is performed on the substrate using the second mask layer as a mask to form a plurality of discrete active regions in the substrate.

The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure has at least the following advantages:

In the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure, a first mask layer is formed on a substrate, the first mask layer includes a plurality of discrete graphic units, a first gap or a second gap is provided between adjacent graphic units, and the size of the first gap along the first direction is smaller than the size of the second gap along the first direction. A protective layer is formed on the sidewall of the graphic unit, the protective layer fills the first gap but does not fill the second gap, and then the protective layer in the second gap is removed, and the protective layer in the first gap is retained, so that the sidewall of the graphic unit in contact with the second gap is exposed, thereby thinning the sidewall of the graphic unit in contact with the second gap. In the process of etching the substrate, the sidewall of the graphic unit in contact with the second gap is thinned, which can compensate for the load effect that the size of the second gap along the first direction is larger than the size of the first gap along the first direction. On the one hand, the two long sides opposite to each other along the first direction in the cross section of the obtained active area parallel to the substrate surface direction are relatively straight, and the uniformity of the active area along its extension direction is better. On the other hand, it can also improve the defects such as insufficient etching of the active area or pattern collapse, thereby improving the performance of the semiconductor structure.

According to some embodiments, the second aspect of the present disclosure provides a semiconductor structure, which includes an active region, the active region is formed by the manufacturing method as described above, and the cross section of the active region parallel to the substrate surface direction is a rectangle with two flat short sides and two straight long sides. The uniformity of the active region along its extension direction is good, and the performance of the semiconductor structure is improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of an active region in the related art;

FIG2 is a schematic diagram of a structure after forming a first mask layer in the related art;

FIG3 is a cross-sectional view of point A in FIG2 ;

FIG4 is a schematic diagram of a structure after an active region is formed in the related art;

FIG5 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present disclosure;

FIG6 is a schematic structural diagram of a substrate in an embodiment of the present disclosure;

FIG7 is a schematic diagram of a structure after forming a first mask layer in an embodiment of the present disclosure;

FIG8 is a cross-sectional view of point A in FIG7;

FIG9 is a cross-sectional view of point B in FIG7;

FIG10 is a cross-sectional view of a point C in FIG7 ;

FIG11 is a schematic diagram of a structure after a protective layer is formed in one embodiment of the present disclosure;

FIG12 is a cross-sectional view of point A in FIG11;

FIG13 is a cross-sectional view of point B in FIG11;

FIG14 is a cross-sectional view of a point C in FIG11;

FIG15 is a schematic diagram of the etching direction of anisotropic etching in one embodiment of the present disclosure;

FIG16 is a schematic diagram of a structure after a portion of the protective layer is removed in an embodiment of the present disclosure;

FIG17 is a cross-sectional view of point A in FIG16;

FIG18 is a cross-sectional view of point B in FIG16;

FIG19 is a cross-sectional view of a point C in FIG16;

FIG20 is a schematic diagram of a cross section A after etching a portion of the sidewall of a graphic unit in an embodiment of the present disclosure;

FIG21 is a schematic diagram of a cross section B after etching a portion of the sidewall of a graphic unit in an embodiment of the present disclosure;

FIG22 is a schematic diagram of a C-section after etching a portion of the sidewall of a graphic unit in an embodiment of the present disclosure;

FIG23 is a schematic diagram of a cross section A after removing the remaining protective layer in an embodiment of the present disclosure;

FIG24 is a schematic diagram of a cross section B after the remaining protective layer is removed in an embodiment of the present disclosure;

FIG25 is a schematic diagram of a C-section after removing the remaining protective layer in an embodiment of the present disclosure;

FIG26 is a schematic diagram of a structure after an active region is formed in an embodiment of the present disclosure;

FIG. 27 is a cross-sectional view taken along line C in FIG. 26 .

Description of reference numerals:
10-substrate; 11-active region;
20-first mask layer; 21-graphic unit;
22-first gap; 23-second gap;
24-silicon oxide layer; 25-polysilicon layer;
30-protective layer; 31-hole;
40 - second mask layer.

Detailed ways

Referring to FIG. 1 , the semiconductor structure in the related art has the problem of poor performance. As shown in FIG. 1 , the active area 11 is located in the substrate 10, and the extension direction of the active area 11 is the vertical direction (Y direction) as shown in FIG. 1 . Along the extension direction of the active area 11, the middle parts of the two opposite side walls of the active area 11 are convex. The width of the active area 11 is different, and the width of the middle part of the active area 11 is greater than the width of the end of the active area 11. The uniformity of each active area 11 is poor, resulting in poor performance of the semiconductor structure.

The inventors have found that the uniformity of each active area 11 is poor. Referring to Figures 2 to 4, the reason is that when making the active area 11, as shown in Figures 2 and 3, a first mask layer 20 is usually formed on the substrate 10, and then the substrate 10 is etched using the first mask layer 20 as a mask, as shown in Figure 4, to form the active area 11. The first mask layer 20 usually includes a plurality of graphic units 21, and the plurality of graphic units 21 form an array arrangement of multiple rows and columns. Exemplarily, the extension direction of the graphic unit 21 is the column direction (the Y direction shown in Figure 2), and the row direction (the X direction shown in Figure 2) intersects with the column direction, wherein the row direction and the column direction are not perpendicular.

The spacing of the graphic units 21 along the column direction is equal, and the spacing along the row direction is also equal. Since the row direction and the column direction are not perpendicular, along the direction perpendicular to the column direction (Z direction shown in FIG. 2 ), part of the graphic unit 21 in the same column is opposite to the graphic unit 21 in the adjacent column, and the spacing is smaller, as shown at L1 in FIG. 2 and FIG. 3 . Another part of the graphic unit 21 in the same column is opposite to the graphic unit 21 in the next column, and the spacing is larger, as shown at L2 in FIG. 2 and FIG. 3 .

In the process of etching the substrate 10 using the first mask layer 20 as a mask, due to the loading effect of etching, the etchant in the area between adjacent graphic units 21 with a larger spacing is consumed quickly, and the etching rate decreases. The middle part of the active area 11 is insufficiently etched along its extension direction, and the sidewalls of the middle part of the active area 11 are convex. The shape uniformity of the active area 11 itself is poor, and in severe cases, the active area 11 may collapse. To this end, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, wherein the first mask layer on the substrate has a plurality of discrete graphic units arranged in an array, and there is a first gap or a second gap between adjacent graphic units, and the size of the first gap along the first direction is smaller than the size of the second gap along the first direction. By thinning the sidewalls of the graphic units in contact with the larger second gap, the loading effect when etching the substrate is compensated, so that the active area 11 is The width of the region along its extension direction is relatively uniform, thereby improving the performance of the semiconductor structure.

In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

The present disclosure provides a method for manufacturing a semiconductor structure. Referring to FIG5 , the method may include the following steps:

Step S100: providing a substrate.

Referring to FIG. 6 , the material of the substrate 10 may be a semiconductor, such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanium, germanium on insulator (GOI) or silicon on insulator (SOI), or other materials known to those skilled in the art. The substrate 10 may be a doped substrate or an undoped substrate. For example, the substrate 10 is a P-type substrate.

Step S200: forming a first mask layer on a substrate, the first mask layer comprising a plurality of discrete graphic units arranged in an array, with a first gap or a second gap between adjacent graphic units, a size of the first gap in a first direction being smaller than a size of the second gap in the first direction, wherein the first direction is parallel to the surface of the substrate.

Referring to Figures 7 to 10, Figures 8, 9 and 10 are schematic cross-sectional views of points A, B and C in Figure 7, respectively. The cross section shown in Figure 8 is a plane perpendicular to the extension direction of the graphic unit, the cross section shown in Figure 9 is a cross section perpendicular to the extension direction of the bit line and located on the word line, and the cross section shown in Figure 10 is a cross section perpendicular to the extension direction of the bit line and located between adjacent word lines.

As shown in FIGS. 7 to 10 , the first mask layer 20 may be a single layer or a stacked layer. For example, the first mask layer 20 includes a silicon oxide layer 24 disposed on the substrate 10 and a polysilicon layer 25 disposed on the silicon oxide layer 24 .

The first mask layer 20 includes a plurality of pattern units 21, and the pattern units 21 are used to form the active area 11. As shown in FIG. 7 , the plurality of pattern units 21 are independent of each other and do not contact each other, so that a portion of the substrate 10 is exposed. The plurality of pattern units 21 are arranged in an array of multiple rows and columns, wherein the row direction intersects with the column direction and is not perpendicular to it. The column direction may be the extension direction of the pattern unit 21, such as The vertical direction (Y direction in FIG2 ) shown in FIG2 and the row direction (X direction in FIG2 ) are not perpendicular to the column direction. As shown in FIG2 , the row direction is inclined relative to the horizontal direction.

Referring to FIG. 7 again, the graphic units 21 of adjacent columns are staggered along the column direction, that is, the graphic units 21 of each column are not aligned along the direction perpendicular to the column direction (first direction). There is a first gap 22 or a second gap 23 between adjacent graphic units 21, the first gap 22 is the area enclosed by the dotted line in FIG. 7, and the second gap 23 is the area enclosed by the dots in FIG. 7. The size of the first gap 22 in the first direction (as shown at L1 in FIG. 7 to FIG. 10) is smaller than the size of the second gap 23 in the first direction (as shown at L2 in FIG. 7 to FIG. 10). The first direction is parallel to the surface of the substrate 10. The first direction (Z direction) is parallel to the substrate 10, and it can be perpendicular to the column direction of the graphic units 21.

The first gap 22 is located between adjacent graphic units 21 in alternate columns, the second gap 23 is located between two adjacent columns of graphic units 21, and the first gap 22 is connected to the second gap 23. The size of the second gap 23 in the first direction is equal to twice the size of the first gap 22 in the first direction plus the size of the graphic unit 21 in the first direction.

Step S300: forming a protection layer on the substrate, wherein the protection layer covers the sidewalls of the graphic unit exposed in the second gap and fills the first gap.

11 to 15 , the protective layer 30 can be formed on the substrate 10 by deposition or spin coating, and fills between the first gap 22 and the second gap 23. The protective layer 30 fills the first gap 22 and covers the sidewalls of the graphic unit 21 in the second gap 23, but does not fill the second gap 23. The material of the protective layer 30 includes carbon, such as amorphous carbon (Amorphous carbon, a-C) or spin on carbon (SOC), so as to facilitate subsequent removal.

In some possible embodiments, a protective layer is formed on the first mask layer, the protective layer covers the sidewalls of the graphic unit exposed in the second gap and fills the first gap, including: depositing a protective layer on the sidewalls of the graphic unit and the surface facing away from the substrate, and on the substrate, the protective layer fills the first gap, and the protective layer located in the second gap encloses a hole.

As shown in Figures 7 to 14, a protective layer 30 is deposited on the side and top surfaces of the graphic unit 21 and the exposed substrate 10. Since the size of the first gap 22 in the first direction is smaller than the size of the second gap 22 in the first direction, by controlling the thickness of the protective layer 30, the protective layer 30 can fill the first gap 22 and not fill the second gap 23.

In some possible embodiments, the size of the second gap 23 in the second direction is larger than that of the second gap 23 in the second direction. The size of the gap 23 in the first direction, wherein the second direction is perpendicular to the first direction and parallel to the surface of the substrate 10; the thickness of the protective layer 30 is greater than or equal to half of the size of the first gap 22 in the first direction, and the thickness of the protective layer 30 is less than half of the size of the second gap 23 in the first direction.

The second direction may be the extension direction of the graphic unit 21, that is, the column direction of the graphic unit 21, and the second direction is parallel to the substrate 10 and perpendicular to the first direction. The size of the second gap 23 along the second direction is greater than the size of the first gap 22 along the first direction, that is, the spacing between the graphic units 21 along the column direction is the largest. At this time, the thickness of the protective layer 30 is greater than or equal to half of the size of the first gap 22 in the first direction, and less than half of the size of the second gap 23 in the first direction. In this way, along the first direction, the protective layer 30 on the side wall of the graphic unit 21 exposed in the first gap 22 is in contact with each other to form a whole, and the protective layer 30 on the side wall of the graphic unit 21 exposed in the second gap 23 has a certain distance along the first direction and the second direction, so that the protective layer 30 in the second gap 23 is enclosed to form a hole 31.

In other possible embodiments, the size of the second gap 23 in the second direction is smaller than the size of the second gap 23 in the first direction, wherein the second direction is perpendicular to the first direction and parallel to the surface of the substrate 10; the thickness of the protective layer 30 is greater than or equal to half of the size of the first gap 22 in the first direction; the thickness of the protective layer 30 is smaller than half of the size of the second gap 23 in the first direction and smaller than half of the size of the second gap 23 in the second direction.

The size of the second gap 23 in the second direction is smaller than the size of the second gap 23 in the first direction. In order to avoid the protective layer 30 in the second gap 23 from contacting each other along the second direction and filling up the second gap 23, the thickness of the protective layer 30 is greater than or equal to half of the size of the first gap 22 in the first direction and less than half of the size of the second gap 23 in the first direction, and is also less than half of the size of the second gap 23 in the second direction. With such a configuration, along the second direction, there is also a certain distance between the protective layer 30 on the side wall of the graphic unit 21 in the second gap 23, so as to avoid the protective layer 30 on the side wall of the graphic unit 21 in the second gap 23 from contacting each other, so that the protective layer 30 in the second gap 23 can enclose and form a hole 31.

Optionally, the dimension of the first gap 22 in the first direction is less than 20 nm, and correspondingly, the thickness of the protective layer 30 is at least less than or equal to 10 nm. The manufacturing method in the embodiment of the present disclosure can be used to manufacture semiconductor structures with smaller critical dimensions (Critical Dimension, CD for short).

Step S400: Perform a first etching to remove the pattern unit covering the second gap. The protective layer on the sidewall exposes the sidewall of the graphic unit contacting the second gap, and retains the protective layer covering the sidewall of the graphic unit contacting the first gap.

11 to 19, after the first etching is performed, the protective layer 30 located in the second gap 23 is removed, and the protective layer 30 located in the first gap 22 is still retained, so that the side wall of the graphic unit 21 in contact with the second gap 23 is exposed, and the side wall of the graphic unit 21 in contact with the first gap 22 is not exposed. The thickness of the protective layer 30 removed by etching can be equal to the thickness of the deposited protective layer 30, so that the protective layer 30 formed in the second gap 23 and the protective layer 30 on the top surface of the graphic unit 21 are completely removed, and the protective layer 30 in the first gap 22 is removed as little as possible.

In the embodiment where the material of the protective layer 30 is carbon, the etching gas used to remove the protective layer 30 includes oxygen, that is, the protective layer 30 can be removed by an ashing process. The protective layer 30 is relatively thin and can be easily removed by plasma ashing without damaging the surface of the substrate 10, thereby ensuring that the surface of the substrate 10 is smooth.

Step S500: performing a second etching to thin the sidewalls of the graphic unit contacting the second gap, so that the first mask layer is transformed into the second mask layer.

Referring to FIGS. 16 to 19 , after the first etching, the second gap 23 is exposed, and the first gap 22 is still filled with the protective layer 30. At this time, referring to FIGS. 20 to 22 , the second etching is performed to remove the sidewalls of the graphic unit 21 in contact with the second gap 23 along the first direction, so that the first mask layer 20 is transformed into the second mask layer 40. The second mask layer 40 includes a plurality of thinned graphic units 21, and the two opposite sidewalls of the graphic unit 21 along the first direction are both concave.

In some possible embodiments, a second etch is performed to thin the sidewalls of the graphic unit in contact with the second gap so that the first mask layer is transformed into the second mask layer, and the method further includes: while thinning the sidewalls of the graphic unit in contact with the second gap in the first direction, flattening the sidewalls of the graphic unit in contact with the second gap in the second direction.

In the process of forming the graphic unit 21, the sidewalls at both ends of the graphic unit 21 are not flat along the extension direction of the graphic unit 21, and the sidewalls at the ends of the graphic unit 21 are convex at both sides and concave in the middle. For the convenience of drawing, the sidewalls at both ends of the graphic unit 21 in FIG. 7 along the extension direction thereof are not drawn with curvature, and their shapes can be referred to FIG. 2.

This is because in the process of forming the first mask layer 20, the etching pattern obtained by the combination of the parallel and spaced stripe pattern and the staggered circular hole pattern, that is, the pattern unit 21 is obtained by cutting the stripe pattern by the circular hole pattern. The depression inside the strip pattern, that is, the side wall of the end of the graphic unit 21 is convex on both sides and concave in the middle. When etching the substrate 10 with the first mask layer 20 as a mask, this concave shape will also be transferred to the substrate 10 to a certain extent, further making the shape uniformity of the active area 11 itself poor, resulting in leakage or other electrical problems. While etching the side wall of the graphic unit 21 in contact with the second gap 23 in the first direction to be thinned, the side wall of the graphic unit 21 in contact with the second gap 23 in the second direction is also etched. The side wall of the graphic unit 21 in contact with the second gap 23 in the second direction will be thinned and flattened, and the flattening effect is more obvious than the thinning effect, so that the side wall of the graphic unit 21 in contact with the second gap 23 in the second direction is straighter.

Based on the embodiment in which the first mask layer 20 includes a silicon oxide layer 24 disposed on the substrate 10 and a polysilicon layer 25 disposed on the silicon oxide layer 24, the second etching is isotropic etching, and at least the sidewall of the silicon oxide layer 24 in contact with the second gap 23 is thinned. Since the silicon oxide layer 24 and the polysilicon layer 25 are made of different materials and have different etching rates, during isotropic etching, the etching accuracy of the silicon oxide layer 24 is prioritized, and at least the sidewall of the silicon oxide layer 24 in contact with the second gap 23 is thinned to ensure the accuracy of the pattern of the active region 11.

Step S600: removing the protective layer, and performing a third etching on the substrate using the second mask layer as a mask to form a plurality of discrete active regions in the substrate.

Referring to FIGS. 23 to 25 , the protective layer 30 located in the first gap 22 is removed to completely expose the second mask layer 40 . The protective layer 30 can be removed by oxygen etching. The substrate 10 is etched using the second mask layer 40 as a mask to form an active region 11 in the substrate 10 , and the active region 11 corresponds to the graphic unit 21 of the second mask layer 40 .

The side walls of the graphic units 21 of the second mask layer 40 that are spaced relatively large from adjacent graphic units 21 are thinned, which can compensate for the load effect during the third etching. On the one hand, the two long sides of the active area 11 obtained in the cross section parallel to the surface of the substrate 10 along the first direction are relatively straight, and the active area 11 has better uniformity along its extension direction, which can improve defects such as insufficient etching of the active area 11 or graphic collapse.

In addition, by smoothing the side walls relative to each other along the second direction in the graphic unit 21 of the second mask layer 40, the two short sides relative to each other along the second direction in the cross section of the active area 11 parallel to the surface direction of the substrate 10 can be relatively flat, so that the active area 11 obtains a relatively flat profile, further improving the uniformity of the active area 11, reducing defects in the active area 11, and improving the performance of the semiconductor structure.

In some possible embodiments, the protective layer is removed, and the substrate is After performing the third etching to form a plurality of discrete active regions in the substrate (step S600), the method further includes: removing the second mask layer to expose the active regions. It is understood that after forming the active regions, the film layer above the active regions is removed to expose the active regions.

In an embodiment where the first mask layer 20 includes a silicon oxide layer 24 and a polysilicon layer 25, the protective layer is removed, and the substrate is subjected to a third etch using the second mask layer as a mask to form a plurality of discrete active regions in the substrate (step S600). The surface of the active region facing away from the substrate is still covered with at least a portion of the silicon oxide layer.

26 and 27, the top surface of the active region 11 is also covered with silicon oxide to reduce oxidation of the active region 11. In some possible implementations, during the third etching process on the substrate 10, the polysilicon layer 25 in the second mask layer 40 is completely consumed, and the silicon oxide layer 24 in the second mask layer 40 is not consumed, or is not completely consumed, and the silicon oxide layer 24 is retained. In other possible implementations, during the third etching process on the substrate 10, the polysilicon layer 25 is not completely consumed, that is, the polysilicon layer 25 remains, and the remaining polysilicon layer 25 and at most a portion of the silicon oxide layer 24 can be removed, and the silicon oxide layer 24 is completely retained or a portion is retained.

In summary, in the method for manufacturing a semiconductor structure of the embodiment of the present disclosure, a first mask layer 20 is formed on a substrate 10, and the first mask layer 20 includes a plurality of discrete graphic units 21. There is a first gap 22 or a second gap 23 between adjacent graphic units 21, and the size of the first gap 22 along the first direction is smaller than the size of the second gap 23 along the first direction. By forming a protective layer 30 on the sidewall of the graphic unit 21, the protective layer 30 fills the first gap 22 but does not fill the second gap 23, and then removes the protective layer 30 in the second gap 23, and retains the protective layer 30 in the first gap 22, the sidewall of the graphic unit 21 in contact with the second gap 23 is exposed, so that the sidewall of the graphic unit 21 in contact with the second gap 23 can be thinned. In the process of etching the substrate 10, the sidewall of the graphic unit 21 in contact with the second gap 23 is thinned, which can compensate for the load effect that the size of the second gap 23 along the first direction is larger than the size of the first gap 22 along the first direction. On the one hand, the two long sides opposite to each other along the first direction in the cross section of the obtained active area 11 parallel to the surface direction of the substrate 10 are relatively straight, and the uniformity of the active area 11 along its extension direction is better, which can improve defects such as insufficient etching of the active area 11 or pattern collapse; on the other hand, the two short sides opposite to each other along the second direction are relatively flat, without depressions or sharp corners, which can also reduce electrical problems such as leakage of the active area 11 and improve the performance of the semiconductor structure.

In some possible embodiments, a first etching is performed to remove the covering layer in contact with the second gap. The protective layer on the sidewall of the graphic unit of the embodiment of the present invention is removed, the sidewall of the graphic unit contacting the second gap is exposed, and the protective layer covering the sidewall of the graphic unit contacting the first gap is retained (step S400), comprising:

A first etching is performed on the protection layer exposed in the hole and the protection layer located on the surface of the pattern unit facing away from the substrate, exposing the surface of the pattern unit facing away from the substrate and a portion of the sidewall facing the second gap, as well as the substrate.

As shown in FIGS. 11 to 19 , the protective layer 30 on the top surface of the graphic unit 21 and the protective layer 30 in the second gap 23 are removed by etching, so that the top surface of the graphic unit 21 and the sidewall in contact with the second gap 23, as well as the substrate 10 are exposed. After removing part of the protective layer 30, the hole 31 is widened to the second gap 23, that is, the second gap 23 is exposed, and the first gap 22 is not exposed.

Since the protective layer 30 fills the first gap 22, there is no hole 31 in the protective layer 30 located in the first gap 22, and only the top surface is exposed, which is not easy to remove. The protective layer 30 in the second gap 23 encloses and forms a hole 31, and the sidewalls and bottom of the hole 31 are all protective layer 30. The protective layer 30 located on the sidewalls and bottom of the hole 31 can be directly etched along the hole 31. This part of the protective layer 30 has a large etching area and is easy to remove.

It is understandable that, in the process of removing the protective layer 30, the protective layer 30 in the first gap 22 is rarely or almost not removed, and the protective layer 30 in the first gap 22 is retained, so that the side wall of the graphic unit 21 in contact with the first gap 22 is not exposed and is not processed subsequently. The protective layer 30 in the second gap 23 is almost completely removed, so that the side wall of the graphic unit 21 in contact with the second gap 23 is exposed for subsequent processing.

In some possible implementations, the first etching is isotropic etching or anisotropic etching with an inclination angle perpendicular to the surface direction of the substrate 10, and the inclination angle ranges from 5° to 85°. Exemplarily, the first etching can be dry etching or wet etching. Dry etching can achieve isotropic etching or anisotropic etching, while wet etching can only achieve isotropic etching.

Referring to FIG. 15 , during anisotropic etching, the etching direction has an inclination angle of 5° to 85° compared to the perpendicular direction of the substrate 10, that is, the angle between the etching direction and the perpendicular direction of the substrate 10 is 5° to 85°. In this way, the protective layer 30 on the sidewall and bottom of the hole 31 can be removed, so that the required sidewall of the graphic unit 21 is completely exposed, which is convenient for processing the sidewall of the graphic unit 21. The etching direction refers to the direction in which the etching occurs, that is, the etching is only or mainly in the etching direction. occur.

In the embodiment of the present disclosure, the protective layer 30 can be removed by etching through the hole 31, and the protective layer 30 on the side wall and the bottom of the hole 31 needs to be removed. When the protective layer 30 located at the intersection of the bottom and the side wall of the hole 31 is removed by isotropic etching, it is easier to remove the protective layer 30 at this position than by anisotropic etching. In addition, isotropic etching is also easier to implement than anisotropic etching.

In some possible embodiments, a first mask layer is formed on a substrate, the first mask layer includes a plurality of discrete graphic units arranged in an array, a first gap or a second gap is provided between adjacent graphic units, a size of the first gap in a first direction is smaller than a size of the second gap in the first direction, wherein the first direction is parallel to a surface of the substrate (step S100), including:

An initial mask layer is deposited on the substrate 10. The initial mask layer is formed on the substrate 10 by a deposition process or the like, and the initial mask layer covers the substrate 10 and is a whole layer.

After the initial mask layer is formed, the initial mask layer is etched for the fourth time by a self-aligned double patterning process to form a plurality of initial graphic units arranged at intervals. The initial mask layer is etched for the fourth time to remove a portion of the initial mask layer to form a plurality of initial graphic units arranged at intervals, and grooves are formed between adjacent initial graphic units. The fourth etching can be performed by a self-aligned double patterning (SADP) process to make the key dimension uniformity of the formed initial graphic unit better. When performing the fourth etching, the mask layer of the initial mask layer has a stripe pattern.

After the initial graphic unit is formed, the fifth etching is performed to disconnect the initial graphic unit to form a graphic unit 21, and the disconnection positions of adjacent initial graphic units are staggered, and the remaining initial mask layer forms a first mask layer 20. By etching the initial graphic unit, each initial graphic unit is disconnected to form at least two graphic units 21. The disconnection positions of adjacent initial graphic units are staggered so that there is a first gap 22 and a second gap 23 between the formed graphic units 21, and along the first direction, the size of the first gap 22 is smaller than the size of the second gap 23. Wherein, when the fifth etching is performed, the mask layer of the initial graphic unit has a circular hole pattern, so that the side wall of the end of the formed graphic unit 21 is convex on both sides and concave in the middle.

The present disclosure also provides a semiconductor structure, which includes an active region 11. The active region 11 is formed by the above-mentioned manufacturing method. The cross section of the formed active region 11 parallel to the surface direction of the substrate 10 is a rectangle with two flat short sides and two straight long sides, so that the uniformity of the active region 11 is good. The performance of the conductor structure is better.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

A method for manufacturing a semiconductor structure, comprising:

Providing a substrate (10);

A first mask layer (20) is formed on the substrate (10), wherein the first mask layer (20) comprises a plurality of discrete graphic units (21) arranged in an array, wherein a first gap (22) or a second gap (23) is provided between adjacent graphic units (21), wherein the size of the first gap (22) in a first direction is smaller than the size of the second gap (23) in the first direction, wherein the first direction is parallel to the surface of the substrate (10);

forming a protective layer (30) on the substrate (10), wherein the protective layer (30) covers the side walls of the graphic unit (21) exposed in the second gap (23) and fills the first gap (22);

Performing a first etching process to remove the protective layer (30) covering the side wall of the graphic unit (21) in contact with the second gap (23), exposing the side wall of the graphic unit (21) in contact with the second gap (23), and retaining the protective layer (30) covering the side wall of the graphic unit (21) in contact with the first gap (22);

Performing a second etching to thin the sidewall of the graphic unit (21) in contact with the second gap (23), so that the first mask layer (20) is transformed into a second mask layer (40);

The protective layer (30) is removed, and a third etching is performed on the substrate (10) using the second mask layer (40) as a mask, so as to form a plurality of discrete active regions (11) in the substrate (10).
The manufacturing method according to claim 1, wherein a protective layer (30) is formed on the substrate (10), the protective layer (30) covers the sidewalls of the graphic unit (21) exposed in the second gap (23) and fills the first gap (22), comprising:

A protective layer (30) is deposited on the sidewalls of the graphic unit (21) and the surface facing away from the substrate (10), as well as on the substrate (10); the protective layer (30) fills the first gap (22); and the protective layer (30) located in the second gap (23) encloses a hole (31).
The manufacturing method according to claim 2, wherein performing a first etching to remove the protective layer (30) covering the side wall of the graphic unit (21) in contact with the second gap (23), exposing the side wall of the graphic unit (21) in contact with the second gap (23), and retaining the protective layer (30) covering the side wall of the graphic unit (21) in contact with the first gap (22), comprises:

The first etching is performed on the protective layer (30) exposed in the hole (31) and the protective layer (30) located on the surface of the graphic unit (21) facing away from the substrate (10), thereby exposing the surface of the graphic unit (21) facing away from the substrate (10) and a portion of the side wall facing the second gap (23), as well as the substrate (10).
The manufacturing method according to any one of claims 1 to 3, wherein a size of the second gap (23) in a second direction is smaller than a size of the second gap (23) in the first direction, wherein the second direction is perpendicular to the first direction and parallel to the surface of the substrate (10);

The thickness of the protective layer (30) is greater than or equal to half the size of the first gap (22) in the first direction;

The thickness of the protective layer (30) is less than half of the size of the second gap (23) in the first direction, and is less than half of the size of the second gap (23) in the second direction.
The manufacturing method according to claim 4, wherein a size of the first gap (22) in the first direction is less than 20 nm.
The manufacturing method according to claim 4 or 5, wherein a second etching is performed to thin the sidewall of the graphic unit (21) in contact with the second gap (23) so that the first mask layer (20) is transformed into a second mask layer (40), and further comprising:

While thinning the side wall of the graphic unit (21) in contact with the second gap (23) in the first direction, the side wall of the graphic unit (21) in contact with the second gap (23) in the second direction is flattened.
The manufacturing method according to any one of claims 1 to 6, wherein the first etching is isotropic etching or anisotropic etching having an inclination angle with respect to a direction perpendicular to the surface of the substrate (10), and the inclination angle ranges from 5° to 85°.
The manufacturing method according to any one of claims 1 to 7, wherein the material of the protective layer (30) comprises carbon.
The manufacturing method according to claim 8, wherein the etching gas used when removing the protective layer (30) includes oxygen.
The manufacturing method according to any one of claims 1 to 9, wherein after removing the protective layer (30) and performing a third etching on the substrate (10) using the second mask layer (40) as a mask to form a plurality of discrete active areas (11) in the substrate (10), the method further comprises:

The second mask layer (40) is removed to expose the active area (11).
The manufacturing method according to any one of claims 1 to 10, wherein the first mask layer (20) comprises a silicon oxide layer (24) disposed on the substrate (10), and a polysilicon layer (25) disposed on the silicon oxide layer (24).
The manufacturing method according to claim 11, wherein after the protective layer (30) is removed and the substrate (10) is subjected to a third etching process using the second mask layer (40) as a mask to form a plurality of discrete active areas (11) in the substrate (10), the surface of the active area (11) facing away from the substrate (10) is still covered with at least a portion of the silicon oxide layer (24).
The manufacturing method according to claim 11 or 12, wherein the second etching is isotropic etching, which at least thins the side wall of the silicon oxide layer (24) in contact with the second gap (23).
The manufacturing method according to any one of claims 1 to 13, wherein a first mask layer (20) is formed on the substrate (10), the first mask layer (20) comprising a plurality of discrete graphic units (21) arranged in an array, a first gap (22) or a second gap (23) is provided between adjacent graphic units (21), a size of the first gap (22) in a first direction is smaller than a size of the second gap (23) in the first direction, wherein the first direction is parallel to the surface of the substrate (10), comprising:

depositing an initial mask layer on the substrate (10);

Performing a fourth etching on the initial mask layer by a self-aligned double process to form a plurality of initial graphic units arranged at intervals;

A fifth etching is performed to disconnect the initial graphic unit to form the graphic unit (21), the disconnection positions of adjacent initial graphic units are staggered, and the remaining initial mask layer forms the first mask layer (20).
A semiconductor structure comprising:

An active region (11), wherein the active region (11) is formed by the manufacturing method according to any one of claims 1 to 14, and a cross section of the active region (11) parallel to the surface of the substrate (10) is a rectangle with two flat short sides and two straight long sides.