WO2024101174A1

WO2024101174A1 - Semiconductor device

Info

Publication number: WO2024101174A1
Application number: PCT/JP2023/038769
Authority: WO
Inventors: 弘招松原
Original assignee: ローム株式会社
Priority date: 2022-11-10
Filing date: 2023-10-26
Publication date: 2024-05-16

Abstract

This semiconductor device comprises: a substrate having a principal surface and a back surface that face opposite directions from one another in a first direction; a wiring layer disposed on the principal surface; terminals disposed on the back surface; a redistribution layer accommodated in the substrate and connected to the wiring layer and the terminals; and a semiconductor element that is electrically connected to the wiring layer. The substrate has end surfaces that each face a direction orthogonal to the first direction. The semiconductor device additionally comprises dummy wiring that is at least partially accommodated in the substrate. The dummy wiring connects to the terminals and is exposed on the end surfaces.

Description

Semiconductor Device

This disclosure relates to a semiconductor device.

Patent Document 1 discloses an example of a semiconductor device having a multi-layered substrate. In this semiconductor device, multiple semiconductor elements are mounted on the substrate. A wiring pattern is provided on one side of the substrate. A back electrode is provided on the other side of the substrate. An intermediate layer that provides electrical conductivity between the wiring pattern and the back electrode is provided inside the substrate. Each of the multiple semiconductor elements is electrically connected to the wiring pattern by wire bonding.

In the semiconductor device disclosed in Patent Document 1, when viewed in the thickness direction of the substrate, the back electrode is located away from the periphery of the substrate. Therefore, when the semiconductor device is mounted on a wiring substrate, the volume of solder adhering to the back electrode is relatively small. This poses the problem that the bonding strength of the semiconductor device to the wiring substrate is insufficient.

JP 2015-53465 A

One of the objectives of this disclosure is to provide a semiconductor device that is an improvement over conventional semiconductor devices. In particular, in view of the above circumstances, one of the objectives of this disclosure is to provide a semiconductor device that can improve the bonding strength of the device to the wiring board.

A semiconductor device provided by one aspect of the present disclosure includes a substrate having a main surface and a back surface facing opposite each other in a first direction, a wiring layer disposed on the main surface, a terminal disposed on the back surface, a redistribution layer housed in the substrate and connected to the wiring layer and the terminal, and a semiconductor element conducting to the wiring layer. The substrate has an end surface facing a direction perpendicular to the first direction, and further includes a dummy wiring, at least a portion of which is housed in the substrate. The dummy wiring is connected to the terminal and is exposed from the end surface.

The above configuration makes it possible to improve the bonding strength of the semiconductor device to the wiring board.

Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a bottom view of the semiconductor device shown in FIG. FIG. 3 is a right side view of the semiconductor device shown in FIG. FIG. 4 is a front view of the semiconductor device shown in FIG. FIG. 5 is a cross-sectional view taken along line VV in FIG. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. FIG. 8 is a partially enlarged plan view of the semiconductor device shown in FIG. 1, with the sealing resin not shown. FIG. 9 is a partially enlarged view of FIG. 4 and corresponds to FIG. FIG. 10 is a cross-sectional view taken along line XX in FIG. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. FIG. 12 is a partially enlarged plan view of the semiconductor device according to the second embodiment of the present disclosure, with the sealing resin not shown. FIG. 13 is a partially enlarged front view of the semiconductor device shown in FIG. 12 and corresponds to FIG. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. FIG. 15 is a plan view of a semiconductor device according to a third embodiment of the present disclosure. 16 is a bottom view of the semiconductor device shown in FIG. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. FIG. 19 is a partially enlarged view of FIG. 20A to 20C are cross-sectional views for explaining the manufacturing process of the semiconductor device shown in FIG. 21A to 21C are cross-sectional views for explaining the manufacturing process of the semiconductor device shown in FIG. 22A to 22C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. 23A to 23C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG.

The form for implementing this disclosure will be explained with reference to the attached drawings.

First embodiment:
A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to Figures 1 to 11. The semiconductor device A10 includes a base material 10, a wiring layer 21, a plurality of terminals 22, a rewiring layer 23, a plurality of dummy wirings 30, a semiconductor element 41, a plurality of passive elements 42, a sealing resin 50, an insulating layer 61, and a plurality of heat dissipation layers 62. The semiconductor device A10 is in a resin package format that is surface-mounted on a wiring board. The resin package format is a QFN (quad flat non-leaded package) in which a plurality of leads do not protrude from the sealing resin 50. Here, FIG. 8 omits the sealing resin 50 for ease of understanding.

In describing the semiconductor device A10, for convenience, an example of the normal direction of the main surface 11 of the substrate 10 described below is referred to as the "first direction z." An example of a direction perpendicular to the first direction z is referred to as the "second direction x." An example of a direction perpendicular to the first direction z and the second direction x is referred to as the "third direction y." As shown in FIG. 1, the semiconductor device A10 is rectangular when viewed in the first direction z.

As shown in Figures 5 to 7, the substrate 10 supports the wiring layer 21 and the sealing resin 50. The substrate 10 has electrical insulation properties. An example of the material of the substrate 10 is black epoxy resin. The substrate 10 has a main surface 11, a back surface 12, and multiple end surfaces 13. The main surface 11 and the back surface 12 face opposite each other in the first direction z. The main surface 11 faces the wiring layer 21. When the semiconductor device A10 is mounted on a wiring board, the back surface 12 faces the wiring board. The multiple end surfaces 13 face in a direction perpendicular to the first direction z. Each of the multiple end surfaces 13 is connected to the main surface 11 and the back surface 12. The multiple end surfaces 13 include two first end surfaces 131 facing the second direction x and two second end surfaces 132 facing the third direction y.

3 to 7, the substrate 10 has a first substrate 101, a second substrate 102, and a third substrate 103. The first substrate 101 includes a back surface 12. The second substrate 102 includes a main surface 11. When viewed in the first direction z, the second substrate 102 overlaps the first substrate 101. The third substrate 103 is located between the first substrate 101 and the second substrate 102 in the first direction z. The third substrate 103 is in contact with each of the first substrate 101 and the second substrate 102. The third substrate 103 is stacked on the first substrate 101. The second substrate 102 is stacked on the third substrate 103. As a result, in the semiconductor device A10, the substrate 10 has a multi-layer structure made up of the first substrate 101, the second substrate 102, and the third substrate 103. Each of the first substrate 101, the second substrate 102, and the third substrate 103 includes a plurality of end surfaces 13.

The wiring layer 21 is disposed on the main surface 11 of the substrate 10, as shown in Figs. 5 to 7. The wiring layer 21, together with the multiple terminals 22 and the rewiring layer 23, constitutes a conductive path between the semiconductor element 41 and the multiple passive elements 42 and the wiring board on which the semiconductor device A10 is mounted. The wiring layer 21 contains, for example, copper (Cu).

As shown in Figures 5 to 7, when viewed in the first direction z, the wiring layer 21 is separated from the periphery 111 of the main surface 11 of the substrate 10.

The multiple terminals 22 are arranged on the rear surface 12 of the substrate 10 as shown in FIG. 2 and FIG. 5 to FIG. 7. When viewed in the first direction z, each of the multiple terminals 22 overlaps the peripheral edge 121 of the rear surface 12. The multiple terminals 22 include, for example, copper.

As shown in FIG. 2, the multiple terminals 22 include multiple first terminals 221 and four second terminals 222. The multiple first terminals 221 include multiple first terminals 221 arranged along the second direction x and multiple first terminals 221 arranged along the third direction y. Each of the multiple first terminals 221 is rectangular. The four second terminals 222 are individually arranged at the four corners of the rear surface 12 of the substrate 10. Each of the four second terminals 222 is square. When viewed in the first direction z, the dimensions of each of the four second terminals 222 in the second direction x and the third direction y are smaller than the dimensions of each of the multiple first terminals 221 in the long side direction.

The redistribution layer 23 is housed in the substrate 10, as shown in Figs. 5 to 7. The redistribution layer 23 is connected to the wiring layer 21. Furthermore, the redistribution layer 23 is connected to at least some of the first terminals 221 of the terminals 22. As a result, at least some of the first terminals 221 are electrically connected to the wiring layer 21. Alternatively, the redistribution layer 23 may be connected to each of the four second terminals 222 of the terminals 22. The redistribution layer 23 contains, for example, copper.

As shown in Figures 5 to 7, the redistribution layer 23 has a plurality of vias 231. Each of the plurality of vias 231 is connected to at least one of the wiring layer 21 and each of the plurality of first terminals 221. Each of the plurality of vias 231 is spaced apart from the plurality of end faces 13 of the substrate 10. The plurality of vias 231 include a plurality of first vias 231A and a plurality of second vias 231B. The plurality of first vias 231A are accommodated in the first substrate 101. Each of the plurality of first vias 231A is connected to one of the plurality of first terminals 221 among the plurality of terminals 22. The plurality of second vias 231B are accommodated in the second substrate 102. Each of the plurality of second vias 231B is connected to the wiring layer 21.

As shown in Figures 5 to 7, the redistribution layer 23 has an intermediate layer 232. The intermediate layer 232 is connected to each of the multiple first vias 231A and each of the multiple second vias 231B. The intermediate layer 232 has a first intermediate wiring 232A, a second intermediate wiring 232B, and multiple intermediate vias 232C. The first intermediate wiring 232A is sandwiched between the third substrate 103 and the first substrate 101, and is connected to each of the multiple first vias 231A. The second intermediate wiring 232B is sandwiched between the third substrate 103 and the second substrate 102, and is connected to each of the multiple second vias 231B. The multiple intermediate vias 232C are housed in the third substrate 103. Each of the multiple intermediate vias 232C is connected to the first intermediate wiring 232A and the second intermediate wiring 232B.

The semiconductor element 41 is electrically connected to the wiring layer 21. In the semiconductor device A10, the semiconductor element 41 is an LSI (Large Scale Integration). As shown in Figures 5 and 6, the semiconductor element 41 has a plurality of electrodes 411 facing the wiring layer 21. Each of the plurality of electrodes 411 is conductively joined to the wiring layer 21 via a bonding layer 49. The bonding layer 49 is, for example, solder. Alternatively, the bonding layer 49 may be a sintered metal containing silver (Ag) or the like.

Each of the multiple passive elements 42 is electrically connected to the wiring layer 21. As shown in FIG. 1, the multiple passive elements 42 are located on one side of the semiconductor element 41 in the second direction x. The multiple passive elements 42 are arranged along the third direction y. Each of the multiple passive elements 42 is a resistor, a capacitor, or an inductor. Each of the multiple passive elements 42 has two electrodes 421 that are spaced apart from each other in a direction perpendicular to the first direction z. Each of the two electrodes 421 is electrically conductively connected to the wiring layer 21 via a bonding layer 49.

As shown in Figures 5 to 7, the sealing resin 50 covers the wiring layer 21, the semiconductor element 41, and the multiple passive elements 42. The sealing resin 50 is in contact with the main surface 11 of the substrate 10.

As shown in Figures 3 to 7, the sealing resin 50 has a top surface 51 and multiple side surfaces 52. The top surface 51 faces the same side as the main surface 11 of the substrate 10 in the first direction z. Each of the multiple side surfaces 52 faces in a direction perpendicular to the first direction z and is connected to the top surface 51. Each of the multiple side surfaces 52 is flush with each of the multiple end surfaces 13 of the substrate 10. The sealing resin 50 has electrical insulation properties. One example of a material for the sealing resin 50 is a black epoxy resin.

As shown in Figures 5 and 6, at least a portion of each of the multiple dummy wirings 30 is housed in the substrate 10. As shown in Figures 3 to 6, the multiple dummy wirings 30 are individually connected to multiple terminals 22. Each of the multiple dummy wirings 30 is exposed from one of the multiple end faces 13 of the substrate 10. The multiple dummy wirings 30 include, for example, copper.

As shown in Figures 9 to 11, each of the multiple dummy wirings 30 has a first dummy via portion 31, a top portion 34, and multiple relay portions 35. The first dummy via portion 31 is housed in the substrate 10 and is connected to one of the multiple terminals 22. The first dummy via portion 31 is exposed from one of the multiple end faces 13 of the substrate 10. The first dummy via portion 31 is separated from the multiple vias 231 of the redistribution layer 23. In the semiconductor device A10, the minimum dimension of the first dummy via portion 31 is greater than the dimension of each of the multiple vias 231 when viewed in the first direction z.

As shown in Figures 9 to 11, the first dummy via portion 31 has a first portion 311, a second portion 312, and a third portion 313. The first portion 311 is housed in the first substrate 101 and is connected to one of the multiple terminals 22. The second portion 312 is housed in the second substrate 102. The third portion 313 is housed in the third substrate 103. The first portion 311, the second portion 312, and the third portion 313 are separated from each other in the first direction z. When viewed in the first direction z, the second portion 312 overlaps each of the first portion 311 and the third portion 313.

As shown in Figures 8, 10 and 11, the top 34 is disposed on the main surface 11 of the substrate 10. The top 34 is connected to the second portion 312 of the first dummy via portion 31. When viewed in the first direction z, the top 34 overlaps the periphery 111 of the main surface 11 and the entire first dummy via portion 31. The top 34 is spaced apart from the wiring layer 21. A portion of the top 34 is covered by the sealing resin 50. The top 34 is exposed from one of the multiple side surfaces 52 of the sealing resin 50.

As shown in Figures 9 to 11, the multiple relay parts 35 are located between the first substrate 101 and the second substrate 102. The multiple relay parts 35 are housed in the substrate 10. Each of the multiple relay parts 35 is exposed from one of the multiple end faces 13 of the substrate 10. When viewed in the first direction z, the apex 34 overlaps each of the multiple relay parts 35. Each of the multiple relay parts 35 includes a portion that overlaps the first dummy via part 31 when viewed in the first direction z, and a portion that protrudes further than the first dummy via part 31 in a direction perpendicular to the first direction z.

As shown in Figures 9 to 11, the multiple relay portions 35 include a first relay portion 351 and a second relay portion 352. The first relay portion 351 is sandwiched between the third substrate 103 and the first substrate 101, and is connected to the third portion 313 and the first portion 311 of the first dummy via portion 31. The second relay portion 352 is sandwiched between the third substrate 103 and the second substrate 102, and is connected to the third portion 313 and the second portion 312 of the first dummy via portion 31. As a result, the top portion 34 is electrically connected to one of the multiple terminals 22 via the first dummy via portion 31 and the multiple relay portions 35.

As shown in FIG. 8, the dummy wiring 30 connected to four of the second terminals 222 among the multiple terminals 22 is exposed from either of the two first end faces 131 and either of the two second end faces 132.

In addition to the configuration described above, the dummy wiring 30 may have a configuration that does not include multiple relay portions 35, but instead includes an integrated first dummy via portion 31 that reaches the top portion 34 from one of the multiple terminals 22.

As shown in FIG. 2 and FIG. 5 to FIG. 7, the insulating layer 61 covers the rear surface 12 of the substrate 10. When viewed in the first direction z, the insulating layer 61 overlaps the peripheral edge 121 of the rear surface 12. Each of the multiple terminals 22 is exposed from the insulating layer 61. The insulating layer 61 is, for example, a solder resist. The dimension of the insulating layer 61 in the first direction z is smaller than the dimension of each of the first substrate 101, the second substrate 102, and the third substrate 103 in the first direction z.

The multiple heat dissipation layers 62 are disposed on the rear surface 12 of the substrate 10, as shown in FIG. 2 and FIG. 5 to FIG. 7. The multiple heat dissipation layers 62 are surrounded by multiple terminals 22. Each of the multiple heat dissipation layers 62 is exposed from the insulating layer 61. When viewed in the first direction z, the semiconductor element 41 overlaps each of the multiple heat dissipation layers 62. The multiple heat dissipation layers 62 contain, for example, copper. Each of the multiple heat dissipation layers 62 is separated from the redistribution layer 23.

Next, the effects of the semiconductor device A10 will be explained.

The semiconductor device A10 includes a substrate 10, a wiring layer 21 disposed on the main surface 11 of the substrate 10, a terminal 22 disposed on the rear surface 12 of the substrate 10, a rewiring layer 23 housed in the substrate 10, and a semiconductor element 41 that is conductive to the wiring layer 21. The rewiring layer 23 is connected to the wiring layer 21 and the terminal 22. The semiconductor device A10 further includes a dummy wiring 30 at least a part of which is housed in the substrate 10. The dummy wiring 30 is connected to the terminal 22 and is exposed from the end surface 13 of the substrate 10. With this configuration, when the semiconductor device A10 is mounted on a wiring board, molten solder adheres to the terminal 22 and the dummy wiring 30. As a result, a solder fillet is formed in contact with the dummy wiring 30. Therefore, with this configuration, the semiconductor device A10 can improve the bonding strength of the semiconductor device A10 to the wiring board.

Furthermore, the solder fillet is exposed to the outside of both the semiconductor device A10 and the wiring board. As a result, after the semiconductor device A10 is mounted on the wiring board, the mounting state of the semiconductor device A10 on the wiring board can be easily confirmed by visual inspection of the appearance.

The redistribution layer 23 has a via 231 connected to at least one of the wiring layer 21 and the terminal 22. The dummy wiring 30 has a first dummy via portion 31 connected to the terminal 22. The via 231 is spaced apart from the end face 13 of the substrate 10. The first dummy via portion 31 is exposed from the end face 13 and is spaced apart from the via 231. With this configuration, the first dummy via portion 31, which is part of the dummy wiring 30, can be formed simultaneously (or approximately simultaneously) with the formation of the via 231, which is part of the redistribution layer 23.

The dummy wiring 30 is disposed on the main surface 11 of the substrate 10 and has a top 34 that is connected to the first dummy via portion 31. When viewed in the first direction z, the top 34 overlaps the periphery 111 of the main surface 11. With this configuration, the top 34 can be used as a conductive path when the dummy wiring 30 is formed by electrolytic plating. Furthermore, the surface of the top 34 that faces a direction perpendicular to the first direction z can be exposed from the end surface 13 of the substrate 10 together with the first dummy via portion 31. This allows the volume of the solder fillet in contact with the dummy wiring 30 to be further increased.

When viewed in the first direction z, the top 34 overlaps the entire first dummy via portion 31. This configuration makes it possible to prevent damage to the first dummy via portion 31 when the dummy wiring 30 is formed by electrolytic plating.

In the semiconductor device A10, the minimum dimension of the first dummy via portion 31 is larger than the dimension of the via 231 of the redistribution layer 23 when viewed in the first direction z. This configuration is effective when it is possible to form a first dummy via portion 31 that is larger than the via 231.

When viewed in the first direction z, the wiring layer 21 is spaced apart from the main surface 11 of the substrate 10. This configuration can prevent the wiring layer 21 from coming into contact with a dicing blade or the like when the semiconductor device A10 is diced into individual pieces during the manufacturing process of the semiconductor device A10. This prevents metal burrs from being generated on the wiring layer 21, thereby preventing short circuits between the wiring layer 21 and the dummy wiring 30 caused by the metal burrs.

The top 34 is separated from the wiring layer 21. This configuration makes it possible to prevent a short circuit between the wiring layer 21 and the dummy wiring 30.

The semiconductor device A10 further includes an insulating layer 61 that covers the rear surface 12 of the substrate 10. The terminals 22 are exposed from the insulating layer 61. This configuration makes it possible to prevent short circuits in the conductive paths of the semiconductor device A10 caused by solder when the semiconductor device A10 is mounted on a wiring board.

The semiconductor device A10 further includes a heat dissipation layer 62 disposed on the rear surface 12 of the substrate 10. The heat dissipation layer 62 is exposed from the insulating layer 61. When viewed in the first direction z, the semiconductor element 41 overlaps the heat dissipation layer 62. With this configuration, heat generated from the semiconductor element 41 can be efficiently dissipated to the outside via the substrate 10 and the heat dissipation layer 62.

The semiconductor device A10 includes a plurality of terminals 22. The plurality of terminals 22 include a plurality of first terminals 221 that are electrically connected to the wiring layer 21, and four second terminals 222 that are arranged at the four corners of the rear surface 12 of the substrate 10. Dummy wiring 30 is connected to each of the four second terminals 222. Unlike the plurality of first terminals 221, the four second terminals 222 are not electrically connected to the wiring layer 21. With this configuration, when thermal stress occurs at the interface between the wiring board and the plurality of terminals 22, the thermal stress can be concentrated on the four second terminals 222. This reduces the thermal stress that occurs at the interface between the wiring board and the plurality of first terminals 221, and thus suppresses the occurrence of cracks in the solder at the interface.

Second embodiment:
A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 12 to 14. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. Here, for ease of understanding, Figure 12 omits the illustration of the sealing resin 50. Figure 13 corresponds to Figure 9 showing the semiconductor device A10.

In semiconductor device A20, the configuration of the multiple dummy wirings 30 differs from that of semiconductor device A10.

First, the dummy wiring 30 connected to one of the first terminals 221 among the terminals 22 will be described. As shown in FIG. 13, the dummy wiring 30 has a first dummy via portion 31, a second dummy via portion 32, a third dummy via portion 33, a top portion 34, and a number of relay portions 35. Of these, the configuration of the top portion 34 and each of the multiple relay portions 35 is the same as that of the semiconductor device A10.

As shown in Figures 12 and 13, the second dummy via portion 32 is located next to the first dummy via portion 31 in either the second direction x or the third direction y. The second dummy via portion 32 is housed in the substrate 10 and is connected to one of the multiple first terminals 221 and the top 34. The second dummy via portion 32 is exposed from one of the multiple end faces 13 of the substrate 10. The second dummy via portion 32 is separated from the multiple vias 231 of the redistribution layer 23 and the first dummy via portion 31. When viewed in the first direction z, the top 34 overlaps the entire second dummy via portion 32.

13 and 14, the second dummy via portion 32 has a fourth portion 321, a fifth portion 322, and a sixth portion 323. The fourth portion 321 is housed in the first substrate 101 and is connected to one of the plurality of first terminals 221 and the first relay portion 351. The fifth portion 322 is housed in the second substrate 102 and is connected to the top portion 34 and the second relay portion 352. The sixth portion 323 is housed in the third substrate 103 and is connected to the first relay portion 351 and the second relay portion 352. The fourth portion 321, the fifth portion 322, and the sixth portion 323 are separated from each other in the first direction z. When viewed in the first direction z, the fifth portion 322 overlaps with each of the fourth portion 321 and the sixth portion 323.

As shown in Figures 12 and 13, the third dummy via portion 33 is located on the opposite side to the first dummy via portion 31 with respect to the second dummy via portion 32. The third dummy via portion 33 is housed in the substrate 10 and is connected to one of the multiple first terminals 221 and the top portion 34. The third dummy via portion 33 is exposed from one of the multiple end faces 13 of the substrate 10. The third dummy via portion 33 is separated from the multiple vias 231 of the redistribution layer 23 and from the first dummy via portion 31 and the second dummy via portion 32. When viewed in the first direction z, the top portion 34 overlaps the entire third dummy via portion 33.

13, the third dummy via portion 33 has a seventh portion 331, an eighth portion 332, and a ninth portion 333. The seventh portion 331 is housed in the first substrate 101 and is connected to one of the plurality of first terminals 221 and the first relay portion 351. The eighth portion 332 is housed in the second substrate 102 and is connected to the top portion 34 and the second relay portion 352. The ninth portion 333 is housed in the third substrate 103 and is connected to the first relay portion 351 and the second relay portion 352. The seventh portion 331, the eighth portion 332, and the ninth portion 333 are separated from each other in the first direction z. When viewed in the first direction z, the eighth portion 332 overlaps with each of the seventh portion 331 and the ninth portion 333.

When viewed in the first direction z, the maximum dimension of each of the first dummy via portion 31, the second dummy via portion 32, and the third dummy via portion 33 is approximately equal to the maximum dimension of each of the multiple vias 231 in the redistribution layer 23.

As shown in FIG. 13, each of the multiple relay sections 35 is connected to a first dummy via section 31, a second dummy via section 32, and a third dummy via section 33.

Next, the dummy wiring 30 connected to one of the four second terminals 222 out of the multiple terminals 22 will be described. As shown in FIG. 13, the dummy wiring 30 has a first dummy via portion 31, two second dummy via portions 32, two third dummy via portions 33, a top portion 34, and multiple relay portions 35. Except for the arrangement of the first dummy via portion 31, the two second dummy via portions 32, and the two third dummy via portions 33, the configuration of the dummy wiring 30 connected to one of the multiple first terminals 221 described above is the same.

As shown in FIG. 12, one of the two second dummy via portions 32 is located next to the first dummy via portion 31 in the second direction x. The other second dummy via portion 32 is located next to the first dummy via portion 31 in the third direction y. One of the two third dummy via portions 33 is located on the opposite side to the first dummy via portion 31 with respect to the one second dummy via portion 32 mentioned above. The other third dummy via portion 33 is located on the opposite side to the first dummy via portion 31 with respect to the other second dummy via portion 32 mentioned above. As a result, the first dummy via portion 31 is exposed from either of the two first end faces 131 of the substrate 10 and either of the two second end faces 132 of the substrate 10. The two second dummy via portions 32 are individually exposed from one of the two first end faces 131 and one of the two second end faces 132. The two third dummy via portions 33 are individually exposed from one of the two first end faces 131 and one of the two second end faces 132.

Next, the effects of the semiconductor device A20 will be explained.

The semiconductor device A20 includes a substrate 10, a wiring layer 21 disposed on the main surface 11 of the substrate 10, a terminal 22 disposed on the rear surface 12 of the substrate 10, a rewiring layer 23 housed in the substrate 10, and a semiconductor element 41 that is conductive to the wiring layer 21. The rewiring layer 23 is connected to the wiring layer 21 and the terminal 22. The semiconductor device A20 further includes a dummy wiring 30 at least a part of which is housed in the substrate 10. The dummy wiring 30 is connected to the terminal 22 and is exposed from the end surface 13 of the substrate 10. Therefore, according to this configuration, the semiconductor device A20 can also improve the bonding strength of the semiconductor device A20 to the wiring board. Furthermore, the semiconductor device A20 has a configuration common to the semiconductor device A10, and thereby achieves the same effects as the semiconductor device A10.

In the semiconductor device A20, the first dummy via portion 31 has a second dummy via portion 32 that is connected to the terminal 22 and the top portion 34. The second dummy via portion 32 is exposed from the end face 13 of the substrate 10, and is separated from both the via 231 of the redistribution layer 23 and the first dummy via portion 31. This configuration is effective when there is a constraint that the maximum dimension of the first dummy via portion 31 must be approximately equal to the maximum dimension of the via 231 when viewed in the first direction z. This makes it possible to prevent the area of the dummy wiring 30 exposed from the end face 13 from being excessively reduced.

In the above case, the first dummy via portion 31 has a relay portion 35 located between the first substrate 101 and the second substrate 102. The relay portion 35 is exposed from the end face 13 of the substrate 10 and is connected to the first dummy via portion 31 and the second dummy via portion 32. By adopting this configuration, the area of the dummy wiring 30 exposed from the end face 13 can be increased.

When viewed in the first direction z, the apex 34 overlaps the entire first dummy via portion 31 and the entire second dummy via portion 32. This configuration makes it possible to prevent damage to the first dummy via portion 31 and the second dummy via portion 32 when the dummy wiring 30 is formed by electrolytic plating.

Third embodiment:
A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to Fig. 15 to Fig. 19. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted.

The semiconductor device A30 differs from the semiconductor device A10 in the configuration of the sealing resin 50 and in the additional inclusion of multiple coating layers 70.

As shown in Figures 16 to 19, each of the multiple side surfaces 52 of the sealing resin 50 includes a first region 521 and a second region 522. The first region 521 is connected to the top surface 51 and faces a direction perpendicular to the first direction z. The second region 522 is located on the opposite side of the top surface 51 in the first direction z with the first region 521 as a reference, and is connected to the first region 521. When viewed in the first direction z, the first region 521 overlaps the top surface 51.

The multiple coating layers 70 are exposed to the outside, as shown in Figures 16 to 18. Any of the multiple coating layers 70 covers any of the multiple terminals 22 and an area of the dummy wiring 30 connected thereto that is exposed from any of the multiple end faces 13 of the substrate 10. Additionally, any of the multiple coating layers 70 covers the top 34 of any of the multiple dummy wirings 30 that is exposed from any of the multiple side faces 52 of the sealing resin 50. Furthermore, some of the multiple coating layers 70 individually cover the multiple heat dissipation layers 62.

The multiple coating layers 70 are conductors containing gold (Au). The multiple coating layers 70 are conductively bonded to the wiring board via solder, thereby mounting the semiconductor device A10 on the wiring board. Each of the multiple coating layers 70 includes multiple metal layers. The multiple metal layers are stacked in the order of a nickel (Ni) layer and a gold layer, starting from the side closer to one of the multiple terminals 22 or the multiple heat dissipation layers 62. Alternatively, the multiple metal layers may be stacked in the order of a nickel layer, a palladium (Pd) layer and a gold layer, starting from the side closer to one of the multiple terminals 22 or the multiple heat dissipation layers 62.

Next, an example of a manufacturing method for semiconductor device A30 will be described with reference to Figures 20 to 23. Here, the cross-sectional positions of each of Figures 20 to 23 are the same (or approximately the same) as the cross-sectional position of Figure 17.

First, as shown in FIG. 20, the sealing resin 50 is formed and an insulating layer 61 is placed on the back surface 12 of the substrate 10, and then a support member 80 is attached to the top surface 51 of the sealing resin 50. The support member 80 is, for example, a dicing tape.

21, a first blade 81 having a width b1 is used to remove a portion of each of the base material 10, the sealing resin 50, and the insulating layer 61, a portion of each of the multiple terminals 22, and a portion of each of the multiple dummy wirings 30, thereby forming a plurality of grooves 83 recessed in the first direction z. The multiple grooves 83 are formed in a lattice pattern along each of the second direction x and the third direction y.

22, multiple coating layers 70 are formed to individually cover the multiple terminals 22 and each area of the multiple heat dissipation layers 62 exposed to the outside from the insulating layer 61, and the multiple dummy wirings 30 exposed to the outside from the substrate 10 and the sealing resin 50. The multiple coating layers 70 are formed by electroless plating.

Finally, as shown in FIG. 23, the sealing resin 50 is cut using a second blade 82 having a width b2. The width b2 is smaller than the width b1 of the first blade 81. In this process, when cutting the sealing resin 50, the second blade 82 is passed through each of the multiple grooves 83, and then moved in the first direction z until the second blade 82 contacts the support member 80. By going through the above process, the semiconductor device A30 is obtained.

Next, the effects of the semiconductor device A30 will be explained.

The semiconductor device A30 includes a substrate 10, a wiring layer 21 disposed on the main surface 11 of the substrate 10, a terminal 22 disposed on the rear surface 12 of the substrate 10, a rewiring layer 23 housed in the substrate 10, and a semiconductor element 41 that is conductive to the wiring layer 21. The rewiring layer 23 is connected to the wiring layer 21 and the terminal 22. The semiconductor device A30 further includes dummy wiring 30, at least a portion of which is housed in the substrate 10. The dummy wiring 30 is connected to the terminal 22 and is exposed from the end surface 13 of the substrate 10. Therefore, according to this configuration, the semiconductor device A30 can also improve the bonding strength of the semiconductor device A30 to the wiring board. Furthermore, the semiconductor device A30 has a configuration common to the semiconductor device A10, and thereby achieves the same effects as the semiconductor device A10.

The semiconductor device A30 further includes a coating layer 70 that covers the terminals 22 and the areas of the dummy wiring 30 exposed from the end surface 13 of the substrate 10. The coating layer 70 is a conductor that contains gold. With this configuration, when the semiconductor device A30 is mounted on a wiring board, the wettability of the molten solder to the coating layer 70 is good. This further increases the volume of the solder fillet in contact with the coating layer 70, thereby further improving the bonding strength of the semiconductor device A30 to the wiring board.

In the semiconductor device A30, the configuration of the multiple dummy wirings 30 can be changed from that of the semiconductor device A10 to that of the semiconductor device A20.

This disclosure is not limited to the embodiments described above. The specific configuration of each part of this disclosure can be freely designed in various ways.

The present disclosure includes the embodiments described in the appended claims below.
Appendix 1.
A substrate having a main surface and a back surface facing in opposite directions in a first direction;
A wiring layer disposed on the main surface;
A terminal disposed on the back surface;
a rewiring layer that is accommodated in the base material and is connected to the wiring layer and the terminal;
a semiconductor element electrically connected to the wiring layer;
The base material has an end surface facing a direction perpendicular to the first direction,
At least a portion of the dummy wiring is accommodated in the base material,
The dummy wiring is connected to the terminal and exposed from the end surface.
Appendix 2.
the semiconductor element has an electrode facing the wiring layer,
2. The semiconductor device according to claim 1, wherein the electrode is conductively connected to the wiring layer.
Appendix 3.
the redistribution layer has a via connected to at least one of the wiring layer and the terminal;
the dummy wiring has a first dummy via portion connected to the terminal,
the via is spaced from the end face;
3. The semiconductor device according to claim 2, wherein the first dummy via portion is exposed from the end face and is spaced apart from the via.
Appendix 4.
the dummy wiring is disposed on the main surface and has a top portion connected to the first dummy via portion,
4. The semiconductor device according to claim 3, wherein, when viewed in the first direction, the top portion overlaps a peripheral edge of the main surface.
Appendix 5.
5. The semiconductor device according to claim 4, wherein, when viewed in the first direction, the top portion overlaps the entire first dummy via portion.
Appendix 6.
6. The semiconductor device according to claim 5, wherein a minimum dimension of the first dummy via portion is greater than a dimension of the via when viewed in the first direction.
Appendix 7.
the dummy wiring has a second dummy via portion connected to the terminal and the top portion,
6. The semiconductor device according to claim 5, wherein the second dummy via portion is exposed from the end face and is spaced apart from each of the via and the first dummy via portion.
Appendix 8.
8. The semiconductor device according to claim 7, wherein, when viewed in the first direction, the top portion overlaps the entire second dummy via portion.
Appendix 9.
the base material includes a first base material including the back surface and a second base material overlapping the first base material when viewed in the first direction and including the main surface;
the dummy wiring has a relay portion located between the first base material and the second base material,
9. The semiconductor device according to claim 8, wherein the relay portion is exposed from the end face and is connected to the first dummy via portion and the second dummy via portion.
Appendix 10.
the vias include a first via that is accommodated in the first base material and connected to the terminal, and a second via that is accommodated in the second base material and connected to the wiring layer;
the redistribution layer has an intermediate layer located between the first substrate and the second substrate;
10. The semiconductor device according to claim 9, wherein the intermediate layer is connected to the first via and the second via.
Appendix 11.
11. The semiconductor device according to claim 4, wherein the wiring layer is spaced apart from a periphery of the main surface when viewed in the first direction.
Appendix 12.
12. The semiconductor device of claim 11, wherein the top is spaced from the wiring layer.
Appendix 13.
a sealing resin for covering the wiring layer and the semiconductor element,
13. The semiconductor device according to claim 12, wherein the top portion is exposed from the sealing resin.
Appendix 14.
a covering layer that covers the terminals and the areas of the dummy wiring exposed from the end faces,
The semiconductor device described in Appendix 13, wherein the coating layer is a conductor containing gold.
Appendix 15.
Further comprising an insulating layer covering the back surface,
15. The semiconductor device according to claim 14, wherein the terminal is exposed from the insulating layer.
Appendix 16.
a passive element conductively connected to the wiring layer;
16. The semiconductor device according to claim 15, wherein the passive element is covered with the sealing resin.
Appendix 17.
Further comprising a heat dissipation layer disposed on the back surface,
the heat dissipation layer is exposed from the insulating layer,
17. The semiconductor device according to claim 16, wherein, when viewed in the first direction, the semiconductor element overlaps the heat dissipation layer.

A10, A20, A30: semiconductor device 10: substrate 101: first substrate 102: second substrate 103: third substrate 11: main surface 111: periphery 12: back surface 121: periphery 13: end surface 131: first end surface 132: second end surface 21: wiring layer 22: terminal 221: first terminal 222: second terminal 23: rewiring layer 231: via 231A: first via 231B: second via 232: intermediate layer 232A: first intermediate wiring 232B: second intermediate wiring 232C: intermediate via 30: dummy wiring 31: first dummy via portion 311: first portion 312: second portion 313: third portion 32: second dummy via portion 321: fourth portion 322: fifth portion 323: sixth portion 33: third dummy via portion 331: seventh portion 332: eighth portion 333: ninth portion 34: top portion 35: relay portion 351: first relay portion 352: second relay portion 41: semiconductor element 411: electrode 42: passive element 421: electrode 50: sealing resin 51: top surface 52: side surface 521: first region 522: second region 61: insulating layer 62: heat dissipation layer 70: coating layer 80: support member 81: first blade 82: second blade 83: groove z: first direction x: second direction y: third direction

Claims

A substrate having a main surface and a back surface facing in opposite directions in a first direction;
A wiring layer disposed on the main surface;
A terminal disposed on the back surface;
a rewiring layer that is accommodated in the base material and is connected to the wiring layer and the terminal;
a semiconductor element electrically connected to the wiring layer;
The base material has an end surface facing a direction perpendicular to the first direction,
a dummy wiring, at least a portion of which is accommodated in the base material;
The dummy wiring is connected to the terminal and exposed from the end surface.
the semiconductor element has an electrode facing the wiring layer,
The semiconductor device according to claim 1 , wherein the electrode is conductively connected to the wiring layer.
the redistribution layer has a via connected to at least one of the wiring layer and the terminal;
the dummy wiring has a first dummy via portion connected to the terminal,
the via is spaced from the end face;
The semiconductor device according to claim 2 , wherein the first dummy via portion is exposed from the end face and is spaced apart from the via.
the dummy wiring is disposed on the main surface and has a top portion connected to the first dummy via portion,
The semiconductor device according to claim 3 , wherein the top portion overlaps a peripheral edge of the main surface when viewed in the first direction.
The semiconductor device according to claim 4, wherein, when viewed in the first direction, the top portion overlaps the entire first dummy via portion.
The semiconductor device according to claim 5, wherein the minimum dimension of the first dummy via portion is greater than the dimension of the via when viewed in the first direction.
the dummy wiring has a second dummy via portion connected to the terminal and the top portion,
The semiconductor device according to claim 5 , wherein the second dummy via portion is exposed from the end face and is spaced apart from both the via and the first dummy via portion.
The semiconductor device according to claim 7, wherein, when viewed in the first direction, the top portion overlaps the entire second dummy via portion.
the base material includes a first base material including the back surface and a second base material overlapping the first base material when viewed in the first direction and including the main surface;
the dummy wiring has a relay portion located between the first base material and the second base material,
The semiconductor device according to claim 8 , wherein the relay portion is exposed from the end face and is connected to the first dummy via portion and the second dummy via portion.
the vias include a first via that is accommodated in the first base material and connected to the terminal, and a second via that is accommodated in the second base material and connected to the wiring layer;
the redistribution layer has an intermediate layer located between the first substrate and the second substrate;
The semiconductor device according to claim 9 , wherein the intermediate layer is connected to the first via and the second via.
The semiconductor device according to any one of claims 4 to 10, wherein the wiring layer is spaced apart from the periphery of the main surface when viewed in the first direction.
The semiconductor device of claim 11, wherein the top is spaced apart from the wiring layer.
a sealing resin for covering the wiring layer and the semiconductor element,
The semiconductor device according to claim 12 , wherein the top portion is exposed from the sealing resin.
a covering layer that covers the terminals and the areas of the dummy wiring exposed from the end faces,
The semiconductor device according to claim 13 , wherein the covering layer is a conductor containing gold.
Further comprising an insulating layer covering the back surface,
The semiconductor device according to claim 14 , wherein the terminal is exposed from the insulating layer.
a passive element conductively connected to the wiring layer;
The semiconductor device according to claim 15 , wherein the passive elements are covered with the sealing resin.
Further comprising a heat dissipation layer disposed on the back surface,
the heat dissipation layer is exposed from the insulating layer,
The semiconductor device according to claim 16 , wherein the semiconductor element overlaps the heat dissipation layer when viewed in the first direction.