WO2024099182A1 - 一种主从节点确定方法、装置、电子设备及存储介质 - Google Patents

一种主从节点确定方法、装置、电子设备及存储介质 Download PDF

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Publication number
WO2024099182A1
WO2024099182A1 PCT/CN2023/128590 CN2023128590W WO2024099182A1 WO 2024099182 A1 WO2024099182 A1 WO 2024099182A1 CN 2023128590 W CN2023128590 W CN 2023128590W WO 2024099182 A1 WO2024099182 A1 WO 2024099182A1
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Prior art keywords
node
master
target node
character
signal
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PCT/CN2023/128590
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English (en)
French (fr)
Inventor
陈江
韩舒
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苏州元脑智能科技有限公司
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Publication of WO2024099182A1 publication Critical patent/WO2024099182A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/12—Discovery or management of network topologies
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements
    • H04L41/085—Retrieval of network configuration; Tracking network configuration history
    • H04L41/0853—Retrieval of network configuration; Tracking network configuration history by actively collecting configuration information or by backing up configuration information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • the present application relates to the technical field of master-slave node determination, and in particular to a master-slave node determination method, a master-slave node determination device, an electronic device, and a computer-readable storage medium.
  • a multi-node server is a server with multiple nodes. It consists of multiple nodes and a management unit that manages the entire device. It can reduce the load on the server, can be diverted and flexibly applied, and can also be used as a virtual disk server.
  • the multi-node server is also very easy to manage. Each of its nodes can be managed independently. It can achieve a unified management working mode through the chassis management module. It has better versatility and better usability.
  • the multi-node server also has modular deployment. Each node can be flexibly matched and mixed.
  • the modular front window can be matched with different types of node front windows according to user needs.
  • the flexible expansion feature can achieve nearly customized product configuration. It can be used for a variety of different workloads. Different computing nodes can be matched with different large-capacity hard disks. Whether it is multi-network expansion or high IOPS (Input/Output Operations Per Second, a computer storage device), it can be perfectly supported.
  • data is stored on multi-node servers. Although there are multiple storage nodes, the content on each node is different. If it is broken, the data will be lost. In order to ensure the high availability of these data, each node host needs to be backed up. These backups are called slave nodes. With the master-slave, extended functions such as read-write separation (master shard write, replica read) can be realized. Therefore, how to determine the master and slave nodes from the multiple storage nodes of the multi-node server has become a technical problem that technicians in this field need to overcome.
  • the embodiments of the present application provide a method, device, electronic device and computer-readable storage medium for determining a master-slave node to solve the problem of how to determine a master node from multiple storage nodes of a multi-node server.
  • the present application embodiment discloses a method for determining a master-slave node, which is applied to a multi-node server, wherein the multi-node server includes a plurality of storage nodes.
  • the method may include:
  • the first target node includes first verification data
  • the first verification data includes a first first character and a first last character
  • the first target node is determined to be the master node.
  • the first target node is a slave node, and when the first heartbeat signal is in a normal state, and the first master-disable signal is invalid, and the second master-disable signal is invalid, and the third master-disable signal is invalid, the first target node is determined as a master node;
  • the first target node is a slave node
  • the first heartbeat signal is in an abnormal state, and/or the first master-disable signal is valid, and/or the second master-disable signal is valid, and/or the third master-disable signal is valid
  • the first target node is determined to be a slave node
  • the first target node is not a slave node, and when the first heartbeat signal is in an abnormal state, and/or the first master-disable signal is valid, determining the first target node as a slave node;
  • the first target node is determined as a slave node.
  • the first first character is the same as the first last character, and the first first character and the first last character are the same as a preset value, it is determined whether there is a master node among the first target node, the third target node and the fourth target node through the first heartbeat signal, the first master-disable signal, the third heartbeat signal, the third master-disable signal, the fourth heartbeat signal and the fourth master-disable signal;
  • the second target node is determined as the master node
  • the second target node is determined to be the master node.
  • the second target node is determined as a slave node
  • the second target node is determined to be a slave node, and the second heartbeat signal is in an abnormal state, and/or the second master-inhibit signal is valid, and/or the third master-inhibit signal is valid, and/or the first heartbeat signal is in a normal state, and/or the first master-inhibit signal is invalid, the second target node is determined to be a slave node;
  • the second target node is determined to be a slave node.
  • the second target node includes second verification data
  • the second verification data includes a second first character and a second last character, and may further include:
  • the first first character and the first last character are different, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are the same, and the second first character and the second last character are the same as a preset value, determine whether there is a master node between the third target node and the fourth target node through the third heartbeat signal, the third master-disable signal, the fourth heartbeat signal, and the fourth master-disable signal;
  • the second target node is determined as a master node
  • the second target node is determined to be the master node.
  • the second target node is determined as a slave node
  • the second target node is determined as a slave node.
  • the second target node is not a slave node, and the second heartbeat signal is in an abnormal state, and/or the second master-disable signal is valid, determining the second target node as a slave node;
  • the second target node is a slave node and the second heartbeat signal is in an abnormal state, and/or the second master-disable signal is valid, and/or the third master-disable signal is valid, the second target node is determined to be a slave node.
  • first first character and the first last character are the same and the first first character and the first last character are the same as a preset value, or the second first character and the second last character are the same and the second first character and the second last character are the same as a preset value, determine whether there is a master node among the first target node, the second target node and the fourth target node through the first heartbeat signal, the first master-disable signal, the second heartbeat signal, the second master-disable signal, the fourth heartbeat signal and the fourth master-disable signal;
  • the third target node is determined as a master node
  • the third target node is a slave node, and the second master-disable signal is valid, and the third heartbeat signal is in a normal state, and the third master-disable signal is invalid, the third target node is determined as a master node;
  • the third target node is a slave node, and the second master-disable signal is invalid, and the third heartbeat signal is in a normal state
  • the third master disable signal is invalid and the first heartbeat signal is in an abnormal state or the first master disable signal is valid and the second heartbeat signal is in an abnormal state
  • the third target node is determined as the master node.
  • the third target node is determined to be a slave node
  • the third target node is a slave node, and the second master-disable signal is valid, and the third heartbeat signal is in an abnormal state, and/or the third master-disable signal is valid, the third target node is determined to be a slave node;
  • the third target node is determined as the master node.
  • the third target node includes third verification data
  • the third verification data includes a third first character and a third last character, and may further include:
  • the third target node is determined to be the master node.
  • the third target node is determined as a slave node
  • the third first character and the third last character are the same and the third first character and the third last character are the same as a preset value, and when it is determined that the fourth target node is a master node, the third target node is determined as a slave node;
  • the third first character and the third last character are different from a preset value.
  • the characters are the same and the third first character and the third last character are the same as the preset values, and it is determined that the fourth target node is not the master node, and when the third heartbeat signal is in an abnormal state, and/or the third master-disable signal is valid, the third target node is determined as a slave node.
  • the first first character and the first last character are the same and the first first character and the first last character are the same as a preset value, or, the second first character and the second last character are the same and the second first character and the second last character are the same as a preset value, or, the third first character and the third last character are the same and the third first character and the third last character are the same as a preset value, determine whether any of the first target node, the second target node and the third target node is a master node through the first heartbeat signal, the first disable master signal, the second heartbeat signal, the second disable master signal, the third heartbeat signal and the third disable master signal;
  • the fourth target node is determined as a master node
  • the fourth target node When it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is valid, and the fourth heartbeat signal is in a normal state, and the fourth master-disable signal is invalid, and the third heartbeat signal is in an abnormal state or the third master-disable signal is valid, the fourth target node is determined as a master node;
  • the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is valid, and the fourth heartbeat signal is in a normal state, and the fourth master-disable signal is invalid, the fourth target node is determined to be a master node;
  • the fourth target node is a slave node, and the second master disable signal is invalid, and the third master disable signal is invalid, and the first heartbeat signal is in an abnormal state or the first master disable signal is valid, and the second heartbeat signal is in an abnormal state, and the third heartbeat signal is in an abnormal state, the fourth target node is determined as the master node.
  • the third target node is determined as a slave node
  • the fourth target node is determined to be a slave node
  • the fourth target node When it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is valid, and the fourth heartbeat signal is in an abnormal state, and/or the fourth master-disable signal is valid, and the third heartbeat signal is in an abnormal state, and/or the third master-disable signal is valid, the fourth target node is determined to be a slave node;
  • the fourth target node When it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is valid, and the fourth heartbeat signal is in an abnormal state, and/or the fourth master-disable signal is valid, the fourth target node is determined to be a slave node;
  • the fourth target node When it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is invalid, and the first heartbeat signal is in a normal state, and/or the first master-disable signal is invalid, and/or the second heartbeat signal is in a normal state, and/or the third heartbeat signal is in a normal state, the fourth target node is determined as a slave node;
  • the fourth target node is determined as a slave node.
  • the fourth first character and the fourth last character are the same and the fourth first character and the fourth last character are the same as the preset value, and when the fourth heartbeat signal is in normal state and the fourth master disable signal is invalid, the fourth target node is determined as the master node.
  • the fourth target node is determined as a slave node.
  • the first target node, the second target node, the third target node and the fourth target node respectively have corresponding baseboard management controllers BMC
  • the baseboard management controller BMC is used to generate a first heartbeat signal and a first disable master signal for the first target node using the first baseboard management controller BMC, and generate a second heartbeat signal and a second disable master signal for the second target node, and generate a third heartbeat signal and a third disable master signal for the third target node, and generate a fourth heartbeat signal and a fourth disable master signal for the fourth target node.
  • the multi-node server includes a logic programming device CPLD, and the logic programming device CPLD is used to determine the first target node, the second target node, the third target node, and the fourth heartbeat signal as a master node or a slave node.
  • CPLD logic programming device
  • the embodiment of the present application further discloses a master-slave node determination device, which is applied to a multi-node server, wherein the multi-node server includes a plurality of storage nodes, and the device includes:
  • a target node determination module used to determine a first target node, a second target node, a third target node and a fourth target node from the plurality of storage nodes;
  • a first signal generating module used for generating a first heartbeat signal and a first master disable signal for the first target node
  • a second signal generating module used for generating a second heartbeat signal and a second master disable signal for the second target node
  • a third signal generating module used for generating a third heartbeat signal and a third master disable signal for the third target node
  • a fourth signal generating module used for generating a fourth heartbeat signal and a fourth master disable signal for the fourth target node
  • a master node determination module configured to determine the master node when the first master disable signal is valid and the second heartbeat signal, the second master disable signal, the third heartbeat signal, the third master disable signal, the fourth heartbeat signal and the fourth master disable signal are received; When it is determined that there is no master node among the second target node, the third target node and the fourth target node, and the first target node is the master node, and the first master disable signal is invalid, and the first heartbeat signal is in a normal state, the first target node is determined as the master node.
  • the first module used in some embodiments of the present application, may also include:
  • the second module is used to determine the first target node as a master node when the first target node is a slave node, and when the first heartbeat signal is in a normal state, and the first master-disable signal is invalid, and the second master-disable signal is invalid, and the third master-disable signal is invalid;
  • a third module configured to determine the first target node as a slave node when the first target node is a slave node and when the first heartbeat signal is in an abnormal state, and/or the first master-disable signal is valid, and/or the second master-disable signal is valid, and/or the third master-disable signal is valid;
  • a fourth module is configured to determine the first target node as a slave node when the first target node is not a slave node and when the first heartbeat signal is in an abnormal state and/or the first master-disable signal is valid;
  • the fifth module is used to determine the first target node as a slave node when the first first character and the first last character are different and/or the first first character and the first last character are different from preset values.
  • the sixth module is used for judging whether there is a master node among the first target node, the third target node and the fourth target node through the first heartbeat signal, the first master-disabled signal, the third heartbeat signal, the third master-disabled signal, the fourth heartbeat signal and the fourth master-disabled signal when the first first character and the first last character are the same, and the first first character and the first last character are the same as a preset value;
  • the seventh module is used to determine the second target node as the master node when it is determined that there is no master node among the first target node, the third target node and the fourth target node, and the second target node is not a slave node, and the second heartbeat signal is in a normal state, and the second master-disable signal is invalid;
  • the eighth module is used to determine the second target node as the master node when it is determined that there is no master node among the first target node, the third target node and the fourth target node, and the second target node is a slave node, and the second heartbeat signal is in a normal state, and the second master-disable signal is invalid, and the third master-disable signal is invalid, and the first heartbeat signal is in an abnormal state or the first master-disable signal is valid.
  • a ninth module configured to determine the second target node as a slave node when it is determined that there is a master node among the first target node, the third target node and the fourth target node;
  • a tenth module is used to determine the second target node as a slave node when it is determined that there is no master node among the first target node, the third target node and the fourth target node, and the second target node is a slave node, and the second heartbeat signal is in an abnormal state, and/or the second master-forbidden signal is valid, and/or the third master-forbidden signal is valid, and/or the first heartbeat signal is in a normal state, and/or the first master-forbidden signal is invalid;
  • the eleventh module is used to determine the second target node as a slave node when it is determined that there is no master node among the first target node, the third target node and the fourth target node, and the second target node is not a slave node, and the second heartbeat signal is in an abnormal state, and/or the second master-disable signal is valid.
  • the second target node includes second verification data
  • the second verification data includes a second first character and a second last character, and may further include:
  • a twelfth module is used for judging whether there is a master node among the third target node and the fourth target node by using the third heartbeat signal, the third master-disable signal, the fourth heartbeat signal and the fourth master-disable signal when the first first character and the first last character are different and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are the same, and the second first character and the second last character are the same as a preset value;
  • a thirteenth module is used to determine the second target node as the master node when it is determined that there is no master node between the third target node and the fourth target node, and the second target node is not a slave node, and the second heartbeat signal is in a normal state, and the second master-disable signal is invalid;
  • the fourteenth module is used to determine the second target node as the master node when it is determined that there is no master node between the third target node and the fourth target node, and the second target node is a slave node, and the second heartbeat signal is in a normal state, and the second master-disable signal is invalid, and the third master-disable signal is invalid.
  • a fifteenth module is configured to determine the second target node as a slave node when the first first character and the first last character are different and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are different and/or the second first character and the second last character are different from a preset value;
  • a sixteenth module is used to determine the second target node as a slave node when the first first character and the first last character are different, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are the same, and the second first character and the second last character are the same as a preset value, and when it is determined that a master node exists between the third target node and the fourth target node.
  • a seventeenth module is used to determine the second target node as a slave node when the second target node is not a slave node and the second heartbeat signal is in an abnormal state and/or the second master-disable signal is valid;
  • the eighteenth module is used to determine the second target node as a slave node when the second target node is a slave node and the second heartbeat signal is in an abnormal state, and/or the second master-disable signal is valid, and/or the third master-disable signal is valid.
  • a nineteenth module is used to determine whether there is a master node among the first target node, the second target node and the fourth target node through the first heartbeat signal, the first master-disable signal, the second heartbeat signal, the second master-disable signal, the fourth heartbeat signal and the fourth master-disable signal when the first first character and the first last character are the same and the first first character and the first last character are the same as a preset value, or the second first character and the second last character are the same and the second first character and the second last character are the same as a preset value;
  • a twentieth module configured to determine the third target node as a master node when it is determined that there is no master node among the first target node, the second target node, and the fourth target node, and the third target node is not a slave node, and the third heartbeat signal is in a normal state, and the third master-disable signal is invalid;
  • a twenty-first module is configured to determine the third target node as a master node when it is determined that there is no master node among the first target node, the second target node, and the fourth target node, and the third target node is a slave node, and the second master-disable signal is valid, and the third heartbeat signal is in a normal state, and the third master-disable signal is invalid;
  • the twenty-second module is used to determine the first target node, the second target node and the fourth target node.
  • the third target node is a slave node, and the second master disable signal is invalid, and the third heartbeat signal is in a normal state, and the third master disable signal is invalid, and the first heartbeat signal is in an abnormal state or the first master disable signal is valid, and the second heartbeat signal is in an abnormal state
  • the third target node is determined as the master node.
  • a twenty-third module is configured to determine the third target node as a slave node when it is determined that there is a master node among the first target node, the second target node and the fourth target node;
  • a twenty-fourth module is used to determine the third target node as a slave node when it is determined that there is no master node among the first target node, the second target node and the fourth target node, and the third target node is not a slave node, and the third heartbeat signal is in an abnormal state, and/or the third master-disable signal is valid;
  • a twenty-fifth module is configured to determine the third target node as a slave node when it is determined that there is no master node among the first target node, the second target node, and the fourth target node, and the third target node is a slave node, and the second master-disable signal is valid, and the third heartbeat signal is in an abnormal state, and/or the third master-disable signal is valid;
  • the twenty-sixth module is used to determine the third target node as the master node when it is determined that there is no master node among the first target node, the second target node and the fourth target node, and the third target node is a slave node, and the second master-disable signal is invalid, and the third heartbeat signal is in an abnormal state, and/or the third master-disable signal is valid, and/or the first heartbeat signal is in a normal state, and/or the first master-disable signal is invalid, and/or the second heartbeat signal is in a normal state.
  • the third target node includes third verification data
  • the third verification data includes a third first character and a third last character, and may further include:
  • Module 27 used for determining whether the fourth target node is a master node by using the fourth heartbeat signal and the fourth master-disable signal when the first first character and the first last character are different from each other, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are different from each other, and/or the second first character and the second last character are different from each other, and the third first character and the third last character are the same as each other, and the third first character and the third last character are the same as each other;
  • the twenty-eighth module is used to determine the third target node as the master node when it is determined that the fourth target node is not the master node and when the third heartbeat signal is in a normal state and the third master-disable signal is invalid.
  • Module 29 for determining the third target node as a slave node when the first first character and the first last character are different, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are different, and/or the second first character and the second last character are different from a preset value, and the third first character and the third last character are different, and/or the third first character and the third last character are different from a preset value;
  • Module 30 for determining the third target node as a slave node when the first first character and the first last character are different, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are different from a preset value, and the third first character and the third last character are the same and the third first character and the third last character are the same as a preset value, and when it is determined that the fourth target node is a master node, determining the third target node as a slave node;
  • the thirty-first module is used for when the first first character and the first last character are different, and/or the first The first first character and the first last character are different from the preset value, and the second first character and the second last character are different, and/or the second first character and the second last character are different from the preset value, and the third first character and the third last character are the same and the third first character and the third last character are the same as the preset value, and it is determined that the fourth target node is not the master node, and when the third heartbeat signal is in an abnormal state, and/or the third master-disable signal is valid, the third target node is determined as a slave node.
  • Module 32 used for judging whether any of the first target node, the second target node and the third target node is a master node by using the first heartbeat signal, the first disable master signal, the second heartbeat signal, the second disable master signal, the third heartbeat signal and the third disable master signal, when the first first character and the first last character are the same and the first first character and the first last character are the same as a preset value, or the second first character and the second last character are the same and the second first character and the second last character are the same as a preset value, or the third first character and the third last character are the same and the third first character and the third last character are the same as a preset value;
  • a thirty-third module is used to determine the fourth target node as a master node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is not a slave node, and the fourth heartbeat signal is in a normal state, and the fourth master-disable signal is invalid;
  • a thirty-fourth module is used to determine the fourth target node as the master node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is valid, and the fourth heartbeat signal is in a normal state, and the fourth master-disable signal is invalid, and the third heartbeat signal is in an abnormal state or the third master-disable signal is valid;
  • a thirty-fifth module is used to determine the fourth target node as the master node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is valid, and the fourth heartbeat signal is in a normal state, and the fourth master-disable signal is invalid;
  • the thirty-sixth module is used to determine the fourth target node as the master node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master disable signal is invalid, and the third master disable signal is invalid, and the first heartbeat signal is in an abnormal state or the first master disable signal is valid, and the second heartbeat signal is in an abnormal state, and the third heartbeat signal is in an abnormal state.
  • a thirty-seventh module is used to determine the third target node as a slave node when it is determined that there is a master node among the first target node, the second target node and the third target node;
  • a thirty-eighth module is used to determine the fourth target node as a slave node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is not a slave node, and the fourth heartbeat signal is in an abnormal state, and/or the fourth master-disable signal is invalid;
  • a thirty-ninth module is used to determine the fourth target node as a slave node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-forbidden signal is valid, and the fourth heartbeat signal is in an abnormal state, and/or the fourth master-forbidden signal is valid, and the third heartbeat signal is in an abnormal state, and/or the third master-forbidden signal is valid;
  • the 40th module is used to determine the first target node, the second target node and the third target node.
  • the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is valid, and the fourth heartbeat signal is in an abnormal state, and/or, when the fourth master-disable signal is valid, the fourth target node is determined to be a slave node;
  • a forty-first module is used to determine the fourth target node as a slave node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is invalid, and the first heartbeat signal is in a normal state, and/or the first master-disable signal is invalid, and/or the second heartbeat signal is in a normal state, and/or the third heartbeat signal is in a normal state;
  • the 42nd module is used to determine the fourth target node as a slave node when it is determined that there is a master node among the first target node, the second target node and the third target node.
  • the forty-third module is used to determine the fourth target node as the master node when the first first character and the first last character are different, and/or the first first character and the first last character are different from the preset value, and the second first character and the second last character are different, and/or the second first character and the second last character are different from the preset value, and the third first character and the third last character are different, and/or the third first character and the third last character are different from the preset value, and the fourth first character and the fourth last character are the same and the fourth first character and the fourth last character are the same as the preset value, and when the fourth heartbeat signal is in normal state and the fourth master disable signal is invalid.
  • a forty-fourth module is used to determine the fourth target node as a slave node when the fourth first character and the fourth last character are different and/or the fourth first character and the fourth last character are different from a preset value;
  • the forty-fifth module is used to determine the fourth target node as a slave node when the fourth first character and the fourth last character are the same and the fourth first character and the fourth last character are the same as the preset value, and the fourth heartbeat signal is in an abnormal state, and/or the fourth master-disable signal is valid.
  • the first target node, the second target node, the third target node and the fourth target node respectively have corresponding baseboard management controllers BMC
  • the baseboard management controller BMC is used to generate a first heartbeat signal and a first disable master signal for the first target node using the first baseboard management controller BMC, and generate a second heartbeat signal and a second disable master signal for the second target node, and generate a third heartbeat signal and a third disable master signal for the third target node, and generate a fourth heartbeat signal and a fourth disable master signal for the fourth target node.
  • the multi-node server includes a logic programming device CPLD, and the logic programming device CPLD is used to determine the first target node, the second target node, the third target node, and the fourth heartbeat signal as a master node or a slave node.
  • CPLD logic programming device
  • the embodiment of the present application also discloses an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus;
  • the memory is used to store computer programs
  • the processor is used to implement the method described in the embodiment of the present application when executing the program stored in the memory.
  • the embodiment of the present application also discloses a computer-readable storage medium having instructions stored thereon, which, when executed by one or more processors, enables the processors to execute the method described in the embodiment of the present application.
  • the embodiments of the present application include the following advantages:
  • the first target node, the second target node, the third target node and the fourth target node are determined from the multiple storage nodes; a heartbeat signal and a master disable signal are generated for the target nodes; when the first leading character and the first last character of the verification data are the same and the first leading character and the first last character are the same as the preset value, and the second target node, the third target node and the fourth target node are determined not to be master nodes through the second heartbeat signal, the second master disable signal, the third heartbeat signal, the third master disable signal, the fourth heartbeat signal and the fourth master disable signal, and the first target node is not a slave node, and the first heartbeat signal is in a normal state, the first target node is determined to be the master node, thereby achieving the determination of the master node.
  • FIG1 is a flowchart of a method for determining a master and slave node provided in an embodiment of the present application
  • FIG2 is a schematic diagram of the structure of a storage controller provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of the structure of a storage controller node provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of a step flow diagram of a method for determining a master-slave relationship of a first target node provided in an embodiment of the present application
  • FIG5 is a schematic diagram of a step flow diagram of a method for determining a master-slave relationship of a second target node provided in an embodiment of the present application
  • FIG6 is a schematic diagram of a step flow diagram of a method for determining a master-slave relationship of a third target node provided in an embodiment of the present application;
  • FIG. 7 is a schematic diagram of the steps of a method for determining a master-slave relationship of a fourth target node provided in an embodiment of the present application.
  • FIG8 is a structural block diagram of a master-slave node determination device provided in an embodiment of the present application.
  • FIG. 9 is a hardware structure block diagram of an electronic device provided in each embodiment of the present application.
  • Step 101 determining a first target node, a second target node, a third target node and a fourth target node from the plurality of storage nodes; the first target node includes first verification data, and the first verification data includes a first first character and a first last character;
  • Step 102 generating a first heartbeat signal and a first master disable signal for the first target node
  • Step 103 generating a second heartbeat signal and a second master disable signal for the second target node
  • Step 104 generating a third heartbeat signal and a third master disable signal for the third target node
  • Step 105 generating a fourth heartbeat signal and a fourth master disable signal for the fourth target node
  • Step 106 when the first first character and the first last character are the same and the first first character and the first last character are the same as the preset value, and it is determined by the second heartbeat signal, the second disable master signal, the third heartbeat signal, the third disable master signal, the fourth heartbeat signal and the fourth disable master signal that there is no master node among the second target node, the third target node and the fourth target node, and the first target node is not a slave node, and the first disable master signal is invalid, and the first heartbeat signal is in a normal state, the first target node is determined to be the master node.
  • the present application can be applied to a multi-node server, which may include a storage controller.
  • a storage controller may include four nodes, and each node is interconnected with a backplane inside the storage controller.
  • the storage controller also includes multiple shared components: such as a disk array, a fan, a PSU (power supply unit), an interface card, etc.
  • each node of the storage controller may be completely identical in hardware design; each node includes a logic programming device CPLD module responsible for internal control of the node and a baseboard management controller BMC responsible for internal hardware management of the node.
  • CPLD logic programming device
  • BMC baseboard management controller
  • BMC executive server remote management controller
  • Baseboard Management Controller also known as baseboard management controller
  • CPLD Complex Programmable Logic Device
  • Complex PLD a logic element that is more complex than PLD.
  • CPLD is a digital integrated circuit that users can construct logic functions according to their own needs. Its basic design method is to use the integrated development software platform, schematic diagram, hardware description language and other methods to generate the corresponding target file, and transfer the code to the target chip through the download cable ("in-system" programming) to realize the designed digital system.
  • FIG. 3 is a structural schematic diagram of a storage controller node provided in an embodiment of the present application, the CPLD and the BMC can realize data interaction through interface signals, the embodiment of the present application can generate a first target node, a second target node, a third target node and a fourth target node from multiple storage nodes for the target, and in some embodiments of the present application, the embodiment of the present application can be used to generate a first heartbeat signal and a first master-disable signal for the first target node through the BMC; generate a second heartbeat signal and a second master-disable signal for the second target node; generate a third heartbeat signal and a third master-disable signal for the third target node; generate a fourth heartbeat signal and a fourth master-d
  • bmc_heart signal also called the heartbeat signal of BMC.
  • the BMC works normally.
  • the bmc_heart signal is abnormal, the BMC works abnormally.
  • a node with abnormal BMC cannot be used as the master node.
  • master_disable signal also known as the master disable signal (forbidding this node to become the master node) sent by the BMC; when the master_disable signal is valid, this node cannot be used as the master node; it is known that the master_disable signal is a 10ms pulse signal; the master_disable signal is valid when it is at a high level; in specific design, when the master_disable signal is used, the master node is switched in a fixed order of ABCD.
  • node B there are four nodes ABCD inside the storage controller; currently, node B is the master node; after the master_disable signal sent by the BMC of node B is valid, node B is called a slave node, and node C is promoted to the master node. After the master_disable signal sent by the BMC of node B is invalid, node B can still become the master node if the conditions are met.
  • each storage node may have corresponding verification data, which may include the first character and the last character.
  • the verification data may be different flag values obtained from the backplane when the storage node is inserted into different slots on the backplane.
  • the embodiment of the present application can determine whether the data of the storage node is valid by determining whether the first character and the last character are the same, and whether the first character and the last character are equal to a preset value.
  • the preset value of the storage node X is 1.
  • the first character of the verification data of the storage node X is 1 and the last character is 1, it can be determined that the data of the storage node X is valid.
  • the embodiment of the present application can determine whether the first target node is currently a slave node when the first first character and the first last character are the same and the same as the preset value, and when it is determined that there is no master node among the second target node, the third target node and the fourth target node through the second heartbeat signal, the second master-forbidden signal, the third heartbeat signal, the third master-forbidden signal, the fourth heartbeat signal and the fourth master-forbidden signal, when the first target node is not currently a slave node, and when the first master-forbidden signal is invalid, and the first heartbeat signal is In a normal state, the first target node is determined as a master node. After the master node is determined, other nodes inside the storage controller can be used as slave nodes.
  • Figure 4 is a step flow diagram of a method for determining the master-slave relationship of a first target node provided in an embodiment of the present application.
  • Node A can be equivalent to the first target node
  • node B can be equivalent to the second target node
  • node C can be equivalent to the third target node
  • node D can be equivalent to the fourth target node.
  • node A When the first first character and the first last character of the verification data of node A are the same and the first first character and the first last character are the same as the preset value, that is, the data of node A is valid, and it is determined that there is no master node among the second target node, the third target node and the fourth target node through the second heartbeat signal, the second master-disabled signal, the third heartbeat signal, the third master-disabled signal, the fourth heartbeat signal and the fourth master-disabled signal, and when node A is not currently a slave node and the first heartbeat signal is in a normal state, node A is determined to be the master node.
  • a first target node, a second target node, a third target node and a fourth target node are determined from the multiple storage nodes;
  • the first target node includes a first verification data, and the first verification data includes a first first character and a first last character;
  • a first heartbeat signal and a first master-disable signal are generated for the first target node;
  • a second heartbeat signal and a second master-disable signal are generated for the second target node;
  • a third heartbeat signal and a third master-disable signal are generated for the third target node;
  • a fourth heartbeat signal and a fourth master-disable signal are generated for the fourth target node; when the first first character and the first last character are the same and the first first character and the first last character are the same as a preset value, and it is determined by the second heartbeat signal, the second master-disable signal, the third heartbeat signal, the third master-disable signal, the fourth heartbeat signal and the fourth master-
  • the first target node when the first target node is a slave node, and when the first heartbeat signal is in a normal state, and the first master-disable signal is invalid, and the second master-disable signal is invalid, and the third master-disable signal is invalid, the first target node is determined to be a master node;
  • the first target node is a slave node
  • the first heartbeat signal is in an abnormal state, and/or the first master-disable signal is valid, and/or the second master-disable signal is valid, and/or the third master-disable signal is valid
  • the first target node is determined to be a slave node
  • the first target node is not a slave node, and when the first heartbeat signal is in an abnormal state, and/or the first master-disable signal is valid, determining the first target node as a slave node;
  • the first target node is determined as a slave node.
  • Node A can be equivalent to the first target node
  • node B can be equivalent to the second target node
  • node C can be equivalent to the third target node
  • node D can be equivalent to the fourth target node.
  • the first first character and the first last character are the same, and the first first character and the first last character are the same as a preset value, it can be judged whether there is a master node among the first target node, the third target node and the fourth target node through the first heartbeat signal, the first master-disabled signal, the third heartbeat signal, the third master-disabled signal, the fourth heartbeat signal and the fourth master-disabled signal;
  • the second target node is determined as the master node
  • the second target node is determined as the master node.
  • the second target node is determined as the master node, and the efficiency of determining the master and slave storage nodes is further improved.
  • the second target node when it is determined that there is a master node among the first target node, the third target node and the fourth target node, the second target node is determined as a slave node;
  • the second target node is determined to be a slave node, and the second heartbeat signal is in an abnormal state, and/or the second master-inhibit signal is valid, and/or the third master-inhibit signal is valid, and/or the first heartbeat signal is in a normal state, and/or the first master-inhibit signal is invalid, the second target node is determined to be a slave node;
  • the second target node is determined to be a slave node, thereby realizing the determination of the second target node as a slave node, and further improving the efficiency of determining the master and slave storage nodes.
  • the second target node includes second verification data
  • the second verification data includes a second first character and a second last character
  • the second first character and the first last character are different, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are the same, and the second first character and the second last character are the same as a preset value
  • it can be determined whether there is a master node between the third target node and the fourth target node by using the third heartbeat signal, the third master-disable signal, the fourth heartbeat signal, and the fourth master-disable signal;
  • the second target node is determined as a master node
  • the second target node is determined to be the master node, thereby realizing the determination of the second target node as the master node, and further improving the efficiency of determining the master and slave storage nodes.
  • the second target node is determined as a slave node
  • the second target node is determined as a slave node
  • the second target node is not a slave node, and the second heartbeat signal is in an abnormal state, and/or the second master-disable signal is valid, determining the second target node as a slave node;
  • the second target node is a slave node
  • the second heartbeat signal is in an abnormal state, and/or the second master-disable signal is valid, and/or the third master-disable signal is valid
  • the second target node is determined as a slave node.
  • the second target node is determined as a slave node, and the efficiency of determining the master and slave storage nodes is further improved.
  • Node A can be equivalent to the first target node
  • node B can be equivalent to the second target node
  • node C can be equivalent to the third target node
  • node D can be equivalent to the fourth target node.
  • the first first character and the first last character are the same and the first first character and the first last character are the same as a preset value, or the second first character and the second last character are the same and the second first character and the second last character are the same as a preset value
  • the third target node is determined as a master node
  • the third target node is a slave node, and the second master-disable signal is valid, and the third heartbeat signal is in a normal state, and the third master-disable signal is invalid, the third target node is determined as a master node;
  • the third target node is a slave node, and the second master disable signal is invalid, and the third heartbeat signal is in a normal state, and the third master disable signal is invalid, and the first heartbeat signal is in an abnormal state or the first master disable signal is valid, and the second heartbeat signal is in an abnormal state
  • the third target node is determined as the master node, thereby realizing the determination of the third target node as the master node, and further improving the efficiency of determining the master and slave storage nodes.
  • the third target node is determined as a slave node
  • the third target node is determined to be a slave node
  • the third target node is a slave node, and the second master-disable signal is valid, and the third heartbeat signal is in an abnormal state, and/or the third master-disable signal is valid, the third target node is determined to be a slave node;
  • the third target node is determined to be a slave node, thereby realizing the determination of the third target node as a slave node, and further improving the efficiency of determining the master and slave storage nodes.
  • the third target node includes third verification data
  • the third verification data includes a third first character and a third last character, and when the first first character and the first last character are different, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are different, and/or the second first character and the second last character are different from the preset value, and the third first character and the third last character are the same, and the third first character and the third last character are the same as the preset value, then judging whether the fourth target node is a master node by using the fourth heartbeat signal and the fourth master-disable signal;
  • the third target node is determined to be the master node, thereby realizing the determination of the third target node as the master node, and further improving the efficiency of determining the master and slave storage nodes.
  • the third target node may be determined as a slave node when the first first character and the first last character are different, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are different, and/or the second first character and the second last character are different from a preset value, and the third first character and the third last character are different, and/or the third first character and the third last character are different from a preset value;
  • the third first character and the third last character are the same and the third first character and the third last character are the same as a preset value, and when it is determined that the fourth target node is a master node, the third target node is determined as a slave node;
  • the third target node is determined as a slave node, thereby realizing the determination of the third target node as a slave node, further improving the efficiency of determining the master and slave storage nodes.
  • Node A can be equivalent to the first target node
  • node B can be equivalent to the second target node
  • node C can be equivalent to the third target node
  • node D can be equivalent to the fourth target node.
  • the first first character and the first last character are the same and the first first character and the first last character are the same as a preset value, or, the second first character and the second last character are the same and the second first character and the second last character are the same as a preset value, or, the third first character and the third last character are the same and the third first character and the third last character are the same as the preset value
  • the fourth target node is determined as a master node
  • the fourth target node When it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is valid, and the fourth heartbeat signal is in a normal state, and the fourth master-disable signal is invalid, and the third heartbeat signal is in an abnormal state or the third master-disable signal is valid, the fourth target node is determined as a master node;
  • the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is valid, and the fourth heartbeat signal is in a normal state, and the fourth master-disable signal is invalid, the fourth target node is determined to be a master node;
  • the fourth target node When it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is invalid, and the first heartbeat signal is in an abnormal state or the first master-disable signal is valid, and the second heartbeat signal is in an abnormal state, and the third heartbeat signal is in an abnormal state, the fourth target node is determined as a master node.
  • the fourth target node is determined as a master node, and the efficiency of determining the master and slave storage nodes of the storage nodes is further improved.
  • the third target node is determined as a slave node
  • the fourth target node is determined to be a slave node
  • the fourth target node When it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is valid, and the fourth heartbeat signal is in an abnormal state, and/or the fourth master-disable signal is valid, and the third heartbeat signal is in an abnormal state, and/or the third master-disable signal is valid, the fourth target node is determined to be a slave node;
  • the fourth target node When it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is valid, and the fourth heartbeat signal is in an abnormal state, and/or the fourth master-disable signal is valid, the fourth target node is determined to be a slave node;
  • the fourth target node When it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is invalid, and the first heartbeat signal is in a normal state, and/or the first master-disable signal is invalid, and/or the second heartbeat signal is in a normal state, and/or the third heartbeat signal is in a normal state, the fourth target node is determined as a slave node;
  • the fourth target node is determined as a slave node, thereby determining the fourth target node as a slave node, and further improving the efficiency of determining the master and slave storage nodes.
  • the fourth target node includes fourth verification data
  • the fourth verification data includes a fourth first character and a fourth last character. It can also be achieved by when the first first character and the first last character are different, and/or, the first first character and the first last character are different from a preset value, and the second first character and the second last character are different, and/or, the second first character and the second last character are different from the preset value, and the third first character and the third last character are different, and/or, the third first character and the third last character are different from the preset value, and the fourth first character and the fourth last character are the same and the The fourth first character and the fourth last character are the same as the preset value, and when the fourth heartbeat signal is in a normal state and the fourth master-disable signal is invalid, the fourth target node is determined as the master node.
  • the fourth target node is determined as the master node, and the efficiency of determining the master and slave storage nodes is further improved.
  • the fourth target node may be determined as a slave node when the fourth first character and the fourth last character are different and/or the fourth first character and the fourth last character are different from a preset value;
  • the fourth target node is determined as a slave node, thereby realizing the determination of the fourth target node as a slave node, and further improving the efficiency of determining the master and slave storage nodes.
  • a block diagram of a master-slave node determination device provided in an embodiment of the present application is shown, which may specifically include the following modules:
  • the target node determination module 801 is used to determine a first target node, a second target node, a third target node and a fourth target node from the plurality of storage nodes; the first target node includes first verification data, and the first verification data includes a first first character and a first last character;
  • a first signal generating module 802 configured to generate a first heartbeat signal and a first master disable signal for the first target node
  • a second signal generating module 803, configured to generate a second heartbeat signal and a second master disable signal for the second target node
  • a third signal generating module 804 is used to generate a third heartbeat signal and a third master disable signal for the third target node;
  • a fourth signal generating module 805, configured to generate a fourth heartbeat signal and a fourth master disable signal for the fourth target node
  • the master node determination module 806 is used to determine the first target node as the master node when the first first character and the first last character are the same and the first first character and the first last character are the same as the preset value, and it is determined through the second heartbeat signal, the second disable master signal, the third heartbeat signal, the third disable master signal, the fourth heartbeat signal and the fourth disable master signal that there is no master node among the second target node, the third target node and the fourth target node, and the first target node is not a slave node, and the first disable master signal is invalid, and the first heartbeat signal is in a normal state.
  • the first module used in some embodiments of the present application, may also include:
  • the second module is used to determine the first target node as a master node when the first target node is a slave node, and when the first heartbeat signal is in a normal state, and the first master-disable signal is invalid, and the second master-disable signal is invalid, and the third master-disable signal is invalid;
  • a third module configured to determine the first target node as a slave node when the first target node is a slave node and when the first heartbeat signal is in an abnormal state, and/or the first master-disable signal is valid, and/or the second master-disable signal is valid, and/or the third master-disable signal is valid;
  • a fourth module is configured to determine the first target node as a slave node when the first target node is not a slave node and when the first heartbeat signal is in an abnormal state and/or the first master-disable signal is valid;
  • the fifth module is used to determine the first target node as a slave node when the first first character and the first last character are different and/or the first first character and the first last character are different from preset values.
  • the sixth module is used for judging whether there is a master node among the first target node, the third target node and the fourth target node through the first heartbeat signal, the first master-disabled signal, the third heartbeat signal, the third master-disabled signal, the fourth heartbeat signal and the fourth master-disabled signal when the first first character and the first last character are the same, and the first first character and the first last character are the same as a preset value;
  • the seventh module is used to determine the second target node as the master node when it is determined that there is no master node among the first target node, the third target node and the fourth target node, and the second target node is not a slave node, and the second heartbeat signal is in a normal state, and the second master-disable signal is invalid;
  • the eighth module is used to determine the second target node as the master node when it is determined that there is no master node among the first target node, the third target node and the fourth target node, and the second target node is a slave node, and the second heartbeat signal is in a normal state, and the second master-disable signal is invalid, and the third master-disable signal is invalid, and the first heartbeat signal is in an abnormal state or the first master-disable signal is valid.
  • a ninth module configured to determine the second target node as a slave node when it is determined that there is a master node among the first target node, the third target node and the fourth target node;
  • a tenth module is used to determine the second target node as a slave node when it is determined that there is no master node among the first target node, the third target node and the fourth target node, and the second target node is a slave node, and the second heartbeat signal is in an abnormal state, and/or the second master-forbidden signal is valid, and/or the third master-forbidden signal is valid, and/or the first heartbeat signal is in a normal state, and/or the first master-forbidden signal is invalid;
  • the eleventh module is used to determine the second target node as a slave node when it is determined that there is no master node among the first target node, the third target node and the fourth target node, and the second target node is not a slave node, and the second heartbeat signal is in an abnormal state, and/or the second master-disable signal is valid.
  • the second target node includes second verification data
  • the second verification data includes a second first character and a second last character, and may further include:
  • a twelfth module is used for judging whether there is a master node among the third target node and the fourth target node by using the third heartbeat signal, the third master-disable signal, the fourth heartbeat signal and the fourth master-disable signal when the first first character and the first last character are different and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are the same, and the second first character and the second last character are the same as a preset value;
  • a thirteenth module is used to determine the second target node as the master node when it is determined that there is no master node between the third target node and the fourth target node, and the second target node is not a slave node, and the second heartbeat signal is in a normal state, and the second master-disable signal is invalid;
  • the fourteenth module is used to determine the second target node as the master node when it is determined that there is no master node between the third target node and the fourth target node, and the second target node is a slave node, and the second heartbeat signal is in a normal state, and the second master-disable signal is invalid, and the third master-disable signal is invalid.
  • a fifteenth module is configured to determine the second target node as a slave node when the first first character and the first last character are different and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are different and/or the second first character and the second last character are different from a preset value;
  • a sixteenth module is used to determine the second target node as a slave node when the first first character and the first last character are different, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are the same, and the second first character and the second last character are the same as a preset value, and when it is determined that a master node exists between the third target node and the fourth target node.
  • a seventeenth module is used to determine the second target node as a slave node when the second target node is not a slave node and the second heartbeat signal is in an abnormal state and/or the second master-disable signal is valid;
  • the eighteenth module is used to determine the second target node as a slave node when the second target node is a slave node and the second heartbeat signal is in an abnormal state, and/or the second master-disable signal is valid, and/or the third master-disable signal is valid.
  • a nineteenth module is used to determine whether there is a master node among the first target node, the second target node and the fourth target node through the first heartbeat signal, the first master-disable signal, the second heartbeat signal, the second master-disable signal, the fourth heartbeat signal and the fourth master-disable signal when the first first character and the first last character are the same and the first first character and the first last character are the same as a preset value, or the second first character and the second last character are the same and the second first character and the second last character are the same as a preset value;
  • a twentieth module configured to determine the third target node as a master node when it is determined that there is no master node among the first target node, the second target node, and the fourth target node, and the third target node is not a slave node, and the third heartbeat signal is in a normal state, and the third master-disable signal is invalid;
  • a twenty-first module is configured to determine the third target node as a master node when it is determined that there is no master node among the first target node, the second target node, and the fourth target node, and the third target node is a slave node, and the second master-disable signal is valid, and the third heartbeat signal is in a normal state, and the third master-disable signal is invalid;
  • the twenty-second module is used to determine the third target node as the master node when it is determined that there is no master node among the first target node, the second target node and the fourth target node, and the third target node is a slave node, and the second master-disable signal is invalid, and the third heartbeat signal is in a normal state, and the third master-disable signal is invalid, and the first heartbeat signal is in an abnormal state or the first master-disable signal is valid, and the second heartbeat signal is in an abnormal state.
  • a twenty-third module is configured to determine the third target node as a slave node when it is determined that there is a master node among the first target node, the second target node and the fourth target node;
  • a twenty-fourth module is used for determining that there is no master node among the first target node, the second target node and the fourth target node, and the third target node is not a slave node, and the third heartbeat signal is in an abnormal state, and /or, the third master-disable signal is valid, and the third target node is determined as a slave node;
  • a twenty-fifth module is configured to determine the third target node as a slave node when it is determined that there is no master node among the first target node, the second target node, and the fourth target node, and the third target node is a slave node, and the second master-disable signal is valid, and the third heartbeat signal is in an abnormal state, and/or the third master-disable signal is valid;
  • the twenty-sixth module is used to determine the third target node as the master node when it is determined that there is no master node among the first target node, the second target node and the fourth target node, and the third target node is a slave node, and the second master-disable signal is invalid, and the third heartbeat signal is in an abnormal state, and/or the third master-disable signal is valid, and/or the first heartbeat signal is in a normal state, and/or the first master-disable signal is invalid, and/or the second heartbeat signal is in a normal state.
  • the third target node includes third verification data
  • the third verification data includes a third first character and a third last character, and may further include:
  • Module 27 used for determining whether the fourth target node is a master node by using the fourth heartbeat signal and the fourth master-disable signal when the first first character and the first last character are different from each other, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are different from each other, and/or the second first character and the second last character are different from each other, and the third first character and the third last character are the same as each other, and the third first character and the third last character are the same as each other;
  • the twenty-eighth module is used to determine the third target node as the master node when it is determined that the fourth target node is not the master node and when the third heartbeat signal is in a normal state and the third master-disable signal is invalid.
  • Module 29 for determining the third target node as a slave node when the first first character and the first last character are different, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are different, and/or the second first character and the second last character are different from a preset value, and the third first character and the third last character are different, and/or the third first character and the third last character are different from a preset value;
  • Module 30 for determining the third target node as a slave node when the first first character and the first last character are different, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are different from a preset value, and the third first character and the third last character are the same and the third first character and the third last character are the same as a preset value, and when it is determined that the fourth target node is a master node, determining the third target node as a slave node;
  • the thirty-first module is used to determine the third target node as a slave node when the first first character and the first last character are different, and/or the first first character and the first last character are different from a preset value, and the second first character and the second last character are different from a preset value, and the third first character and the third last character are the same and the third first character and the third last character are the same as the preset value, and the fourth target node is determined not to be a master node, and when the third heartbeat signal is in an abnormal state, and/or the third master-disable signal is valid.
  • the thirty-second module is used for when the first first character and the first last character are the same and the first first character and the first last character are the same as a preset value, or the second first character and the second last character are the same and the When the second first character and the second last character are the same as the preset value, or when the third first character and the third last character are the same and the third first character and the third last character are the same as the preset value, determine whether any of the first target node, the second target node and the third target node is a master node through the first heartbeat signal, the first disable master signal, the second heartbeat signal, the second disable master signal, the third heartbeat signal and the third disable master signal;
  • a thirty-third module is used to determine the fourth target node as a master node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is not a slave node, and the fourth heartbeat signal is in a normal state, and the fourth master-disable signal is invalid;
  • a thirty-fourth module is used to determine the fourth target node as the master node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is valid, and the fourth heartbeat signal is in a normal state, and the fourth master-disable signal is invalid, and the third heartbeat signal is in an abnormal state or the third master-disable signal is valid;
  • a thirty-fifth module is used to determine the fourth target node as the master node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is valid, and the fourth heartbeat signal is in a normal state, and the fourth master-disable signal is invalid;
  • the thirty-sixth module is used to determine the fourth target node as the master node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master disable signal is invalid, and the third master disable signal is invalid, and the first heartbeat signal is in an abnormal state or the first master disable signal is valid, and the second heartbeat signal is in an abnormal state, and the third heartbeat signal is in an abnormal state.
  • a thirty-seventh module is used to determine the third target node as a slave node when it is determined that there is a master node among the first target node, the second target node and the third target node;
  • a thirty-eighth module is used to determine the fourth target node as a slave node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is not a slave node, and the fourth heartbeat signal is in an abnormal state, and/or the fourth master-disable signal is invalid;
  • a thirty-ninth module is used to determine the fourth target node as a slave node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-forbidden signal is valid, and the fourth heartbeat signal is in an abnormal state, and/or the fourth master-forbidden signal is valid, and the third heartbeat signal is in an abnormal state, and/or the third master-forbidden signal is valid;
  • the 40th module is used to determine the fourth target node as a slave node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is valid, and the fourth heartbeat signal is in an abnormal state, and/or the fourth master-disable signal is valid;
  • a forty-first module is used to determine the fourth target node as a slave node when it is determined that there is no master node among the first target node, the second target node and the third target node, and the fourth target node is a slave node, and the second master-disable signal is invalid, and the third master-disable signal is invalid, and the first heartbeat signal is in a normal state, and/or the first master-disable signal is invalid, and/or the second heartbeat signal is in a normal state, and/or the third heartbeat signal is in a normal state;
  • the 42nd module is used to determine the fourth target node as a slave node when it is determined that there is a master node among the first target node, the second target node and the third target node.
  • the forty-third module is used to determine the fourth target node as the master node when the first first character and the first last character are different, and/or the first first character and the first last character are different from the preset value, and the second first character and the second last character are different, and/or the second first character and the second last character are different from the preset value, and the third first character and the third last character are different, and/or the third first character and the third last character are different from the preset value, and the fourth first character and the fourth last character are the same and the fourth first character and the fourth last character are the same as the preset value, and when the fourth heartbeat signal is in normal state and the fourth master disable signal is invalid.
  • a forty-fourth module is used to determine the fourth target node as a slave node when the fourth first character and the fourth last character are different and/or the fourth first character and the fourth last character are different from a preset value;
  • the forty-fifth module is used to determine the fourth target node as a slave node when the fourth first character and the fourth last character are the same and the fourth first character and the fourth last character are the same as the preset value, and the fourth heartbeat signal is in an abnormal state, and/or the fourth master-disable signal is valid.
  • the first target node, the second target node, the third target node and the fourth target node respectively have corresponding baseboard management controllers BMC
  • the baseboard management controller BMC is used to generate a first heartbeat signal and a first disable master signal for the first target node using the first baseboard management controller BMC, and generate a second heartbeat signal and a second disable master signal for the second target node, and generate a third heartbeat signal and a third disable master signal for the third target node, and generate a fourth heartbeat signal and a fourth disable master signal for the fourth target node.
  • the multi-node server includes a logic programming device CPLD, and the logic programming device CPLD is used to determine the first target node, the second target node, the third target node, and the fourth heartbeat signal as a master node or a slave node.
  • CPLD logic programming device
  • the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
  • an embodiment of the present application also provides an electronic device, including: a processor, a memory, and a computer program stored in the memory and executable on the processor.
  • a computer program stored in the memory and executable on the processor.
  • the embodiment of the present application also provides a non-volatile computer-readable storage medium, as shown in FIG10 , a computer program is stored on the non-volatile computer-readable storage medium, and when the computer program is executed by the processor, each process of the above-mentioned master-slave node determination method embodiment is implemented, and the same technical effect can be achieved, so it will not be repeated here to avoid repetition.
  • the computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.
  • FIG. 9 is a schematic diagram of the hardware structure of an electronic device implementing various embodiments of the present application.
  • the electronic device 900 includes but is not limited to: a radio frequency unit 901, a network module 902, an audio output unit 903, an input unit 904, a sensor 905, a display unit 906, a user input unit 907, an interface unit 908, a memory 909, a processor 910, and a power supply 911.
  • a radio frequency unit 901 includes but is not limited to: a radio frequency unit 901, a network module 902, an audio output unit 903, an input unit 904, a sensor 905, a display unit 906, a user input unit 907, an interface unit 908, a memory 909, a processor 910, and a power supply 911.
  • the electronic device structure shown in FIG. 9 does not constitute a
  • the electronic device may include more or fewer components than shown in the figure, or may combine certain components, or arrange the components differently.
  • the electronic device includes but is not limited to a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted terminal, a wearable device, and
  • the radio frequency unit 901 can be used for receiving and sending signals during information transmission or calls. Specifically, after receiving downlink data from the base station, it is sent to the processor 910 for processing; in addition, uplink data is sent to the base station.
  • the radio frequency unit 901 includes but is not limited to an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, etc.
  • the radio frequency unit 901 can also communicate with the network and other devices through a wireless communication system.
  • the electronic device provides users with wireless broadband Internet access through the network module 902, such as helping users to send and receive emails, browse web pages, and access streaming media.
  • the audio output unit 903 can convert the audio data received by the RF unit 901 or the network module 902 or stored in the memory 909 into an audio signal and output it as sound. Moreover, the audio output unit 903 can also provide audio output related to a specific function performed by the electronic device 900 (for example, a call signal reception sound, a message reception sound, etc.).
  • the audio output unit 903 includes a speaker, a buzzer, a receiver, etc.
  • the input unit 904 is used to receive audio or video signals.
  • the input unit 904 may include a graphics processor (GPU) 9041 and a microphone 9042, and the graphics processor 9041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode.
  • the processed image frame can be displayed on the display unit 906.
  • the image frame processed by the graphics processor 9041 can be stored in the memory 909 (or other storage medium) or sent via the radio frequency unit 901 or the network module 902.
  • the microphone 9042 can receive sound and can process such sound into audio data.
  • the processed audio data can be converted into a format output that can be sent to a mobile communication base station via the radio frequency unit 901 in the case of a telephone call mode.
  • the electronic device 900 also includes at least one sensor 905, such as a light sensor, a motion sensor, and other sensors.
  • the light sensor includes an ambient light sensor and a proximity sensor, wherein the ambient light sensor can adjust the brightness of the display panel 9061 according to the brightness of the ambient light, and the proximity sensor can turn off the display panel 9061 and/or the backlight when the electronic device 900 is moved to the ear.
  • the accelerometer sensor can detect the magnitude of acceleration in each direction (generally three axes), and can detect the magnitude and direction of gravity when stationary, which can be used to identify the posture of the electronic device (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, tapping), etc.; the sensor 905 can also include a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, etc., which will not be repeated here.
  • the display unit 906 is used to display information input by the user or information provided to the user.
  • the display unit 906 may include a display panel 9061, which may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • the touch detection device detects the user's touch direction, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into touch point coordinates, and then sends it to the processor 910, receiving the signal sent by the processor 910.
  • the touch panel 9071 can be implemented by various types such as resistive, capacitive, infrared, and surface acoustic wave.
  • the user input unit 907 can also include other input devices 9072.
  • the other input devices 9072 can include but are not limited to physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which will not be repeated here.
  • the touch panel 9071 may be covered on the display panel 9061.
  • the touch panel 9071 detects a touch operation on or near it, it is transmitted to the processor 910 to determine the type of the touch event, and then the processor 910 provides a corresponding visual output on the display panel 9061 according to the type of the touch event.
  • the touch panel 9071 and the display panel 9061 are used as two independent components to implement the input and output functions of the electronic device, in some embodiments, the touch panel 9071 and the display panel 9061 may be integrated to implement the input and output functions of the electronic device, which is not limited here.
  • the interface unit 908 is an interface for connecting an external device to the electronic device 900.
  • the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input/output (I/O) port, a video I/O port, a headphone port, etc.
  • the interface unit 908 may be used to receive input (e.g., data information, power, etc.) from an external device and transmit the received input to one or more elements within the electronic device 900 or may be used to transmit data between the electronic device 900 and an external device.
  • the memory 909 can be used to store software programs and various data.
  • the memory 909 can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc.
  • the memory 909 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.
  • the processor 910 is the control center of the electronic device. It uses various interfaces and lines to connect various parts of the entire electronic device. It executes various functions of the electronic device and processes data by running or executing software programs and/or modules stored in the memory 909, and calling data stored in the memory 909, so as to monitor the electronic device as a whole.
  • the processor 910 may include one or more processing units; preferably, the processor 910 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 910.
  • the electronic device 900 may also include a power supply 911 (such as a battery) for supplying power to each component.
  • a power supply 911 (such as a battery) for supplying power to each component.
  • the power supply 911 may be logically connected to the processor 910 through a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system.
  • the electronic device 900 includes some functional modules not shown, which will not be described in detail here.
  • the technical solution of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, A disk or optical disk) includes several instructions for enabling a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in the various embodiments of the present application.
  • a storage medium such as ROM/RAM, A disk or optical disk
  • a terminal which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.
  • the disclosed devices and methods can be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.
  • Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application.
  • the aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

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Abstract

本申请实施例提供了一种主从节点确定方法、装置、电子设备及存储介质，通过从所述多个储存节点中确定出第一目标节点、第二目标节点、第三目标节点和第四目标节点；生成针对目标节点的心跳信号和禁主信号；当校验数据的第一首位字符和第一末位字符相同且第一首位字符和第一末位字符与预设值相同，且通过第二心跳信号、第二禁主信号、第三心跳信号、第三禁主信号、第四心跳信号和第四禁主信号判定第二目标节点、第三目标节点和第四目标节点不为主节点，且第一目标节点为主节点，且第一心跳信号处于正常状态时，将第一目标节点确定为主节点，从而实现了针对主节点的确定。

Description

一种主从节点确定方法、装置、电子设备及存储介质
相关申请的交叉引用
本申请要求于2022年11月10日提交中国专利局，申请号为202211408144.1，申请名称为“一种主从节点确定方法、装置、电子设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及主从节点确定技术领域，特别是涉及一种主从节点确定方法、一种主从节点确定装置、一种电子设备以及一种计算机可读存储介质。
背景技术
多节点服务器顾名思义就是多个节点的服务器，它由多个节点和管理装置整体的管理单元构成它可以减轻服务器的负载，可以进行分流并灵活应用也可以作为虚拟的磁盘服务器。多节点服务器还非常的易于管理，它的每个节点可以独立的进行管理，它可以通过机箱管理模块达到统一的管理工作模式，它具备了更好的通用性和更优的易用性。多节点服务器还拥有着模块化的部署，各节点可以灵活的进行搭配，可以混合进行部署，模块化的前窗可以根据用户的需求搭配不同种类的节点前窗。灵活扩展的特性，可以实现近乎定制化的产品配置。它可以面向多种不同的工作负载不同的计算节点可搭配不同块的大容量硬盘，无论是多网络扩展还是高IOPS(Input/Output Operations Per Second，是一个用于计算机存储设备)均可以得到完美的支持。
在实际应用中，针对多节点服务器进行数据存放。虽然具有多个储存节点，但是每个节点上面的内容不一样，如果坏了，数据就会丢失。为了保证这些数据的高可用，每个节点主机需要做备份，这些备份称为从节点，有了主从后，可以实现读写分离(主分片写，副本读)等扩展功能，所以，如何从多节点服务器的多个储存节点中确定出主从节点，成为了本领域技术人员需要攻克的技术问题。
发明内容
本申请实施例是提供一种主从节点确定方法、装置、电子设备以及计算机可读存储介质，以解决如何从多节点服务器的多个储存节点中确定出主节点的问题。
本申请实施例公开了一种主从节点确定方法，应用于多节点服务器，所述多节点服务器包括多个储存节点，所述方法可以包括：
从所述多个储存节点中确定出第一目标节点、第二目标节点、第三目标节点和第四目标节点；所述第一目标节点包括第一校验数据，所述第一校验数据包括第一首位字符和第一末位字符；
生成针对所述第一目标节点的第一心跳信号和第一禁主信号；
生成针对所述第二目标节点的第二心跳信号和第二禁主信号；
生成针对所述第三目标节点的第三心跳信号和第三禁主信号；
生成针对所述第四目标节点的第四心跳信号和第四禁主信号；
当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符 与预设值相同，且通过所述第二心跳信号、所述第二禁主信号、所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判定所述第二目标节点、所述第三目标节点和所述第四目标节点中不存在主节点时，且所述第一目标节点不为从节点，且所述第一禁主信号无效，且所述第一心跳信号处于正常状态时，将所述第一目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
当所述第一目标节点为从节点，且当所述第一心跳信号处于正常状态，且所述第一禁主信号无效，且所述第二禁主信号无效，且所述第三禁主信号无效时，将所述第一目标节点确定为主节点；
当所述第一目标节点为从节点，且当所述第一心跳信号处于异常状态，和/或，所述第一禁主信号有效，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效时，将所述第一目标节点确定为从节点；
当所述第一目标节点不为从节点，且当所述第一心跳信号处于异常状态，和/或，所述第一禁主信号有效，将所述第一目标节点确定为从节点；
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同时，将所述第一目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
当所述第一首位字符和所述第一末位字符相同，且所述第一首位字符和所述第一末位字符与预设值相同，则通过所述第一心跳信号、所述第一禁主信号、所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第一目标节点、所述第三目标节点和所述第四目标节点中是否存在主节点；
当判定所述第一目标节点、所述第三目标节点和所述第四目标节点不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，将第二目标节点确定为主节点；
当判定所述第一目标节点、所述第三目标节点和所述第四目标节点不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，且所述第三禁主信号无效，且所述第一心跳信号为异常状态或所述第一禁主信号有效时，将第二目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中存在主节点时，将第二目标节点确定为从节点；
当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效，和/或，所述第一心跳信号处于正常状态，和/或，所述第一禁主信号无效时，将所述第二目标节点确定为从节点；
当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，将所述第二目标节点确定为从节点。
在本申请一些实施例中，所述第二目标节点包括第二校验数据，所述第二校验数据包括第二首位字符和第二末位字符，还可以包括：
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符相同，且所述第二首位字符和所述第二末位字符与预设值相同时，通过所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第三目标节点和所述第四目标节点中是否存在主节点；
当判定所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，将所述第二目标节点确定为主节点；
当判定所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效，且所述第三禁主信号无效，将所述第二目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同时，将所述第二目标节点确定为从节点；
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符相同，且所述第二首位字符和所述第二末位字符与预设值相同，且判定所述第三目标节点和所述第四目标节点中存在主节点时，将第二目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
当所述第二目标节点不为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效时，将第二目标节点确定为从节点；
当所述第二目标节点为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效时，将所述第二目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，或，所述第二首位字符和所述第二末位字符相同且所述第二首位字符和所述第二末位字符与预设值相同时，通过所述第一心跳信号、所述第一禁主信号、所述第二心跳信号、所述第二禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第一目标节点、所述第二目标节点和所述第四目标节点中是否具有存在主节点；
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点不为从节点，且所述第三心跳信号为正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点；
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号有效，且所述第三心跳信号为正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点；
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号无效，且所述第三心跳信号为正常状态， 且所述第三禁主信号无效，且所述第一心跳信号处于异常状态或所述第一禁主信号有效，且第二心跳信号处于异常状态时，将所述第三目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中存在主节点时，将所述第三目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点不为从节点，且所述第三心跳信号处于异常状态，和/或，所述第三禁主信号有效，将所述第三目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号有效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效时，将所述第三目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号无效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效，和/或，所述第一心跳信号处于正常状态，和/或，所述第一禁主信号无效，和/或，第二心跳信号处于正常状态时，将所述第三目标节点确定为主节点。
在本申请一些实施例中，所述第三目标节点包括第三校验数据，所述第三校验数据包括第三首位字符和第三末位字符，还可以包括：
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，则通过所述第四心跳信号和所述第四禁主信号判断所述第四目标节点是否为主节点；
当判定所述第四目标节点不为主节点，则当所述第三心跳信号处于正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符不相同，和/或，所述第三首位字符和所述第三末位字符与预设值不相同时，将所述第三目标节点确定为从节点；
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，且判定所述第四目标节点为主节点时，将所述第三目标节点确定为从节点；
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位 字符相同且所述第三首位字符和所述第三末位字符与预设值相同，且判定所述第四目标节点不为主节点，且当所述第三心跳信号处于异常状态，和/或，所述第三禁主信号有效，将所述第三目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，或，所述第二首位字符和所述第二末位字符相同且所述第二首位字符和所述第二末位字符与预设值相同，或，所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同时，通过所述第一心跳信号、所述第一禁主信号、所述第二心跳信号、所述第二禁主信号、所述第三心跳信号和所述第三禁主信号判断所述第一目标节点、所述第二目标节点和所述第三目标节点中是否具有任一目标节点为主节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点不为从节点，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号有效，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，且所述第三心跳信号为异常状态或所述第三禁主信号有效时，将所述第四目标节点确定为主节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号有效，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号无效，且所述第一心跳信为异常状态或所述第一禁主信号有效，且所述第二心跳信号为异常状态，且所述第三心跳信号为异常状态时，将所述第四目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中存在主节点，将所述第三目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点不为从节点，且所述第四心跳信号为异常状态，和/或，所述第四禁主信号无效时，将所述第四目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号有效，且所述第四心跳信号处于异常状态，和/或，所述第四禁主信号有效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效时，将所述第四目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号有效，且所述第四心跳信号为异常状态，和/或，所述第四禁主信号有效时，将所述第四目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号无效，且所述第一心跳信为正常状态，和/或，所述第一禁主信号无效，和/或，所述第二心跳信号为正常状态，和/或，所述第三心跳信号为正常状态时，将所述第四目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中存在主节点，将所述第四目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符不相同，和/或，所述第三首位字符和所述第三末位字符与预设值不相同，且所述第四首位字符和所述第四末位字符相同且所述第四首位字符和所述第四末位字符与预设值相同，且当所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
当所述第四首位字符和所述第四末位字符不相同，和/或，所述第四首位字符和所述第四末位字符与预设值不相同，将所述第四目标节点确定为从节点；
当所述第四首位字符和所述第四末位字符相同且所述第四首位字符和所述第四末位字符与预设值相同，且所述第四心跳信号处于异常状态，和/或，所述第四禁主信号有效，将所述第四目标节点确定为从节点。
在本申请一些实施例中，所述第一目标节点、所述第二目标节点、所述第三目标节点和所述第四目标节点分别具有对应的基板管理控制器BMC，所述基板管理控制器BMC用于生成采用所述第一基板管理控制器BMC生成针对所述第一目标节点的第一心跳信号和第一禁主信号，以及生成针对所述第二目标节点的第二心跳信号和第二禁主信号，以及生成针对所述第三目标节点的第三心跳信号和第三禁主信号，以及生成针对所述第四目标节点的第四心跳信号和第四禁主信号。
在本申请一些实施例中，多节点服务器包括逻辑编程器件CPLD，所述逻辑编程器件CPLD用于将第一目标节点、第二目标节点、第三目标节点、第四心跳信号确定为主节点或从节点。
本申请实施例还公开了一种主从节点确定装置，应用于多节点服务器，所述多节点服务器包括多个储存节点，所述装置包括：
目标节点确定模块，用于从所述多个储存节点中确定出第一目标节点、第二目标节点、第三目标节点和第四目标节点；
第一信号生成模块，用于生成针对所述第一目标节点的第一心跳信号和第一禁主信号；
第二信号生成模块，用于生成针对所述第二目标节点的第二心跳信号和第二禁主信号；
第三信号生成模块，用于生成针对所述第三目标节点的第三心跳信号和第三禁主信号；
第四信号生成模块，用于生成针对所述第四目标节点的第四心跳信号和第四禁主信号；
主节点确定模块，用于当所述第一禁主信号有效，且通过所述第二心跳信号、所述第二禁主信号、所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号 判定所述第二目标节点、所述第三目标节点和所述第四目标节点中不存在主节点时，且所述第一目标节点为主节点，且所述第一禁主信号无效，且所述第一心跳信号处于正常状态时，将所述第一目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第一模块，用于在本申请一些实施例中，还可以包括：
第二模块，用于当所述第一目标节点为从节点，且当所述第一心跳信号处于正常状态，且所述第一禁主信号无效，且所述第二禁主信号无效，且所述第三禁主信号无效时，将所述第一目标节点确定为主节点；
第三模块，用于当所述第一目标节点为从节点，且当所述第一心跳信号处于异常状态，和/或，所述第一禁主信号有效，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效时，将所述第一目标节点确定为从节点；
第四模块，用于当所述第一目标节点不为从节点，且当所述第一心跳信号处于异常状态，和/或，所述第一禁主信号有效，将所述第一目标节点确定为从节点；
第五模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同时，将所述第一目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
第六模块，用于当所述第一首位字符和所述第一末位字符相同，且所述第一首位字符和所述第一末位字符与预设值相同，则通过所述第一心跳信号、所述第一禁主信号、所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第一目标节点、所述第三目标节点和所述第四目标节点中是否存在主节点；
第七模块，用于当判定所述第一目标节点、所述第三目标节点和所述第四目标节点不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，将第二目标节点确定为主节点；
第八模块，用于当判定所述第一目标节点、所述第三目标节点和所述第四目标节点不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，且所述第三禁主信号无效，且所述第一心跳信号为异常状态或所述第一禁主信号有效时，将第二目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第九模块，用于当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中存在主节点时，将第二目标节点确定为从节点；
第十模块，用于当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效，和/或，所述第一心跳信号处于正常状态，和/或，所述第一禁主信号无效时，将所述第二目标节点确定为从节点；
第十一模块，用于当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，将所述第二目标节点确定为从节点。
在本申请一些实施例中，所述第二目标节点包括第二校验数据，所述第二校验数据包括第二首位字符和第二末位字符，还可以包括：
第十二模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符相同，且所述第二首位字符和所述第二末位字符与预设值相同时，通过所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第三目标节点和所述第四目标节点中是否存在主节点；
第十三模块，用于当判定所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，将所述第二目标节点确定为主节点；
第十四模块，用于当判定所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效，且所述第三禁主信号无效，将所述第二目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第十五模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同时，将所述第二目标节点确定为从节点；
第十六模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符相同，且所述第二首位字符和所述第二末位字符与预设值相同，且判定所述第三目标节点和所述第四目标节点中存在主节点时，将第二目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
第十七模块，用于当所述第二目标节点不为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效时，将第二目标节点确定为从节点；
第十八模块，用于当所述第二目标节点为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效时，将所述第二目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
第十九模块，用于当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，或，所述第二首位字符和所述第二末位字符相同且所述第二首位字符和所述第二末位字符与预设值相同时，通过所述第一心跳信号、所述第一禁主信号、所述第二心跳信号、所述第二禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第一目标节点、所述第二目标节点和所述第四目标节点中是否具有存在主节点；
第二十模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点不为从节点，且所述第三心跳信号为正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点；
第二十一模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号有效，且所述第三心跳信号为正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点；
第二十二模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点 中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号无效，且所述第三心跳信号为正常状态，且所述第三禁主信号无效，且所述第一心跳信号处于异常状态或所述第一禁主信号有效，且第二心跳信号处于异常状态时，将所述第三目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第二十三模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中存在主节点时，将所述第三目标节点确定为从节点；
第二十四模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点不为从节点，且所述第三心跳信号处于异常状态，和/或，所述第三禁主信号有效，将所述第三目标节点确定为从节点；
第二十五模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号有效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效时，将所述第三目标节点确定为从节点；
第二十六模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号无效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效，和/或，所述第一心跳信号处于正常状态，和/或，所述第一禁主信号无效，和/或，第二心跳信号处于正常状态时，将所述第三目标节点确定为主节点。
在本申请一些实施例中，所述第三目标节点包括第三校验数据，所述第三校验数据包括第三首位字符和第三末位字符，还可以包括：
第二十七模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，则通过所述第四心跳信号和所述第四禁主信号判断所述第四目标节点是否为主节点；
第二十八模块，用于当判定所述第四目标节点不为主节点，则当所述第三心跳信号处于正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第二十九模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符不相同，和/或，所述第三首位字符和所述第三末位字符与预设值不相同时，将所述第三目标节点确定为从节点；
第三十模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，且判定所述第四目标节点为主节点时，将所述第三目标节点确定为从节点；
第三十一模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第 一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，且判定所述第四目标节点不为主节点，且当所述第三心跳信号处于异常状态，和/或，所述第三禁主信号有效，将所述第三目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
第三十二模块，用于当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，或，所述第二首位字符和所述第二末位字符相同且所述第二首位字符和所述第二末位字符与预设值相同，或，所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同时，通过所述第一心跳信号、所述第一禁主信号、所述第二心跳信号、所述第二禁主信号、所述第三心跳信号和所述第三禁主信号判断所述第一目标节点、所述第二目标节点和所述第三目标节点中是否具有任一目标节点为主节点；
第三十三模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点不为从节点，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点；
第三十四模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号有效，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，且所述第三心跳信号为异常状态或所述第三禁主信号有效时，将所述第四目标节点确定为主节点；
第三十五模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号有效，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点；
第三十六模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号无效，且所述第一心跳信为异常状态或所述第一禁主信号有效，且所述第二心跳信号为异常状态，且所述第三心跳信号为异常状态时，将所述第四目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第三十七模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中存在主节点，将所述第三目标节点确定为从节点；
第三十八模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点不为从节点，且所述第四心跳信号为异常状态，和/或，所述第四禁主信号无效时，将所述第四目标节点确定为从节点；
第三十九模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号有效，且所述第四心跳信号处于异常状态，和/或，所述第四禁主信号有效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效时，将所述第四目标节点确定为从节点；
第四十模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中 不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号有效，且所述第四心跳信号为异常状态，和/或，所述第四禁主信号有效时，将所述第四目标节点确定为从节点；
第四十一模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号无效，且所述第一心跳信为正常状态，和/或，所述第一禁主信号无效，和/或，所述第二心跳信号为正常状态，和/或，所述第三心跳信号为正常状态时，将所述第四目标节点确定为从节点；
第四十二模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中存在主节点，将所述第四目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
第四十三模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符不相同，和/或，所述第三首位字符和所述第三末位字符与预设值不相同，且所述第四首位字符和所述第四末位字符相同且所述第四首位字符和所述第四末位字符与预设值相同，且当所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第四十四模块，用于当所述第四首位字符和所述第四末位字符不相同，和/或，所述第四首位字符和所述第四末位字符与预设值不相同，将所述第四目标节点确定为从节点；
第四十五模块，用于当所述第四首位字符和所述第四末位字符相同且所述第四首位字符和所述第四末位字符与预设值相同，且所述第四心跳信号处于异常状态，和/或，所述第四禁主信号有效，将所述第四目标节点确定为从节点。
在本申请一些实施例中，所述第一目标节点、所述第二目标节点、所述第三目标节点和所述第四目标节点分别具有对应的基板管理控制器BMC，所述基板管理控制器BMC用于生成采用所述第一基板管理控制器BMC生成针对所述第一目标节点的第一心跳信号和第一禁主信号，以及生成针对所述第二目标节点的第二心跳信号和第二禁主信号，以及生成针对所述第三目标节点的第三心跳信号和第三禁主信号，以及生成针对所述第四目标节点的第四心跳信号和第四禁主信号。
在本申请一些实施例中，多节点服务器包括逻辑编程器件CPLD，所述逻辑编程器件CPLD用于将第一目标节点、第二目标节点、第三目标节点、第四心跳信号确定为主节点或从节点。
本申请实施例还公开了一种电子设备，包括处理器、通信接口、存储器和通信总线，其中，所述处理器、所述通信接口以及所述存储器通过所述通信总线完成相互间的通信；
所述存储器，用于存放计算机程序；
所述处理器，用于执行存储器上所存放的程序时，实现如本申请实施例所述的方法。
本申请实施例还公开了一种计算机可读存储介质，其上存储有指令，当由一个或多个处理器执行时，使得所述处理器执行如本申请实施例所述的方法。
本申请实施例包括以下优点：本申请实施例，通过从所述多个储存节点中确定出第一目标节点、第二目标节点、第三目标节点和第四目标节点；生成针对目标节点的心跳信号和禁主信号；当校验数据的第一首位字符和第一末位字符相同且第一首位字符和第一末位字符与预设值相同，且通过第二心跳信号、第二禁主信号、第三心跳信号、第三禁主信号、第四心跳信号和第四禁主信号判定第二目标节点、第三目标节点和第四目标节点不为主节点，且第一目标节点不为从节点，且第一心跳信号处于正常状态时，将第一目标节点确定为主节点，从而实现了针对主节点的确定。
附图说明
图1是本申请实施例中提供的一种主从节点确定方法的步骤流程图；
图2是本申请实施例中提供的一种储存控制器的结构示意图；
图3是本申请实施例中提供的一种储存控制器节点的结构示意图；
图4是本申请实施例中提供的一种第一目标节点主从关系确定方法的步骤流程示意图；
图5是本申请实施例中提供的一种第二目标节点主从关系确定方法的步骤流程示意图；
图6是本申请实施例中提供的一种第三目标节点主从关系确定方法的步骤流程示意图；
图7是本申请实施例中提供的一种第四目标节点主从关系确定方法的步骤流程示意图；
图8是本申请实施例中提供的一种主从节点确定装置的结构框图；
图9是本申请各实施例中提供的一种电子设备的硬件结构框图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本申请作进一步详细的说明。
参照图1，示出了本申请实施例中提供的一种主从节点确定方法的步骤流程图，具体可以包括如下步骤：
步骤101，从所述多个储存节点中确定出第一目标节点、第二目标节点、第三目标节点和第四目标节点；所述第一目标节点包括第一校验数据，所述第一校验数据包括第一首位字符和第一末位字符；
步骤102，生成针对所述第一目标节点的第一心跳信号和第一禁主信号；
步骤103，生成针对所述第二目标节点的第二心跳信号和第二禁主信号；
步骤104，生成针对所述第三目标节点的第三心跳信号和第三禁主信号；
步骤105，生成针对所述第四目标节点的第四心跳信号和第四禁主信号；
步骤106，当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，且通过所述第二心跳信号、所述第二禁主信号、所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判定所述第二目标节点、所述第三目标节点和所述第四目标节点中不存在主节点时，且所述第一目标节点不为从节点，且所述第一禁主信号无效，且所述第一心跳信号处于正常状态时，将所述第一目标节点确定为主节点。
在具体实现中，本申请可以应用于多节点服务器，多节点服务器可以包括储存控制器，参考图2，图2是本申请实施例中提供的一种储存控制器的结构示意图，存储控制器可以包括四个节点，各个节点均与存储控制器内部的背板互联；除各个节点(控制单元)外，存储控制器内部还包括多个共享部件：如磁盘阵列、风扇、PSU(供电单元)，接口卡等。
在本申请一些实施例中，存储控制器的每个节点在硬件设计上可以完全相同；每个节点都包含负责节点内部控制的逻辑编程器件CPLD模块和负责节点内部硬件管理的基板管理控制器BMC。
BMC，执行伺服器远端管理控制器，英文全称为Baseboard Management Controller，也称为基板管理控制器。
CPLD(Complex Programmable Logic Device)是Complex PLD的简称,一种较PLD为复杂的逻辑元件。CPLD是一种用户根据各自需要而自行构造逻辑功能的数字集成电路。其基本设计方法是借助集成开发软件平台，用原理图、硬件描述语言等方法，生成相应的目标文件，通过下载电缆(“在系统”编程)将代码传送到目标芯片中，实现设计的数字系统。
存储控制器内部各节点(控制单元)的主从节点属性由各节点内部的CPLD确定；示例性地，任一节点内，CPLD和BMC之间有3个接口信号，参考图3，图3是本申请实施例中提供的一种储存控制器节点的结构示意图，CPLD和BMC可以通过接口信号实现数据交互，本申请实施例可以生成针对目标从多个储存节点中确定出第一目标节点、第二目标节点、第三目标节点和第四目标节点，并在本申请一些实施例中，本申请实施例可以通过BMC可以用于生成针对所述第一目标节点的第一心跳信号和第一禁主信号；生成针对所述第二目标节点的第二心跳信号和第二禁主信号；生成针对所述第三目标节点的第三心跳信号和第三禁主信号；生成针对所述第四目标节点的第四心跳信号和第四禁主信号，CPLD将第一目标节点、第二目标节点、第三目标节点、第四心跳信号确定为主节点或从节点后，通过信号线将此信号传递到BMC，供BMC使用。
bmc_heart信号：也称为BMC的心跳信号，bmc_heart信号正常时，BMC正常工作；反之，bmc_heart信号异常时，BMC工作异常；BMC工作异常的节点不能做为主节点；
master_disable信号：也称为BMC发送的禁主(禁止本节点成为主节点)信号；master_disable信号有效时，本节点不能做为主节点；已知master_disable信号是一个10ms的脉冲信号；master_disable信号为高电平时为有效状态；具体设计时，要求使用master_disable信号时，主节点按照ABCD的固定顺序切换。例如：存储控制器内部有ABCD四个节点；当前B节点为主节点；B节点的BMC发送的master_disable信号有效后，B节点称为从节点，C节点升为主节点。B节点的BMC发送的master_disable信号无效后，在符合条件时，B节点仍然可成为主节点。
在实际应用中，各储存节点可以分别具有对应的校验数据，校验数据可以包括首位字符和末位字符，示例性地，校验数据可以为储存节点插在背板上的不同槽位时，从背板上获取到的不同标志值。
在具体实现中，本申请实施例可以通过判断首位字符和末位字符是否相同，以及，判断首位字符和末位字符是否等于预设值，从而判定该储存节点的数据是否有效。
例如，储存节点X的预设值为1，当储存节点X的校验数据的首位字符为1，且末位字符为1时，可以判定储存节点X的数据有效。
本申请实施例可以当第一首位字符和第一末位字符相同且与预设值相同，且通过第二心跳信号、第二禁主信号、第三心跳信号、第三禁主信号、第四心跳信号和第四禁主信号判定第二目标节点、第三目标节点和第四目标节点中不存在主节点时，判断第一目标节点当前是否为从节点，当第一目标节点当前不为从节点，且当第一禁主信号无效，且第一心跳信号处 于正常状态时，将第一目标节点确定为主节点，当确定出主节点后，可以将存储控制器内部其他节点作为从节点。
例如，参考图4，图4是本申请实施例中提供的一种第一目标节点主从关系确定方法的步骤流程示意图，A节点可以相当于第一目标节点，B节点可以相当于第二目标节点，C节点可以相当于第三目标节点，D节点可以相当于第四目标节点，当A节点的校验数据的第一首位字符和第一末位字符相同且第一首位字符和第一末位字符与预设值相同，即，A节点数据有效，且通过第二心跳信号、第二禁主信号、第三心跳信号、第三禁主信号、第四心跳信号和第四禁主信号判定第二目标节点、第三目标节点和第四目标节点中不存在主节点，且当A节点当前不为从节点，且第一心跳信号处于正常状态时，将A节点确定为主节点。
本申请实施例，通过从所述多个储存节点中确定出第一目标节点、第二目标节点、第三目标节点和第四目标节点；所述第一目标节点包括第一校验数据，所述第一校验数据包括第一首位字符和第一末位字符；生成针对所述第一目标节点的第一心跳信号和第一禁主信号；生成针对所述第二目标节点的第二心跳信号和第二禁主信号；生成针对所述第三目标节点的第三心跳信号和第三禁主信号；生成针对所述第四目标节点的第四心跳信号和第四禁主信号；当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，且通过所述第二心跳信号、所述第二禁主信号、所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判定所述第二目标节点、所述第三目标节点和所述第四目标节点中不存在主节点时，且所述第一目标节点不为从节点，且所述第一禁主信号无效，且所述第一心跳信号处于正常状态时，将所述第一目标节点确定为主节点，从而实现了针对主节点的确定。
在上述实施例的基础上，提出了上述实施例的变型实施例，在此需要说明的是，为了使描述简要，在变型实施例中仅描述与上述实施例的不同之处。
参考图4，在本申请的一些实施例中，可以通过当所述第一目标节点为从节点，且当所述第一心跳信号处于正常状态，且所述第一禁主信号无效，且所述第二禁主信号无效，且所述第三禁主信号无效时，将所述第一目标节点确定为主节点；
当所述第一目标节点为从节点，且当所述第一心跳信号处于异常状态，和/或，所述第一禁主信号有效，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效时，将所述第一目标节点确定为从节点；
当所述第一目标节点不为从节点，且当所述第一心跳信号处于异常状态，和/或，所述第一禁主信号有效，将所述第一目标节点确定为从节点；
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同时，将所述第一目标节点确定为从节点。
参考图5，图5是本申请实施例中提供的一种第二目标节点主从关系确定方法的步骤流程示意图，A节点可以相当于第一目标节点，B节点可以相当于第二目标节点，C节点可以相当于第三目标节点，D节点可以相当于第四目标节点，在本申请的一些实施例中，还可以通过当所述第一首位字符和所述第一末位字符相同，且所述第一首位字符和所述第一末位字符与预设值相同，则通过所述第一心跳信号、所述第一禁主信号、所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第一目标节点、所述第三目标节点和所述第四目标节点中是否存在主节点；
当判定所述第一目标节点、所述第三目标节点和所述第四目标节点不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，将第二目标节点确定为主节点；
当判定所述第一目标节点、所述第三目标节点和所述第四目标节点不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，且所述第三禁主信号无效，且所述第一心跳信号为异常状态或所述第一禁主信号有效时，将第二目标节点确定为主节点。从而实现了对第二目标节点作为主节点进行判定，更进一步地提升了针对储存节点主从储存节点的确定效率。
参考图5，在本申请的一些实施例中，还可以通过当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中存在主节点时，将第二目标节点确定为从节点；
当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效，和/或，所述第一心跳信号处于正常状态，和/或，所述第一禁主信号无效时，将所述第二目标节点确定为从节点；
当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，将所述第二目标节点确定为从节点，从而实现了对第二目标节点作为从节点进行判定，更进一步地提升了针对储存节点主从储存节点的确定效率。
参考图5，在本申请的一些实施例中，所述第二目标节点包括第二校验数据，所述第二校验数据包括第二首位字符和第二末位字符，还可以通过当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符相同，且所述第二首位字符和所述第二末位字符与预设值相同时，通过所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第三目标节点和所述第四目标节点中是否存在主节点；
当判定所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，将所述第二目标节点确定为主节点；
当判定所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效，且所述第三禁主信号无效，将所述第二目标节点确定为主节点，从而实现了对第二目标节点作为主节点进行判定，更进一步地提升了针对储存节点主从储存节点的确定效率。
参考图5，在本申请的一些实施例中，还可以通过当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同时，将所述第二目标节点确定为从节点；
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符相同，且所述第二首位字符和所述第二末位字符与预设值相同，且判定所述第三目标节点和所述第四目标节点中存在主节点时，将第二目标节点确定为从节点；
当所述第二目标节点不为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效时，将第二目标节点确定为从节点；
当所述第二目标节点为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效时，将所述第二目标节点确定为从节点。从而实现了对第二目标节点作为从节点进行判定，更进一步地提升了针对储存节点主从储存节点的确定效率。
参考图6，图6是本申请实施例中提供的一种第三目标节点主从关系确定方法的步骤流程示意图，A节点可以相当于第一目标节点，B节点可以相当于第二目标节点，C节点可以相当于第三目标节点，D节点可以相当于第四目标节点，在本申请的一些实施例中，可以当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，或，所述第二首位字符和所述第二末位字符相同且所述第二首位字符和所述第二末位字符与预设值相同时，通过所述第一心跳信号、所述第一禁主信号、所述第二心跳信号、所述第二禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第一目标节点、所述第二目标节点和所述第四目标节点中是否具有存在主节点；
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点不为从节点，且所述第三心跳信号为正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点；
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号有效，且所述第三心跳信号为正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点；
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号无效，且所述第三心跳信号为正常状态，且所述第三禁主信号无效，且所述第一心跳信号处于异常状态或所述第一禁主信号有效，且第二心跳信号处于异常状态时，将所述第三目标节点确定为主节点，从而实现了对第三目标节点作为主节点进行判定，更进一步地提升了针对储存节点主从储存节点的确定效率。
参考图6，在本申请的一些实施例中，还可以通过当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中存在主节点时，将所述第三目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点不为从节点，且所述第三心跳信号处于异常状态，和/或，所述第三禁主信号有效，将所述第三目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号有效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效时，将所述第三目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号无效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效，和/或，所述第一心跳信号处于正常状态，和/或，所述第一禁主信号无效，和/或，第二心跳信号处于正常状态时，将所述第三目标节点确定为从节点，从而实现了对第三目标节点作为从节点进行判定，更进一步地提升了针对储存节点主从储存节点的确定效率。
参考图6，在本申请的一些实施例中，所述第三目标节点包括第三校验数据，所述第三校验数据包括第三首位字符和第三末位字符，还可以通过当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，则通过所述第四心跳信号和所述第四禁主信号判断所述第四目标节点是否为主节点；
当判定所述第四目标节点不为主节点，则当所述第三心跳信号处于正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点，从而实现了对第三目标节点作为主节点进行判定，更进一步地提升了针对储存节点主从储存节点的确定效率。
参考图6，在本申请的一些实施例中，还可以通过当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符不相同，和/或，所述第三首位字符和所述第三末位字符与预设值不相同时，将所述第三目标节点确定为从节点；
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，且判定所述第四目标节点为主节点时，将所述第三目标节点确定为从节点；
当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，且判定所述第四目标节点不为主节点，且当所述第三心跳信号处于异常状态，和/或，所述第三禁主信号有效，将所述第三目标节点确定为从节点，从而实现了对第三目标节点作为从节点进行判定，更进一步地提升了针对储存节点主从储存节点的确定效率。
参考图7，图7是本申请实施例中提供的一种第四目标节点主从关系确定方法的步骤流程示意图，A节点可以相当于第一目标节点，B节点可以相当于第二目标节点，C节点可以相当于第三目标节点，D节点可以相当于第四目标节点，在本申请的一些实施例中，还可以通过当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，或，所述第二首位字符和所述第二末位字符相同且所述第二首位字符和所述第二末位字符与预设值相同，或，所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同时，通过所述第一心跳信号、所述第一禁主信号、所述第二心跳信号、所述第二禁主信号、所述第三心跳信号和所述第三禁主信号判断所述第一目标节点、所述第二目标节点和所述第三目标节点中是否具有任一目标节点为主节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点不为从节点，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号有效，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，且所述第三心跳信号为异常状态或所述第三禁主信号有效时，将所述第四目标节点确定为主节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号有效，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号无效，且所述第一心跳信为异常状态或所述第一禁主信号有效，且所述第二心跳信号为异常状态，且所述第三心跳信号为异常状态时，将所述第四目标节点确定为主节点。从而实现了对第四目标节点作为主节点进行判定，更进一步地提升了针对储存节点主从储存节点的确定效率。
参考图7，在本申请的一些实施例中，还可以通过当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中存在主节点，将所述第三目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点不为从节点，且所述第四心跳信号为异常状态，和/或，所述第四禁主信号无效时，将所述第四目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号有效，且所述第四心跳信号处于异常状态，和/或，所述第四禁主信号有效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效时，将所述第四目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号有效，且所述第四心跳信号为异常状态，和/或，所述第四禁主信号有效时，将所述第四目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号无效，且所述第一心跳信为正常状态，和/或，所述第一禁主信号无效，和/或，所述第二心跳信号为正常状态，和/或，所述第三心跳信号为正常状态时，将所述第四目标节点确定为从节点；
当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中存在主节点，将所述第四目标节点确定为从节点。从而实现了对第四目标节点作为从节点进行判定，更进一步地提升了针对储存节点主从储存节点的确定效率。
参考图7，在本申请的一些实施例中，所述第四目标节点包括第四校验数据，所述第四校验数据包括第四首位字符和第四末位字符，还可以通过当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符不相同，和/或，所述第三首位字符和所述第三末位字符与预设值不相同，且所述第四首位字符和所述第四末位字符相同且所 述第四首位字符和所述第四末位字符与预设值相同，且当所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点。从而实现了对第四目标节点作为主节点进行判定，更进一步地提升了针对储存节点主从储存节点的确定效率。
参考图7，在本申请的一些实施例中，还可以通过当所述第四首位字符和所述第四末位字符不相同，和/或，所述第四首位字符和所述第四末位字符与预设值不相同，将所述第四目标节点确定为从节点；
当所述第四首位字符和所述第四末位字符相同且所述第四首位字符和所述第四末位字符与预设值相同，且所述第四心跳信号处于异常状态，和/或，所述第四禁主信号有效，将所述第四目标节点确定为从节点，从而实现了对第四目标节点作为从节点进行判定，更进一步地提升了针对储存节点主从储存节点的确定效率。
需要说明的是，对于方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请实施例并不受所描述的动作顺序的限制，因为依据本申请实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作并不一定是本申请实施例所必须的。
参照图8，示出了本申请实施例中提供的一种主从节点确定装置的结构框图，具体可以包括如下模块：
目标节点确定模块801，用于从所述多个储存节点中确定出第一目标节点、第二目标节点、第三目标节点和第四目标节点；所述第一目标节点包括第一校验数据，所述第一校验数据包括第一首位字符和第一末位字符；
第一信号生成模块802，用于生成针对所述第一目标节点的第一心跳信号和第一禁主信号；
第二信号生成模块803，用于生成针对所述第二目标节点的第二心跳信号和第二禁主信号；
第三信号生成模块804，用于生成针对所述第三目标节点的第三心跳信号和第三禁主信号；
第四信号生成模块805，用于生成针对所述第四目标节点的第四心跳信号和第四禁主信号；
主节点确定模块806，用于当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，且通过所述第二心跳信号、所述第二禁主信号、所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判定所述第二目标节点、所述第三目标节点和所述第四目标节点中不存在主节点时，且所述第一目标节点不为从节点，且所述第一禁主信号无效，且所述第一心跳信号处于正常状态时，将所述第一目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第一模块，用于在本申请一些实施例中，还可以包括：
第二模块，用于当所述第一目标节点为从节点，且当所述第一心跳信号处于正常状态，且所述第一禁主信号无效，且所述第二禁主信号无效，且所述第三禁主信号无效时，将所述第一目标节点确定为主节点；
第三模块，用于当所述第一目标节点为从节点，且当所述第一心跳信号处于异常状态，和/或，所述第一禁主信号有效，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效时，将所述第一目标节点确定为从节点；
第四模块，用于当所述第一目标节点不为从节点，且当所述第一心跳信号处于异常状态，和/或，所述第一禁主信号有效，将所述第一目标节点确定为从节点；
第五模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同时，将所述第一目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
第六模块，用于当所述第一首位字符和所述第一末位字符相同，且所述第一首位字符和所述第一末位字符与预设值相同，则通过所述第一心跳信号、所述第一禁主信号、所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第一目标节点、所述第三目标节点和所述第四目标节点中是否存在主节点；
第七模块，用于当判定所述第一目标节点、所述第三目标节点和所述第四目标节点不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，将第二目标节点确定为主节点；
第八模块，用于当判定所述第一目标节点、所述第三目标节点和所述第四目标节点不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，且所述第三禁主信号无效，且所述第一心跳信号为异常状态或所述第一禁主信号有效时，将第二目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第九模块，用于当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中存在主节点时，将第二目标节点确定为从节点；
第十模块，用于当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效，和/或，所述第一心跳信号处于正常状态，和/或，所述第一禁主信号无效时，将所述第二目标节点确定为从节点；
第十一模块，用于当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，将所述第二目标节点确定为从节点。
在本申请一些实施例中，所述第二目标节点包括第二校验数据，所述第二校验数据包括第二首位字符和第二末位字符，还可以包括：
第十二模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符相同，且所述第二首位字符和所述第二末位字符与预设值相同时，通过所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第三目标节点和所述第四目标节点中是否存在主节点；
第十三模块，用于当判定所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，将所述第二目标节点确定为主节点；
第十四模块，用于当判定所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效，且所述第三禁主信号无效，将所述第二目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第十五模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同时，将所述第二目标节点确定为从节点；
第十六模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符相同，且所述第二首位字符和所述第二末位字符与预设值相同，且判定所述第三目标节点和所述第四目标节点中存在主节点时，将第二目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
第十七模块，用于当所述第二目标节点不为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效时，将第二目标节点确定为从节点；
第十八模块，用于当所述第二目标节点为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效时，将所述第二目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
第十九模块，用于当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，或，所述第二首位字符和所述第二末位字符相同且所述第二首位字符和所述第二末位字符与预设值相同时，通过所述第一心跳信号、所述第一禁主信号、所述第二心跳信号、所述第二禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第一目标节点、所述第二目标节点和所述第四目标节点中是否具有存在主节点；
第二十模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点不为从节点，且所述第三心跳信号为正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点；
第二十一模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号有效，且所述第三心跳信号为正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点；
第二十二模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号无效，且所述第三心跳信号为正常状态，且所述第三禁主信号无效，且所述第一心跳信号处于异常状态或所述第一禁主信号有效，且第二心跳信号处于异常状态时，将所述第三目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第二十三模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中存在主节点时，将所述第三目标节点确定为从节点；
第二十四模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点不为从节点，且所述第三心跳信号处于异常状态，和 /或，所述第三禁主信号有效，将所述第三目标节点确定为从节点；
第二十五模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号有效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效时，将所述第三目标节点确定为从节点；
第二十六模块，用于当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号无效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效，和/或，所述第一心跳信号处于正常状态，和/或，所述第一禁主信号无效，和/或，第二心跳信号处于正常状态时，将所述第三目标节点确定为主节点。
在本申请一些实施例中，所述第三目标节点包括第三校验数据，所述第三校验数据包括第三首位字符和第三末位字符，还可以包括：
第二十七模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，则通过所述第四心跳信号和所述第四禁主信号判断所述第四目标节点是否为主节点；
第二十八模块，用于当判定所述第四目标节点不为主节点，则当所述第三心跳信号处于正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第二十九模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符不相同，和/或，所述第三首位字符和所述第三末位字符与预设值不相同时，将所述第三目标节点确定为从节点；
第三十模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，且判定所述第四目标节点为主节点时，将所述第三目标节点确定为从节点；
第三十一模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，且判定所述第四目标节点不为主节点，且当所述第三心跳信号处于异常状态，和/或，所述第三禁主信号有效，将所述第三目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
第三十二模块，用于当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，或，所述第二首位字符和所述第二末位字符相同且所述 第二首位字符和所述第二末位字符与预设值相同，或，所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同时，通过所述第一心跳信号、所述第一禁主信号、所述第二心跳信号、所述第二禁主信号、所述第三心跳信号和所述第三禁主信号判断所述第一目标节点、所述第二目标节点和所述第三目标节点中是否具有任一目标节点为主节点；
第三十三模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点不为从节点，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点；
第三十四模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号有效，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，且所述第三心跳信号为异常状态或所述第三禁主信号有效时，将所述第四目标节点确定为主节点；
第三十五模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号有效，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点；
第三十六模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号无效，且所述第一心跳信为异常状态或所述第一禁主信号有效，且所述第二心跳信号为异常状态，且所述第三心跳信号为异常状态时，将所述第四目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第三十七模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中存在主节点，将所述第三目标节点确定为从节点；
第三十八模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点不为从节点，且所述第四心跳信号为异常状态，和/或，所述第四禁主信号无效时，将所述第四目标节点确定为从节点；
第三十九模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号有效，且所述第四心跳信号处于异常状态，和/或，所述第四禁主信号有效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效时，将所述第四目标节点确定为从节点；
第四十模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号有效，且所述第四心跳信号为异常状态，和/或，所述第四禁主信号有效时，将所述第四目标节点确定为从节点；
第四十一模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号无效，且所述第一心跳信为正常状态，和/或，所述第一禁主信号无效，和/或，所述第二心跳信号为正常状态，和/或，所述第三心跳信号为正常状态时，将所述第四目标节点确定为从节点；
第四十二模块，用于当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中存在主节点，将所述第四目标节点确定为从节点。
在本申请一些实施例中，还可以包括：
第四十三模块，用于当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符不相同，和/或，所述第三首位字符和所述第三末位字符与预设值不相同，且所述第四首位字符和所述第四末位字符相同且所述第四首位字符和所述第四末位字符与预设值相同，且当所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点。
在本申请一些实施例中，还可以包括：
第四十四模块，用于当所述第四首位字符和所述第四末位字符不相同，和/或，所述第四首位字符和所述第四末位字符与预设值不相同，将所述第四目标节点确定为从节点；
第四十五模块，用于当所述第四首位字符和所述第四末位字符相同且所述第四首位字符和所述第四末位字符与预设值相同，且所述第四心跳信号处于异常状态，和/或，所述第四禁主信号有效，将所述第四目标节点确定为从节点。
在本申请一些实施例中，所述第一目标节点、所述第二目标节点、所述第三目标节点和所述第四目标节点分别具有对应的基板管理控制器BMC，所述基板管理控制器BMC用于生成采用所述第一基板管理控制器BMC生成针对所述第一目标节点的第一心跳信号和第一禁主信号，以及生成针对所述第二目标节点的第二心跳信号和第二禁主信号，以及生成针对所述第三目标节点的第三心跳信号和第三禁主信号，以及生成针对所述第四目标节点的第四心跳信号和第四禁主信号。
在本申请一些实施例中，多节点服务器包括逻辑编程器件CPLD，所述逻辑编程器件CPLD用于将第一目标节点、第二目标节点、第三目标节点、第四心跳信号确定为主节点或从节点。
对于装置实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
另外，本申请实施例还提供了一种电子设备，包括：处理器，存储器，存储在存储器上并可在处理器上运行的计算机程序，该计算机程序被处理器执行时实现上述主从节点确定方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
本申请实施例还提供了一种非易失性计算机可读存储介质，如图10所示，非易失性计算机可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现上述主从节点确定方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。其中，所述的计算机可读存储介质，如只读存储器(Read-Only Memory，简称ROM)、随机存取存储器(Random Access Memory，简称RAM)、磁碟或者光盘等。
图9为实现本申请各个实施例的一种电子设备的硬件结构示意图。
该电子设备900包括但不限于：射频单元901、网络模块902、音频输出单元903、输入单元904、传感器905、显示单元906、用户输入单元907、接口单元908、存储器909、处理器910、以及电源911等部件。本领域技术人员可以理解，图9中示出的电子设备结构并不构成 对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本申请实施例中，电子设备包括但不限于手机、平板电脑、笔记本电脑、掌上电脑、车载终端、可穿戴设备、以及计步器等。
应理解的是，本申请实施例中，射频单元901可用于收发信息或通话过程中，信号的接收和发送，具体的，将来自基站的下行数据接收后，给处理器910处理；另外，将上行的数据发送给基站。通常，射频单元901包括但不限于天线、至少一个放大器、收发信机、耦合器、低噪声放大器、双工器等。此外，射频单元901还可以通过无线通信系统与网络和其他设备通信。
电子设备通过网络模块902为用户提供了无线的宽带互联网访问，如帮助用户收发电子邮件、浏览网页和访问流式媒体等。
音频输出单元903可以将射频单元901或网络模块902接收的或者在存储器909中存储的音频数据转换成音频信号并且输出为声音。而且，音频输出单元903还可以提供与电子设备900执行的特定功能相关的音频输出(例如，呼叫信号接收声音、消息接收声音等等)。音频输出单元903包括扬声器、蜂鸣器以及受话器等。
输入单元904用于接收音频或视频信号。输入单元904可以包括图形处理器(Graphics Processing Unit，GPU)9041和麦克风9042，图形处理器9041对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。处理后的图像帧可以显示在显示单元906上。经图形处理器9041处理后的图像帧可以存储在存储器909(或其它存储介质)中或者经由射频单元901或网络模块902进行发送。麦克风9042可以接收声音，并且能够将这样的声音处理为音频数据。处理后的音频数据可以在电话通话模式的情况下转换为可经由射频单元901发送到移动通信基站的格式输出。
电子设备900还包括至少一种传感器905，比如光传感器、运动传感器以及其他传感器。具体地，光传感器包括环境光传感器及接近传感器，其中，环境光传感器可根据环境光线的明暗来调节显示面板9061的亮度，接近传感器可在电子设备900移动到耳边时，关闭显示面板9061和/或背光。作为运动传感器的一种，加速计传感器可检测各个方向上(一般为三轴)加速度的大小，静止时可检测出重力的大小及方向，可用于识别电子设备姿态(比如横竖屏切换、相关游戏、磁力计姿态校准)、振动识别相关功能(比如计步器、敲击)等；传感器905还可以包括指纹传感器、压力传感器、虹膜传感器、分子传感器、陀螺仪、气压计、湿度计、温度计、红外线传感器等，在此不再赘述。
显示单元906用于显示由用户输入的信息或提供给用户的信息。显示单元906可包括显示面板9061，可以采用液晶显示器(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light-Emitting Diode,OLED)等形式来配置显示面板9061。
用户输入单元907可用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。具体地，用户输入单元907包括触控面板9071以及其他输入设备9072。触控面板9071，也称为触摸屏，可收集用户在其上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触控面板9071上或在触控面板9071附近的操作)。触控面板9071可包括触摸检测装置和触摸控制器两个部分。其中，触摸检测装置检测用户的触摸方位，并检测触摸操作带来的信号，将信号传送给触摸控制器；触摸控制器从触摸检测装置上接收触摸信息，并将它转换成触点坐标，再送给处理器910，接收处理器910发 来的命令并加以执行。此外，可以采用电阻式、电容式、红外线以及表面声波等多种类型实现触控面板9071。除了触控面板9071，用户输入单元907还可以包括其他输入设备9072。具体地，其他输入设备9072可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
进一步的，触控面板9071可覆盖在显示面板9061上，当触控面板9071检测到在其上或附近的触摸操作后，传送给处理器910以确定触摸事件的类型，随后处理器910根据触摸事件的类型在显示面板9061上提供相应的视觉输出。虽然在图9中，触控面板9071与显示面板9061是作为两个独立的部件来实现电子设备的输入和输出功能，但是在某些实施例中，可以将触控面板9071与显示面板9061集成而实现电子设备的输入和输出功能，具体此处不做限定。
接口单元908为外部装置与电子设备900连接的接口。例如，外部装置可以包括有线或无线头戴式耳机端口、外部电源(或电池充电器)端口、有线或无线数据端口、存储卡端口、用于连接具有识别模块的装置的端口、音频输入/输出(I/O)端口、视频I/O端口、耳机端口等等。接口单元908可以用于接收来自外部装置的输入(例如，数据信息、电力等等)并且将接收到的输入传输到电子设备900内的一个或多个元件或者可以用于在电子设备900和外部装置之间传输数据。
存储器909可用于存储软件程序以及各种数据。存储器909可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据手机的使用所创建的数据(比如音频数据、电话本等)等。此外，存储器909可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。
处理器910是电子设备的控制中心，利用各种接口和线路连接整个电子设备的各个部分，通过运行或执行存储在存储器909内的软件程序和/或模块，以及调用存储在存储器909内的数据，执行电子设备的各种功能和处理数据，从而对电子设备进行整体监控。处理器910可包括一个或多个处理单元；优选的，处理器910可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器910中。
电子设备900还可以包括给各个部件供电的电源911(比如电池)，优选的，电源911可以通过电源管理系统与处理器910逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。
另外，电子设备900包括一些未示出的功能模块，在此不再赘述。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、 磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。
本领域普通技术人员可以意识到，结合本申请实施例中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种主从节点确定方法，其特征在于，应用于多节点服务器，所述多节点服务器包括多个储存节点，所述方法包括：
    从所述多个储存节点中确定出第一目标节点、第二目标节点、第三目标节点和第四目标节点；所述第一目标节点包括第一校验数据，所述第一校验数据包括第一首位字符和第一末位字符；
    生成针对所述第一目标节点的第一心跳信号和第一禁主信号；
    生成针对所述第二目标节点的第二心跳信号和第二禁主信号；
    生成针对所述第三目标节点的第三心跳信号和第三禁主信号；
    生成针对所述第四目标节点的第四心跳信号和第四禁主信号；
    当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，且通过所述第二心跳信号、所述第二禁主信号、所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判定所述第二目标节点、所述第三目标节点和所述第四目标节点中不存在主节点时，且所述第一目标节点不为从节点，且所述第一禁主信号无效，且所述第一心跳信号处于正常状态时，将所述第一目标节点确定为主节点。
  2. 根据权利要求1所述的方法，其特征在于，还包括：
    当所述第一目标节点为从节点，且当所述第一心跳信号处于正常状态，且所述第一禁主信号无效，且所述第二禁主信号无效，且所述第三禁主信号无效时，将所述第一目标节点确定为主节点；
    当所述第一目标节点为从节点，且当所述第一心跳信号处于异常状态，和/或，所述第一禁主信号有效，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效时，将所述第一目标节点确定为从节点；
    当所述第一目标节点不为从节点，且当所述第一心跳信号处于异常状态，和/或，所述第一禁主信号有效，将所述第一目标节点确定为从节点；
    当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同时，将所述第一目标节点确定为从节点。
  3. 根据权利要求1所述的方法，其特征在于，还包括：
    当所述第一首位字符和所述第一末位字符相同，且所述第一首位字符和所述第一末位字符与预设值相同，则通过所述第一心跳信号、所述第一禁主信号、所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第一目标节点、所述第三目标节点和所述第四目标节点中是否存在主节点；
    当判定所述第一目标节点、所述第三目标节点和所述第四目标节点不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，将第二目标节点确定为主节点；
    当判定所述第一目标节点、所述第三目标节点和所述第四目标节点不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，且所述第三禁主信号无效，且所述第一心跳信号为异常状态或所述第一禁主信号有效时，将第二目标节点确定为主节点。
  4. 根据权利要求3所述的方法，其特征在于，还包括：
    当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中存在主节点时，将第二目标节点确定为从节点；
    当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效，和/或，所述第一心跳信号处于正常状态，和/或，所述第一禁主信号无效时，将所述第二目标节点确定为从节点；
    当判定所述第一目标节点、所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，将所述第二目标节点确定为从节点。
  5. 根据权利要求3所述的方法，其特征在于，所述第二目标节点包括第二校验数据，所述第二校验数据包括第二首位字符和第二末位字符，还包括：
    当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符相同，且所述第二首位字符和所述第二末位字符与预设值相同时，通过所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第三目标节点和所述第四目标节点中是否存在主节点；
    当判定所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点不为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效时，将所述第二目标节点确定为主节点；
    当判定所述第三目标节点和所述第四目标节点中不存在主节点，且所述第二目标节点为从节点，且所述第二心跳信号为正常状态，且所述第二禁主信号无效，且所述第三禁主信号无效，将所述第二目标节点确定为主节点。
  6. 根据权利要求5所述的方法，其特征在于，还包括：
    当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同时，将所述第二目标节点确定为从节点；
    当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符相同，且所述第二首位字符和所述第二末位字符与预设值相同，且判定所述第三目标节点和所述第四目标节点中存在主节点时，将第二目标节点确定为从节点。
  7. 根据权利要求6所述的方法，其特征在于，还包括：
    当所述第二目标节点不为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效时，将第二目标节点确定为从节点；
    当所述第二目标节点为从节点，且所述第二心跳信号处于异常状态，和/或，所述第二禁主信号有效，和/或，所述第三禁主信号有效时，将所述第二目标节点确定为从节点。
  8. 根据权利要求5所述的方法，其特征在于，还包括：
    当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，或，所述第二首位字符和所述第二末位字符相同且所述第二首位字 符和所述第二末位字符与预设值相同时，通过所述第一心跳信号、所述第一禁主信号、所述第二心跳信号、所述第二禁主信号、所述第四心跳信号和所述第四禁主信号判断所述第一目标节点、所述第二目标节点和所述第四目标节点中是否具有存在主节点；
    当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点不为从节点，且所述第三心跳信号为正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点；
    当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号有效，且所述第三心跳信号为正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点；
    当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号无效，且所述第三心跳信号为正常状态，且所述第三禁主信号无效，且所述第一心跳信号处于异常状态或所述第一禁主信号有效，且第二心跳信号处于异常状态时，将所述第三目标节点确定为主节点。
  9. 根据权利要求8所述的方法，其特征在于，还包括：
    当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中存在主节点时，将所述第三目标节点确定为从节点；
    当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点不为从节点，且所述第三心跳信号处于异常状态，和/或，所述第三禁主信号有效，将所述第三目标节点确定为从节点；
    当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号有效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效时，将所述第三目标节点确定为从节点；
    当判定所述第一目标节点、所述第二目标节点和所述第四目标节点中不存在主节点，且所述第三目标节点为从节点，且所述第二禁主信号无效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效，和/或，所述第一心跳信号处于正常状态，和/或，所述第一禁主信号无效，和/或，第二心跳信号处于正常状态时，将所述第三目标节点确定为从节点。
  10. 根据权利要求8所述的方法，其特征在于，所述第三目标节点包括第三校验数据，所述第三校验数据包括第三首位字符和第三末位字符，还包括：
    当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，则通过所述第四心跳信号和所述第四禁主信号判断所述第四目标节点是否为主节点；
    当判定所述第四目标节点不为主节点，则当所述第三心跳信号处于正常状态，且所述第三禁主信号无效时，将所述第三目标节点确定为主节点。
  11. 根据权利要求10所述的方法，其特征在于，还包括：
    当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所 述第三末位字符不相同，和/或，所述第三首位字符和所述第三末位字符与预设值不相同时，将所述第三目标节点确定为从节点；
    当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，且判定所述第四目标节点为主节点时，将所述第三目标节点确定为从节点；
    当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同，且判定所述第四目标节点不为主节点，且当所述第三心跳信号处于异常状态，和/或，所述第三禁主信号有效，将所述第三目标节点确定为从节点。
  12. 根据权利要求10所述的方法，其特征在于，还包括：
    当所述第一首位字符和所述第一末位字符相同且所述第一首位字符和所述第一末位字符与预设值相同，或，所述第二首位字符和所述第二末位字符相同且所述第二首位字符和所述第二末位字符与预设值相同，或，所述第三首位字符和所述第三末位字符相同且所述第三首位字符和所述第三末位字符与预设值相同时，通过所述第一心跳信号、所述第一禁主信号、所述第二心跳信号、所述第二禁主信号、所述第三心跳信号和所述第三禁主信号判断所述第一目标节点、所述第二目标节点和所述第三目标节点中是否具有任一目标节点为主节点；
    当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点不为从节点，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点；
    当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号有效，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，且所述第三心跳信号为异常状态或所述第三禁主信号有效时，将所述第四目标节点确定为主节点；
    当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号有效，且所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点；
    当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号无效，且所述第一心跳信为异常状态或所述第一禁主信号有效，且所述第二心跳信号为异常状态，且所述第三心跳信号为异常状态时，将所述第四目标节点确定为主节点。
  13. 根据权利要求12所述的方法，其特征在于，还包括：
    当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中存在主节点，将所述第三目标节点确定为从节点；
    当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节 点，且所述第四目标节点不为从节点，且所述第四心跳信号为异常状态，和/或，所述第四禁主信号无效时，将所述第四目标节点确定为从节点；
    当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号有效，且所述第四心跳信号处于异常状态，和/或，所述第四禁主信号有效，且所述第三心跳信号为异常状态，和/或，所述第三禁主信号有效时，将所述第四目标节点确定为从节点；
    当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号有效，且所述第四心跳信号为异常状态，和/或，所述第四禁主信号有效时，将所述第四目标节点确定为从节点；
    当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中不存在主节点，且所述第四目标节点为从节点，且所述第二禁主信号无效，且所述第三禁主信号无效，且所述第一心跳信为正常状态，和/或，所述第一禁主信号无效，和/或，所述第二心跳信号为正常状态，和/或，所述第三心跳信号为正常状态时，将所述第四目标节点确定为从节点；
    当判定所述第一目标节点、所述第二目标节点和所述第三目标节点中存在主节点，将所述第四目标节点确定为从节点。
  14. 根据权利要求12所述的方法，其特征在于，所述第四目标节点包括第四校验数据，所述第四校验数据包括第四首位字符和第四末位字符，还包括：
    当所述第一首位字符和所述第一末位字符不相同，和/或，所述第一首位字符和所述第一末位字符与预设值不相同，且所述第二首位字符和所述第二末位字符不相同，和/或，所述第二首位字符和所述第二末位字符与预设值不相同，且所述第三首位字符和所述第三末位字符不相同，和/或，所述第三首位字符和所述第三末位字符与预设值不相同，且所述第四首位字符和所述第四末位字符相同且所述第四首位字符和所述第四末位字符与预设值相同，且当所述第四心跳信号为正常状态，且所述第四禁主信号无效时，将所述第四目标节点确定为主节点。
  15. 根据权利要求14所述的方法，其特征在于，还包括：
    当所述第四首位字符和所述第四末位字符不相同，和/或，所述第四首位字符和所述第四末位字符与预设值不相同，将所述第四目标节点确定为从节点；
    当所述第四首位字符和所述第四末位字符相同且所述第四首位字符和所述第四末位字符与预设值相同，且所述第四心跳信号处于异常状态，和/或，所述第四禁主信号有效，将所述第四目标节点确定为从节点。
  16. 根据权利要求1所述的方法，其特征在于，所述第一目标节点、所述第二目标节点、所述第三目标节点和所述第四目标节点分别具有对应的基板管理控制器BMC，所述基板管理控制器BMC用于生成采用所述第一基板管理控制器BMC生成针对所述第一目标节点的第一心跳信号和第一禁主信号，以及生成针对所述第二目标节点的第二心跳信号和第二禁主信号，以及生成针对所述第三目标节点的第三心跳信号和第三禁主信号，以及生成针对所述第四目标节点的第四心跳信号和第四禁主信号。
  17. 根据权利要求1所述的方法，其特征在于，多节点服务器包括逻辑编程器件CPLD，所述逻辑编程器件CPLD用于将第一目标节点、第二目标节点、第三目标节点、第 四心跳信号确定为主节点或从节点。
  18. 一种主从节点确定装置，其特征在于，应用于多节点服务器，所述多节点服务器包括多个储存节点，所述装置包括：
    目标节点确定模块，用于从所述多个储存节点中确定出第一目标节点、第二目标节点、第三目标节点和第四目标节点；
    第一信号生成模块，用于生成针对所述第一目标节点的第一心跳信号和第一禁主信号；
    第二信号生成模块，用于生成针对所述第二目标节点的第二心跳信号和第二禁主信号；
    第三信号生成模块，用于生成针对所述第三目标节点的第三心跳信号和第三禁主信号；
    第四信号生成模块，用于生成针对所述第四目标节点的第四心跳信号和第四禁主信号；
    主节点确定模块，用于当所述第一禁主信号有效，且通过所述第二心跳信号、所述第二禁主信号、所述第三心跳信号、所述第三禁主信号、所述第四心跳信号和所述第四禁主信号判定所述第二目标节点、所述第三目标节点和所述第四目标节点中不存在主节点时，且所述第一目标节点为主节点，且所述第一禁主信号无效，且所述第一心跳信号处于正常状态时，将所述第一目标节点确定为主节点。
  19. 一种电子设备，其特征在于，包括处理器、通信接口、存储器和通信总线，其中，所述处理器、所述通信接口以及所述存储器通过所述通信总线完成相互间的通信；
    所述存储器，用于存放计算机程序；
    所述处理器，用于执行存储器上所存放的程序时，实现如权利要求1-17任一项所述的方法。
  20. 一种非易失性计算机可读存储介质，其上存储有指令，当由一个或多个处理器执行时，使得所述处理器执行如权利要求1-17任一项所述的方法。
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