WO2024098841A1 - 控制方法、装置、设备及存储介质 - Google Patents

控制方法、装置、设备及存储介质 Download PDF

Info

Publication number
WO2024098841A1
WO2024098841A1 PCT/CN2023/109993 CN2023109993W WO2024098841A1 WO 2024098841 A1 WO2024098841 A1 WO 2024098841A1 CN 2023109993 W CN2023109993 W CN 2023109993W WO 2024098841 A1 WO2024098841 A1 WO 2024098841A1
Authority
WO
WIPO (PCT)
Prior art keywords
communication
chip
data
module
error rate
Prior art date
Application number
PCT/CN2023/109993
Other languages
English (en)
French (fr)
Inventor
王德平
王强
于长虹
田辉
吴茜
廖波
焦育成
宋金海
王泽尉
赵晓雪
Original Assignee
中国第一汽车股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国第一汽车股份有限公司 filed Critical 中国第一汽车股份有限公司
Publication of WO2024098841A1 publication Critical patent/WO2024098841A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0823—Errors, e.g. transmission errors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/16—Threshold monitoring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/14—Session management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Definitions

  • Embodiments of the present application relate to the field of vehicle technology, for example, to a control method, device, equipment and storage medium.
  • Communication chips are widely used in mobile communications, wireless Internet and wireless data transmission industries, and are about to become the largest application market for the global semiconductor chip industry in the early 21st century.
  • PHY physical layer
  • the embodiments of the present application provide a control method, apparatus, device and storage medium, which solve the problem that the communication chip cannot guarantee communication failure. It can communicate through the internal PHY function module of the communication chip when the bit error rate is less than the first threshold, and communicate through the external expansion PHY chip when the bit error rate is greater than or equal to the first threshold, thereby ensuring the timeliness of communication.
  • the present application provides a control method, which is applied to a communication device, wherein the communication device includes: a communication chip and an external PHY chip, wherein the communication chip includes a PHY function module, and the control method includes:
  • the present application provides a control device, which is configured in a communication device, wherein the communication device includes: a communication chip and an external PHY chip, wherein the communication chip includes a PHY function module, and the control device includes:
  • the acquisition module is set to obtain the bit error rate
  • the first control module is configured to, when the bit error rate is less than a first threshold, The modules can communicate;
  • the second control module is configured to communicate through the external expansion PHY chip when the bit error rate is greater than or equal to the first threshold.
  • the present application provides an electronic device, the electronic device comprising:
  • a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the control method described in any embodiment of the present application.
  • the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the control method described in any embodiment of the present application when executed.
  • FIG1 is a schematic diagram of the structure of a communication device in an embodiment of the present application.
  • FIG2 is a flow chart of a control method in an embodiment of the present application.
  • FIG3 is a schematic diagram of a printed circuit board (PCB) calibration of a clock edge
  • FIG4 is a schematic diagram of the routing of clock lines and data lines on a PCB in an embodiment of the present application
  • FIG5 is a schematic diagram of a communication information verification process in an embodiment of the present application.
  • FIG6 is a schematic diagram of a heat dissipation structure in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of data self-collection diagnosis of a communication chip in a vehicle test in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a communication chip full load delay test method in an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a communication chip full load bit error rate test method in an embodiment of the present application.
  • FIG. 10 is a schematic diagram of another communication chip full load bit error rate test method in an embodiment of the present application.
  • FIG11 is a schematic diagram of the structure of a control device in an embodiment of the present application.
  • FIG. 12 is a schematic diagram of the structure of an electronic device in an embodiment of the present application.
  • Figure 1 is a schematic diagram of the structure of a communication device, wherein the communication device includes: a communication chip and an external PHY chip, wherein the communication chip includes a PHY functional module and a core.
  • the core is configured to obtain a bit error rate, and when the bit error rate is greater than or equal to a first threshold, switch to communicating through the external PHY chip.
  • the domestic switching chip selected for the gateway controller has PHY function. Normal communication can be carried out through the PHY function module. Once the amount of data increases, the system kernel statistics of the 100M/1G bit error rate rises to more than 30%, which cannot meet the communication needs of the entire vehicle. In this case, it switches to the external expansion PHY chip for communication to ensure communication timeliness.
  • FIG2 is a flow chart of a control method provided in an embodiment of the present application.
  • the present embodiment is applicable to the case of controlling a communication chip.
  • the method can be executed by a control device in an embodiment of the present application.
  • the device can be implemented in software and/or hardware. As shown in FIG2 , the method includes the following steps:
  • the bit error rate is a 100M/1000M bit error rate, that is, an Ethernet communication bit error rate of 100M Ethernet and 1000M Ethernet.
  • the bit error rate of the communication chip is obtained in this application.
  • the bit error rate can be obtained by: using the core of the communication device to count the bit error rate of 100M or 1000M.
  • the first threshold may be 30% or other values, which is not limited in the embodiment of the present application.
  • the method of judging whether the communication chip is in normal communication may be: when the bit error rate is less than the first threshold, determining that the communication chip is in normal communication state.
  • the communication mode is switched to communicating through the external expansion PHY chip.
  • FIG3 is a schematic diagram of PCB calibration of the clock edge, and a design scheme for using PCB delay to match the high-speed signal delay.
  • the communication rate of the automotive-grade communication chip reaches gigabit, it will be affected by the high-voltage signal and electromagnetic radiation on the vehicle, and the clock signal and the data signal will not match.
  • the data signal is delayed on the PCB to match the clock signal.
  • the original clock signal is a 1G signal. Because of the interference of the signal on the vehicle, the clock signal changes from 1G to 900M, resulting in the clock signal and the data signal cannot match the rising edge, data failure, and the data signal needs to be delayed on the PCB.
  • FIG4 is a schematic diagram of the routing of the clock line and the data line on the PCB.
  • the PCB board to which the communication chip belongs adopts the method of routing the data line around the clock line, the data line can be longer than the clock line, and the delay is consumed. Signal symmetry is required to prevent interference.
  • control method also includes: receiving communication information sent by a vehicle networking terminal (Telematics BOX, TBOX) through an on-board Ethernet interface; verifying the communication information; and if the communication information verification fails, discarding the communication information.
  • vehicle networking terminal Telematics BOX, TBOX
  • the communication information may be verified by determining a verification code according to the last 5 digits of the communication information, and verifying the communication information according to the verification code.
  • FIG. 5 is a schematic diagram of the communication information verification process.
  • the TBOX component that communicates with the gateway controller on the vehicle transmits the communication information to the communication chip through the vehicle Ethernet interface.
  • the last 5 bits of the communication information are the check code obtained by the cyclic redundancy algorithm.
  • the kernel verifies the communication information. If the verification is correct, the communication information is used. If the verification is wrong, the communication information is discarded.
  • This solution solves the problem of high bit error rate of communication signals of domestic automotive-grade chips, such as Gigabit Ethernet signals. Due to the importance of data, the automotive controller will not verify and identify errors. Therefore, the solution can be applied to the Ethernet communication of the vehicle entertainment system, allowing a certain error rate and verifying the data.
  • control method further includes: acquiring temperature data of the communication chip; and reducing the main frequency and/or workload of the communication chip when the temperature data of the communication chip is greater than or equal to a temperature threshold.
  • One is active heat dissipation, which increases the heat dissipation area and heat dissipation fluidity.
  • the other is to monitor the temperature of the communication chip and reduce the main frequency and/or workload of the communication chip when the temperature is too high.
  • Figure 6 includes: a gateway controller, a ventilation valve and an air-conditioning system
  • the gateway controller includes: a communication chip, a system-level chip (System on Chip, SoC), a ventilation valve driver and a board temperature sensor, wherein the SoC is an external expansion chip
  • the communication chip includes: a temperature intellectual property core (Intellectual Property Core, IP) and an internal central processing unit (Central Processing Unit, CPU).
  • the chip is scanned for electromagnetic compatibility (EMC) to identify EMC risks. Since the communication chip is IP integrated inside, the radiation emission at the interface may exceed the standard. Shielding circuits can be arranged in advance to reduce radiation emission and improve anti-interference capabilities.
  • control method further includes: sending the data of the communication chip to a data recorder via an Ethernet diagnostic interface, so that the data recorder records the data of the communication chip.
  • Figure 7 is a schematic diagram of the data self-collection diagnosis of the communication chip in the vehicle test.
  • the chip diagnosis and information transmission are realized through the core of the exchange chip itself, and the chip data is transmitted to the data recorder through the automotive Ethernet diagnostic port TX for data recording, and the core temperature, core voltage, core power, Ethernet data frames sent and received, data delay, etc. are summarized and counted.
  • the diagnostic information comes from the interface status.
  • the technical solution provided in the embodiment of the present application is mainly based on the diagnosis of the fault of the chip itself, and it can operate normally even if the chip has a fault.
  • the communication chip also includes: a first communication module and a second communication module; when the total load rate of the first communication module and the second communication module is greater than a load rate threshold, the target information sent by the CPU is received through the first communication module, and the target information is sent to the second communication module; the target information is sent to the CPU through the second communication module, so that the CPU determines the full load delay of the communication chip based on the time when the target information is received and the timestamp carried by the target information.
  • the communication chip includes: at least two communication modules. If the communication chip includes three communication modules: communication module 1, communication module 2 and communication module 3, communication module 1 is determined as the first communication module, and communication module 2 is determined as the second communication module. Alternatively, communication module 1 is determined as the first communication module, and communication module 3 is determined as the second communication module. Alternatively, communication module 2 is determined as the first communication module, and communication module 3 is determined as the second communication module. The embodiments of the present application are not limited to this.
  • FIG8 is a schematic diagram of a communication chip full-load delay test method.
  • the ETH0 module is selected to communicate with the ETH1 module inside the communication chip.
  • the communication rate is set to 1000M and the bus load rate is set to 95%, that is, 95% of the data bus is busy.
  • Some of the information in the communication between the ETH0 module and the ETH1 module contains a timestamp, that is, the CPU transmits a data to ETH0, and the data contains time information with the power-on time as the reference zero point.
  • ETH0 and ETH1 perform on-board Gigabit Ethernet communication at 95% of the bus load.
  • ETH0 transmits the received data to ETH1. After the transmitted data reaches ETH1, ETH1 sends the information containing the timestamp to the CPU.
  • the CPU makes a difference between the time when the information is received and the time in the information to obtain the communication chip full-load delay.
  • control method further includes: sending data to the flow meter through the first communication module, so that the flow meter sends the received data to the second communication module; determining the communication chip according to the data sent to the flow meter by the first communication module and the data sent by the flow meter received by the second communication module Full load bit error rate.
  • FIG9 is a schematic diagram of a communication chip full-load bit error rate test method; the kernel controls ETH0 to send data to the flow meter, the flow meter completely delivers the data to ETH1, and ETH1 then passes the data to the kernel for verification. The kernel compares the sent data with the received data and calculates the bit error rate of the transmitted data.
  • control method also includes: receiving data sent by the flow meter through the second communication module, and sending the received data to the first communication module; sending the received data to the flow meter through the first communication module, so that the flow meter determines the full-load bit error rate of the communication chip based on the data sent to the second communication module and the data sent by the first communication module.
  • Figure 10 is a schematic diagram of another communication chip full-load bit error rate test method; the flow meter sends data to ETH1, the two Ethernet communication modules communicate directly through the routing table, ETH1 sends the received data to ETH0, ETH0 transmits the data back to the flow meter, and the flow meter obtains the bit error rate of the transmitted data by comparing the sent data with the received data.
  • the technical solution of this embodiment is to communicate through the PHY functional module when the bit error rate is less than the first threshold; and to communicate through the external expansion PHY chip when the bit error rate is greater than or equal to the first threshold, thereby ensuring the timeliness of communication.
  • FIG11 is a schematic diagram of the structure of a control device provided in an embodiment of the present application. This embodiment can be applied to the case of controlling a communication chip, the device can be implemented in software and/or hardware, and the device can be integrated in any device that provides a control function. As shown in FIG11 , the control device includes: an acquisition module 210, a first control module 220, and a second control module 230.
  • An acquisition module is configured to acquire a bit error rate; a first control module is configured to communicate through the PHY functional module when the bit error rate is less than a first threshold; and a second control module is configured to communicate through the external expansion PHY chip when the bit error rate is greater than or equal to the first threshold.
  • the device also includes: a receiving module, configured to receive communication information sent by TBOX through an on-board Ethernet interface; a verification module, configured to verify the communication information; and an information screening module, configured to discard the communication information if the communication information verification fails.
  • a receiving module configured to receive communication information sent by TBOX through an on-board Ethernet interface
  • a verification module configured to verify the communication information
  • an information screening module configured to discard the communication information if the communication information verification fails.
  • the device also includes: a temperature data acquisition module, configured to acquire temperature data of the communication chip; and a third control module, configured to reduce the main frequency and/or workload of the communication chip when the temperature data of the communication chip is greater than or equal to a temperature threshold.
  • a temperature data acquisition module configured to acquire temperature data of the communication chip
  • a third control module configured to reduce the main frequency and/or workload of the communication chip when the temperature data of the communication chip is greater than or equal to a temperature threshold.
  • the device further comprises: a recording module configured to record the data of the communication chip via Ethernet.
  • the network diagnostic interface sends the data to the data recorder so that the data recorder records the data of the communication chip.
  • the communication chip also includes: a first communication module and a second communication module.
  • the control device also includes: an information sending module, which is configured to receive target information sent by the CPU through the first communication module and send the target information to the second communication module when the total load rate of the first communication module and the second communication module is greater than the load rate threshold; a first determination module, which is configured to send the target information to the CPU through the second communication module, so that the CPU determines the full load delay of the communication chip according to the time when the target information is received and the timestamp carried by the target information.
  • an information sending module which is configured to receive target information sent by the CPU through the first communication module and send the target information to the second communication module when the total load rate of the first communication module and the second communication module is greater than the load rate threshold
  • a first determination module which is configured to send the target information to the CPU through the second communication module, so that the CPU determines the full load delay of the communication chip according to the time when the target information is received and the timestamp carried by the target information.
  • the device also includes: a first data sending module, configured to send data to the flow meter through the first communication module, so that the flow meter sends the received data to the second communication module; a second determination module, configured to determine the full-load bit error rate of the communication chip based on the data sent by the first communication module to the flow meter and the data sent by the flow meter received by the second communication module.
  • a first data sending module configured to send data to the flow meter through the first communication module, so that the flow meter sends the received data to the second communication module
  • a second determination module configured to determine the full-load bit error rate of the communication chip based on the data sent by the first communication module to the flow meter and the data sent by the flow meter received by the second communication module.
  • the device also includes: a second data sending module, configured to receive data sent by the flow meter through the second communication module, and send the received data to the first communication module; a third determination module, configured to send the received data to the flow meter through the first communication module, so that the flow meter determines the full-load bit error rate of the communication chip based on the data sent to the second communication module and the data sent by the first communication module.
  • a second data sending module configured to receive data sent by the flow meter through the second communication module, and send the received data to the first communication module
  • a third determination module configured to send the received data to the flow meter through the first communication module, so that the flow meter determines the full-load bit error rate of the communication chip based on the data sent to the second communication module and the data sent by the first communication module.
  • the above-mentioned product can execute the method provided by any embodiment of the present application, and has the corresponding functional modules and effects of the execution method.
  • the technical solution of this embodiment is to communicate through the PHY functional module when the bit error rate is less than the first threshold; and to communicate through the external expansion PHY chip when the bit error rate is greater than or equal to the first threshold, so as to ensure the timeliness of communication.
  • FIG12 shows a block diagram of an electronic device 10 that can be used to implement an embodiment of the present application.
  • the electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers.
  • the electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices.
  • the components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and/or required herein.
  • the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11 in communication, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores data that can be
  • the processor 11 can perform various appropriate actions and processes according to the computer program stored in the ROM 12 or the computer program loaded from the storage unit 18 to the RAM 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored.
  • the processor 11, the ROM 12 and the RAM 13 are connected to each other through the bus 14.
  • the input/output (I/O) interface 15 is also connected to the bus 14.
  • the I/O interface 15 includes: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc.
  • the communication unit 19 allows the electronic device 10 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks.
  • the processor 11 may be a variety of general and/or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a variety of dedicated artificial intelligence (AI) computing chips, a variety of processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc.
  • the processor 11 performs the multiple methods and processes described above, such as the control method.
  • control method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18.
  • part or all of the computer program may be loaded and/or installed on the electronic device 10 via the ROM 12 and/or the communication unit 19.
  • the processor 11 may be configured to perform the control method in any other suitable manner (e.g., by means of firmware).
  • Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof.
  • FPGAs field programmable gate arrays
  • ASICs application specific integrated circuits
  • ASSPs application specific standard products
  • SOCs systems on chips
  • CPLDs complex programmable logic devices
  • These various embodiments may include: being implemented in one or more computer programs that are executable and/or interpreted on a programmable system that includes at least one programmable processor that may be a special purpose or general purpose programmable processor that may receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.
  • a programmable processor may be a special purpose or general purpose programmable processor that may receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.
  • the computer program for implementing the method of the present application may be in any of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that when the computer program is executed by the processor, the functions/operations specified in the flowchart and/or block diagram are implemented.
  • the computer program can be executed entirely on the machine, partially on the machine, as a separate software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.
  • a computer readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or apparatus.
  • a computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing.
  • a computer readable storage medium may be a machine readable signal medium.
  • a machine readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a RAM, a ROM, an Erasable Programmable Read-Only Memory (EPROM) or a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
  • the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD) monitor) configured to display information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device.
  • a display device e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD) monitor
  • a keyboard and pointing device e.g., a mouse or trackball
  • Other types of devices may also be configured to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).
  • the systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components.
  • the components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: Local Area Network (LAN), Wide Area Network (WAN), blockchain network, and the Internet.
  • a computing system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship between client and server is generated by a computer program that creates a client-server relationship.
  • the server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of traditional physical hosts and virtual private servers (VPS) services, such as difficult management and weak business scalability.
  • VPN virtual private servers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Environmental & Geological Engineering (AREA)
  • Computer And Data Communications (AREA)

Abstract

本申请公开了一种控制方法、装置、设备及存储介质。该方法包括：获取误码率；在误码率小于第一阈值的情况下，通过所述PHY功能模块进行通信；在误码率大于或者等于第一阈值的情况下，通过所述外扩PHY芯片进行通信。

Description

控制方法、装置、设备及存储介质
本申请要求在2022年11月07日提交中国专利局、申请号为202211385383.X的中国专利申请的优先权，以上申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及车辆技术领域，例如涉及一种控制方法、装置、设备及存储介质。
背景技术
近年来通信芯片的需求量大幅度增长，给全球半导体业注入新的活力，通信芯片广泛应用于移动通信、无线internet和无线数据传输业，即将成为21世纪初全球半导体芯片业最大的应用市场。
随着车规级通信芯片进入市场，通信芯片可能会因为模拟电路的误差导致物理层(Physical Layer，PHY)功能失效，存在无法保证通信时效的问题。
发明内容
本申请实施例提供一种控制方法、装置、设备及存储介质，解决了通信芯片无法保证通信失效的问题，能够在误码率小于第一阈值时通过通信芯片内部PHY功能模块进行通信，在误码率大于或者等于第一阈值时通过外扩PHY芯片进行通信，进而保证通信时效。
本申请提供了一种控制方法，应用于通信设备，所述通信设备包括：通信芯片和外扩PHY芯片，其中，所述通信芯片包括PHY功能模块，所述控制方法包括：
获取误码率；
在误码率小于第一阈值的情况下，通过所述PHY功能模块进行通信；
在误码率大于或者等于第一阈值的情况下，通过所述外扩PHY芯片进行通信。
本申请提供了一种控制装置，配置在通信设备中，所述通信设备包括：通信芯片和外扩PHY芯片，其中，所述通信芯片包括PHY功能模块，所述控制装置包括：
获取模块，设置为获取误码率；
第一控制模块，设置为在误码率小于第一阈值的情况下，通过所述PHY功 能模块进行通信；
第二控制模块，设置为在误码率大于或者等于第一阈值的情况下，通过所述外扩PHY芯片进行通信。
本申请提供了一种电子设备，所述电子设备包括：
至少一个处理器；以及
与所述至少一个处理器通信连接的存储器；其中，所述存储器存储有可被所述至少一个处理器执行的计算机程序，所述计算机程序被所述至少一个处理器执行，以使所述至少一个处理器能够执行本申请任一实施例所述的控制方法。
本申请提供了一种计算机可读存储介质，所述计算机可读存储介质存储有计算机指令，所述计算机指令用于使处理器执行时实现本申请任一实施例所述的控制方法。
附图说明
下面将对实施例中所需要使用的附图作简单地介绍。
图1是本申请实施例中的通信设备的结构示意图；
图2是本申请实施例中的一种控制方法的流程图；
图3是时钟沿的印制电路板(Printed Circuit Board，PCB)校准示意图；
图4是本申请实施例中的PCB上时钟线和数据线走线示意图；
图5是本申请实施例中的通信信息校验流程的示意图；
图6是本申请实施例中的散热结构示意图；
图7是本申请实施例中的整车试验中通信芯片的数据自收集诊断示意图；
图8是本申请实施例中的通信芯片满负荷延时测试方法示意图；
图9是本申请实施例中的一种通信芯片满负荷误码率测试方法示意图；
图10是本申请实施例中的另一种通信芯片满负荷误码率测试方法示意图；
图11是本申请实施例中的一种控制装置的结构示意图；
图12是本申请实施例中的一种电子设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行说明。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
实施例一
图1为通信设备的结构示意图，通信设备包括：通信芯片和外扩PHY芯片，其中，所述通信芯片包括PHY功能模块和内核。所述内核设置为获取误码率，并在误码率大于或者等于第一阈值时，切换至通过所述外扩PHY芯片进行通信。
网关控制器所选用的国产交换芯片带有PHY功能，正常通信可以通过PHY功能模块进行通信，一旦数据量增加，系统内核统计百兆千兆误码率升高至30％以上，满足不了整车的通信需求，则切换至外扩PHY芯片进行通信，以保证通信时效。
图2为本申请实施例提供的一种控制方法的流程图，本实施例可适用于对通信芯片进行控制的情况，该方法可以由本申请实施例中的控制装置来执行，该装置可采用软件和/或硬件的方式实现，如图2所示，该方法包括如下步骤：
S110，获取误码率。
所述误码率为百兆千兆误码率，即百兆以太网及千兆以太网的以太网通信误码率。
本申请中获取的是通信芯片的误码率。获取误码率的方式可以为：通过通信设备的内核统计百兆千兆误码率。
S120，在误码率小于第一阈值的情况下，通过所述PHY功能模块进行通信。
所述第一阈值可以为30％，也可以为其他数值，本申请实施例对此不进行限制。
在正常通信时，通过通信芯片内部的PHY功能模块进行通信。判断通信芯片是否处于正常通信的方式可以为：在误码率小于第一阈值的情况下，确定通信芯片处于正常通信状态。
S130，在误码率大于或者等于第一阈值的情况下，通过所述外扩PHY芯片进行通信。
若检测到误码率大于或者等于第一阈值，则将通信方式切换至通过外扩PHY芯片进行通信。
如图3所示，图3为时钟沿的PCB校准示意图，使用PCB的延时匹配高速信号延时的设计方案。车规级通信芯片的通信速率在达到千兆时，面临车上高压信号和电磁辐射的影响，会出现时钟信号和数据信号不匹配的情况，为了防止信号故障，使数据信号在PCB上进行延时以匹配时钟信号。如图3所示原定的clock信号为1G信号，因为收到车上信号干扰，clock信号由1G变为900M,导致clock信号与数据信号不能上升沿匹配，数据故障，需要在PCB上将数据信号做延迟处理。如图4所示，图4为PCB上时钟线和数据线走线示意图，在通信芯片所属PCB板卡采用数据线围绕时钟线进行环绕布线的方式进行布线时，能够使得数据线比时钟线走线更长，将延时消耗掉，为防止干扰需要信号对称。
可选的，所述控制方法还包括：通过车载以太网接口接收车联网终端(Telematics BOX，TBOX)发送的通信信息；对所述通信信息进行校验；在通信信息校验失败的情况下，舍弃所述通信信息。
对所述通信信息进行校验的方式可以为：根据所述通信信息的后5位确定校验码，根据校验码对通信信息进行校验。
如图5所示，图5为通信信息校验流程的示意图，车上与网关控制器通信的部件TBOX将通信信息通过车载以太网接口传递给通信芯片，通信信息的后5位为循环冗余算法得到的校验码，内核接到该通信信息后对该通信信息进行校验，校验正确就使用该通信信息，校验错误即舍弃该通信信息。此方案解决了国产车规级芯片通信信号，例如千兆以太网信号，误码率较高问题。汽车用控制器因数据的重要不会对数据进行校验和错误识别，因此方案可适用于车载娱乐系统的以太网通信，允许一定的错误率，可以对数据进行校验。
可选的，所述控制方法还包括：获取通信芯片的温度数据；在所述通信芯片的温度数据大于或者等于温度阈值的情况下，降低通信芯片主频和/或工作负荷。
为防止车规级通信芯片过热，需要增加两个特殊处理，一种是主动散热，加大散热面积和散热流动性，另一种是监控通信芯片的温度，温度过高时要降低通信芯片主频和/或工作负荷。
如图6所示，图6包括：网关控制器、通风阀和空调系统，所述网关控制器包括：通信芯片、系统级芯片(System on Chip，SoC)、通风阀驱动以及板温传感器，其中，SoC为外扩芯片，通信芯片包括：温度知识产权核(Intellectual Property Core，IP)和内部中央处理器(Central Processing Unit，CPU)。
为保证芯片的辐射发射、传导发射和抗扰性能，对芯片进行电磁兼容性(Electromagnetic Compatibility，EMC)扫描识别EMC风险，因通信芯片内部为IP集成，导致接口处会有辐射发射超标现象，可以提前布置屏蔽电路用于降低辐射的发射和提高抗干扰能力。
可选的，所述控制方法还包括：将通信芯片的数据通过以太网诊断接口发送至数据记录仪，以使数据记录仪对通信芯片的数据进行记录。
如图7所示，图7为整车试验中通信芯片的数据自收集诊断示意图，为验证交换芯片的能力，强化芯片的工作负荷，提供芯片的状态分析所需数据，通过交换芯片自带的内核实现芯片诊断及信息传递，并通过汽车以太网诊断口TX将芯片的数据传递给数据记录仪进行数据记录，对内核的温度、内核的电压、内核的功率、以太网发送接收的数据帧、数据延时等进行汇总统计。相关技术中的汽车控制器方案，诊断信息是来自于接口状态，本申请实施例提供的技术方案主要是根据芯片本身的故障进行的诊断，即使芯片有故障也可以正常运行。
可选的，所述通信芯片还包括：一个第一通信模块和一个第二通信模块；在所述第一通信模块和所述第二通信模块的总负荷率大于负荷率阈值的情况下，通过第一通信模块接收CPU发送的目标信息，并将所述目标信息发送至第二通信模块；通过所述第二通信模块将目标信息发送至CPU，以使CPU根据接收到目标信息的时间和目标信息携带的时间戳确定通信芯片满负荷时延。
所述通信芯片包括：至少两个通信模块。若通信芯片包括3个通信模块：通信模块1、通信模块2以及通信模块3，则将通信模块1确定为第一通信模块，通信模块2确定为第二通信模块。或者，将通信模块1确定为第一通信模块，通信模块3确定为第二通信模块。或者，将通信模块2确定为第一通信模块，通信模块3确定为第二通信模块。本申请实施例对此不进行限制。
如图8所示，图8为通信芯片满负荷延时测试方法示意图，在通信芯片内部选用ETH0模块与ETH1模块进行通信，在通信芯片的通信总线上，使通信速率达到千兆并使总线负荷率达到95％，即95％的数据总线为繁忙状态。ETH0模块与ETH1模块的通信的内容里有部分信息含有时间戳，即CPU传递一个数据给ETH0，数据里面含有以上电时间为基准零点的时间信息，ETH0和ETH1以95％的总线负荷进行车载千兆以太网通信，ETH0将接收到的数据传递给ETH1，传递的数据到达ETH1后，ETH1把含有时间戳的信息给CPU，CPU把接到信息的时间和信息内的时间做差，得到通信芯片满负荷延时。
可选的，所述控制方法还包括：通过所述第一通信模块向打流仪发送数据，以使打流仪将接收到的数据发送至第二通信模块；根据所述第一通信模块向打流仪发送的数据和所述第二通信模块接收到的打流仪发送的数据确定通信芯片 满负荷误码率。
如图9所示，图9为一种通信芯片满负荷误码率测试方法示意图；内核控制ETH0发送数据给打流仪，打流仪将数据完全交付给ETH1,ETH1再把数据传递给内核校验，内核将发送出去的数据和接收到的数据进行对比，计算得到传递数据的误码率。
可选的，所述控制方法还包括：通过所述第二通信模块接收打流仪发送的数据，并将接收到的数据发送至所述第一通信模块；通过所述第一通信模块将接收到的数据发送至所述打流仪，以使所述打流仪根据向第二通信模块发送的数据和接收到的第一通信模块发送的数据确定通信芯片满负荷误码率。
如图10所示，图10为另一种通信芯片满负荷误码率测试方法示意图；打流仪发送数据给ETH1,两个以太网通信模块通过路由表进行直接通信，ETH1将接收到的数据发送至ETH0，ETH0传递数据回打流仪，打流仪通过对比发送出去的数据和接收到的数据，得到传递数据的误码率。
本实施例的技术方案，在误码率小于第一阈值的情况下，通过所述PHY功能模块进行通信；在误码率大于或者等于第一阈值的情况下，通过所述外扩PHY芯片进行通信，能够保证通信时效。
实施例二
图11为本申请实施例提供的一种控制装置的结构示意图。本实施例可适用于对通信芯片进行控制的情况，该装置可采用软件和/或硬件的方式实现，该装置可集成在任何提供控制功能的设备中，如图11所示，所述控制装置包括：获取模块210、第一控制模块220和第二控制模块230。
获取模块，设置为获取误码率；第一控制模块，设置为在误码率小于第一阈值的情况下，通过所述PHY功能模块进行通信；第二控制模块，设置为在误码率大于或者等于第一阈值的情况下，通过所述外扩PHY芯片进行通信。
可选的，所述装置还包括：接收模块，设置为通过车载以太网接口接收TBOX发送的通信信息；校验模块，设置为对所述通信信息进行校验；信息筛选模块，设置为在所述通信信息校验失败的情况下，舍弃所述通信信息。
可选的，所述装置还包括：温度数据获取模块，设置为获取通信芯片的温度数据；第三控制模块，设置为在所述通信芯片的温度数据大于或者等于温度阈值的情况下，降低通信芯片主频和/或工作负荷。
可选的，所述装置还包括：记录模块，设置为将通信芯片的数据通过以太 网诊断接口发送至数据记录仪，以使数据记录仪对通信芯片的数据进行记录。
可选的，所述通信芯片还包括：一个第一通信模块和一个第二通信模块。
所述控制装置还包括：信息发送模块，设置为在所述第一通信模块和所述第二通信模块的总负荷率大于负荷率阈值的情况下，通过第一通信模块接收CPU发送的目标信息，并将所述目标信息发送至第二通信模块；第一确定模块，设置为通过所述第二通信模块将目标信息发送至CPU，以使CPU根据接收到目标信息的时间和目标信息携带的时间戳确定通信芯片满负荷时延。
可选的，所述装置还包括：第一数据发送模块，设置为通过所述第一通信模块向打流仪发送数据，以使打流仪将接收到的数据发送至第二通信模块；第二确定模块，设置为根据所述第一通信模块向打流仪发送的数据和所述第二通信模块接收到所述打流仪发送的的数据确定通信芯片满负荷误码率。
可选的，所述装置还包括：第二数据发送模块，设置为通过所述第二通信模块接收打流仪发送的数据，并将接收到的数据发送至所述第一通信模块；第三确定模块，设置为通过所述第一通信模块将接收到的数据发送至所述打流仪，以使所述打流仪根据向第二通信模块发送的数据和接收到的第一通信模块发送的数据确定通信芯片满负荷误码率。
上述产品可执行本申请任意实施例所提供的方法，具备执行方法相应的功能模块和效果。
本实施例的技术方案，在误码率小于第一阈值时，通过所述PHY功能模块进行通信；在误码率大于或者等于第一阈值时，通过所述外扩PHY芯片进行通信，能够保证通信时效。
实施例三
图12示出了可以用来实施本申请的实施例的电子设备10的结构示意图。电子设备旨在表示多种形式的数字计算机，诸如，膝上型计算机、台式计算机、工作台、个人数字助理、服务器、刀片式服务器、大型计算机、和其它适合的计算机。电子设备还可以表示多种形式的移动装置，诸如，个人数字处理、蜂窝电话、智能电话、可穿戴设备(如头盔、眼镜、手表等)和其它类似的计算装置。本文所示的部件、它们的连接和关系、以及它们的功能仅仅作为示例，并且不意在限制本文中描述的和/或者要求的本申请的实现。
如图12所示，电子设备10包括至少一个处理器11，以及与至少一个处理器11通信连接的存储器，如只读存储器(Read-Only Memory，ROM)12、随机访问存储器(Random Access Memory，RAM)13等，其中，存储器存储有可被 至少一个处理器执行的计算机程序，处理器11可以根据存储在ROM12中的计算机程序或者从存储单元18加载到RAM13中的计算机程序，来执行多种适当的动作和处理。在RAM 13中，还可存储电子设备10操作所需的多种程序和数据。处理器11、ROM 12以及RAM 13通过总线14彼此相连。输入/输出(Input/Output，I/O)接口15也连接至总线14。
电子设备10中的多个部件连接至I/O接口15，多个部件包括：输入单元16，例如键盘、鼠标等；输出单元17，例如多种类型的显示器、扬声器等；存储单元18，例如磁盘、光盘等；以及通信单元19，例如网卡、调制解调器、无线通信收发机等。通信单元19允许电子设备10通过诸如因特网的计算机网络和/或多种电信网络与其他设备交换信息/数据。
处理器11可以是多种具有处理和计算能力的通用和/或专用处理组件。处理器11的一些示例包括但不限于中央处理单元(Central Processing Unit，CPU)、图形处理单元(Graphic Processing Unit，GPU)、多种专用的人工智能(Artificial Intelligence，AI)计算芯片、多种运行机器学习模型算法的处理器、数字信号处理器(Digital Signal Processing，DSP)、以及任何适当的处理器、控制器、微控制器等。处理器11执行上文所描述的多个方法和处理，例如控制方法。
在一些实施例中，控制方法可被实现为计算机程序，其被有形地包含于计算机可读存储介质，例如存储单元18。在一些实施例中，计算机程序的部分或者全部可以经由ROM 12和/或通信单元19而被载入和/或安装到电子设备10上。当计算机程序加载到RAM 13并由处理器11执行时，可以执行上文描述的控制方法的一个或多个步骤。备选地，在其他实施例中，处理器11可以通过其他任何适当的方式(例如，借助于固件)而被配置为执行控制方法。
本文中以上描述的系统和技术的多种实施方式可以在数字电子电路系统、集成电路系统、场可编程门阵列(Field Programmable Gate Array，FPGA)、专用集成电路(Application Specific Integrated Circuit，ASIC)、专用标准产品(Application Specific Standard Product，ASSP)、芯片上的系统(System on Chip，SOC)、负载可编程逻辑设备(Complex Programmable Logic Device，CPLD)、计算机硬件、固件、软件、和/或它们的组合中实现。这些多种实施方式可以包括：实施在一个或者多个计算机程序中，该一个或者多个计算机程序可在包括至少一个可编程处理器的可编程系统上执行和/或解释，该可编程处理器可以是专用或者通用可编程处理器，可以从存储系统、至少一个输入装置、和至少一个输出装置接收数据和指令，并且将数据和指令传输至该存储系统、该至少一个输入装置、和该至少一个输出装置。
用于实施本申请的方法的计算机程序可以采用一个或多个编程语言的任何 组合来编写。这些计算机程序可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理器，使得计算机程序当由处理器执行时使流程图和/或框图中所规定的功能/操作被实施。计算机程序可以完全在机器上执行、部分地在机器上执行，作为独立软件包部分地在机器上执行且部分地在远程机器上执行或完全在远程机器或服务器上执行。
在本申请的上下文中，计算机可读存储介质可以是有形的介质，其可以包含或存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的计算机程序。计算机可读存储介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。备选地，计算机可读存储介质可以是机器可读信号介质。机器可读存储介质可以包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、RAM、ROM、可擦除可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EPROM)或快闪存储器、光纤、便捷式紧凑盘只读存储器(Compact Disc Read-Only Memory，CD-ROM)、光学储存设备、磁储存设备、或上述内容的任何合适组合。
为了提供与用户的交互，可以在电子设备上实施此处描述的系统和技术，该电子设备具有：设置为向用户显示信息的显示装置(例如，阴极射线管(Cathode Ray Tube，CRT)或者液晶显示器(Liquid Crystal Display，LCD)监视器)；以及键盘和指向装置(例如，鼠标或者轨迹球)，用户可以通过该键盘和该指向装置来将输入提供给电子设备。其它种类的装置还可以设置为提供与用户的交互；例如，提供给用户的反馈可以是任何形式的传感反馈(例如，视觉反馈、听觉反馈、或者触觉反馈)；并且可以用任何形式(包括声输入、语音输入或者、触觉输入)来接收来自用户的输入。
可以将此处描述的系统和技术实施在包括后台部件的计算系统(例如，作为数据服务器)、或者包括中间件部件的计算系统(例如，应用服务器)、或者包括前端部件的计算系统(例如，具有图形用户界面或者网络浏览器的用户计算机，用户可以通过该图形用户界面或者该网络浏览器来与此处描述的系统和技术的实施方式交互)、或者包括这种后台部件、中间件部件、或者前端部件的任何组合的计算系统中。可以通过任何形式或者介质的数字数据通信(例如，通信网络)来将系统的部件相互连接。通信网络的示例包括：局域网(Local Area Network，LAN)、广域网(Wide Area Network，WAN)、区块链网络和互联网。
计算系统可以包括客户端和服务器。客户端和服务器一般远离彼此并且通常通过通信网络进行交互。通过在相应的计算机上运行并且彼此具有客户端-服 务器关系的计算机程序来产生客户端和服务器的关系。服务器可以是云服务器，又称为云计算服务器或云主机，是云计算服务体系中的一项主机产品，以解决了传统物理主机与虚拟专用服务器(Virtual Private Server，VPS)服务中，存在的管理难度大，业务扩展性弱的缺陷。

Claims (10)

  1. 一种控制方法，应用于通信设备，所述通信设备包括：通信芯片和外扩物理层PHY芯片，其中，所述通信芯片包括PHY功能模块，所述控制方法包括：
    获取误码率；
    在所述误码率小于第一阈值的情况下，通过所述PHY功能模块进行通信；
    在所述误码率大于或者等于第一阈值的情况下，通过所述外扩PHY芯片进行通信。
  2. 根据权利要求1所述的方法，还包括：
    通过车载以太网接口接收车联网终端TBOX发送的通信信息；
    对所述通信信息进行校验；
    在所述通信信息校验失败的情况下，舍弃所述通信信息。
  3. 根据权利要求1所述的方法，还包括：
    获取通信芯片的温度数据；
    在所述通信芯片的温度数据大于或者等于温度阈值的情况下，降低通信芯片的主频和通信芯片的工作负荷中的至少一种。
  4. 根据权利要求1所述的方法，还包括：
    将通信芯片的数据通过以太网诊断接口发送至数据记录仪，以使所述数据记录仪对所述通信芯片的数据进行记录。
  5. 根据权利要求1所述的方法，其中，所述通信芯片还包括：一个第一通信模块和一个第二通信模块；
    所述控制方法还包括：
    在所述第一通信模块和所述第二通信模块的总负荷率大于负荷率阈值的情况下，通过所述第一通信模块接收中央处理器CPU发送的目标信息，并将所述目标信息发送至所述第二通信模块；
    通过所述第二通信模块将目标信息发送至所述CPU，以使所述CPU根据接收到目标信息的时间和目标信息携带的时间戳确定通信芯片满负荷时延。
  6. 根据权利要求5所述的方法，还包括：
    通过所述第一通信模块向打流仪发送数据，以使打流仪将接收到的数据发送至所述第二通信模块；
    根据所述第一通信模块向打流仪发送的数据和所述第二通信模块接收到的 所述打流仪发送的数据确定通信芯片满负荷误码率。
  7. 根据权利要求5所述的方法，还包括：
    通过所述第二通信模块接收打流仪发送的数据，并将接收到的数据发送至所述第一通信模块；
    通过所述第一通信模块将接收到的数据发送至所述打流仪，以使所述打流仪根据向所述第二通信模块发送的数据和接收到的所述第一通信模块发送的数据确定通信芯片满负荷误码率。
  8. 一种控制装置，配置在通信设备中，所述通信设备包括：通信芯片和外扩PHY芯片，其中，所述通信芯片包括PHY功能模块，所述控制装置包括：
    获取模块，设置为获取误码率；
    第一控制模块，设置为在误码率小于第一阈值的情况下，通过所述PHY功能模块进行通信；
    第二控制模块，设置为在误码率大于或者等于第一阈值的情况下，通过所述外扩PHY芯片进行通信。
  9. 一种电子设备，包括：
    至少一个处理器；以及
    与所述至少一个处理器通信连接的存储器；其中，所述存储器存储有可被所述至少一个处理器执行的计算机程序，所述计算机程序被所述至少一个处理器执行，以使所述至少一个处理器能够执行权利要求1-7中任一项所述的控制方法。
  10. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机指令，所述计算机指令用于使处理器执行时实现权利要求1-7中任一项所述的控制方法。
PCT/CN2023/109993 2022-11-07 2023-07-28 控制方法、装置、设备及存储介质 WO2024098841A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211385383.XA CN115914327B (zh) 2022-11-07 2022-11-07 一种控制方法、装置、设备及存储介质
CN202211385383.X 2022-11-07

Publications (1)

Publication Number Publication Date
WO2024098841A1 true WO2024098841A1 (zh) 2024-05-16

Family

ID=86477741

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/109993 WO2024098841A1 (zh) 2022-11-07 2023-07-28 控制方法、装置、设备及存储介质

Country Status (2)

Country Link
CN (1) CN115914327B (zh)
WO (1) WO2024098841A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115914327B (zh) * 2022-11-07 2024-03-26 中国第一汽车股份有限公司 一种控制方法、装置、设备及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107204783A (zh) * 2017-05-25 2017-09-26 迈锐数据（北京）有限公司 一种无线通信系统、方法和装置
WO2020102928A1 (zh) * 2018-11-19 2020-05-28 深圳市欢太科技有限公司 一种无线信号发送方法、无线信号发送装置及终端设备
WO2022078426A1 (zh) * 2020-10-15 2022-04-21 华为技术有限公司 数据传输方法、系统和计算机可读存储介质
CN115914327A (zh) * 2022-11-07 2023-04-04 中国第一汽车股份有限公司 一种控制方法、装置、设备及存储介质

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102984030B (zh) * 2012-12-06 2015-05-20 盛科网络（苏州）有限公司 芯片级实现以太网oam帧时延测量的方法和装置
CN105406998A (zh) * 2015-11-06 2016-03-16 天津津航计算技术研究所 基于fpga的双冗余千兆以太网介质访问控制器ip核
CN112788651A (zh) * 2019-11-07 2021-05-11 Oppo（重庆）智能科技有限公司 一种控制方法、终端及存储介质
CN110995533A (zh) * 2019-11-22 2020-04-10 配天机器人技术有限公司 一种以太网打流测试系统
CN214202082U (zh) * 2020-12-15 2021-09-14 中国第一汽车股份有限公司 车载网络系统及汽车
CN213585817U (zh) * 2020-12-21 2021-06-29 沈阳东信创智科技有限公司 一种基于rtl9047aa的汽车网关硬件平台
CN115022851A (zh) * 2021-03-03 2022-09-06 瑞昱半导体股份有限公司 具有通信范围延伸机制的蓝牙网状网络系统及其联机方法
CN115168253A (zh) * 2021-04-06 2022-10-11 合肥杰发科技有限公司 一种usb工作模式的切换方法与电子设备
CN115185364A (zh) * 2022-09-09 2022-10-14 北京智芯微电子科技有限公司 智能设备及其功耗管理方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107204783A (zh) * 2017-05-25 2017-09-26 迈锐数据（北京）有限公司 一种无线通信系统、方法和装置
WO2020102928A1 (zh) * 2018-11-19 2020-05-28 深圳市欢太科技有限公司 一种无线信号发送方法、无线信号发送装置及终端设备
WO2022078426A1 (zh) * 2020-10-15 2022-04-21 华为技术有限公司 数据传输方法、系统和计算机可读存储介质
CN115914327A (zh) * 2022-11-07 2023-04-04 中国第一汽车股份有限公司 一种控制方法、装置、设备及存储介质

Also Published As

Publication number Publication date
CN115914327A (zh) 2023-04-04
CN115914327B (zh) 2024-03-26

Similar Documents

Publication Publication Date Title
CN105163375B (zh) 带有状态保持的链路功率节省
WO2024098841A1 (zh) 控制方法、装置、设备及存储介质
WO2021238248A1 (zh) 一种网络流量的分类处理方法、装置、设备及介质
EP2568665B1 (en) Methods and devices for transmitting scsi packets on a pcie bus
WO2017052973A1 (en) Technologies for performance inspection at an endpoint node
CN110764585B (zh) 一种通用的独立bmc板卡
US10275354B2 (en) Transmission of a message based on a determined cognitive context
WO2024125185A1 (zh) 主从设备间通讯的通讯转换方法、装置及存储介质
US10404676B2 (en) Method and apparatus to coordinate and authenticate requests for data
US10366024B2 (en) Synchronous input/output computer system including hardware invalidation of synchronous input/output context
CN111638951A (zh) 拟态裁决装置和方法、拟态防御系统及拟态服务器
WO2023207571A1 (zh) 一种数据传输方法及装置
CN114742000A (zh) 基于FPGA集群的SoC芯片验证系统、验证方法、装置
CN116306408B (zh) 片上系统soc的验证环境确定方法、装置、设备和存储介质
WO2023273539A1 (zh) 航班查询系统业务监控方法、装置、设备及存储介质
CN212623045U (zh) 一种报文离散性可控的标准数字功率源
US11151011B2 (en) Uncore input/output latency analysis
US20120317316A1 (en) System to manage input/output performance and/or deadlock in network attached storage gateway connected to a storage area network environment
CN117850396A (zh) 车载平台的测试方法、装置、电子设备及存储介质
CN112668263B (zh) 基于PCIe总线的处理层设计方法、结构及应用
CN115859876A (zh) 基于uvm的从设备接口压力测试平台及测试方法
CN116306407B (zh) 片上网络noc的验证方法、装置、设备和存储介质
WO2024120469A1 (zh) 时钟同步方法、装置、设备、存储介质及计算机程序
EP4428545A1 (en) Section-by-section testing method for functional safety testing circuit, and electronic device and storage medium
CN116112382A (zh) 一种网络数据捕获方法、装置、电子设备及存储介质

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23887537

Country of ref document: EP

Kind code of ref document: A1