WO2024098739A1

WO2024098739A1 - Memory and electronic device

Info

Publication number: WO2024098739A1
Application number: PCT/CN2023/098864
Authority: WO
Inventors: 朱正勇; 康卜文; 赵超
Original assignee: 北京超弦存储器研究院; 长鑫科技集团股份有限公司
Priority date: 2022-11-07
Filing date: 2023-06-07
Publication date: 2024-05-16

Abstract

A memory and an electronic device. The memory comprises a storage array, which comprises a plurality of storage units. Each storage unit comprises one transistor (T), and the transistor (T) has two gate electrodes, wherein one gate electrode (107) is connected to a word line (WL), and the other gate electrode (114) is connected to a bit line (BL2); or each storage unit comprises two transistors connected in series, and each transistor has a gate electrode, wherein a gate electrode (104) of one transistor (T1) is connected to the bit line (BL2), and a gate electrode (111) of the other transistor (T2) is connected to the word line (WL). By means of a signal on the bit line (BL2) and a signal on the word line (WL), the currently selected storage unit is controlled to be triggered, and the other storage units belonging to the same row are not triggered. During a write operation, a certain storage unit or certain storage units can be randomly selected, such that charge sharing, signal sensing and amplification operations are performed only on the selected storage unit(s), and the other unselected storage units are all in a turned-off state, thereby reducing the power consumption.

Description

Memory and electronic devices

Related cross references

This application claims priority to Chinese patent applications with application numbers 202211387525.6, 202211387526.0 and 202211386962.6 filed with the State Intellectual Property Office on November 7, 2022, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to the field of memory, and in particular, to a memory and an electronic device.

Background technique

Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.

Taking DRAM as an example, the traditional known DRAM has multiple repeated "storage cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.

In order to reduce the cost of products as much as possible, people hope to make as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products.

Summary of the invention

The present disclosure provides a memory and an electronic device.

In a first aspect, an embodiment of the present disclosure provides a memory, including a storage array, the storage array including a plurality of storage units;

The memory cell includes a transistor having two gates, one of which is connected to a word line and the other is connected to a bit line; or the memory cell includes two transistors connected in series, each transistor having a gate, one of which is connected to a bit line and the other is connected to a word line;

Through the signal on the bit line and the signal on the word line, the currently selected storage cell is controlled to be triggered, and other storage cells belonging to the same row are not triggered.

In a second aspect, an embodiment of the present disclosure provides an electronic device, comprising the memory as described above.

The technical solution provided by the embodiments of the present disclosure has at least the following beneficial effects:

The disclosed embodiment provides a new memory, which includes at least one memory array. The memory array includes a plurality of memory cells, and the memory cell includes a transistor, the transistor has two gates, one of which is connected to a word line, and the other is connected to a bit line; or the memory cell includes two transistors connected in series, each transistor has a gate, the gate of one transistor is connected to a bit line, and the gate of the other transistor is connected to a word line; through the signal on the bit line and the signal on the word line, the currently selected memory cell is controlled to be triggered, and other memory cells belonging to the same row are not triggered.

Additional aspects and advantages of the present disclosure will be partially presented in the following description, which will become apparent from the following description. It may be apparent or learned through practice of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

FIG1 is a schematic diagram of a circuit structure of a memory provided by an embodiment of the present disclosure;

FIG2a is a schematic diagram of a circuit principle of a storage unit in a memory provided by an embodiment of the present disclosure;

FIG2b is another schematic diagram of the transistor in FIG2a;

FIG3 is an Id-Vg curve diagram of transistors in a memory cell with different deviations provided by an embodiment of the present disclosure;

FIG4a is a schematic diagram of the structure of a storage unit provided by an embodiment of the present disclosure;

FIG4b is a schematic diagram of the structure of another storage unit provided in an embodiment of the present disclosure;

FIG5 is a schematic flow chart of a method for manufacturing a memory provided by an embodiment of the present disclosure;

6a-11b are schematic structural diagrams of different manufacturing processes in the method for manufacturing a memory provided by an embodiment of the present disclosure;

FIG12 is a schematic diagram of a circuit structure of a memory in the related art;

FIG13 is a circuit diagram of a storage unit provided in an embodiment of the present disclosure;

FIG. 14 is an Id-Vg curve diagram of the first transistor T1 in FIG. 13 with different deviations;

FIG15 is a schematic diagram of a circuit structure of a memory composed of the storage unit in FIG13;

FIG16 is a circuit diagram of another storage unit provided in an embodiment of the present disclosure;

FIG. 17 is an Id-Vg curve diagram of the first transistor T1 in FIG. 16 with different deviations;

FIG18 is a schematic diagram of a circuit structure of a memory composed of the storage unit in FIG16;

FIG19 is a schematic flow chart of a method for accessing a memory according to an embodiment of the present disclosure;

FIG20 is a schematic diagram of the structure of the storage unit corresponding to FIG13;

21a-21c are schematic diagrams of the structures of the storage unit corresponding to FIG. 16;

22a to 29b are schematic structural diagrams of different manufacturing processes in a method for manufacturing a memory in FIG. 20 ;

30a to 37b are schematic structural diagrams of different manufacturing processes in a method for manufacturing a memory in FIG. 21a;

FIG38 is a schematic diagram of a circuit structure of a memory provided by an embodiment of the present disclosure;

FIG39a is a schematic diagram of a circuit principle of a storage unit in a memory provided by an embodiment of the present disclosure;

FIG39b is a schematic diagram of a circuit principle of a storage unit in another memory provided by an embodiment of the present disclosure;

FIG40 is a characteristic curve diagram of the transistor in the memory cell when different voltages are applied to BL2 and WL;

FIG41 is a schematic structural diagram of a storage unit in FIG39a;

FIG42 is a schematic flow chart of a method for manufacturing a memory device according to an embodiment of the present disclosure;

43a to 50b are schematic structural diagrams of different manufacturing processes in the method for manufacturing the memory provided in an embodiment of the present disclosure.

Detailed ways

The present disclosure is described in detail below, and examples of embodiments of the present disclosure are shown in the accompanying drawings, wherein the same or Similar reference numerals represent the same or similar parts or parts having the same or similar functions. In addition, if a detailed description of a known technology is not necessary for the features of the present disclosure shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present disclosure, and cannot be interpreted as limiting the present disclosure.

As used herein, the term "substrate" means and includes a base material or structure on which a material such as a vertical field effect transistor is formed. The substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

As shown in FIG12 , a DRAM memory generally includes a plurality of memory cells, each of which includes a transistor and a capacitor, i.e., a 1T1C memory cell. In a DRAM composed of 1T1C memory cells, the gates of transistors in a plurality of memory cells in the same row are connected to a word line (WL), and one electrode of transistors in a plurality of memory cells in the same column is connected to a bit line (BL). It can also be understood that each word line (WL) connects the gates of transistors in a plurality of memory cells in the same row together, and each bit line (BL) connects one electrode of transistors in a memory cell in the same column together.

For basic write, read or refresh operations, for read operations, set an initial voltage on BL (for example, the initial voltage is set to VDD/2), set a selected row WL high (for example, VPP, VPP>VDD), then all transistors in the storage cells of the row are turned on, the capacitor charges BL (stored data "1") or discharges (stored data "0"), and then the signal generated on BL is sensed and amplified accordingly, and the data stored in each storage cell can be read out (for example, data "1" and "0" correspond to VDD and zero respectively). Then the read data is written back to the storage cell, which is a refresh operation. For write operations, the read operation must be performed first, and then the write operation.

As can be seen from the above, for a read or write operation, all storage cells associated with the selected WL need to share charges, and all BLs need to perform signal sensing and amplification. However, for some DRAM memories, only a small portion of the data needs to be read or written, which results in relatively high overall power consumption of the device.

The present disclosure provides a memory and an electronic device, aiming to improve the above technical problems.

The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

An embodiment of the present disclosure provides a memory, which includes a memory array, which includes a plurality of memory cells; the memory cell includes a transistor, the transistor has two gates, one of which is connected to a word line, and the other is connected to a bit line; or the memory cell includes two transistors connected in series, each transistor has a gate, the gate of one transistor is connected to a bit line, and the gate of the other transistor is connected to a word line; through the signal on the bit line and the signal on the word line, the currently selected memory cell is controlled to be triggered, and other memory cells belonging to the same row are not triggered.

The present disclosure provides a new memory by using the signal on the bit line and the signal on the word line. The number controls the currently selected storage unit to be triggered, and other storage units in the same row are not triggered.

For example, during a write operation, a certain storage cell or some storage cells can be arbitrarily selected to be in an activated state, so that charge sharing, signal sensing and amplification operations are performed only in the selected storage cells, and each transistor of other unselected storage cells is in a closed state, thereby reducing power consumption. The present disclosure provides a memory, as shown in FIG1 , the memory includes: a plurality of storage cells 10, a plurality of word lines WL, a plurality of first bit lines BL1 and a plurality of second bit lines BL2.

In one embodiment, for a DRAM memory of a 1T1C storage unit, in FIG1 , BL1_1, BL1_2, BL1_3, …, BL1_n represent the first, second, …, third, and nth first bit lines BL1, respectively; BL2_1, BL2_2, BL2_3, …, BL2_n represent the first, second, …, third, and nth second bit lines BL2, respectively; WL1, WL2, WL3, …, WLm represent the first, second, third, …, and mth word lines WL, respectively; and m and n are positive integers.

As shown in FIG. 2 a and FIG. 2 b , the memory cell 10 includes a transistor T and a capacitor C. There are two different representation methods of the transistor T. FIG. 2 a and FIG. 2 b show two different representation methods of the transistor T. FIG.

The capacitor C includes a first electrode 102 and a second electrode 104 insulated from each other; the transistor T includes a third electrode 106, a fourth electrode 109, a first gate 107 and a second gate 114;

The first electrode 102 of the capacitor C is electrically connected to the reference potential terminal Vrefn, the second electrode 104 of the capacitor C is electrically connected to the third electrode 106 of the transistor T, the fourth electrode 109 of the transistor T is electrically connected to the first bit line BLI, the first gate 107 of the transistor T is electrically connected to the word line WL, and the second gate 114 of the transistor T is electrically connected to the second bit line BL2.

It should be noted that the transistor T in the embodiment of the present disclosure may be an N-type transistor or a P-type transistor, which is not limited in the present disclosure. For the convenience of description, the principle of the memory is described by taking an N-type transistor as an example.

As shown in combination with FIG. 2a, FIG. 2b and FIG. 3, the transistor T in the embodiment of the present disclosure is a transistor of a dual-gate structure, that is, the transistor has two gates, one of which is electrically connected to the word line WL as a control gate electrode, and the other gate is electrically connected to the second bit line BL2. By applying a voltage to the second bit line BL2, the other gate of the transistor T receives a different bias voltage, thereby shifting the threshold voltage Vth of the transistor T. For example, for an N-type MOSFET, the threshold voltage Vth of the transistor will shift negatively as the bias voltage applied to the gate increases.

For n-type transistors, when a suitable voltage is applied to the word line WL controlling the gate electrode of the same row and a lower voltage is applied to the second bit line BL2, the transistors in each memory cell are turned off.

If a certain memory cell in a row needs to be selected, but other memory cells in the row do not need to be selected, a higher voltage is applied only to the second bit line connected to the transistor in the selected memory cell to turn on the transistor, while the transistors in other memory cells that do not need to be selected remain turned off.

In FIG3 , BL2 “high” indicates that BL2 is at a high level, BL2 “low” indicates that BL2 is at a low level, “unselected WL” indicates that WL is not activated or not selected, and WL is at a low level, and “selected WL” indicates that WL is activated or selected, and WL is at a high level.

For n-type transistors, when at least one of the word line WL and the second bit line BL2 is at a low level, at least one gate of the transistor T in the storage unit is loaded with a low level, and the transistor T is in the off state. That is, the word line WL is at a low level and the second bit line BL2 is at a high level; or, the word line WL is at a high level and the second bit line BL2 is at a low level; or, the word line WL and the second bit line BL2 are both at a low level. In these three cases, the transistor T in the storage unit is in the off state by controlling the high level voltage to be appropriate. When the word line WL and the second bit line BL2 are both at a high level, the two gates of the transistor T in the storage unit are loaded with a high level of an appropriate voltage value to ensure that the transistor T is turned on; therefore, in some embodiments, when the word line WL and the second bit line BL2 are both at a high level, and the high level voltage is controlled to be an appropriate voltage, the transistor T in the storage unit will be turned on, and the memory can be accessed.

The disclosed embodiment provides a new memory, which includes at least one memory array, a plurality of word lines WL, a plurality of first bit lines BLI and a plurality of second bit lines BL2; the memory array includes a plurality of memory cells 10, and the memory cell 10 includes a transistor and a capacitor. The two gates of the transistor are controlled respectively by the second bit line BL2 and the word line WL, thereby controlling the on and off of the transistor. During the read or write operation, a certain memory cell or certain memory cells can be arbitrarily selected, so that charge sharing, signal sensing and amplification operations are performed only in the selected memory cells, and other unselected memory cells are all in a closed state, thereby reducing power consumption.

In addition, when writing data, the traditional 1T1C memory usually reads first and then writes, that is, the read operation must be performed first and then the write operation. However, when the memory provided by the embodiment of the present disclosure is used, since the transistors in the unselected storage cells remain in the off state during the write operation, the data in the unselected storage cells will not be destroyed, and the write operation can be performed directly without the need for the read and amplification operations before the write operation, thereby facilitating the improvement of the data writing speed and the reduction of power consumption.

Continuing with FIG1 , a plurality of memory cells 10 in the memory array form a plurality of memory cell rows and a plurality of memory cell columns; each memory cell 10 in each memory cell row is electrically connected to a word line WL; each memory cell 10 in each memory cell column is electrically connected to a first bit line BL1 (BL1_1, BL1_2, BL1_3, ..., BL1_n) and a second bit line BL2 (BL2_1, BL2_2, BL2_3, ..., BL2_n).

The multiple memory cells 10 in the memory array are distributed in an array. For a row of memory cells, different second bit lines BL2 and the same word line WL connected to each memory cell are used to control the two gates of each transistor respectively, thereby controlling the on and off of the transistor. During a read or write operation, a certain memory cell or certain memory cells can be arbitrarily selected, so that charge sharing, signal sensing and amplification operations are performed only in the selected memory cells, and other unselected memory cells are in a closed state, thereby reducing power consumption.

As shown in FIG1 , through the second bit line BL2_2 and the word line WL3, only the memory cell 10 in the dotted circle is selected, and the read or write operation can be directly performed on the memory cell 10. In this case, only the first bit line BL1_2 will undergo the charging and discharging process, perform signal sensing and amplification, and other unselected memory cells are in a closed state, thereby reducing power consumption. In the read or write operation of the traditional 1T1C memory, all memory cells associated with the selected WL need to share charges, and all BLs need to perform signal sensing and amplification.

In some examples, several columns can be parallelized by selecting several second bit lines BL2 and one word line WL. Read or write operation: For example, three second bit lines (BL2_1, BL2_2, BL2_3) and one word line (WL3) may be selected to read or write data to three columns in parallel.

In some embodiments, as shown in FIG4a and FIG4b, the capacitor C is located on one side of the substrate 100; the transistor T is located on the side of the capacitor C away from the substrate 100. The transistor T is located on the capacitor C and is stacked with the capacitor C in a direction perpendicular to the substrate 100.

The transistor and capacitor of the memory cell provided in the embodiment of the present disclosure are arranged up and down, that is, the transistor is located above the capacitor, which can achieve more compact space, save area, and facilitate high-density integration and manufacturing. The transistor and capacitor of the conventional 1T1C memory cell are arranged side by side, that is, the capacitor is arranged next to the transistor, which is relatively wasteful in terms of area.

Optionally, as shown in FIG. 4 a and FIG. 4 b , the transistor T is located directly above the capacitor C, which can achieve a more compact space, save area, and facilitate high-density integration and manufacturing.

In some embodiments, as shown in FIG. 4 a and FIG. 4 b , the capacitor C further includes a capacitor dielectric layer 103 ; the first electrode 102 and the second electrode 104 are insulated from each other by the capacitor dielectric layer 103 ;

A first electrode 102, located on one side of the substrate 100;

The capacitor dielectric layer 103 is located on a side of the first electrode 102 away from the substrate 100 , and the orthographic projection of the capacitor dielectric layer 103 on the substrate 100 overlaps with the orthographic projection of the first electrode 102 on the substrate 100 ;

The second electrode 104 is located on a side of the capacitor dielectric layer 103 away from the substrate 100 , and its orthographic projection on the substrate 100 is located within the orthographic projection of the capacitor dielectric layer 103 on the substrate 100 .

The capacitor C provided in the embodiment of the present disclosure has a simple structure, which is conducive to high-density integration and manufacturing.

In some embodiments, as shown in FIG. 4 a and FIG. 4 b , the transistor T further includes a semiconductor layer 112 ;

The third electrode 106 is located at a side of the second electrode 104 away from the substrate 100 and connected to the second electrode 104;

A first gate 107 is located at a side of the third electrode 106 away from the substrate 100 and is insulated from the third electrode 106;

The fourth electrode 109 is located on a side of the first gate 107 away from the substrate 100 , and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the first gate 107 on the substrate 100 , and is insulated from the first gate 107 ;

The semiconductor layer 112 is located on a side of the fourth electrode 109 away from the substrate 100 and is connected to the fourth electrode 109 and the third electrode 106 and is insulated from the first gate 107;

The second gate 114 is located on a side of the semiconductor layer 112 away from the substrate 100 , and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the semiconductor layer 112 on the substrate 100 , and is insulated from the semiconductor layer 112 .

Specifically, the first gate 107 can be a part of the word line WL, or the first gate 107 is connected to the word line WL. The second gate 114 can be a second bit line BL2, or the second gate 114 is connected to the second bit line 114. The semiconductor layer 112 is connected to the fourth electrode 109 and the third electrode 106, respectively.

The transistor T provided in the embodiment of the present disclosure has a simple structure, which is conducive to high-density integration and manufacturing.

In a specific embodiment, the third electrode 106 is located on a side of the second electrode 104 away from the substrate, and the third electrode 106 is connected to the second electrode 104;

The semiconductor layer 112 is located on the third electrode 106 and connected to the third electrode 106. Extending in a direction perpendicular to the substrate 100 and connected to the fourth electrode 109;

The fourth electrode 109 is located on a side of the semiconductor layer 112 close to the substrate 100;

The second gate 114 is located at a side of the semiconductor layer 112 away from the substrate 100 and is insulated from the semiconductor layer 112;

The first gate 107 surrounds a portion of the channel region of the semiconductor layer 112 and is insulated from the semiconductor layer 112. The channel of the semiconductor layer 112 is a vertical channel.

Optionally, the orthographic projection of the second gate 114 on the substrate 100 , the orthographic projection of the semiconductor layer 112 on the substrate 100 , the orthographic projection of the fourth electrode 109 on the substrate 100 , and the orthographic projection of the third electrode 106 on the substrate 100 all overlap.

In some embodiments, as shown in FIG. 4 a and FIG. 4 b , the transistor T further includes a first gate insulating layer 111 and a second gate insulating layer 113 ;

A first gate insulating layer 111, located between the first gate 107 and the semiconductor layer 112;

The second gate insulating layer 113 is located between the second gate 114 and the semiconductor layer 112 , and an orthographic projection of the second gate insulating layer 113 on the substrate 100 overlaps with an orthographic projection of the semiconductor layer 112 on the substrate 100 .

Optionally, on a plane perpendicular to the substrate 100 , an orthographic projection of the first gate insulating layer 111 overlaps with an orthographic projection of the first gate 107 .

Optionally, the first electrode 102 serves as a reference potential terminal Vrefn (as shown in FIG. 4a ), or the first electrode 102 is connected to a separate reference potential terminal Vrefn, and the reference potential terminal Vrefn receives a reference signal; the substrate 100 can serve as a separate reference potential terminal Vrefn, or a reference potential terminal Vrefn can be set on the substrate 100 (as shown in FIG. 4b ).

The first gate 107 is a part of the word line WL, or the first gate 107 is disposed in the same layer and connected to the word line WL;

The fourth electrode 109 is a part of the first bit line BL1, or the fourth electrode 109 is disposed in the same layer and connected to the first bit line BL1;

The second gate 114 is a part of the second bit line BL2 , or the second gate 114 is disposed in the same layer as and connected to the second bit line BL2 .

Preferably, the first gate 107 is a part of the word line WL, the fourth electrode 109 is a part of the first bit line BL1, the second gate 114 is a part of the second bit line BL2, the first gate and the word line WL are both marked with "107", the fourth electrode and the first bit line BL1 are both marked with "109", and the second gate and the second bit line BL2 are both marked with "114". This can further simplify the structure of the memory and improve the integration of the memory.

In some embodiments, as shown in FIG. 4a , the first electrode 102 reuses the reference potential terminal Vrefn (both the first electrode and the reference potential terminal Vrefn are marked with “102”). As shown in FIG. 4b , the first electrode 102 and the reference potential terminal Vrefn may also be separately provided and connected.

Based on the same inventive concept, the present disclosure provides a method for manufacturing a memory, wherein the memory includes: at least one memory array, the memory array includes a plurality of memory cells, a plurality of word lines, a plurality of first bit lines, and a plurality of second bit lines; the memory cells include transistors and capacitors. As shown in FIG5 , the method for manufacturing the memory includes:

S1: forming a capacitor and a reference potential terminal on one side of the substrate by a patterning process; the capacitor comprises a first electrode and a second electrode; the first electrode of the capacitor is electrically connected to the reference potential terminal;

S2: A transistor, a word line, a first bit line and a second bit line are formed on a side of the capacitor away from the substrate through a patterning process; the transistor includes a third electrode, a fourth electrode, a first gate and a second gate; the third electrode of the transistor is electrically connected to the second electrode of the capacitor; the fourth electrode of the transistor is electrically connected to the first bit line, the first gate of the transistor is electrically connected to the word line, and the second gate of the transistor is electrically connected to the second bit line.

The manufacturing method of the memory provided by the embodiment of the present disclosure is relatively simple. The capacitor and the reference potential terminal are first manufactured, and then the transistor, the word line, the first bit line and the second bit line are manufactured. That is, the transistor and the capacitor of the storage unit are arranged in an upper and lower manner, that is, the transistor is located above the capacitor. This can achieve a more compact space, save area, and facilitate high-density integration and manufacturing.

The following describes in detail the manufacturing process of a memory in an embodiment of the present disclosure in conjunction with Figures 6a to 11b. The patterning process in the embodiment of the present disclosure includes part or all of the processes of deposition, photolithography, etching and planarization.

In some embodiments, a capacitor and a reference potential terminal are formed on one side of a substrate, including:

forming a first electrode and a reference potential terminal on one side of the substrate;

A capacitor dielectric layer and a second electrode are sequentially formed on the first electrode and the side of the reference potential terminal away from the substrate.

Specifically, as shown in FIG. 6a and FIG. 6b, FIG. 6a and FIG. 6b are side views and top views of the manufacturing process of the memory, respectively. A metal film can be formed on one side of the substrate 100, and then a portion of the metal film is removed by an etching step in the patterning process. Afterwards, a dielectric layer is deposited on one side of the substrate 100 and flattened to form a first dielectric layer 101. Afterwards, a receiving hole is formed that penetrates the above-mentioned metal film, and then a first electrode 102 and a reference potential terminal Vrefn located outside the receiving hole are formed by a patterning process, and a capacitor dielectric layer 103 and a second electrode 104 located inside the receiving hole are formed. In this embodiment, the first electrode 102 reuses the reference potential terminal Vrefn (the first electrode and the reference potential terminal Vrefn are both marked with "102").

In some embodiments, forming a transistor, a word line, a first bit line, and a second bit line on a side of the capacitor away from the substrate includes:

A third electrode, a fourth electrode, a semiconductor layer, a gate insulating layer, a second gate, a gate dielectric layer and a first gate are sequentially formed on a side of the second electrode away from the substrate.

Specifically, as shown in Figure 7a and Figure 7b, Figure 7a and Figure 7b are respectively a side view and a top view of the manufacturing process of the memory. The third electrode 106 is sequentially formed on the side of the second electrode 104 away from the substrate 100 by a patterning process.

As shown in Figure 8a and Figure 8b, Figure 8a and Figure 8b are respectively a side view and a top view of the manufacturing process of the memory. A second dielectric layer 105 and a sacrificial layer 116 are formed on a side of the third electrode 106 away from the substrate 100 by a patterning process.

As shown in Figures 9a and 9b, Figures 9a and 9b are respectively a side view and a top view of the manufacturing process of the memory. A third dielectric layer 108, a fourth electrode 109 and a receiving hole 117 are formed on the side of the sacrificial layer 116 away from the substrate 100 through a patterning process. The fourth electrode 109 reuses the first bit line BL1 (the fourth electrode and the first bit line BL1 are both marked with "109").

As shown in FIG. 10a and FIG. 10b, FIG. 10a and FIG. 10b are respectively a side view and a top view of the manufacturing process of the memory. The semiconductor layer 112 is formed by a patterning process.

As shown in FIG. 11a and FIG. 11b, FIG. 11a and FIG. 11b are respectively a side view and a top view of the manufacturing process of the memory. A gate insulating layer 113 and a second gate 114 are sequentially formed by a patterning process, and then a portion of the third dielectric layer 108 and a complete removal of the sacrificial layer 116 are removed by a patterning process, and then a gate dielectric layer 111 and a first gate 107 are sequentially formed. The second gate 114 reuses the second bit line BL2 (the second gate and the second bit line BL2 are both marked with "114"). The first gate 107 reuses the word line WL (the first gate and the word line WL are both marked with "107").

Based on the same inventive concept, an embodiment of the present disclosure provides a method for accessing a memory, including:

Applying a first voltage to the first gate of each transistor in a row of memory cells through a word line;

A second voltage is applied to the second gate of the transistor in the memory cell that needs to be accessed in a row of memory cells through the second bit line to turn on the transistor, and a data signal is written to the storage node connected to the transistor through the first bit line connected to the transistor; and a third voltage is applied to the second gate of the transistor in the memory cell that does not need to be accessed in a row of memory cells through the second bit line to turn off the transistor.

Specifically, as shown in FIG. 1 and FIG. 2a, a first voltage (high level) is applied to the first gate 107 of the transistor T through the word line WL, and a second voltage (high level) is applied to the second gate 114 of the transistor T through the second bit line BL2, so that the transistor T is turned on, and the memory cell is accessed through the first bit line BL1. For example, a read operation or a write operation can be performed on the memory cell. During the read or write operation, the transistor is controlled to be turned on through the word line WL and the second bit line BL2, and a certain memory cell or some memory cells can be arbitrarily selected, so that charge sharing, signal sensing and amplification operations are performed only in the selected memory cells, and other unselected memory cells are all in a closed state, thereby reducing power consumption.

The memory access method provided by the embodiment of the present disclosure applies appropriate voltages to the second bit line and the word line to control the two gates of the transistor respectively, thereby controlling the transistors in the memory cells that need to be accessed to be turned on, and controlling the transistors in the memory cells that do not need to be accessed to be turned off. During the read or write operation, a certain memory cell or some memory cells can be arbitrarily selected, and other unselected memory cells are in a closed state, thereby avoiding waste of power consumption and reducing power consumption.

In addition, in the prior art, when writing data, it is usually read first and then written, that is, the read operation must be performed first and then the write operation. However, using the memory access method provided by the embodiment of the present disclosure, when performing a write operation, it is not necessary to read first and the write operation can be performed directly, which is conducive to improving the speed of writing data.

In another embodiment, for a DRAM memory of a common 2T0C memory cell, the DRAM memory includes multiple memory cells, the common 2T0C memory cell includes two transistors, and in the DRAM composed of 2T0C memory cells, each WL connects multiple memory cells in the same row together, and each BL connects memory cells in the same column together.

Wherein, the write word line WWL represents a word line for writing data; the write bit line WBL represents a bit line for writing data; the read word line RWL represents a word line for reading data; and the read bit line RBL represents a bit line for reading data;

To access the memory, for example, for a write operation, a selected write word line WWL is activated, and then if all write bit lines WBL are not prepared with correct data, all memory cells associated with the selected write word line WWL are activated. Therefore, the read operation should generally be performed before the write operation, that is, read first and then write (similar to the access of DRAM composed of 1T1C storage units).

As can be seen from the above, for a write operation, all storage cells associated with the selected WL need to share charges, and all BLs need to perform signal sensing and amplification. However, for some DRAM memories, only a small portion of data needs to be read or written, which results in most BL operations being useless, and only a small portion of the total power consumption is valuable, resulting in a waste of power consumption.

The embodiment of the present disclosure provides a memory, as shown in FIG. 13 to FIG. 18 , the memory includes a plurality of storage units 10;

As shown in FIG. 13 and FIG. 16 , the memory cell 10 includes a first transistor T1 and a second transistor T2; wherein the first transistor includes a first electrode, a second electrode, a first gate and a second gate; the second transistor includes at least a third gate; the first transistor is a write transistor, and the second transistor is a read transistor, the write transistor is used for a write operation, and the read transistor is used for a read operation. The write transistor has two gates. The read transistor may have one gate or two gates.

The first electrode is connected to the first write bit line (WBL1/BL1); the second electrode is connected to the third gate, and the third gate is configured as a storage node (SN) of the storage unit; the first gate is connected to the write word line (WWL), and the second gate is connected to the second write bit line (WBL2/BL2); the first transistor is turned on or off under the common control of the write word line (WWL) and the second write bit line (WBL2/BL2), and when the first transistor is turned on, the data signal is written to the storage node (SN) through the second write bit line.

It should be noted that the transistors in the embodiments of the present disclosure may be N-type transistors or P-type transistors, which are not limited in the present disclosure. For the convenience of description, the principle of the memory is described by taking N-type transistors as an example.

FIG13 and FIG16 show two embodiments. In combination with FIG13 and FIG14, the first transistor T1 in the embodiment of the present disclosure is a transistor of a dual-gate structure, that is, the first transistor has two gates, one of which is electrically connected to the write word line WWL and serves as a control gate electrode, and the other gate is electrically connected to the second write bit line WBL2. By applying a voltage to the second write bit line WBL2, the other gate of the first transistor T1 receives a different bias voltage, thereby causing the threshold voltage Vth of the first transistor T1 to shift. For example, for an N-type MOSFET, the threshold voltage Vth of the transistor will shift negatively as the bias voltage applied to the gate increases (as shown in FIG14).

For n-type transistors, when a suitable voltage is applied to the write word line WWL of the same row control gate electrode and a lower voltage is applied to the second write bit line WBL2, the transistors in the memory cells that need to be selected are turned on, and the transistors in the memory cells that do not need to be selected are turned off.

If a certain memory cell in a row needs to be selected, but other memory cells in the row do not need to be selected, a higher voltage is applied to the second write bit line WBL2 connected to the transistor in the selected memory cell to turn on the transistor, while the transistors in other memory cells that do not need to be selected remain turned off.

In FIG14 , WBL2 “high” indicates that WBL2 is at a high level, WBL2 “low” indicates that WBL2 is at a low level, “unselected WWL” indicates that WWL is not activated or not selected, and WWL is at a low level, and “selected WWL” indicates that WWL is activated or selected, and WWL is at a high level.

For n-type transistors, when at least one of the write word line WWL and the second write bit line WBL2 is at a low level, at least one gate of the first transistor T1 in the storage unit is loaded with a low level, and the first transistor T1 is in an off state. That is, the write word line WWL is at a low level and the second write bit line WBL2 is at a high level; or, the write word line WWL is at a high level and the second write bit line WBL2 is at a low level; or, the write word line WWL and the second write bit line WBL2 are both at a low level. In these three cases, the first transistor T1 in the storage unit is in an off state. When the write word line WWL and the second write bit line WBL2 are both at a high level, both gates of the first transistor T1 in the storage unit are loaded with a high level, and the first transistor T1 is turned on; therefore, only when the write word line WWL and the second write bit line WBL2 are both at a high level, the first transistor T1 in the storage unit will be turned on, and the memory can be accessed.

FIG16 and FIG17, similar to FIG13-14, in combination with FIG16 and FIG17, the first transistor T1 in another embodiment of the present disclosure is a transistor of a dual-gate structure, that is, the first transistor has two gates, one of which is electrically connected to the write word line WWL, and the other gate is electrically connected to the second write bit line BL2. By loading a voltage on the second write bit line BL2, the other gate of the first transistor T1 receives a different bias voltage, so that the threshold voltage Vth of the first transistor T1 is shifted. For example, for an N-type MOSFET, the threshold voltage Vth of the transistor will be negatively shifted as the bias voltage loaded on the gate increases (as shown in FIG17).

For n-type transistors, when a suitable voltage is applied to the write word line WWL of the control gate electrode in the same row and a lower voltage is applied to the second write bit line BL2, each memory cell is turned off.

If a certain memory cell in a row needs to be selected, but other memory cells in the row do not need to be selected, a higher voltage is applied to the second write bit line BL2 connected to the transistor in the selected memory cell to turn on the transistor, while the transistors in other memory cells that do not need to be selected remain turned off.

In FIG17 , BL2 “high” indicates that BL2 is at a high level, BL2 “low” indicates that BL2 is at a low level, “unselected WWL” indicates that WWL is not activated or not selected, and WWL is at a low level, and “selected WWL” indicates that WWL is activated or selected, and WWL is at a high level.

For n-type transistors, when at least one of the write word line WWL and the second write bit line BL2 is at a low level, at least one gate of the first transistor T1 in the storage unit is loaded with a low level, and the first transistor T1 is in an off state. That is, the write word line WWL is at a low level and the second write bit line BL2 is at a high level; or, the write word line WWL is at a high level and the second write bit line BL2 is at a low level; or, the write word line WWL and the second write bit line BL2 are both at a low level. In these three cases, the first transistor T1 in the storage unit is in an off state. When the write word line WWL and the second write bit line BL2 are both at a high level, both gates of the first transistor T1 in the storage unit are loaded with a high level, and the first transistor T1 is turned on; therefore, only when the write word line WWL and the second write bit line BL2 are both at a high level, the first transistor T1 in the storage unit will be turned on, and the memory can be accessed.

The disclosed embodiment provides a new memory, which includes a plurality of memory cells, wherein the memory cell includes two connected first transistors and second transistors, wherein the first transistor is a write transistor and the second transistor is a read transistor. The first transistor is turned on or off under the common control of a write word line (WWL) and a second write bit line (WBL2/BL2). When the first transistor is turned on, a data signal is written to the storage node (SN) through the second write bit line. During a write operation, any one or some memory cells can be selected, so that only the selected memory cells are read. The cells perform charge sharing, signal sensing and amplification operations, while other unselected memory cells are in a closed state, thereby reducing power consumption.

Moreover, when writing data, the traditional 2T0C memory usually reads first and then writes, that is, the read operation must be performed first and then the write operation. However, when the memory provided by the embodiment of the present disclosure is used, since the transistors in the unselected storage cells remain in the off state during the write operation, the data in the unselected storage cells will not be destroyed, and the write operation can be performed directly without the need for the read and amplification operations before the write operation, thereby facilitating the improvement of the data writing speed and the reduction of power consumption.

In some embodiments, as shown in Figure 13, the second transistor T2 also includes a third electrode and a fourth electrode; the third electrode is connected to the read bit line (RBL), and the fourth electrode is connected to the read word line (RWL); the second transistor is configured to read out the data signal stored in the storage node (SN).

In some embodiments, as shown in FIG. 13 and FIG. 15 , the plurality of memory cells form a plurality of memory cell rows and a plurality of memory cell columns; and the plurality of memory cells are distributed in an array.

The first gates of the first transistors in a row of memory cells are connected to a write word line (WWL), the second gates of the first transistors are connected to different second write bit lines (WBL2), and the first electrodes of the first transistors are connected to different first write bit lines (WBL1).

The third electrodes of the second transistors in a row of memory cells are connected to different read bit lines (RBL), and the fourth electrodes of the second transistors are connected to one read word line (RWL).

In FIG15 , WWL1, WWL2, WWL3, …, WWLm represent the first write word line, the second write word line, the third write word line, …, and the mth write word line, respectively. RWL1, RWL2, RWL3, …, and RWLm represent the first read word line, the second read word line, the third read word line, …, and the mth read word line, respectively. RBL1, RBL2, RBL3, …, and RBLn represent the first read bit line, the second read bit line, the third read bit line, …, and the nth read bit line, respectively. WBL1_1, WBL1_2, WBL1_3, …, and WBL1_n represent the first first write bit line, the second first write bit line, the third first write bit line, …, and the nth first write bit line, respectively. WBL2_1, WBL2_2, WBL2_3, ..., WBL2_n represent the first second write bit line, the second second write bit line, the third second write bit line, ..., the nth second write bit line, respectively. Both m and n are greater than 1.

The plurality of memory cells in the memory array are distributed in an array. The two gates of the first transistor T1 are controlled respectively by the write word line WWL and the second write bit line WBL2, thereby controlling the on and off of the first transistor T1. During a write operation, any one or some memory cells can be selected, so that charge sharing, signal sensing and amplification operations are performed only in the selected memory cells, and other unselected memory cells are in a closed state, thereby reducing power consumption.

As shown in FIG15 , through the write word line WWL and the second write bit line WBL2, only the memory cell in the dotted circle is selected, and the write operation can be directly performed on the memory cell. In this case, only the first write bit line WBL1_n will undergo the charging and discharging process, perform signal sensing and amplification, and other unselected memory cells are in a closed state, thereby reducing power consumption. In the write operation of the traditional 1T1C memory, all memory cells associated with the selected WL need to share charges, and all BLs need to perform signal sensing and amplification.

In some examples, several columns can be read or written in parallel by selecting several second write bit lines WBL2 and one write word line WWL. For example, three second write bit lines (WBL2_1, WBL2_2, WBL2_3) and one word line (WWL2) can be selected to write data in parallel to three columns.

In some other embodiments, as shown in FIG16, the second transistor T2 further includes a third electrode, a fourth electrode and a fourth gate; the third electrode is connected to the reference potential terminal (Vrefn), the fourth electrode is connected to the read bit line, the read bit line is connected to the first write bit line, and is connected to a lead BL1 (as shown in FIG16, the first electrode of the first transistor T1 is connected to the fourth electrode of the second transistor T2, and is connected to a lead BL1). The fourth gate is connected to the read word line (RWL); the second transistor is configured to read out the data signal stored in the storage node (SN).

In this embodiment, the second transistor T2 uses a dual-gate structure transistor, which makes it easier to read data. Like a conventional 1T1C, during the read operation, any one or some memory cells can be selected, so that charge sharing, signal sensing and amplification operations are performed only in the selected memory cells to read data. Other unselected memory cells are in a closed state, thereby reducing power consumption.

In other embodiments, multiple memory cells form multiple memory cell rows and multiple memory cell columns; multiple memory cells are distributed in an array; the first gate of each first transistor belonging to a row of memory cells is connected to a write word line (WWL), the second gate of each first transistor is connected to a different second write bit line (BL2), and the first electrode of each first transistor is connected to a different first write bit line; the third electrode of each second transistor belonging to a row of memory cells is connected to a reference potential terminal (Vrefn), the fourth electrode of each second transistor is connected to a read bit line, and the fourth gate of each second transistor is connected to a read word line (RWL).

In FIG18 , WWL1, WWL2, WWL3, …, WWLm represent the first write word line, the second write word line, the third write word line, …, the mth write word line, respectively. RWL1, RWL2, RWL3, …, RWLm represent the first read word line, the second read word line, the third read word line, …, the mth read word line, respectively. BL1_1, BL1_2, BL1_3, …, BL1_n represent the same lead wire BL1_1, BL1_2, BL1_3, …, BL1_n connecting the first transistor and the second transistor in different columns, respectively. BL2_1, BL2_2, BL2_3, …, BL2_n represent the first second write bit line, the second second write bit line, the third second write bit line, …, the nth second write bit line, respectively. Both m and n are greater than 1.

The plurality of memory cells in the memory array are distributed in an array. The two gates of the first transistor T1 are controlled respectively by the write word line WWL and the second write bit line BL2, thereby controlling the on and off of the first transistor T1. During a write operation, any one or some memory cells can be selected, so that charge sharing, signal sensing and amplification operations are performed only in the selected memory cells, and other unselected memory cells are in a closed state, which can reduce power consumption.

Through the write word line WWL and the second write bit line BL2, only one memory cell can be selected, and other unselected memory cells are in a closed state, thereby reducing power consumption. However, the write operation of the traditional 1T1C memory requires all memory cells associated with the selected WL to share charges, and all BLs need to perform signal sensing and amplification.

In some examples, several columns can be read or written in parallel by selecting several second write bit lines BL2 and one write word line WWL. For example, three second write bit lines (BL2_1, BL2_2, BL2_3) and one write word line (WWL2) can be selected to write data in parallel to three columns.

Based on the same inventive concept, as shown in FIG19 , an embodiment of the present disclosure provides a method for accessing a memory, including:

S1: applying a first voltage to the first gate of each first transistor in a row of memory cells through a write word line;

S2: Apply a second voltage to the second gate of the first transistor in the memory cell that needs to be accessed in a row of memory cells through the second write bit line to turn on the first transistor, and write a data signal to the storage node connected to the first transistor through the first write bit line connected to the first transistor; and apply a third voltage to the second gate of the first transistor in the memory cell that does not need to be accessed in a row of memory cells through the second write bit line to turn off the first transistor.

The memory access method provided by the embodiment of the present disclosure controls the conduction of the first transistor in the memory cell that needs to be accessed and controls the turn-off of the first transistor in the memory cell that does not need to be accessed by applying a suitable voltage to the write word line and the second write bit line. During the write operation, any one or some memory cells can be selected, while other unselected memory cells are in a closed state, thereby avoiding waste of power consumption and reducing power consumption.

Moreover, in the prior art, when writing data, it is usually read first and then written, that is, the read operation needs to be performed first and then the write operation. However, using the memory access method provided by the embodiment of the present disclosure, when performing a write operation, it is not necessary to read first and the write operation can be performed directly, which is conducive to improving the speed of writing data.

Based on the same inventive concept, the embodiment of the present disclosure provides a memory including a plurality of memory cells; the memory cell includes a first transistor T1 and a second transistor T2 connected;

In combination with Figure 13, Figure 20, and Figure 16, Figure 21a, Figure 21b, and Figure 21c, the first transistor T1 and the second transistor T2 are distributed up and down. The first transistor T1 is located at the top, and the second transistor T2 is located at the bottom. Figure 8 corresponds to Figure 1, Figure 20 is an embodiment of the first memory structure, and Figures 21a, 21b, and 21c correspond to Figure 16, and 21a, 21b, and 21c are three embodiments of the second memory structure.

The first transistor T1 and the second transistor T2 of the storage unit in the memory provided by the embodiment of the present disclosure are arranged up and down, which can achieve a more compact space, save area, and facilitate high-density integration and manufacturing.

Specifically, the second transistor T2 is located at one side of the substrate 100; and the third gate 106 of the second transistor T2 is configured as a storage node (SN) of the storage unit; the first transistor T1 is located at a side of the second transistor away from the substrate 100; the third gate 106 of the second transistor T2 reuses the second electrode of the first transistor; the write word line 108 (WWL) is located at a side of the third gate 106 away from the substrate 100, and is insulated from the third gate 106;

The first write bit line 110 (as shown in FIG. 20 ) or the first write bit line 110 a (as shown in FIGS. 21 a , 21 b and 21 c ) is located on a side of the write word line 108 (WWL) away from the substrate 100 , and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the write word line 108 (WWL) on the substrate 100 , and is insulated from the write word line 108 (WWL);

The first transistor T1 also includes a first semiconductor layer 112, which is located on a side of the first write bit line 110 away from the substrate 100 and is connected to the first write bit line 110 (WBL1 or the first write bit line 110a). The first semiconductor layer 112 extends in a direction perpendicular to the substrate 100 to be connected to the third gate 106 and is insulated from the write word line 108 (WWL).

The second write bit line 114 ( WBL2 / BL2 ) is located on a side of the first semiconductor layer 112 away from the substrate 100 , and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the first semiconductor layer 112 on the substrate 100 , and is insulated from the first semiconductor layer 112 .

In some embodiments, the first transistor T1 further includes: a first gate insulating layer 113 and a first gate dielectric layer 111; the first gate dielectric layer 111 is located between the write word line 108 (WWL) and the first semiconductor layer 112; the first gate insulating layer 113 is located between the second write bit line 114 (WBL2/BL2) and the first semiconductor layer 112, and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the first semiconductor layer 112 on the substrate 100.

In some embodiments, the first transistor T1 includes a first electrode, a second electrode, a first gate and a second gate; the second transistor includes a third gate 106. The first gate serves as a part of the write word line 108 (WWL); the second gate serves as a part of the second write bit line 114 (WBL2/BL2); the first electrode serves as a part of the first write bit line 110/110a. This can further simplify the structure of the memory cell 10 and improve the integration of the memory. In some embodiments, as shown in FIG. 13 and FIG. 20, the second transistor T2 is located on one side of the substrate 100; and the third gate 106 of the second transistor T2 is configured as a storage node (SN) of the memory cell.

Specifically, the read bit line 102 (RBL) is located on one side of the substrate 100; the read word line 103 (RWL) is located on the side of the read bit line 102 (RBL) away from the substrate 100, and the orthographic projection on the substrate 100 overlaps with the orthographic projection of the read bit line 102 (RBL) on the substrate 100, and is insulated from the read bit line 102 (RBL); the second transistor T2 also includes a second semiconductor layer 104, which is located on the side of the read word line 103 (RWL) away from the substrate, and is connected to the read word line 103 (RWL), and is connected to the read bit line 102 (RBL) through a via hole penetrating the read word line 103 (RWL); the via hole refers to a receiving hole in the manufacturing process.

The third gate 106 is located on a side of the second semiconductor layer 104 away from the substrate 100, and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the second semiconductor layer 104 on the substrate 100, and is insulated from the second semiconductor layer 104. The second transistor T2 further includes a second gate insulating layer 105, which is located between the third gate 106 and the second semiconductor layer 104, and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the second semiconductor layer 104 on the substrate 100.

Optionally, the second transistor T2 includes a third electrode and a fourth electrode; the read bit line 102 (RBL) is used as the third electrode, and the read word line 103 (RWL) is used as the fourth electrode. This can further simplify the structure of the memory cell 10 and improve the integration of the memory.

In some other embodiments, as shown in FIG. 16 , FIG. 21 a , FIG. 21 b , and FIG. 21 c , the second transistor T2 is located on one side of the substrate 100 ; and the third gate 106 of the second transistor T2 is configured as a storage node (SN) of the memory cell.

Specifically, the substrate 100 can be used as a reference potential terminal Vrefn (as shown in FIG. 21a ). Alternatively, a reference potential terminal Vrefn can be fabricated separately (as shown in FIG. 21b ), and the reference potential terminal 121 (Vrefn) is located at one side of the substrate 100 . This disclosure does not make any special limitation.

Specifically, as shown in FIG. 21 b , the reference potential terminal 121 (Vrefn) is located on one side of the substrate 100 ; the read word line 103 (RWL) is located on a side of the reference potential terminal 121 (Vrefn) away from the substrate 100 and is insulated from the reference potential terminal 121 (Vrefn);

A read bit line 110 b is located on a side of the read word line 103 (RWL) away from the substrate 100 , and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the read word line 103 (RWL) on the substrate 100 , and is insulated from the read word line 103 (RWL);

The second transistor T2 further includes a second semiconductor layer 104, which is located on a side of the read bit line 110b away from the substrate 100 and connected to the read bit line 110b, and the second semiconductor layer 104 extends in a direction perpendicular to the substrate 100 and is connected to a reference potential terminal. The reference potential terminal may be the substrate 100 (as shown in FIG. 21a ) or a separate reference potential terminal 121 (as shown in FIG. 21b and FIG. 21c ).

The third gate 106 is located on a side of the second semiconductor layer 104 away from the substrate 100 , and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the second semiconductor layer 104 on the substrate 100 , and is insulated from the second semiconductor layer 104 .

The second transistor T2 further includes a second gate insulating layer 105 and a second gate dielectric layer 122;

The second gate dielectric layer 122 is located between the read word line 103 (RWL) and the second semiconductor layer 104 . The second gate insulating layer 105 is located between the third gate 106 and the second semiconductor layer 104 , and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the second semiconductor layer 104 on the substrate.

Optionally, the second transistor T2 further includes a third electrode, a fourth electrode and a fourth gate; the reference potential terminal 121 (Vrefn) serves as the third electrode of the second transistor T2, the read bit line 110b serves as the fourth electrode of the second transistor T2, and the read word line 103 (RWL) serves as the fourth gate of the second transistor T2. In this way, the structure of the memory cell 10 can be further simplified and the integration of the memory can be improved.

The first write bit line 110a and the read bit line 110b are connected by a lead line BL1 at the periphery of the memory array structure. Inside the memory array structure, the first write bit line 110a and the read bit line 110b are two separate bit lines.

Alternatively, as shown in FIG. 21 c , the position of the read bit line 110 b and the position of the reference potential terminal 121 (Vrefn) may be interchanged.

In some embodiments, the first transistor T1 is a write transistor, and the second transistor T2 is a read transistor; the material of the first semiconductor layer of the first transistor T1 includes indium gallium zinc oxide. Alternatively, the material of the first semiconductor layer includes other oxide semiconductor materials with similar properties. The use of indium gallium zinc oxide can reduce the leakage of the first transistor T1.

Based on the same inventive concept, the present disclosure provides a method for manufacturing a memory, including:

A second transistor is formed on one side of the substrate by a patterning process; and a third gate of the second transistor is configured as a storage node (SN) of the storage unit; the first transistor includes a first electrode, the second electrode, a first gate and a second gate; the third gate reuses the second electrode;

A first write bit line (WBL1/BL1), a first semiconductor layer, a first gate insulating layer, a second write bit line (WBL2/BL2), a first gate dielectric layer and a write word line (WWL) are sequentially formed on a side of the third gate away from the substrate through a patterning process, wherein the write word line serves as the first gate; the second write bit line serves as the second gate; and the first write bit line serves as the first electrode.

The manufacturing method of the memory provided by the embodiment of the present disclosure is relatively simple. By first manufacturing the second transistor and then manufacturing the first transistor, that is, the first transistor and the second transistor are arranged vertically, it can be more compact in space, save area, and facilitate high-density integration and manufacturing.

In some embodiments, only as an example, the memory structure shown in FIG. 20 is described in detail below in conjunction with FIGS. 22a-29b in detail. The patterning process of the embodiment of the present disclosure includes This includes part or all of the processes of deposition, lithography, etching and planarization.

Specifically, as shown in FIG. 22a and FIG. 22b, FIG. 22a and FIG. 22b are side views and top views of the manufacturing process of the memory, respectively. A metal film may be formed on one side of the substrate 100, and then a portion of the metal film may be removed by etching in the patterning process to form a read bit line 102 (RBL). Afterwards, a dielectric layer is deposited on one side of the substrate 100 and planarized to form a first dielectric layer 101.

As shown in Figure 23a and Figure 23b, Figure 23a and Figure 23b are respectively a side view and a top view of the manufacturing process of the memory. A read word line 103 (RWL) is formed on a side of the first dielectric layer 101 away from the substrate 100 by a patterning process.

As shown in Figure 24a and Figure 24b, Figure 24a and Figure 24b are respectively a side view and a top view of the manufacturing process of the memory, a first receiving hole 115 penetrating the first dielectric layer 101 and the read word line 103 (RWL) is formed by a patterning process.

As shown in Figure 25a and Figure 25b, Figure 25a and Figure 25b are respectively a side view and a top view of the manufacturing process of the memory. The second semiconductor layer 104, the second gate insulating layer 105 and the third gate 106 are formed in sequence through a patterning process.

As shown in Figure 26a and Figure 26b, Figure 26a and Figure 26b are respectively a side view and a top view of the manufacturing process of the memory. A second dielectric layer 107 and a first sacrificial layer 116 are sequentially formed on the side of the third gate 106 away from the substrate 100 by a patterning process.

As shown in Figure 27a and Figure 27b, Figure 27a and Figure 27b are respectively a side view and a top view of the memory manufacturing process. A third dielectric layer 109 and a first write bit line 110 (WBL1) are sequentially formed on the side of the first sacrificial layer 116 away from the substrate 100 by a patterning process.

As shown in Figure 28a and Figure 28b, Figure 28a and Figure 28b are respectively a side view and a top view of the manufacturing process of the memory, a second receiving hole 117 penetrating the first write bit line 110 (WBL1), the first sacrificial layer 116 and the second dielectric layer 107 is formed by a patterning process.

As shown in Figure 29a and Figure 29b, Figure 29a and Figure 29b are respectively a side view and a top view of the manufacturing process of the memory. The first sacrificial layer 116 is completely removed and the third dielectric layer 109 is partially removed by the etching step in the patterning process, and then the first semiconductor layer 112, the first gate insulating layer 113, the second write bit line 114 (WBL2), the first gate dielectric layer 111, and the write word line 108 (WWL) are sequentially formed by the patterning process.

In some embodiments, the memory structure shown in Figure 21a is described in detail below in conjunction with Figures 30a-37b in detail. The patterning process in the embodiment of the present disclosure includes part or all of the processes of deposition, photolithography, etching and planarization.

Specifically, as shown in Figure 30a and Figure 30b, Figure 30a and Figure 30b are respectively a side view and a top view of the memory manufacturing process. The substrate 100 is used as a reference potential terminal Vrefn. A first dielectric layer 101 and a second sacrificial layer 125 are sequentially formed on one side of the substrate 100.

As shown in Figures 31a and 31b, which are respectively a side view and a top view of the manufacturing process of the memory, a fourth dielectric layer 123 is formed on the side of the second sacrificial layer 125 away from the substrate, and a read bit line 110b (BL1) and a fifth dielectric layer 124 are formed on the side of the fourth dielectric layer 123 away from the substrate 100 through a patterning process.

As shown in FIG. 32a and FIG. 32b, FIG. 32a and FIG. 32b are respectively a side view and a top view of the manufacturing process of the memory. The patterning process forms a through-read bit line 110b (BL1), a fourth dielectric layer 123, a second sacrificial layer 125 and the third receiving hole 126 of the first dielectric layer 101 .

As shown in Figures 33a and 33b, Figures 33a and 33b are respectively a side view and a top view of the manufacturing process of the memory. The second sacrificial layer 125 is completely removed by the etching step in the patterning process, and the corresponding dielectric layer is partially removed. After that, the second semiconductor layer 104, the second gate insulating layer 105, the third gate 106, the second gate dielectric layer 122 and the read word line 103 are sequentially formed by the patterning process.

As shown in Figure 34a and Figure 34b, Figure 34a and Figure 34b are respectively a side view and a top view of the manufacturing process of the memory. A second dielectric layer 107 and a second sacrificial layer 127 are sequentially formed on a side of the third gate 106 away from the substrate.

As shown in Figure 35a and Figure 35b, Figure 35a and Figure 35b are respectively a side view and a top view of the manufacturing process of the memory. A third dielectric layer 109 and a first write bit line 110a (BL1) are sequentially formed on the side of the second sacrificial layer 127 away from the substrate 100 by a patterning process.

As shown in Figure 36a and Figure 36b, which are respectively a side view and a top view of the manufacturing process of the memory, a fourth receiving hole 128 penetrating the first write bit line 110a (BL1), the second sacrificial layer 127 and the second dielectric layer 107 is formed by a patterning process.

As shown in Figures 37a and 37b, Figures 37a and 37b are respectively a side view and a top view of the manufacturing process of the memory. The second sacrificial layer 127 is completely removed and the third dielectric layer 109 is partially removed by the etching step in the patterning process. After that, the first semiconductor layer 112, the first gate insulating layer 113, the second write bit line 114 (BL2), the first gate dielectric layer 111, and the write word line 108 (WWL) are sequentially formed by the patterning process.

In another embodiment, as shown in Figure 38, in Figure 38, BL1_1, BL1_2, BL1_3, ..., BL1_n represent the first, second, ..., third, and nth first bit line BL1, respectively; BL2_1, BL2_2, BL2_3, ..., BL2_n represent the first, second, ..., third, and nth second bit line BL2, respectively; WL1, WL2, WL3, ..., WLm represent the first, second, third, ..., mth word line WL, respectively; m and n are both greater than 1.

As shown in FIG. 39 a and FIG. 39 b , the memory cell 10 includes: a first transistor T1, a second transistor T2 and a capacitor C;

The first transistor T1 includes a first electrode 102 , a second electrode 106 and a first gate electrode 104 ; the second transistor T2 includes a third electrode, a fourth electrode 113 and a second gate electrode 111 ; the capacitor C includes a fifth electrode 118 and a sixth electrode 120 which are insulated from each other.

The first electrode 102 of the first transistor T1 is electrically connected to the first bit line BLI, the second electrode 106 of the first transistor T1 is electrically connected to the third electrode of the second transistor T2, the fourth electrode 113 of the second transistor T2 is electrically connected to the fifth electrode 118 of the capacitor C, and the sixth electrode 120 of the capacitor C is used to receive a reference signal.

As shown in Fig. 39a, the first gate 104 of the first transistor T1 is electrically connected to the second bit line BL2, and the second gate 111 of the second transistor T2 is electrically connected to the word line WL. Alternatively, as shown in Fig. 39b, the first gate 104 of the first transistor T1 is electrically connected to the word line WL, and the second gate 111 of the second transistor T2 is electrically connected to the second bit line BL2.

It should be noted that the first transistor T1 and the second transistor T2 in the embodiment of the present disclosure can be N-type transistors or P-type transistors, which is not limited in the present disclosure. The principle of the storage device is explained below.

The memory cell 10 in the embodiment of the present disclosure includes two transistors connected in series, namely, a first transistor T1 and a second transistor T2 connected in series. As shown in FIG39a, the first gate 104 of the first transistor T1 is electrically connected to the second bit line BL2, and the second gate 111 of the second transistor T2 is electrically connected to the word line WL. As shown in FIG39b, the first gate 104 of the first transistor T1 is electrically connected to the word line WL, and the second gate 111 of the second transistor T2 is electrically connected to the second bit line BL2.

As shown in Figures 39a, 29b and 40, in the two transistors in the embodiment of the present disclosure, the gate of one transistor is electrically connected to the word line WL, and the gate of the other transistor is electrically connected to the second bit line BL2. By loading the voltage on the word line WL and the second bit line BL2, the gates of the two transistors receive different bias voltages, thereby controlling the conduction and cutoff of the two transistors.

For n-type transistors, when a suitable voltage is applied to the word line WL controlling the gate electrode in the same row and a lower voltage is applied to the second bit line BL2, each memory cell is turned off.

In FIG40 , BL2 “high” indicates that BL2 is at a high level, BL2 “low” indicates that BL2 is at a low level, “unselected WL” indicates that WL is not activated or not selected, and WL is at a low level, and “selected WL” indicates that WL is activated or selected, and WL is at a high level. The ordinate axis I indicates the current flowing through the first transistor T1 and the second transistor T2, and the abscissa axis V indicates the voltage of the word line WL.

For n-type transistors, in combination with FIG. 39a, FIG. 39b and FIG. 40, when the second bit line BL2 is at a low level and the word line WL is at a low level, the first transistor T1 and the second transistor T2 are both turned off; when the second bit line BL2 is at a low level and the word line WL is at a high level, the first transistor T1 is turned off and the second transistor T2 is turned on; when the second bit line BL2 is at a high level and the word line WL is at a low level, the first transistor T1 is turned on and the second transistor T2 is turned off. Therefore, when at least one of the second bit line BL2 and the word line WL is at a low level, the current flowing through the first transistor T1 and the second transistor T2 is 0. When the second bit line BL2 and the word line WL are at a high level, the first transistor T1 and the second transistor T2 in the storage unit are both loaded with a high level, and the first transistor T1 and the second transistor T2 are both turned on (as shown in the curve of FIG. 40); therefore, only when the word line WL and the second bit line BL2 are both at a high level, the first transistor T1 and the second transistor T2 in the storage unit will be turned on, and the memory can be accessed.

The disclosed embodiment provides a new memory, which includes at least one memory array, a plurality of word lines WL, a plurality of first bit lines BLI and a plurality of second bit lines BL2; the memory array includes a plurality of memory cells 10, and the memory cell 10 includes two transistors connected in series and a capacitor. Through the second bit line BL2 and the word line WL, the conduction and cutoff of the two transistors are controlled respectively, and during the read or write operation, any one or some memory cells can be selected, so that charge sharing, signal sensing and amplification operations are performed only in the selected memory cells, and other unselected memory cells are all in a closed state, so that power consumption can be reduced.

In addition, when writing data, traditional 1T1C memory usually reads first and then writes, that is, the read operation must be performed first. However, when the memory provided by the embodiment of the present disclosure is used, since the transistors in the unselected storage cells remain in the off state during the write operation, the data in the unselected storage cells will not be destroyed, and the write operation can be performed directly without the need for the read and amplification operations before the write operation, thereby facilitating the improvement of the data writing speed and the reduction of power consumption.

In some embodiments, multiple memory cells 10 in a memory array form multiple memory cell rows and multiple memory cell columns; each memory cell 10 in each memory cell row is electrically connected to a word line WL; each memory cell 10 in each memory cell column is electrically connected to a first bit line BL1 (BL1_1, BL1_2, BL1_3, ..., BL1_n) and a second bit line BL2 (BL2_1, BL2_2, BL2_3, ..., BL2_n).

The multiple memory cells 10 in the memory array are distributed in an array. For a row of memory cells, different second bit lines BL2 and the same word line WL connected to each memory cell are used to control the on and off of the two transistors respectively. During the read or write operation, any one or some memory cells can be selected, so that charge sharing, signal sensing and amplification operations are performed only in the selected memory cells, and other unselected memory cells are in a closed state, thereby reducing power consumption.

As shown in FIG38 , through the second bit line BL2_2 and the word line WL3, only the memory cell 10 in the dotted circle is selected, and the read or write operation can be directly performed on the memory cell 10. In this case, only the first bit line BL1_2 will undergo the charging and discharging process, perform signal sensing and amplification, and other unselected memory cells are in a closed state, thereby reducing power consumption. In the read or write operation of the traditional 1T1C memory, all memory cells associated with the selected WL need to share charges, and all BLs need to perform signal sensing and amplification.

In some examples, several columns can be read or written in parallel by selecting several second bit lines BL2 and one word line WL. For example, three second bit lines (BL2_1, BL2_2, BL2_3) and one word line (WL3) can be selected to read or write data in parallel to three columns.

In some embodiments, the first transistor T1 is located on one side of the substrate 100; the second transistor T2 is located on a side of the first transistor T1 away from the substrate 100; and the capacitor C is located on a side of the second transistor T2 away from the substrate 100. Specifically, the first transistor T1 is located on one side of the substrate 100; the second transistor T2 is located on the first transistor T1; the capacitor C is located on the second transistor T2, and the capacitor C, the second transistor T2, and the first transistor T1 are stacked in a direction perpendicular to the substrate 100.

The first transistor, the second transistor and the capacitor of the memory cell provided in the embodiment of the present disclosure are arranged up and down, that is, the second transistor is located above the first transistor, and the capacitor is located above the second transistor, which can achieve more compact space, save area, and facilitate high-density integration and manufacturing. The transistor and capacitor of the conventional 1T1C memory cell are arranged side by side, that is, the capacitor is arranged next to the transistor, which is relatively wasteful in terms of area.

Optionally, as shown in FIG. 41 , the second transistor T2 is located directly above the first transistor T1 , and the capacitor C is located directly above the second transistor T2 , which can achieve a more compact space, save area, and facilitate high-density integration and manufacturing.

In some embodiments, as shown in FIG41 , the first transistor T1 further includes a first semiconductor layer 108 ;

A first electrode 102, located on one side of the substrate 100;

A first gate 104 is located on a side of the first electrode 102 away from the substrate 100 , and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the first electrode 102 on the substrate 100 , and is insulated from the first electrode 102 ;

The second electrode 106 is located on a side of the first gate 104 away from the substrate 100 , and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the first electrode 102 on the substrate 100 , and is insulated from the first gate 104 ;

The first semiconductor layer 108 is located on a side of the second electrode 106 away from the substrate 100 and connected to the second electrode 106 . The first semiconductor layer 108 extends in a direction perpendicular to the substrate 100 to connect to the first electrode 102 and is insulated from the first gate 104 .

The first transistor T1 provided in the embodiment of the present disclosure has a simple structure, which is conducive to high-density integration and manufacturing.

In some embodiments, as shown in FIG. 41 , the first transistor T1 further includes a first gate dielectric layer 107 and a first filling layer 109 ;

A first gate dielectric layer 107 , located between the first gate 104 and the first semiconductor layer 108 ;

The orthographic projection of the first filling layer 109 on the substrate 100 is located within the orthographic projection of the first semiconductor layer 108 on the substrate 100 , and the orthographic projection of the first filling layer 109 on the substrate 100 does not overlap with the orthographic projection of the second electrode 106 on the substrate 100 .

In some embodiments, the second transistor T2 further includes a second semiconductor layer 115;

A third electrode, multiplexing the second electrode 106 of the first transistor;

The second gate 111 is located at a side of the first semiconductor layer 108 away from the substrate 100 , and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the second electrode 106 on the substrate 100 , and is insulated from the second electrode 106 ;

The fourth electrode 113 is located on a side of the second gate 111 away from the substrate 100 , and its orthographic projection on the substrate 100 overlaps with the orthographic projection of the second electrode 106 on the substrate 100 , and is insulated from the second gate 111 ;

The second semiconductor layer 115 is located on a side of the first semiconductor layer 108 away from the substrate 100 and connected to the fourth electrode 113 . The second semiconductor layer 115 extends in a direction perpendicular to the substrate 100 to connect to the first semiconductor layer 108 and is insulated from the second gate 111 .

The second transistor T2 provided in the embodiment of the present disclosure has a simple structure, which is conducive to high-density integration and manufacturing.

In some embodiments, the second transistor T2 further includes a second gate dielectric layer 114 and a second filling layer 116;

The second gate dielectric layer 114 is located between the second gate 111 and the second semiconductor layer 115;

The orthographic projection of the second filling layer 116 on the substrate 100 is located within the orthographic projection of the second semiconductor layer 115 on the substrate 100 , and the orthographic projection of the second filling layer 116 on the substrate 100 does not overlap with the orthographic projection of the fourth electrode 113 on the substrate 100 .

In some embodiments, the capacitor C further includes a capacitor dielectric layer 119; the fifth electrode 118 and the sixth electrode 120 are insulated by the capacitor dielectric layer 119;

The fifth electrode 118 is located on a side of the fourth electrode 113 and the second semiconductor layer 115 away from the substrate 100, and is connected to both the second semiconductor layer 115 and the fourth electrode 113, and its orthographic projection on the substrate 100 is located within the orthographic projection of the capacitor dielectric layer 119 on the substrate 100;

The capacitor dielectric layer 119 is located on a side of the fifth electrode 118 away from the substrate 100;

The sixth electrode 120 is located on a side of the capacitor dielectric layer 119 away from the substrate 100 , and its orthographic projection on the substrate 100 is located within the orthographic projection of the capacitor dielectric layer 119 on the substrate 100 .

In some embodiments, the first electrode 102 is a part of the first bit line BL1 (the first electrode and the first bit line BL1 are both labeled with “102”), and the sixth electrode 120 reuses the reference potential terminal Vrefn (the sixth electrode and the reference potential terminal are both labeled with “120”);

The first gate 104 is a part of the second bit line BL2 (the first gate and the second bit line BL2 are both marked with “104”), and the second gate 111 is a part of the word line WL (the second gate and the word line WL are both marked with “111”);

Alternatively, the first gate 104 is a part of the word line WL (the first gate and the word line WL are both labeled “104”), and the second gate 111 is a part of the second bit line BL2 (the second gate and the second bit line BL2 are both labeled “111”).

This embodiment can further simplify the structure of the storage unit 10 and improve the integration of the memory.

It should be noted that the first electrode 102 and the first bit line BL1 , the sixth electrode 120 and the reference potential terminal Vrefn, the first gate 104 and the second bit line BL2 , and the second gate 111 and the word line WL may also be separately provided and connected, which is not limited in the present disclosure.

Optionally, the material of the first semiconductor layer and the second semiconductor layer includes indium gallium zinc oxide (IGZO). Alternatively, the material of the semiconductor layer includes other oxide semiconductor materials with similar properties. The use of indium gallium zinc oxide can reduce transistor leakage. Of course, the material of the first semiconductor layer and the second semiconductor layer can also be other semiconductor materials, which is not limited in the present disclosure.

Based on the same inventive concept, an embodiment of the present disclosure provides a method for manufacturing a memory, wherein the memory includes at least one memory array, a plurality of word lines, a plurality of first bit lines, and a plurality of second bit lines; the memory array includes a plurality of memory cells; the memory cell includes: a first transistor, a second transistor, and a capacitor; as shown in FIG42 , the manufacturing method includes:

S1: forming a first transistor, a first bit line, and a second bit line on one side of a substrate through a patterning process; forming a second transistor and a word line on a side of the first transistor away from the substrate, and the first transistor is electrically connected to the second transistor; or forming a first transistor, a first bit line, and a word line on one side of a substrate; forming a second transistor and a second bit line on a side of the first transistor away from the substrate, and the first transistor is electrically connected to the second transistor;

S2: A capacitor and a reference potential terminal are formed on a side of the second transistor away from the substrate through a patterning process, and the capacitor is electrically connected to the second transistor.

The manufacturing method of the memory provided by the embodiment of the present disclosure is relatively simple. The first transistor, the first bit line and the second bit line, as well as the second transistor and the word line are first manufactured, and then the capacitor and the reference potential terminal are manufactured. That is, the two transistors and the capacitor connected in series of the storage unit are arranged in an upper and lower manner, that is, the second transistor is located above the first transistor, and the capacitor is located above the second transistor. This can achieve a more compact space, save area, and facilitate high-density integration and manufacturing.

The following describes in detail the manufacturing process of a memory in one embodiment of the present disclosure in conjunction with Figures 43a to 50b. The patterning process in the embodiment of the present disclosure includes part or all of the processes of deposition, photolithography, etching and planarization.

In some embodiments, forming a first transistor, a first bit line, and a second bit line on one side of a substrate includes:

forming a first electrode and a first bit line on one side of the substrate;

A second electrode, a first semiconductor layer, a first filling layer, a first gate dielectric layer, a first gate and a second bit line are sequentially formed on a side of the first electrode and the first bit line away from the substrate;

and forming a first transistor, a first bit line and a word line on one side of the substrate, comprising:

forming a first electrode and a first bit line on one side of the substrate;

A second electrode, a first semiconductor layer, a first filling layer, a first gate dielectric layer, a first gate and a word line are sequentially formed on a side of the first electrode and the first bit line away from the substrate.

Specifically, as shown in FIG. 43a and FIG. 43b, FIG. 43a and FIG. 43b are side views and top views of the manufacturing process of the memory, respectively. A metal film can be formed on one side of the substrate 100, and then a portion of the metal film is removed by an etching step in the patterning process to form a first electrode 102. Thereafter, a dielectric layer is deposited on one side of the first electrode 102 and planarized to form a first dielectric layer 101. The first electrode 102 is a portion of the first bit line BL1 (the first electrode and the first bit line BL1 are both marked with "102").

As shown in Figure 44a and Figure 44b, Figure 44a and Figure 44b are respectively a side view and a top view of the manufacturing process of the memory. A first sacrificial layer 121 and a second dielectric layer 103 are formed on a side of the first dielectric layer 101 away from the substrate 100 by a patterning process.

As shown in Figure 45a and Figure 45b, which are respectively a side view and a top view of the memory manufacturing process, a second dielectric layer 103, a second electrode 106 and a first receiving hole 122 are formed on a side of the first sacrificial layer 121 away from the substrate 100 by a patterning process.

As shown in Figure 46a and Figure 46b, Figure 46a and Figure 46b are respectively a side view and a top view of the manufacturing process of the memory. The first semiconductor layer 108 is formed by a patterning process.

As shown in Figures 47a and 47b, Figures 47a and 47b are respectively a side view and a top view of the manufacturing process of the memory. The first filling layer 109 is formed by a patterning process, and then the second dielectric layer 103 is partially removed and the first sacrificial layer 121 is completely removed by an etching step in the patterning process, and then the first gate dielectric layer 107 and the first gate 104 are sequentially formed by a patterning process. The first gate 104 is a part of the second bit line BL2 (the first gate and the second bit line BL2 are both marked with "104").

In some embodiments, forming a second transistor and a word line on a side of the first transistor away from the substrate includes:

A fourth electrode, a second semiconductor layer, a second filling layer, a second gate dielectric layer, a second gate and a word line are sequentially formed on a side of the first filling layer away from the substrate, and the third electrode reuses the second electrode;

And, forming a second transistor and a second bit line on a side of the first transistor away from the substrate, comprising:

A fourth electrode, a second semiconductor layer, a second filling layer, a second gate dielectric layer, a second gate and a second bit line are sequentially formed on a side of the first filling layer away from the substrate, and the third electrode reuses the second electrode.

Specifically, as shown in Figures 48a and 48b, which are respectively a side view and a top view of the manufacturing process of the memory, the fourth dielectric layer 110, the second sacrificial layer 123, the fifth dielectric layer 112, the fourth electrode 113 and the second receiving hole 124 are formed by a patterning process.

As shown in Figures 49a and 49b, Figures 49a and 49b are side views and top views of the manufacturing process of the memory, respectively. The second filling layer 116 is formed by a patterning process, and then the second sacrificial layer 123 is completely removed and the fifth dielectric layer 112 is partially removed by a patterning process etching step, and then the second gate dielectric layer 114 and the second gate 111 are formed by a patterning process. The second gate 111 is a part of the word line WL (the second gate and the word line WL are both marked with "111").

In some embodiments, forming a capacitor and a reference potential terminal on a side of the second transistor away from the substrate includes:

A fifth electrode, a capacitor dielectric layer, a sixth electrode and a reference potential terminal are sequentially formed on a side of the second filling layer away from the substrate.

Specifically, as shown in Figures 50a and 50b, Figures 50a and 50b are side views and top views of the manufacturing process of the memory, respectively. A thin film is formed on the side of the second filling layer 116 away from the substrate through a composition process, and then a portion of the metal film is removed through an etching step in the composition process. Afterwards, a dielectric layer is deposited on one side of the substrate 100 and flattened to form a sixth dielectric layer 117. Afterwards, a receiving hole is formed that passes through the above-mentioned metal film, and then a fifth electrode 118, a capacitor dielectric layer 119 and a sixth electrode 120 are formed through a composition process. The sixth electrode 120 reuses the reference potential terminal Vrefn (the sixth electrode and the reference potential terminal are both marked with "120").

A first voltage is applied to the second gate of each second transistor in a row of memory cells through a word line; a second voltage is applied to the first gate of a first transistor in a memory cell that needs to be accessed in the row of memory cells through a second bit line, so that both the first transistor and the second transistor are turned on, and a data signal is written to the memory cell through a first bit line; and a third voltage is applied to the first gate of a first transistor in a memory cell that does not need to be accessed in the row of memory cells through a second bit line, so that the first transistor is turned off.

Specifically, as shown in FIG. 38 and FIG. 39a, a first voltage (high level) is applied to the first gate 104 of the first transistor T1 through the second bit line BL2, and a second voltage (high level) is applied to the second gate 111 of the second transistor T2 through the word line WL, so that both the first transistor T1 and the second transistor T2 are turned on, and the storage unit can be accessed through the first bit line BL1, for example, a read operation or a write operation can be performed on the storage unit. During the read or write operation, the first transistor T1 and the second transistor T2 are controlled to be turned on through the second bit line BL2 and the word line WL, and any one or some storage units can be selected, so that charge sharing, signal sensing and amplification operations are performed only in the selected storage units, and other unselected storage units are in a closed state, thereby reducing power consumption.

Alternatively, a first voltage is applied to the first gate of each first transistor in a row of memory cells through a word line; a second voltage is applied to the second gate of the second transistor in the memory cell that needs to be accessed in the row of memory cells through a second bit line, so that the first transistor and the second transistor are both turned on, and a data signal is written to the memory cell through the first bit line; and a third voltage is applied to the second gate of the second transistor in the memory cell that does not need to be accessed in the row of memory cells through the second bit line, so that the second transistor is turned off.

Specifically, as shown in FIG. 39b, a first voltage (high level) is applied to the first gate 104 of the first transistor T1 through the word line WL, and a second voltage (high level) is applied to the second gate 111 of the second transistor T2 through the second bit line BL2. (high level), so that the first transistor T1 and the second transistor T2 are both turned on, and the storage cell can be accessed through the first bit line BL1, for example, a read operation or a write operation can be performed on the storage cell. During the read or write operation, the first transistor T1 and the second transistor T2 are controlled to be turned on through the second bit line BL2 and the word line WL, and any one or some storage cells can be selected, so that charge sharing, signal sensing and amplification operations are performed only in the selected storage cells, and other unselected storage cells are all in a closed state, thereby reducing power consumption.

The memory access method provided by the embodiment of the present disclosure applies appropriate voltages to the second bit line and the word line to control the on and off of the two transistors respectively, thereby controlling the first transistor and the second transistor of the memory cell that needs to be accessed to be turned on, and controlling the first transistor or the second transistor in the memory cell that does not need to be accessed to be turned off. During the read or write operation, any one or some memory cells can be selected, and the other unselected memory cells are in a closed state, thereby avoiding waste of power consumption and reducing power consumption.

In a specific implementation, the transistor in the embodiment of the present disclosure may be a metal oxide semiconductor field effect transistor (MOS), and of course, may be other types of transistors, which are not limited here. In a specific implementation, one electrode of the transistor may be a source, and the other electrode may be a drain, or one electrode of the transistor may be a drain, and the other electrode may be a source. Depending on the type of transistor and the input signal, their functions may be interchangeable, and no specific distinction is made here.

Optionally, the material of the semiconductor layer in the present disclosure includes a metal oxide semiconductor material.

Optionally, the metal in the metal oxide semiconductor material includes at least one of indium, tin, zinc, aluminum, and gallium.

In an exemplary embodiment of the present disclosure, the material of the semiconductor layer may be a material such as silicon or polysilicon with a band gap less than 2 eV, or may be a wide band gap material such as a metal oxide material with a band gap greater than 2 eV.

For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide does not exclude compounds containing other elements, such as N, Si, etc., nor does it exclude the presence of other small amounts of doping elements.

In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium gallium zinc oxide (InGaZnSn ... gallium zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium oxide (InO), tin oxide (SnO), indium gall Indium tungsten (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials, as long as the leakage current of the transistor can meet the requirements The specific settings can be adjusted according to the actual situation.

These materials have a wider band gap and a lower leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is smaller, thereby improving the operating performance of the dynamic memory.

The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

Optionally, the material of the semiconductor layer 112 includes indium gallium zinc oxide (IGZO).

It should be noted that the first direction and the second direction in the present disclosure intersect, and the first direction is perpendicular to the substrate 100. The second direction and the third direction intersect and are parallel to the substrate 100. In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is also included. The state of being greater than -5° and less than 5°. In addition, "vertical" means approximately vertical, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is also included. The state of being greater than 85° and less than 95°.

Based on the same inventive concept, an embodiment of the present disclosure provides an electronic device, which includes a memory provided in any of the above embodiments. The electronic device may include a smart phone, a computer, a tablet computer, an artificial intelligence, a wearable device or a smart mobile terminal.

The electronic device provided in the embodiment of the present disclosure has the same inventive concept and the same beneficial effects as the previous embodiments. The contents not shown in detail in the electronic device can refer to the previous embodiments and will not be repeated here. Specifically, the electronic device in the embodiment of the present disclosure can be the main memory of a computer, etc., which can be determined according to actual conditions.

The above description is only a partial implementation mode of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as the protection scope of the present disclosure.

Claims

A memory, comprising: a storage array, the storage array comprising a plurality of storage units;

The memory cell comprises at least one transistor, wherein the transistor has two gates, wherein one gate is connected to a word line, and the other gate is connected to a bit line; or the memory cell comprises two transistors connected in series, each transistor having a gate, wherein the gate of one transistor is connected to a bit line, and the gate of the other transistor is connected to a word line;

Through the signal on the bit line and the signal on the word line, the currently selected storage cell is controlled to be triggered, and other storage cells belonging to the same row are not triggered.
The memory according to claim 1, comprising: a plurality of word lines, a plurality of first bit lines and a plurality of second bit lines;

The storage unit comprises: the transistor and the capacitor;

The capacitor includes a first electrode and a second electrode insulated from each other; the transistor includes a third electrode and a fourth electrode, and the two gates include a first gate and a second gate;

The first electrode of the capacitor is used to receive a reference signal, the second electrode of the capacitor is electrically connected to the third electrode of the transistor, the fourth electrode of the transistor is electrically connected to the first bit line, the first gate of the transistor is electrically connected to the word line, and the second gate of the transistor is electrically connected to the second bit line.
The memory according to claim 2, wherein:

The plurality of memory cells in the memory array form a plurality of memory cell rows and a plurality of memory cell columns;

Each memory cell in each memory cell row is electrically connected to one word line;

Each memory cell in each of the memory cell columns is electrically connected to one of the first bit lines and one of the second bit lines;

The capacitor is located on one side of the substrate;

The transistor is located on the capacitor and is stacked with the capacitor in a direction perpendicular to the substrate.
The memory according to claim 3, wherein the capacitor further comprises a capacitor dielectric layer, and the first electrode and the second electrode are insulated from each other by the capacitor dielectric layer;

The first electrode is located on one side of the substrate;

The capacitor dielectric layer is located on a side of the first electrode away from the substrate, and an orthographic projection on the substrate overlaps with an orthographic projection of the first electrode on the substrate;

The second electrode is located on a side of the capacitor dielectric layer away from the substrate, and its orthographic projection on the substrate is located within the orthographic projection of the capacitor dielectric layer on the substrate.
The memory according to claim 4, wherein the transistor further comprises a semiconductor layer;

The third electrode is located at a side of the second electrode away from the substrate, and the third electrode is connected to the second electrode;

The first gate is located at a side of the third electrode away from the substrate and is insulated from the third electrode;

The semiconductor layer is located on the third electrode and connected to the third electrode, and the semiconductor layer extending in a direction perpendicular to the substrate and connected to the fourth electrode;

The fourth electrode is located on a side of the semiconductor layer close to the substrate;

The second gate is located at a side of the semiconductor layer away from the substrate and is insulated from the semiconductor layer;

The first gate surrounds a portion of the channel region of the semiconductor layer and is insulated from the semiconductor layer.
The memory according to claim 5, wherein

An orthographic projection of the second gate on the substrate, an orthographic projection of the semiconductor layer on the substrate, an orthographic projection of the fourth electrode on the substrate, and an orthographic projection of the third electrode on the substrate all overlap.
The memory according to claim 6, wherein the transistor further comprises a first gate insulating layer and a second gate insulating layer;

The first gate insulating layer is located between the first gate and the semiconductor layer;

The second gate insulating layer is located between the second gate and the semiconductor layer, and an orthographic projection of the second gate insulating layer on the substrate overlaps with an orthographic projection of the semiconductor layer on the substrate.
The memory according to claim 7, wherein:

The first electrode serves as a reference potential terminal, or the first electrode is connected to a separate reference potential terminal, and the reference potential terminal receives the reference signal.
The memory according to claim 7, wherein the first gate is a part of the word line, or the first gate is arranged in the same layer as the word line and is connected;

The second gate is a part of the second bit line, or the second gate is arranged in the same layer as and connected to the second bit line;

The fourth electrode is a part of the first bit line, or the fourth electrode is disposed in the same layer as and connected to the first bit line.
The memory according to claim 1, wherein

The memory cell comprises a first transistor and a second transistor; the first transistor is a write transistor, the second transistor is a read transistor; the first transistor has two gates;

Wherein, the first transistor includes a first electrode, a second electrode, a first gate and a second gate; the second transistor includes at least a third gate;

The first electrode is connected to a first write bit line; the second electrode is connected to the third gate, and the third gate is configured as a storage node of the memory cell;

The first gate is connected to a write word line, and the second gate is connected to a second write bit line.
The memory according to claim 10, wherein

The second transistor has a gate; the second transistor also includes a third electrode and a fourth electrode; the third electrode is connected to the read bit line, and the fourth electrode is connected to the read word line;

The plurality of storage units are distributed in an array;

The first gates of the first transistors in a row of memory cells are connected to a write word line, the second gates of the first transistors are connected to different second write bit lines, and the first electrodes of the first transistors are connected to different second write bit lines. A first write bit line connection;

The third electrodes of the second transistors in a row of memory cells are connected to different read bit lines, and the fourth electrodes of the second transistors are connected to one read word line.
The memory according to claim 10, wherein

The second transistor has two gates; the second transistor also includes a third electrode, a fourth electrode and a fourth gate; the third electrode is connected to the reference potential terminal, the fourth electrode is connected to the read bit line, and the fourth gate is connected to the read word line;

The plurality of storage units are distributed in an array;

The first gates of the first transistors in a row of memory cells are connected to a write word line, the second gates of the first transistors are connected to different second write bit lines, and the first electrodes of the first transistors are connected to different first write bit lines;

The third electrode of each second transistor in a row of storage cells is connected to the reference potential terminal, the fourth electrode of each second transistor is connected to the read bit line, and the fourth gate of each second transistor is connected to a read word line.
The memory according to claim 12, wherein

Inside the array structure of the memory, the read bit line and the first write bit line are two separate bit lines;

At the periphery of the array structure of the memory, the read bit line is connected to the first write bit line through a lead line.
The memory according to claim 10, wherein the memory cell comprises a first transistor and a second transistor connected;

The second transistor is located at one side of the substrate; and the third gate of the second transistor is configured as a storage node of the memory cell;

The first transistor is located at a side of the second transistor away from the substrate; the third gate of the second transistor reuses the second electrode of the first transistor;

A write word line, located at a side of the third gate away from the substrate and insulated from the third gate;

A first write bit line, located at a side of the write word line away from the substrate, and having an orthographic projection on the substrate overlapping with an orthographic projection of the write word line on the substrate, and insulated from the write word line;

The first transistor further includes a first semiconductor layer, which is located on a side of the first write bit line away from the substrate and connected to the first write bit line, and the first semiconductor layer extends in a direction perpendicular to the substrate and is connected to the third gate and is insulated from the write word line;

The second write bit line is located on a side of the first semiconductor layer away from the substrate, and its orthographic projection on the substrate overlaps with the orthographic projection of the first semiconductor layer on the substrate, and is insulated from the first semiconductor layer.
The memory according to claim 14, wherein the first transistor further comprises: a first gate insulating layer and a first gate dielectric layer;

The first gate dielectric layer is located between the write word line and the first semiconductor layer;

The first gate insulating layer is located between the second write bit line and the first semiconductor layer, and The orthographic projection on the substrate overlaps with the orthographic projection of the first semiconductor layer on the substrate.
The memory according to any one of claims 14-15, wherein the first transistor comprises a first electrode, the second electrode, a first gate and a second gate; the second transistor comprises the third gate; the first transistor is a write transistor, and the second transistor is a read transistor;

The first gate serves as a part of the write word line;

The second gate serves as a part of the second write bit line;

The first electrode serves as a part of the first write bit line.
The memory according to claim 1, comprising: a plurality of word lines, a plurality of first bit lines and a plurality of second bit lines;

The storage unit includes: a first transistor, a second transistor and a capacitor;

The first transistor includes a first electrode, a second electrode and a first gate; the second transistor includes a third electrode, a fourth electrode and a second gate, and the capacitor includes a fifth electrode and a sixth electrode;

The first electrode of the first transistor is electrically connected to the first bit line, the second electrode of the first transistor is electrically connected to the third electrode of the second transistor, the fourth electrode of the second transistor is electrically connected to the fifth electrode of the capacitor, and the sixth electrode of the capacitor is used to receive a reference signal;

The first gate of the first transistor is electrically connected to the second bit line, and the second gate of the second transistor is electrically connected to the word line; or the first gate of the first transistor is electrically connected to the word line, and the second gate of the second transistor is electrically connected to the second bit line.
The memory according to claim 17, wherein:

The plurality of memory cells in the memory array form a plurality of memory cell rows and a plurality of memory cell columns;

Each memory cell in each memory cell row is electrically connected to one word line;

Each memory cell in each of the memory cell columns is electrically connected to one of the first bit lines and one of the second bit lines.
The memory according to claim 17, wherein:

The first transistor is located at one side of the substrate;

The second transistor is located on the first transistor;

The capacitor is located on the second transistor, and is stacked with the second transistor and the first transistor in a direction perpendicular to the substrate.
The memory according to claim 19, wherein the first transistor further comprises a first semiconductor layer;

The first electrode is located on one side of the substrate;

The first gate is located on a side of the first electrode away from the substrate, and its orthographic projection on the substrate overlaps with the orthographic projection of the first electrode on the substrate, and is insulated from the first electrode;

The second electrode is located on a side of the first gate away from the substrate, and its orthographic projection on the substrate overlaps with the orthographic projection of the first electrode on the substrate, and is insulated from the first gate;

The first semiconductor layer is located on a side of the second electrode away from the substrate and is adjacent to the second electrode. The first semiconductor layer is connected to the first electrode and extends along a direction perpendicular to the substrate, and is insulated from the first gate.
The memory according to claim 20, wherein the first transistor further comprises a first gate dielectric layer and a first filling layer;

The first gate dielectric layer is located between the first gate and the first semiconductor layer;

The orthographic projection of the first filling layer on the substrate is located within the orthographic projection of the first semiconductor layer on the substrate, and the orthographic projection of the first filling layer on the substrate does not overlap with the orthographic projection of the second electrode on the substrate.
The memory according to claim 21, wherein the second transistor further comprises a second semiconductor layer;

The third electrode reuses the second electrode of the first transistor;

The second gate is located on a side of the first semiconductor layer away from the substrate, and its orthographic projection on the substrate overlaps with the orthographic projection of the second electrode on the substrate, and is insulated from the second electrode;

The fourth electrode is located on a side of the second gate away from the substrate, and its orthographic projection on the substrate overlaps with the orthographic projection of the second electrode on the substrate, and is insulated from the second gate;

The second semiconductor layer is located on a side of the first semiconductor layer away from the substrate and connected to the fourth electrode. The second semiconductor layer extends in a direction perpendicular to the substrate to connect to the first semiconductor layer and is insulated from the second gate.
The memory according to claim 22, wherein the second transistor further comprises a second gate dielectric layer and a second filling layer;

The second gate dielectric layer is located between the second gate and the second semiconductor layer;

The orthographic projection of the second filling layer on the substrate is located within the orthographic projection of the second semiconductor layer on the substrate, and the orthographic projection of the second filling layer on the substrate does not overlap with the orthographic projection of the fourth electrode on the substrate.
The memory according to claim 23, wherein the capacitor further comprises a capacitor dielectric layer; the fifth electrode and the sixth electrode are insulated from each other by the capacitor dielectric layer;

The fifth electrode is located on a side of the fourth electrode and the second semiconductor layer away from the substrate, and is connected to both the second semiconductor layer and the fourth electrode, and an orthographic projection of the fifth electrode on the substrate is located within an orthographic projection of the capacitor dielectric layer on the substrate;

The capacitor dielectric layer is located on a side of the fifth electrode away from the substrate;

The sixth electrode is located on a side of the capacitor dielectric layer away from the substrate, and its orthographic projection on the substrate is located within the orthographic projection of the capacitor dielectric layer on the substrate.
The memory according to claim 24, wherein

The first electrode is a part of the first bit line, and the sixth electrode reuses the reference potential terminal;

The first gate is a part of the second bit line, and the second gate is a part of the word line; or the first gate is a part of the word line, and the second gate is a part of the second bit line.
An electronic device, comprising a memory as described in any one of claims 1 to 25.