WO2024093407A1 - Time delay circuit and storage system - Google Patents

Abstract

Disclosed are a time delay circuit and a storage system. The time delay circuit comprises: a temperature measurement module, which is configured to measure, when a memory array is in a refresh mode, the temperature of the memory array before the memory array receives an activation command, and to output a first encoded signal; and a delay module, which is configured to receive a first signal and delay the first signal on the basis of the first encoded signal, so as to generate and output a second signal, wherein the second signal is used for controlling the compensation duration of mismatch compensation performed on a sense amplifier, the delay amount of the second signal relative to the first signal corresponds to the first encoded signal, the higher the temperature of the memory array that is represented by the first encoded signal, the smaller the delay amount, and the first signal is sent to the delay module when a fixed duration has elapsed after the memory array receives the activation command.

Description

Delay circuit and storage system

cross reference

This application claims priority to the Chinese patent application entitled “Delay Circuit and Storage System” and application number 202211350854.3, filed on October 31, 2022, which is incorporated herein by reference in its entirety.

Technical Field

The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a delay circuit and a storage system.

Background technique

Semiconductor memories are divided into volatile memory devices and non-volatile memory devices. Volatile memory devices lose the data stored therein when the power supply voltage is turned off, such as static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc.; non-volatile memory devices retain the data stored therein even when the power supply voltage is turned off, such as read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM) and ferroelectric RAM (FRAM).

The sense amplifier (SA) is an important component of semiconductor memory. Its main function is to amplify the small signal on the bit line and then perform data reading and writing operations. The sense amplifier can eliminate the noise caused by the manufacturing differences of transistors in the semiconductor memory, so that the semiconductor memory can store data accurately. When the sense amplifier works in the mismatch compensation stage, the compensation time will affect the mismatch compensation effect.

Summary of the invention

The embodiments of the present disclosure provide a delay circuit and a storage system, which are at least beneficial to improving the mismatch compensation effect under different temperature conditions in a refresh mode.

According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a delay circuit, which is applied to a storage system, wherein the storage system includes a memory array and a sensitive amplifier connected to the memory array, and is characterized in that it includes: a temperature detection module, configured to, when the memory array is in a refresh mode, detect the temperature of the memory array before receiving an activation command, and output a first coded signal, wherein the first coded signal is used to characterize the temperature of the memory array; a delay module, configured to receive a first signal, and delay the first signal based on the first coded signal to generate and output a second signal, wherein the second signal is used to control the compensation time length of the mismatch compensation performed by the sensitive amplifier, the sensitive amplifier is connected to the memory array, the delay amount of the second signal compared to the first signal corresponds to the first coded signal, and the higher the temperature of the memory array represented by the first coded signal, the smaller the delay amount, and the first signal is sent to the delay module after the fixed time length of the memory array receiving the activation command.

In some embodiments, the delay module includes: N cascaded selectors; the selector at the first stage is used to receive the A first signal, in response to the first coded signal, directly outputs the first signal, or delays the first signal by a first preset delay amount to obtain a first delayed signal, and outputs the first delayed signal; the input end of the nth selector is connected to the output end of the n-1th selector, the nth selector is used to respond to the first coded signal, directly output the n-1th delayed signal output from the output end of the n-1th selector, or delays the n-1th delayed signal by an nth preset delay amount to obtain an nth delayed signal, and output the nth delayed signal, n is a natural number greater than or equal to 2, N is a natural number greater than or equal to 2, and n is less than or equal to N; wherein, the first coded signal includes N first sub-coded signals, and each of the selectors receives a corresponding first sub-coded signal.

In some embodiments, the selector includes: a delay circuit, configured to receive an input signal, delay the input signal by a preset delay amount, obtain a delayed signal, and output the delayed signal; a selection circuit, configured to receive the input signal and the delayed signal, and in response to the corresponding first sub-coding signal, select and output one of the received input signal or the delayed signal; wherein the first signal is the input signal received by the selector at the first stage, and the first delayed signal is the delayed signal output by the selector at the first stage; the n-1th delayed signal is the input signal received by the nth selector, and the nth delayed signal is the delayed signal output by the nth selector.

In some embodiments, the preset delay amount of the selector at the previous stage is smaller than the preset delay amount of the selector at the next stage.

In some embodiments, the first coded signal includes a normal state and a shielding state; the delay module also includes: a selection unit, configured to receive the first signal and the first coded signal, and in response to the first coded signal in the shielding state, shield the first signal and generate and output an internal signal to replace the first signal, and in response to the first coded signal in the normal state, output the first signal.

In some embodiments, the selection unit includes: an AND gate, each input end of the AND gate receives N first sub-coding signals respectively, and if the N first sub-coding signals indicate that the first coding signal is in a shielding state, the internal signal is generated and output; an input circuit, one input end of the input circuit receives the first signal, and the other input end is connected to the output end of the AND gate, and the output end of the input circuit is connected to the input end of the selector at the first stage, and is configured such that if the N first sub-coding signals indicate that the first coding signal is in the shielding state, the input circuit shields the first signal, and if the N first sub-coding signals indicate that the first coding signal is in the normal state, the output end of the input circuit outputs the first signal.

In some embodiments, the input circuit includes: an NOR gate, one input end of the NOR gate receives the first signal, the other input end is connected to the output end of the AND gate, and the output end of the NOR gate is connected to the input end of the selector at the first stage; the delay module also includes: an inverting unit, the input end of the inverting unit is connected to the output end of the Nth selector, and the output end of the inverting unit outputs the second signal.

In some embodiments, the system further includes: a latch module, which is used to receive the first coding signal and the activation command, and in response to the activation command, latch the first coding signal received last time before receiving the activation command.

In some embodiments, the latch module includes: a first inverter having a first input terminal and a first output terminal, the first input terminal receiving the activation command and outputting a first control signal through the first output terminal; a second inverter having a second input terminal and a second output terminal The output end of the latch module is a first input end, a first control end and a second control end, wherein the first input end, the first control end and the second control end receive the first coding signal, the first control signal and the second control signal respectively, and the output end of the latch module serves as the output end of the latch module.

In some embodiments, the temperature detection module is further configured to, when the memory array is in a read-write mode, detect the temperature of the memory array before receiving the activation command, and output a second coded signal, wherein the second coded signal is used to characterize the temperature of the memory array; the delay module is further configured to receive the activation command and the read-write command, and delay the activation command and the read-write command based on the second coded signal, and output the delayed activation command and the delayed read-write command.

In some embodiments, the delay module is further configured such that, under the condition that the first coded signal and the second coded signal represent the same temperature, the delay amount of the first signal in the refresh mode is greater than or equal to the delay amount of the first signal in the read-write mode.

In some embodiments, the delay module is further configured to receive a delay adjustment signal, and when the first coded signal remains unchanged, adjust the delay duration of the second signal relative to the first signal based on the delay adjustment signal.

According to some embodiments of the present disclosure, the embodiments of the present disclosure further provide a storage system, including: a memory array and a sense amplifier array connected to the memory array, the sense amplifier array including a plurality of sense amplifiers, the memory array including a plurality of storage units, and each of the storage units and each of the sense amplifiers are connected to a bit line; the delay circuit provided in any of the above embodiments. The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

In the technical solution of the delay circuit provided by the embodiment of the present disclosure, in the refresh mode, the temperature detection module detects the temperature of the memory array before receiving the activation command, and outputs a first coded signal representing the temperature; the delay module delays the first signal based on the first coded signal and outputs a second signal, the delay amount of the second signal compared to the first signal corresponds to the temperature, that is, different temperatures have different delay amounts, and the second signal is used to control the duration of the mismatch compensation of the sensitive amplifier, the greater the delay amount, the longer the compensation duration of the mismatch compensation, and the higher the temperature, the smaller the delay amount, the shorter the corresponding compensation duration, and the lower the temperature, the greater the delay amount, the longer the corresponding compensation duration. That is to say, at a relatively low temperature, the time for mismatch compensation can be extended, thereby compensating for the adverse effects of low temperature on refresh performance, and ensuring excellent refresh performance at low temperatures. At a relatively high temperature, the compensation duration is relatively short, so that while ensuring excellent refresh performance, it can also achieve the purpose of power saving.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a functional block diagram of a semiconductor memory;

FIG2 is a functional block diagram of a delay circuit provided by an embodiment of the present disclosure;

FIG3 is another functional block diagram of a delay circuit;

FIG4 is a functional block diagram of a delay module;

FIG5 is a schematic diagram of a circuit structure of a selector;

FIG6 is another functional block diagram of the delay circuit;

FIG7 is a schematic diagram of a circuit structure of a latch module;

FIG8 is a functional block diagram of a delay circuit;

FIG. 9 is a functional block diagram of a storage system.

Detailed ways

1 is a functional block diagram of a semiconductor memory, which includes: a plurality of memory arrays 10 and a sense amplifier array 11 connected to the corresponding memory array 10, the memory array 10 includes a plurality of memory cells, and the sense amplifier array 11 includes a plurality of sense amplifiers; a row decoding circuit 12 and a column decoding circuit 13, which are used to select the corresponding memory cell during the read and write operation so as to perform the read and write operation on the selected memory cell.

Among them, the working stages of the sense amplifier can be divided into the equalization stage (EQ stage), the device mismatch elimination stage (OC stage), the small signal input stage (CS stage) and the signal amplification stage (sense stage). For the OC stage, the temperature of the memory array of the semiconductor memory will affect the device mismatch elimination effect. At high and low temperatures, the performance requirements of the OC stage need to be different. Therefore, for different temperatures, it is usually necessary to design the sense amplifier to have different OC compensation time tOC, so that the OC compensation time tOC is matched with temperature control to select the optimal OC compensation time tOC setting. The longer tOC is, the longer the activation command time on the path needs to be. In order to ensure that the node of the internal receiving signal remains unchanged, the activation command needs to be advanced accordingly, which increases the tRCD time, resulting in the tRCD parameter not meeting the JDEC regulations. To solve this problem, the delay corresponding to the read and write signals can be increased at the same time, so that the read and write signals are also advanced, so that tRCD remains unchanged, but this will affect the opening speed of CSL and make the refresh time too long. Therefore, tOC should not be too long; but if tOC is too short, the compensation effect will be poor. Among them, tRCD refers to the time between the memory array receiving the activation command and receiving the read and write signals.

An embodiment of the present disclosure provides a delay circuit, which can generate a second signal with different delay amounts under different temperature conditions in a refresh mode. The second signal is used to control the compensation time of the mismatch compensation of the sensitive amplifier, so that the sensitive amplifier can have an excellent mismatch compensation effect under different temperatures.

The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

FIG. 2 is a functional block diagram of a delay circuit provided in an embodiment of the present disclosure.

Referring to FIG. 2 , the delay circuit provided in the embodiment of the present disclosure can be applied to a storage system. The storage system includes a memory array 100 and a sensitive amplifier connected to the memory array 100. The delay circuit includes: a temperature detection module 101, configured to, when the memory array 100 is in a refresh mode, detect the temperature of the memory array 100 before receiving an activation command, and output a first coded signal Tscode1, wherein the first coded signal Tscode1 is used to characterize the temperature of the memory array 100; a delay module 102, configured to receive a first signal Nc, and based on the first coded signal T scode1 delays the first signal Nc to generate and output a second signal Ncdly, wherein the second signal Ncdly is used to control the compensation time of the sensitive amplifier for mismatch compensation. The sensitive amplifier is connected to the memory array 100. The delay amount of the second signal Ncdly compared with the first signal Nc corresponds to the first coding signal Tscode1, and the higher the temperature of the memory array 100 represented by the first coding signal Tscode1, the smaller the delay amount. The first signal Nc is sent to the delay module 102 after the memory array 100 receives the activation command for a fixed time.

The delay circuit provided in the above embodiment can output the first coding signal Tscode1 based on the temperature of the memory array 100 before receiving the activation command in the refresh mode. Correspondingly, the delay module 102 generates a second signal Ncdly corresponding to the first coding signal Tscode1. The second signal Ncdly has a delay amount corresponding to the first coding signal Tscode1 compared to the first signal Nc, and the lower the temperature of the memory array 100, the larger the corresponding delay amount, so as to achieve the purpose of having different compensation time lengths for mismatch compensation at different temperatures, that is, the sensitive amplifier has an OC negative temperature characteristic, so as to meet the corresponding refresh time length requirements of the memory array 100 at different temperatures, thereby enabling the memory array 100 to have good refresh performance at different temperatures, and extend the refresh interval to achieve the purpose of power saving. It can be understood that the larger the delay amount, the longer the compensation time length for the second signal to control the sensitive amplifier to perform mismatch compensation; the smaller the delay amount, the shorter the compensation time length for the second signal to control the sensitive amplifier to perform mismatch compensation.

The delay circuit provided by the embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

The storage system may be a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). In some embodiments, the delay circuit may be applied to an SDRAM (Synchronous Dynamic Random Access Memory), which may be a DDR (Double Data Rate) SDRAM, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

The memory array 100 includes a plurality of memory cells, and the sense amplifier array includes a plurality of sense amplifiers. The sense amplifiers are connected to the bit lines of the corresponding memory cells to amplify and output the data read from the memory cells, or to amplify and write the data to be written into the memory cells. In refresh mode, the memory cells of the memory array 100 are refreshed, that is, 1 or 0 is written back into the memory cells. The better the mismatch compensation effect of the sense amplifier, the better the effect of writing 1 or writing 0 into the memory cells, that is, the higher the refresh performance. Specifically, the longer the compensation time of the mismatch compensation of the sense amplifier, the better the corresponding mismatch compensation effect.

In addition, the mismatch compensation time of the sense amplifier is related to the temperature of the memory array 100. Generally, the higher the temperature of the memory array 100, the easier it is for the data stored in the memory array 100 to be erroneous due to charge leakage. The memory array 100 needs to be refreshed as a whole in a shorter time, thereby shortening the duration of each refresh. The mismatch compensation time needs to be shortened adaptively. When the memory array 100 is in refresh mode, the delay circuit only delays the first signal Nc, without delaying the activation command and the read/write command. When the device array 100 is in the read-write mode, the delay circuit can not only delay the first signal Nc, but also delay the activation command and the read-write command, and at the same temperature, the delay amount of the first signal Nc in the refresh mode can be greater than the delay amount of the first signal Nc in the read-write mode. That is to say, at the same temperature, the compensation time length of the mismatch compensation performed by the sensitive amplifier in the refresh mode is greater than the compensation time length of the mismatch compensation performed by the sensitive amplifier in the read-write mode. The advantage of this setting is that: in the refresh mode, there is no need to consider the tRCD time, so a relatively large compensation time length can be set; in the read-write mode, the tRCD time needs to be considered. If the compensation time length is long, the corresponding tRCD time will become shorter, causing tRCD to fail to meet the parameter requirements. Therefore, the compensation time length will be relatively shortened in the read-write mode to keep the tRCD time as constant as possible.

The first coding signal Tscode1 is a multi-bit signal, and the data of each bit in the multi-bit signal is not exactly the same, so the temperature represented by the first coding signal Tscode1 is different. It is understandable that the "temperature" referred to here actually refers to the temperature range. In some examples, the first coding signal Tscode1 can be a 2-bit signal, and the corresponding first coding signal Tscode1 can represent up to 4 different temperature ranges. It is understandable that the number of bits of the first coding signal Tscode1 can be set according to actual needs. If the first coding signal Tscode1 needs to represent more temperature ranges, the larger the number of bits of the corresponding first coding signal Tscode1. For example, if the number of bits of the first coding signal Tscode1 is 3, then up to 8 different temperature ranges can be represented accordingly. If the number of bits of the first coding signal Tscode1 is 4, then up to 16 different temperature ranges can be represented accordingly.

In some examples, the larger the decimal value represented by the first coding signal Tscode1, the higher the temperature represented by the first coding signal Tscode1 and the smaller the corresponding delay amount, and the smaller the decimal value represented by the first coding signal Tscode1, the lower the temperature represented by the first coding signal Tscode1 and the larger the corresponding delay amount. Taking the first coding signal Tscode1 as a 2-bit signal as an example, Table 1 illustrates a corresponding relationship between the first coding signal Tscode1 and the delay amount.

Table 1

Referring to Table 1, t is the temperature of the memory array 100. If the temperature of the memory array 100 is too high, such as higher than 75°C, the delay module 102 may delay the first signal Nc, which may cause the actual refresh duration to fail to meet the refresh duration limit under the temperature condition. Therefore, in this case, the delay module 102 may not delay the first signal Nc, and the delay circuit may generate an internal signal to replace the first signal Nc. The internal signal is used to control the compensation duration of the mismatch compensation of the sensitive amplifier.

It can be understood that in some examples, it can also be set as follows: the smaller the decimal value represented by the first coding signal Tscode1, the higher the temperature represented by the first coding signal Tscode1 and the smaller the corresponding delay; the larger the decimal value represented by the first coding signal Tscode1, the lower the temperature represented by the first coding signal Tscode1 and the larger the corresponding delay.

FIG3 is another functional block diagram of the delay circuit. Referring to FIG3 , the temperature detection module 101 may include a temperature detection circuit 111 and an encoding circuit 121. The temperature detection circuit 111 is used to detect the temperature value of the memory array 100 before receiving the activation command, and output a detection signal representing the temperature value; the encoding circuit 121 is used to encode the detection signal to generate a corresponding first encoding signal Tscode1. The temperature detection circuit 111 may include a temperature sensor.

FIG4 is a functional block diagram of the delay module 102. Referring to FIG4, the delay module 102 includes: N cascaded selectors 112; the selector 112 at the first stage is used to receive the first signal Nc, and in response to the first coding signal Tscode1, directly output the first signal Nc, or delay the first signal Nc by a first preset delay amount to obtain a first delayed signal, and output the first delayed signal; the input end of the nth selector 112 is connected to the output end of the n-1th selector 112, and the nth selector 112 is used to respond to the first coding signal Tscode1, directly output the n-1th delayed signal output from the output end of the n-1th selector 112, or delay the n-1th delayed signal by an nth preset delay amount to obtain an nth delayed signal, and output the nth delayed signal, n is a natural number greater than or equal to 2, N is a natural number greater than or equal to 2, and n is less than or equal to N; wherein, the first coding signal Tscode1 includes N first sub-coding signals Ts, and each selector 112 receives a corresponding first sub-coding signal Ts. In FIG. 4 , Ncdly1 represents the first delayed signal outputted via the first selector 112 , and Ncdly2 represents the second delayed signal outputted via the second selector 112 .

Since different selectors 112 can have two selection functions of directly outputting the received signal or delaying the received signal before outputting it, the corresponding functions can be performed by controlling different selectors 112, so that the last stage selector 112 can output the second signal Ncdly with different delay amounts. It should be noted that the "second signal Ncdly with different delay amounts" mentioned here is output by the last stage selector 112 at different periods.

The first coding signal Tscode1 can be an N-bit binary value, and each first sub-coding signal Ts is a bit of data in the N-bit binary value, that is, the first sub-coding signal Ts can be 0 or 1. In one example, if the first sub-coding signal Ts received by the selector 112 is 0, the selector 112 chooses to directly output the received first signal Nc, that is, the selector 112 does not delay the first signal Nc. If the first sub-coding signal Ts received by the selector 112 is 1, the selector 112 delays the first signal Nc by a preset delay amount and outputs the delayed first signal Nc. In some examples, if the first sub-coding signal Ts received by the selector 112 is 1, the selector 112 chooses to directly output the received first signal Nc. If the first sub-coding signal Ts received by the selector 112 is 0, the selector 112 delays the first signal Nc by a preset delay amount and outputs the delayed first signal Nc. In Figure 4, Ts[0], Ts[1] to Ts[a] represent each first sub-coding signal, a can be a positive integer greater than or equal to 2, and N is greater than 2. In addition, N may also be 2, and correspondingly, two first sub-coding signals are represented by Ts[0] and Ts[1].

The preset delay amount of the selector 112 of the previous stage may be smaller than the preset delay amount of the selector 112 of the next stage. The advantages of such a setting include: the selector 112 with a relatively small preset delay amount is in the front, and the selector 112 with a relatively large preset delay amount is at a relatively backward position, so that the selector 112 with a relatively small preset delay amount can be used more, and the corresponding selector 112 will have a relatively small noise impact on the signal.

For example, if the preset delay amount of the first-stage selector 112 is 250ps and the preset delay amount of the second-stage selector 112 is 500ps, if only the first-stage selector 112 turns on the delay function and the second-stage selector 112 directly outputs the received signal, then the second-stage selector 112 The delay amount of the second signal Ncdly output by the selector 112 compared to the first signal Nc is 250ps; if the first-stage selector 112 directly outputs the received signal and the second-stage selector 112 turns on the delay function, the delay amount of the second signal Ncdly output by the second-stage selector 112 compared to the first signal Nc is 500ps; if the delay function is turned on for both the first-stage selector 112 and the second-stage selector 112, the delay amount of the second signal Ncdly output by the second-stage selector 112 compared to the first signal Nc is 750ps.

It is understandable that the preset delay amount of the selector 112 of the previous stage may be equal to or greater than the preset delay amount of the selector 112 of the next stage. The extended delay amount of the selectors 112 of the previous and next stages may also have no particular size limitation.

FIG5 is a schematic diagram of a circuit structure of the selector 112. Referring to FIG5, the selector 112 may include: a delay circuit 212 configured to receive an input signal, delay the input signal by a preset delay amount, obtain a delayed signal, and output the delayed signal; a selection circuit 222 configured to receive an input signal and a delayed signal, and in response to a corresponding first sub-coding signal Ts, select and output one of the received input signal or the delayed signal; wherein the first signal Nc is the input signal received by the selector 112 at the first stage, and the first delayed signal is the delayed signal output by the selector 112 at the first stage; the n-1th delayed signal is the input signal received by the nth selector 112, and the nth delayed signal is the delayed signal output by the nth selector 112.

The preset delay amounts of the delay circuits 212 of different selectors 112 may be different. For example, the preset delay amount of the delay circuit 212 of the previous selector 112 is smaller than the preset delay amount of the delay circuit 212 of the next selector 112.

In one example, the selection circuit 222 can receive the first sub-coding signal Ts and the first sub-coding inverted signal TsN, and select to output one of the received input signal or the delayed signal, and the first sub-coding signal Ts and the first sub-coding inverted signal are inverted signals of each other. In a specific example, if the first sub-coding signal Ts is 1 and the first sub-coding inverted signal is 0, the selection circuit 222 selects to output the delayed signal; if the first sub-coding signal Ts is 0 and the first sub-coding inverted signal is 1, the selection circuit 222 selects to output the received input signal. In a specific example, if the first sub-coding signal Ts is 0 and the first sub-coding inverted signal is 1, the selection circuit 222 selects to output the delayed signal; if the first sub-coding signal Ts is 1 and the first sub-coding inverted signal is 0, the selection circuit 222 selects to output the received input signal.

5 , taking the first coded signal as a 2-bit signal as an example, the two first sub-coded signals are respectively indicated by Ts[0] and Ts[1], and the two first sub-coded inverted signals are respectively indicated by TsN[0] and TsN[1].

If the temperature of the memory array 100 is higher than the preset value, the delay circuit can shield the first signal Nc and regenerate an internal signal to replace the first signal Nc. The internal signal is used to control the compensation time of the sensitive amplifier for mismatch compensation. Correspondingly, the first coding signal Tscode1 may include a normal state and a shielding state. If the temperature represented by the first coding signal Tscode1 is higher than the preset value, the first coding signal Tscode1 has a shielding state. If the temperature represented by the first coding signal Tscode1 is within the preset value, the first coding signal Tscode1 has a normal state. The preset value can be set according to actual needs, for example, it can be 70°C, 75°C or 80°C.

Continuing to refer to Figure 5, the delay module 102 may also include: a selection unit 232, configured to receive the first signal Nc and the first coding signal Tscode1, and in response to the first coding signal Tscode1 in the shielded state, shield the first signal Nc and generate and output an internal signal that replaces the first signal Nc, and in response to the first coding signal Tscode1 in the normal state, output the first signal Nc.

If the first coding signal Tscode1 is in a normal state, the selection unit 232 outputs the first signal Nc to the delay circuit 212 and the selection unit 232. The selection circuit 222. If the first coding signal Tscode1 is in the masking state, the selection unit 232 outputs an internal signal to replace the first signal Nc.

Continuing to refer to FIG5 , the selection unit 232 may include: an AND gate 31, each input end of the AND gate 31 receives N first sub-coding signals Ts respectively, and generates and outputs an internal signal if the N first sub-coding signals Ts represent that the first coding signal Tscode1 is in a shielded state; an input circuit 32, one input end of the input circuit 32 receives the first signal Nc, the other input end is connected to the output end of the AND gate 31, and the output end of the input circuit 32 is connected to the input end of the selector 112 at the first stage, and is configured such that if the N first sub-coding signals Ts represent that the first coding signal Tscode1 is in a shielded state, the input circuit 32 shields the first signal Nc, and if the N first sub-coding signals Ts represent that the first coding signal Tscode1 is in a normal state, the output end of the input circuit 32 outputs the first signal Nc. Taking N as 2 as an example, the AND gate 31 has 2 input ends.

In an example, if N first sub-coding signals Ts are all 1, the first coding signal Tscode1 is in a shielded state, and the output end of the AND gate 31 outputs 1; one input end of the input circuit 32 receives 1, and the other input end receives the first signal Nc, and the output end outputs the first signal Nc, wherein the output end outputs the first signal Nc in a manner that: the output end directly outputs the first signal Nc; or, the output end inverts the first signal Nc and outputs the inverted first signal Nc. If the output end of the input circuit 32 outputs the inverted first signal Nc, the output end of the selector 112 of the last stage is connected to an inverting unit 304.

If at least one of the N first sub-coding signals Ts is 0, the first coding signal Tscode1 is in a normal state, and the output terminal of the AND gate 31 outputs 0; one input terminal of the input circuit 32 receives 0, and the other input terminal receives the first signal Nc.

Under high temperature conditions, using the first coding signal Tscode1 to shield the first signal Nc and generate an internal signal for replacing the first signal Nc is beneficial to avoiding unexpected delays of the first signal Nc due to high temperature, thereby avoiding the OC compensation time tOC from being too long and ensuring that the refresh time meets the requirements; at the same time, since the internal signal is generated based on the first coding signal Tscode1, it is beneficial to ensure that the input signal of the selector (i.e., the internal signal) and the selection signal of the selector (i.e., the first coding signal Tscode1) can cooperate with each other well in timing, avoiding the different effects of the high temperature environment on the timing of the first signal Nc and the first coding signal Tscode1, thereby causing the first signal Nc to be accidentally delayed by the selector, thereby leading to the problem of too long OC compensation time tOC.

5 , the AND gate 31 may include: a NAND gate 301 and an inverter 302 connected to the output end of the NAND gate 301 , wherein the input end of the NAND gate 301 receives N first sub-coding signals Ts respectively.

The input circuit 32 may include: a NOR gate, one input end of the NOR gate receives the first signal Nc, the other input end is connected to the output end of the AND gate 31, and the output end of the NOR gate is connected to the input end of the selector 112 at the first stage.

If the output of the AND gate 31 is 0, the output of the NOR gate outputs the inverted first signal Nc; if the output of the AND gate 31 is 1, that is, the first coding signal Tscode1 is in a shielding state, the output of the NOR gate always outputs 0, that is, the input circuit 32 always outputs 0, and it can be considered that the input circuit 32 shields the first signal Nc.

The delay module 102 may further include: an inverting unit 304, the input end of the inverting unit 304 is connected to the output end of the Nth selector 112, and the output end of the inverting unit 304 outputs the second signal Ncdly. From the above analysis, it can be seen that when the first coded signal Tscode1 is in a normal state, the input circuit 32 outputs the inverted first signal Nc. In order to ensure that the phase of the second signal Ncdly finally output by the delay circuit meets If necessary, an inverting unit 304 may be connected to the output end of the selector 112 at the last stage to invert the delayed first signal Nc to obtain a second signal Ncdly having the same phase as the first signal Nc.

The inverting unit 304 may be composed of an inverter, one input end of which is connected to the output end of the selector 112 of the last stage, and the other input end receives the enable signal En. The inverting unit 304 has an inverting function only when the enable signal En is at a high level, i.e., 1. Therefore, when the first coded signal is in a normal state, the enable signal En is at a high level, i.e., 1.

FIG6 is another functional block diagram of the delay circuit. Referring to FIG6, the delay circuit may further include: a latch module 103, which is used to receive the first coding signal Tscode1 and the activation command ActPls, and in response to the activation command ActPls, latch the first coding signal Tscode1 received last time before receiving the activation command ActPls. The latch module 103 can latch the first coding signal Tscode1 to prevent the first coding signal Tscode1 from suddenly changing when the memory array 100 is started, thereby avoiding the timing error that may be caused by the sudden change of the first coding signal Tscode1.

It can be understood that when the activation command ActPls is not received, the first coding signal Tscode1 output by the temperature detection module 101 can be directly given to the delay module 102, and the first coding signal Tscode1 output by the temperature detection module 101 can also be given to the delay module 102 via the latch module 103. At this time, the latch module 103 is equivalent to an intermediate buffer circuit.

FIG7 is a schematic diagram of a circuit structure of the latch module 103. Referring to FIG7, the latch module 103 may include: a first inverter 113 having a first input terminal and a first output terminal, the first input terminal receiving the activation command ActPls, and outputting the first control signal TsLatch through the first output terminal; a second inverter 123 having a second input terminal and a second output terminal, the second input terminal connected to the first output terminal, and outputting the second control signal TsLatchN through the second output terminal; a latch 133 having a first input terminal D, a first control terminal Lat, and a second control terminal LatN, the first input terminal D, the first control terminal Lat, and the second control terminal LatN respectively receiving the first coding signal Tscode1, the first control signal TsLatch, and the second control signal TsLatchN, and the output terminal of the latch serving as the output terminal of the latch module 103. The latch 133 may also have a reset terminal R, and the reset terminal R is used to receive a reset signal Rst.

If the activation command ActPls is a high level signal, that is, the activation command ActPls is 1, it indicates that the memory array 100 is about to start, and the corresponding latch module 103 needs to latch the first coding signal Tscode1. The first control signal TsLatch and the activation command ActPls are inverted signals, and the first control signal TsLatch and the second control signal TsLatchN are inverted signals.

Referring to Figure 7, the latch module 103 may also include: an even number of cascaded third inverters 143, the input end of the third inverter 143 at the first stage is connected to the output end of the latch 133, and the third inverter 143 at the last stage outputs the inverted signal of the first coding signal Tscode1 after latching, and TsN represents the inverted signal of the first coding signal Tscode1 after latching. Among them, the number of third inverters 143 can be any even number such as 2 or 4, and the more the number of third inverters 143, the stronger the driving ability of the latched signal. Taking the first coding signal Tscode1 as 2-bit data as an example, the first coding signal Tscode can be represented by Ts[1:0], and the inverted signal of the first coding signal Tscode1 can be represented by TsN[1:0].

In addition, when the memory array 100 is in the refresh mode, the delay circuit can also generate a second signal Ncdly with different delay amounts based on different temperatures of the memory array 100. The second signal Ncdly controls the compensation time of the sense amplifier for mismatch compensation, that is, the sense amplifier can have different mismatch compensation time lengths to facilitate optimal testing. The optimal testing means that, under different environments, even if the memory array 100 is The device array 100 is at the same temperature, and the sensitive amplifiers still have different compensation time requirements for mismatch compensation. The delay circuit can generate a second signal Ncdly corresponding to different compensation time lengths based on the same temperature, so as to select the second signal Ncdly with the best mismatch compensation effect corresponding to the environment from different second signals Ncdly through testing under different environments.

The delay module 102 is also used to receive a delay adjustment signal, and when the first coding signal Tscode1 remains unchanged, adjust the delay length of the second signal Ncdly relative to the first signal Nc based on the delay adjustment signal. In this way, it is possible to obtain a second signal Ncdly with different delay amounts corresponding to the same temperature in the refresh mode.

In addition, Figure 8 is a functional block diagram of the delay circuit. Referring to Figure 8, the temperature detection module 101 can also be configured to, when the memory array 100 is in the read-write mode, detect the temperature of the memory array 100 before receiving the activation command ActPls, and output a second coding signal Tscode2, where the second coding signal Tscode2 is used to characterize the temperature of the memory array 100; the delay module 102 is also configured to receive the activation command ActPls and the read-write command Rd/Wr, and delay the activation command ActPls and the read-write command Rd/Wr based on the second coding signal Tscode2, and output the delayed activation command ActPlsdly and the delayed read-write command Rd/Wrdly.

That is, the delay circuit can also delay the activation command ActPls and the read/write command Rd/Wr in accordance with the temperature of the memory array 100 in the read/write mode.

Since the compensation time of mismatch compensation is controlled based on the temperature of the memory array 100 in the refresh mode, different compensation time can be selected in the refresh mode, and since there is no read/write operation in the refresh mode, there is no need to consider tRCD, so in the refresh mode the compensation time can be made to correspond to the temperature, and the optimal compensation time can be selected for setting to improve the refresh effect. In the read/write mode, tRCD needs to be considered, so the compensation time in the read/write mode should not be too long.

Therefore, considering the difference between the demand for compensation time in refresh mode and the demand for compensation time in read-write mode, the delay module 102 can also be configured so that, under the condition that the first coding signal Tscode1 and the second coding signal Tscode2 represent the same temperature, the delay amount of the first signal Nc in the refresh mode is greater than or equal to the delay amount of the first signal Nc in the read-write mode. In this way, it can meet the demand for setting different compensation time at different temperatures in both refresh mode and read-write mode, so that the sensitive amplifier has a good mismatch compensation effect in both refresh mode and read-write mode, and avoid affecting the duration of tRCD in read-write mode to ensure the performance of reading and writing.

The delay circuit provided in the embodiment of the present disclosure can compensate for temperature by adjusting the delay amount of the first signal in the refresh mode, so as to generate a second signal with a different delay amount relative to the first signal at different temperatures. The compensation time at a relatively low temperature is longer than that at a higher temperature. Longer compensation is better, which is beneficial to shortening the interval between two adjacent refreshes, thereby achieving the purpose of saving power.

Accordingly, the present disclosure also provides a storage system, including the delay circuit provided in any of the above embodiments. The storage system will be described in detail below. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be repeated below.

FIG9 is a functional block diagram of a memory system. Referring to FIG9 , the memory system may include: a memory array 400 and a sense amplifier array 401 connected to the memory array 400, wherein the sense amplifier array 401 includes a plurality of sense amplifiers, and the sense amplifiers are connected to the memory array 400, and the memory array 400 includes a plurality of memory cells, and each memory cell and each sense amplifier are connected to a bit line BL; The delay circuit 402 generates a second signal which is provided to the sense amplifier to control the compensation time length of the mismatch compensation performed by the sense amplifier.

The storage system may be DRAM or SRAM. The DRAM may be SDRAM, and the SDRAM may be DDR SDRAM, such as DDR4, DDR5, DDR6, LPDDR4, LPDDR5, or LPDDR6.

The memory system may further include a row decoding circuit 403 and a column decoding circuit 404 .

In refresh mode, the delay circuit 402 receives the first signal and generates a second signal. The delay of the second signal compared to the first signal corresponds to the temperature of the memory array, and the second signal controls the compensation time of the sense amplifier for mismatch compensation.

In the read-write mode, the delay circuit 402 receives the first signal and generates a second signal, the delay amount of the second signal compared to the first signal corresponds to the temperature of the memory array, and the second signal controls the compensation time of the sense amplifier for mismatch compensation; in addition, under the same temperature, the delay amount of the second signal compared to the first signal in the read-write mode is less than the delay amount of the second signal compared to the first signal in the refresh mode. The delay circuit 402 can also delay the activation command and the read-write command to output the delayed activation command and the activated read-write command, that is, the temperature can be used to perform timing compensation for the rows and columns at the same time. The delay circuit 402 can delay the signal provided to the column decoding circuit 404 and the row decoding circuit 403, and provide the delayed signal to the column decoding circuit 404 and the row decoding circuit 403.

As can be seen from the above analysis, the storage system provided by the embodiment of the present disclosure can adjust the compensation time for mismatch compensation of the sense amplifier based on temperature in the refresh mode to ensure good refresh effect at different temperatures.

Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims (17)

1. A delay circuit is applied to a storage system, the storage system comprising a storage array (100) and a sensitive amplifier connected to the storage array (100), comprising:

   A temperature detection module (101) is configured to, when the memory array (100) is in a refresh mode, detect the temperature of the memory array (100) before receiving an activation command, and output a first coded signal (Tscode1), wherein the first coded signal (Tscode1) is used to characterize the temperature of the memory array (100);

   A delay module (102) is configured to receive a first signal (Nc) and perform delay processing on the first signal (Nc) based on the first coding signal (Tscode1) to generate and output a second signal (Ncdly), wherein the second signal (Ncdly) is used to control the compensation time of the sensitive amplifier for mismatch compensation, the sensitive amplifier is connected to the memory array (100), the delay amount of the second signal (Ncdly) compared with the first signal (Nc) corresponds to the first coding signal (Tscode1), and the higher the temperature of the memory array (100) represented by the first coding signal (Tscode1), the smaller the delay amount, and the first signal (Nc) is sent to the delay module (102) after the memory array (100) receives the activation command for a fixed time.
2. The delay circuit according to claim 1, wherein the delay module (102) comprises: N cascaded selectors (112);

   The selector (112) at the first stage is used to receive the first signal (Nc), and in response to the first coded signal (Tscode1), directly output the first signal (Nc), or delay the first signal (Nc) by a first preset delay amount to obtain a first delayed signal, and output the first delayed signal;

   The input end of the nth selector (112) is connected to the output end of the n-1th selector (112), and the nth selector (112) is used to directly output the n-1th delayed signal output from the output end of the n-1th selector (112) in response to the first coded signal (Tscode1), or delay the n-1th delayed signal by an nth preset delay amount to obtain an nth delayed signal, and output the nth delayed signal, where n is a natural number greater than or equal to 2, N is a natural number greater than or equal to 2, and n is less than or equal to N;

   The first coded signal (Tscode1) includes N first sub-coded signals (Ts), and each of the selectors (112) receives a corresponding first sub-coded signal (Ts).
3. The delay circuit according to claim 2, wherein the selector (112) comprises:

   The delay circuit (212) is configured to receive an input signal, delay the input signal by a preset delay amount, obtain a delayed signal, and output the delayed signal;

   A selection circuit (222) is configured to receive the input signal and the delayed signal, and select and output one of the received input signal or the delayed signal in response to the corresponding first sub-coded signal;

   Among them, the first signal (Nc) is the input signal received by the selector (112) at the first stage, and the first delayed signal is the delayed signal output by the selector (112) at the first stage; the n-1th delayed signal is the input signal received by the nth selector (112), and the nth delayed signal is the delayed signal output by the nth selector (112).
4. The delay circuit according to claim 3, wherein the preset delay amount of the delay circuit (212) of the selector (112) at the previous stage is smaller than the preset delay amount of the delay circuit (212) of the selector (112) at the next stage.
5. The delay circuit according to claim 2, wherein the preset delay amount of the selector (112) of the previous stage is smaller than the preset delay amount of the selector (112) of the subsequent stage.
6. The delay circuit according to claim 2, wherein the first coding signal (Tscode1) includes a normal state and a shielding state; and the delay module (102) further includes:

   The selection unit (232) is configured to receive the first signal (Nc) and the first coded signal (Tscode1), and in response to the first coded signal (Tscode1) in a shielded state, shield the first signal (Nc) and generate and output an internal signal that replaces the first signal (Nc), and in response to the first coded signal (Tscode1) in a normal state, output the first signal (Nc).
7. The delay circuit according to claim 6, wherein, if the temperature represented by the first coding signal (Tscode1) is higher than a preset value, the first coding signal (Tscode1) has a shielding state, and if the temperature represented by the first coding signal (Tscode1) is within the preset value, the first coding signal (Tscode1) has a normal state.
8. The delay circuit according to claim 6, wherein the selection unit (232) comprises:

   An AND gate (31), each input end of which receives N first sub-coding signals (Ts) respectively, and generates and outputs the internal signal if the N first sub-coding signals (Ts) indicate that the first coding signal (Tscode1) is in a shielded state;

   An input circuit (32), wherein one input end of the input circuit (32) receives the first signal (Nc), the other input end is connected to the output end of the AND gate (31), and the output end of the input circuit (32) is connected to the input end of the selector (112) at the first stage, and is configured such that if N first sub-coding signals (Ts) indicate that the first coding signal (Tscode1) is in the shielding state, the input circuit (32) shields the first signal (Nc); if N first sub-coding signals (Ts) indicate that the first coding signal (Tscode1) is in the normal state, the output end of the input circuit (32) outputs the first signal (Nc).
9. The delay circuit according to claim 8, wherein the input circuit (32) comprises:

   A NOR gate, one input end of which receives the first signal (Nc), the other input end of which is connected to the output end of the AND gate (31), and the output end of the NOR gate is connected to the input end of the selector (112) at the first stage;

   The delay module (102) further includes:

   An inverting unit (304), wherein an input end of the inverting unit (304) is connected to an output end of the Nth selector (112), and an output end of the inverting unit (304) outputs the second signal (Ncdly).
10. The delay circuit according to claim 1, further comprising:

    The latch module (103) is used to receive the first coding signal (Tscode1) and the activation command (ActPls), and in response to the activation command (ActPls), latch the first coding signal (Tscode1) received last time before receiving the activation command (ActPls).
11. The delay circuit according to claim 10, wherein the latch module (103) comprises:

    A first inverter (113) having a first input terminal and a first output terminal, wherein the first input terminal receives the activation command (ActPls) and outputs a first control signal (TsLatch) through the first output terminal;

    A second inverter (123) having a second input terminal and a second output terminal, wherein the second input terminal is connected to the first output terminal, and a second control signal (TsLatchN) is output through the second output terminal;

    The latch (133) has a first input end (D), a first control end (Lat) and a second control end (LatN), wherein the first input end (D), the first control end (Lat) and the second control end (LatN) respectively receive the first coding signal (Tscode1), the first control signal (TsLatch) and the second control signal (TsLatchN), and the output end of the latch (133) serves as the output end of the latch module (103).
12. The delay circuit according to claim 1, wherein the temperature detection module (101) is further configured to, when the memory array (100) is in a read-write mode, detect the temperature of the memory array (100) before receiving the activation command (ActPls), and output a second coded signal (Tscode2), wherein the second coded signal (Tscode2) is used to characterize the temperature of the memory array (100);

    The delay module (102) is further configured to receive the activation command (ActPls) and the read/write command (Rd/Wr), and to delay the activation command (ActPls) and the read/write command (Rd/Wr) based on the second coding signal (Tscode2), and to output the delayed activation command (ActPls) and the delayed read/write command (Rd/Wr).
13. The delay circuit according to claim 12, wherein the delay module (102) is further configured such that, under the condition that the first coding signal (Tscode1) and the second coding signal (Tscode1) represent the same temperature, the delay amount of the first signal (Nc) in the refresh mode is greater than or equal to the delay amount of the first signal (Nc) in the read-write mode.
14. The delay circuit according to claim 1, wherein the delay module (102) is further used to receive a delay adjustment signal, and when the first coded signal (Tscode1) remains unchanged, adjust the delay length of the second signal (Ncdly) relative to the first signal (Nc) based on the delay adjustment signal.
15. The delay circuit according to claim 1, wherein the temperature detection module (101) comprises a temperature detection circuit (111) and an encoding circuit (121), wherein the temperature detection circuit (111) is used to detect the temperature value of the memory array (100) before receiving an activation command (ActPls) and output a detection signal representing the temperature value; and the encoding circuit (121) is used to encode the detection signal to generate the corresponding first encoding signal (Tscode1).
16. A storage system, comprising:

    A memory array (400) and a sense amplifier array (401) connected to the memory array (400), wherein the sense amplifier array (401) includes a plurality of sense amplifiers, and the memory array (400) includes a plurality of memory cells, and each of the memory cells and each of the sense amplifiers are connected to a bit line (BL);

    A delay circuit (402) according to any one of claims 1 to 15.
17. The storage system according to claim 16, further comprising: a row decoding circuit 403 and a column decoding circuit 404, wherein the delay circuit (402) is used to delay the signals provided to the column decoding circuit (404) and the row decoding circuit (403).