WO2024093037A1 - 存储器 - Google Patents

存储器 Download PDF

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Publication number
WO2024093037A1
WO2024093037A1 PCT/CN2023/074398 CN2023074398W WO2024093037A1 WO 2024093037 A1 WO2024093037 A1 WO 2024093037A1 CN 2023074398 W CN2023074398 W CN 2023074398W WO 2024093037 A1 WO2024093037 A1 WO 2024093037A1
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WO
WIPO (PCT)
Prior art keywords
data line
local data
complementary
voltage
voltage difference
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Application number
PCT/CN2023/074398
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English (en)
French (fr)
Inventor
罗怡菲
巴杭天
Original Assignee
长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2024093037A1 publication Critical patent/WO2024093037A1/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Definitions

  • the present disclosure relates to, but is not limited to, a memory.
  • a multi-stage amplifier circuit In a dynamic random access memory (DRAM), a multi-stage amplifier circuit is provided to amplify the voltage difference to realize reading or writing data in a storage unit. Improvements to the multi-stage amplifier circuit can improve the performance of the memory.
  • DRAM dynamic random access memory
  • the present disclosure provides a memory, comprising:
  • a first-stage amplifier circuit is connected to the bit line and the complementary bit line and is used to amplify the voltage difference between the bit line and the complementary bit line;
  • a secondary amplifier circuit is connected to the local data line and the complementary local data line, and also to the global data line and the complementary global data line, and after the local data line and the bit line are connected, and the complementary local data line and the complementary bit line are connected, the voltage difference between the local data line and the complementary local data line is amplified, and a voltage difference is generated between the global data line and the complementary global data line;
  • the driving circuit is connected to the local data line and the complementary local data line, and amplifies the voltage difference between the local data line and the complementary local data line.
  • the memory further comprises:
  • an equalization circuit connected to the local data line and the complementary local data line, and charging the voltage of the local data line and the complementary local data line to a precharge voltage before the local data line is connected to the bit line and before the complementary local data line is connected to the complementary bit line;
  • the driving circuit is used for amplifying the voltage difference between the local data line and the complementary local data line after the voltages of the local data line and the complementary local data line are charged to the pre-charge voltage.
  • the start time when the driving circuit amplifies the voltage difference between the local data line and the complementary local data line is earlier than the start time when the secondary amplifying circuit amplifies the voltage difference between the local data line and the complementary local data line.
  • the first starting time is within a first value range
  • the first starting time is within the second value range
  • the first time interval is the time interval between adjacent row addressing and column addressing of the memory, and the first starting time is the starting time when the driving circuit starts to amplify the voltage difference between the local data line and the complementary local data line;
  • the upper limit value of the first time range is less than or equal to the lower limit value of the second time range, and the upper limit value of the first numerical range is greater than or equal to the lower limit value of the second numerical range.
  • the driver circuit is used to:
  • Amplifying the voltage difference between the local data line and the complementary local data line by driving up the voltage of the local data line and/or the voltage of the complementary local data line;
  • the driving capability of driving the local data line upward is negatively correlated with the voltage on the complementary local data line, and the driving capability of driving the complementary local data line upward is negatively correlated with the voltage on the local data line.
  • the driving circuit includes:
  • the first power supply terminal provides a power supply voltage
  • a first driving unit connected to the local data line and the complementary local data line, and driving the voltage of the local data line upward according to the voltage of the complementary local data line when the first driving unit is connected to the first power supply terminal;
  • the second driving unit is connected to the local data line and the complementary local data line, and drives the voltage of the complementary local data line upward according to the voltage of the local data line when the second driving unit is connected to the first power supply terminal.
  • the driving capability of the first driving unit to drive the local data line is negatively correlated with the voltage of the complementary local data line
  • the driving capability of the second driving unit to drive the complementary local data line is negatively correlated with the voltage of the local data line.
  • the first driving unit includes:
  • a first P-type transistor a source electrode connected to the switch unit, a drain electrode connected to the local data line, and a gate electrode connected to the complementary local data line;
  • the second driving unit comprises:
  • the second P-type transistor has a source connected to the switch unit, a drain connected to the complementary local data line, and a gate connected to the local data line.
  • the switch unit comprises:
  • the third P-type transistor has a source connected to the first power supply terminal, a drain connected to the source of the first P-type transistor, and a drain also connected to the source of the second P-type transistor, and a gate receiving a first control signal.
  • the driving circuit further comprises:
  • a first control circuit wherein the first output end is connected to the control end of the switch unit, and the second output end is connected to the control end of the secondary amplifier circuit; the first input end receives a mode signal, and the second input end receives a reference signal, and is used to generate a first control signal according to the mode signal and the reference signal, and generate a second control signal according to the reference signal;
  • the first control signal starts to be in a valid state earlier than the second control signal starts to be in a valid state, and the second control signal controls the secondary amplifier circuit to amplify the voltage difference between the local data line and the complementary local data line.
  • the start time of the first control signal being in the valid state is later than the end time of the equalization control signal being in the valid state, and the voltage of the local data line and the complementary local data line is charged to the precharge voltage when the equalization control signal is in the valid state.
  • control circuit is used to:
  • the reference signal is processed according to the time step to generate a first control signal.
  • the mode signal is determined by any one or more parameters of the first time interval, the process angle of the memory, the temperature of the memory, and the working voltage of the memory;
  • the first time interval is the time interval between adjacent row addressing and column addressing of the memory.
  • the reference signal is a column selection signal
  • the column selection signal is used to control the connection or disconnection between the bit line and the local data line, and also used to control the connection or disconnection between the complementary bit line and the complementary local data line.
  • the memory further comprises:
  • the second control circuit connects the bit line and the complementary bit line, and also connects the local data line and the complementary local data line, and is used to receive a column selection signal, and control the connection or disconnection between the bit line and the local data line under the control of the column selection signal, and control the connection or disconnection between the complementary bit line and the complementary local data line under the control of the column selection signal.
  • the memory further comprises:
  • the three-stage amplifier circuit is connected to the global data line and the complementary global data line and is used to amplify the voltage difference between the global data line and the complementary global data line.
  • the memory provided by the present disclosure includes a primary amplifier circuit, a secondary amplifier circuit and a driving circuit.
  • the primary amplifier circuit is connected to a bit line and a complementary bit line, and the primary amplifier circuit amplifies the voltage difference between the bit line and the complementary bit line.
  • the driving circuit and the secondary amplifier circuit are both connected to a local data line and a complementary local data line.
  • the secondary amplifier circuit is also connected to a global data line and a complementary global data line. After a voltage difference is generated between the local data line and the complementary local data line, the secondary amplifier circuit amplifies the voltage difference between the local data line and the complementary local data line, and generates a voltage difference between the global data line and the complementary global data line.
  • the driving circuit is also used to amplify the voltage difference between the local data line and the complementary local data line, and compensate for the influence of the coupling capacitor on the voltage of the local data line, so as to shorten the time of amplifying the voltage difference between the local data line and the complementary local data line, and improve the timing parameter performance of the memory.
  • FIG1 is a schematic diagram of a circuit of a memory
  • FIG2 is a wiring diagram of a local data line in a memory
  • FIG3 is a schematic diagram showing the effect of a coupling capacitor on a local data line voltage in a memory
  • FIG4 is a working principle diagram of the effect of coupling capacitance on the local data line voltage in a memory
  • FIG5 is a circuit diagram of a memory provided by an embodiment of the present disclosure.
  • FIG6 is a working timing diagram of a memory provided by an embodiment of the present disclosure.
  • FIG. 7 is a diagram showing the working principle of a memory provided in an embodiment of the present disclosure.
  • a memory includes a first-stage amplifier circuit 100, a second-stage amplifier circuit 200, a third-stage amplifier circuit 300, a second control circuit 400, and an equalization circuit 500.
  • the first-stage amplifier circuit 100 is connected to the bit line BL and the complementary bit line BLB, and the first-stage amplifier circuit 100 is used to amplify the voltage difference between the bit line BL and the complementary bit line BLB.
  • the second-stage amplifier circuit 200 is connected to the local data line LIO and the complementary local data line LIOB, and the second-stage amplifier circuit 200 is also connected to the global data line GIO and the complementary global data line GIOB.
  • the second-stage amplifier circuit 200 is used to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB, and generate a voltage difference between the global data line GIO and the complementary global data line GIOB.
  • the third-stage amplifier circuit 300 is used to amplify the voltage difference between the global data line GIO and the complementary global data line GIOB.
  • the second control circuit 400 connects the bit line BL and the complementary bit line BLB, and the second control circuit 400 connects the local data line LIO and the complementary local data line LIOB.
  • the second control circuit 400 is used to control the connection or disconnection between the bit line BL and the local data line LIO, and the second control circuit 400 is also used to control the connection or disconnection between the complementary bit line BLB and the complementary local data line LIOB.
  • the equalization circuit 500 connects the local data line LIO and the complementary local data line LIOB and is used to charge the local data line LIO and the complementary local data line LIOB to the precharge voltage VCC before the bit line BL and the local data line LIO are connected and before the complementary bit line BLB and the complementary local data line LIOB are connected.
  • the first-stage amplifier circuit 100 amplifies the small voltage difference between the bit line BL and the complementary bit line BLB.
  • the bit line BL and the complementary bit line BLB After the bit line BL and the local data line LIO are connected, and the complementary bit line BLB and the complementary local data line LIOB are connected, the bit line BL and the complementary bit line BLB generate a voltage difference on the local data line LIO and the complementary local data line LIOB, and the secondary amplifier circuit 200 then amplifies the voltage difference on the local data line LIO and the complementary local data line LIOB, thereby realizing data transmission from the bit line BL and the complementary bit line BLB to the local data line LIO and the complementary local data line LIOB.
  • FIG2 is a wiring diagram of some local data lines LIO in the memory.
  • a plurality of local data lines LIO are arranged in sequence.
  • a coupling capacitor exists between two local data lines LIO. When a voltage jump occurs on the coupling capacitor, the voltage on the local data line LIO is affected.
  • the four local data lines LIO in FIG2 are marked as local data line LIO ⁇ 2>, local data line LIO ⁇ 0>, local data line LIO ⁇ 3> and local data line LIO ⁇ 1> from top to bottom.
  • a coupling capacitor exists between the local data line LIO ⁇ 2> and the local data line LIO ⁇ 3>.
  • the secondary amplifier circuit 200 when the secondary amplifier circuit amplifies the voltage difference between the local data line LIO ⁇ 0> and the complementary local data line LIOB ⁇ 0>, the voltage difference ⁇ LIO1 is relatively small, and the secondary amplifier circuit 200 takes a longer time to amplify the voltage difference between the local data line LIO ⁇ 0> and the complementary local data line LIOB ⁇ 0> to the preset value.
  • the timing parameter tCCD of the memory refers to the time interval between the previous column address strobe pulse and the next column address strobe pulse.
  • the timing parameter tCCD of the memory will deteriorate.
  • an embodiment of the present disclosure provides a memory including a first-stage amplifier circuit 100 , a second-stage amplifier circuit 200 , and a driving circuit 600 .
  • the first-stage amplifier circuit 100 is connected to the bit line BL and the complementary bit line BLB
  • the second-stage amplifier circuit 200 is connected to the local data line LIO and the complementary local data line LIOB
  • the second-stage amplifier circuit 200 is also connected to the global data line GIO and the complementary global data line GIOB
  • the driving circuit 600 is connected to the local data line LIO and the complementary local data line LIOB.
  • the local data line LIO is disconnected from the bit line BL, and the complementary local data line LIOB is disconnected from the complementary bit line BLB.
  • the memory cell shares charge with the bit line BL, and a small voltage difference is generated between the bit line BL and the complementary bit line BLB.
  • the first-stage amplifier circuit 100 is used to amplify the small voltage difference between the bit line BL and the complementary bit line BLB.
  • the bit line BL drives the local data line LIO
  • the complementary bit line BLB drives the complementary local data line LIOB
  • a voltage difference is generated between the local data line LIO and the complementary local data line LIOB
  • the secondary amplifier circuit 200 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB, and generates a voltage difference between the global data line GIO and the complementary global data line GIOB.
  • the drive circuit 600 also amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • a driving circuit 600 is provided to connect the local data line LIO and the complementary local data line LIOB. After a voltage difference is generated between the local data line LIO and the complementary local data line LIOB, the secondary amplifier circuit 200 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the driving circuit 600 is also used to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB to compensate for the influence of the coupling capacitor on the voltage of the local data line LIO. This can shorten the time for amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB and improve the timing parameter tCCD of the memory.
  • the memory further includes an equalization circuit 500, which connects the local data line LIO and the complementary local data line LIOB. Before the local data line LIO is connected to the bit line BL, and before the complementary local data line LIOB is connected to the complementary bit line BLB, the equalization circuit 500 charges the voltages of the local data line LIO and the complementary local data line LIOB to a precharge voltage.
  • the equalization circuit 500 charges the voltage of the local data line LIO and the complementary local data line LIOB to the pre-charge voltage
  • the control bit line BL is connected to the local data line LIO
  • the control complementary bit line BLB is connected to the complementary local data line LIOB.
  • a voltage difference is generated between the bit line BL and the complementary bit line BLB between the local data line LIO and the complementary local data line LIOB.
  • the driving circuit 600 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB
  • the secondary amplifier circuit 200 also amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the equalization circuit 500 is connected to a second power supply terminal, and the voltage VintLP of the second power supply terminal is adjustable, so that the pre-charge voltage is also adjustable.
  • the provided voltage VintLP of the second power supply terminal can be adjusted according to the timing parameters of the memory to adjust the pre-charge voltage on the local data line LIO and the complementary local data line LIOB.
  • the driving circuit 600 is turned on and is in a waiting state, after the bit line BL and the local data line LIO are connected, and after the complementary bit line BLB and the complementary local data line LIOB are connected, the bit line BL and the complementary bit line BLB generate a voltage difference between the local data line LIO and the complementary local data line LIOB, and the driving circuit 600 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the driving circuit 600 is turned on, and the driving circuit 600 directly amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB without entering a waiting state.
  • the control driving circuit 600 and the secondary amplifier circuit 200 amplify the voltage difference between the local data line LIO and the complementary local data line LIOB, thereby realizing accurate transmission of data between the bit line BL and the local data line LIO, and between the complementary bit line BLB and the complementary local data line LIOB.
  • the memory also includes a second control circuit 400, the second control circuit 400 connects the bit line BL and the complementary bit line BLB, the second control circuit 400 is also connected to the local data line LIO and the complementary local data line LIOB, the second control circuit 400 is used to receive the column selection signal CSL, the second control circuit 400 controls the bit line BL and the local data line LIO to be connected or disconnected under the control of the column selection signal CSL, and controls the complementary bit line BLB and the complementary local data line LIOB to be connected or disconnected under the control of the column selection signal CSL.
  • the second control circuit 400 includes a first transistor M1 and a second transistor M2, wherein the source or drain of the first transistor M1 is connected to the bit line BL, the drain or source of the first transistor M1 is connected to the local data line LIO, the gate of the first transistor M1 is connected to the column selection line, and receives the column selection signal CSL.
  • the source or drain of the second transistor M2 is connected to the complementary bit line BLB, the drain or source of the second transistor M2 is connected to the complementary local data line LIOB, the gate of the second transistor M2 is connected to the column selection line, and receives the column selection signal CSL.
  • the first transistor M1 and the second transistor M2 are turned on or off under the control of the column selection signal CSL to control the connection or disconnection between the bit line BL and the local data line LIO, and the connection or disconnection between the complementary bit line BLB and the complementary local data line LIOB.
  • the first transistor M1 and the second transistor M2 are N-type transistors, and the first transistor M1 and the second transistor M2 are controlled to be turned on when the column selection signal CSL is at a high level.
  • the memory also includes a three-stage amplifier circuit 300, which is connected to the global data line GIO and the complementary global data line GIOB, and is used to amplify the voltage difference between the global data line GIO and the complementary global data line GIOB.
  • the start time of the driving circuit 600 amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB is earlier than the start time of the secondary amplifier circuit 200 amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the driving circuit 600 first amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB to compensate for the influence of the coupling capacitor on the voltage of the local data line LIO, and then the secondary amplifier circuit 200 and the driving circuit 600 amplify the voltage difference between the local data line LIO and the complementary local data line LIOB together, and generate a voltage difference between the global data line GIO and the complementary global data line GIOB, shortening the time for the secondary amplifier circuit 200 to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB, thereby improving the performance of the timing parameter tCCD of the memory.
  • the first time interval is the time interval tRCD between adjacent row addressing and column addressing of the memory, that is, the time interval between adjacent activation commands and read commands, or the time interval between adjacent activation commands and write commands, that is, the time interval from turning on the word line to turning on the column selection line.
  • the first starting time is the starting time when the driving circuit 600 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the first start time is within the first numerical range.
  • the first start time is within the second numerical range.
  • the upper limit of the first time range is less than or equal to the lower limit of the second time range, and the upper limit of the first numerical range is greater than or equal to the lower limit of the second numerical range.
  • the starting time of the driving circuit 600 amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB is later. If the first time interval is relatively short, when the bit line BL and the local data line LIO are connected, and when the complementary bit line BLB and the complementary local data are connected, the smaller the voltage difference between the bit line BL and the complementary bit line BLB is, the easier it is for the local data line LIO and the complementary local data line LIOB to introduce noise to the bit line BL and the complementary bit line BLB.
  • the driving circuit 600 By delaying the starting time of the driving circuit 600 amplifying the voltage difference between the local data and the complementary local data line LIOB, the influence of the local data line LIO and the complementary local data line LIOB on the bit line BL and the complementary bit line BLB can be reduced, and the introduction of noise can be reduced.
  • the first starting time can also be adjusted by any one or more parameters of the process angle of the memory, the temperature of the memory, and the working voltage of the memory, so as to reduce the noise introduced on the bit line BL and the complementary bit line BLB.
  • the relationship between the process angle of the memory, the temperature of the memory, the working voltage of the memory and the first starting time can be determined by performing multiple tests on the memory.
  • the driving circuit 600 is used to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB by driving the voltage of the local data line LIO upward and/or driving the voltage of the complementary local data line LIOB upward.
  • the driving capability of driving the local data line LIO or the complementary local data line LIOB upward refers to the capability of increasing the voltage of the driving local data line LIO or the complementary local data line LIOB.
  • the voltage change rate is used as the measurement.
  • the driving capability of driving the local data line LIO upward is negatively correlated with the voltage on the complementary local data line LIOB, and the driving capability of driving the complementary local data line LIOB upward is negatively correlated with the voltage on the local data line LIO.
  • the voltage on the local data line LIO is greater than the voltage on the complementary local data line LIOB, that is, the voltage on the local data line LIO is relatively large, and the voltage on the complementary local data line LIOB is relatively small.
  • the driving ability of the driving circuit 600 to drive the complementary local data line LIOB upward is relatively weak.
  • the driving ability of the driving circuit 600 to drive the local data line LIO upward is relatively strong.
  • the driving ability of the driving circuit 600 to drive the complementary local data line LIOB upward is relatively weak, and the driving ability of the driving circuit 600 to drive the local data line LIO upward is relatively strong, the voltage on the local data line LIO will continue to be greater than the voltage on the complementary local data line LIOB, thereby amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the above example illustrates the principle that the driving circuit 600 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB when the voltage on the local data line LIO is greater than the voltage on the complementary local data line LIOB.
  • the principle is similar when the voltage on the local data line LIO is less than the voltage on the complementary local data line LIOB, and will not be repeated here.
  • the driving circuit 600 includes a switch unit 630, a first driving unit 610, and a second driving unit 620.
  • the switch unit 630 is connected to the first driving unit 610, and the switch unit 630 is connected to the second driving unit 620.
  • the first driving unit 610 connects the local data line LIO and the complementary local data line LIOB
  • the second driving unit 620 connects the local data line LIO and the complementary local data line LIOB.
  • the switch unit 630 controls the first driving unit 610 to be connected or disconnected with the first power supply terminal under the control of the first control signal RdEnN.
  • the switch unit 630 also controls the second driving unit 620 to be connected or disconnected with the first power supply terminal under the control of the first control signal RdEnN.
  • the voltage provided by the first power supply terminal is the power supply voltage VCC.
  • the first driving unit 610 drives the voltage of the local data line LIO upward according to the voltage of the complementary local data line LIOB when the first driving unit 610 is connected to the first power terminal
  • the second driving unit 620 drives the voltage of the complementary local data line LIOB upward according to the voltage of the local data line LIO when the second driving unit 620 is connected to the first power terminal.
  • the driving capability of the first driving unit 610 to drive the local data line LIO is negatively correlated with the voltage of the complementary local data line LIOB
  • the driving capability of the second driving unit 620 to drive the complementary local data line LIOB is negatively correlated with the voltage of the local data line LIO.
  • the first driving unit 610 and the second driving unit 620 are used to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB. After the voltage difference is generated between the local data line LIO and the complementary local data line LIOB, for example: the voltage on the local data line LIO is greater than the voltage on the complementary local data line LIOB, that is, the voltage on the local data line LIO is relatively large, and the voltage on the complementary local data line LIOB is relatively small.
  • the voltage on the complementary local data line LIOB is relatively small, and the driving ability of the first driving unit 610 driving circuit 600 to drive the local data line LIO upward is relatively strong.
  • the second driving unit 620 drives the complementary local data line upward.
  • the voltage on the local data line LIO will continue to be greater than the voltage on the complementary local data line LIOB, thereby amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the above example of the case where the voltage on the local data line LIO is greater than the voltage on the complementary local data line LIOB is used to illustrate the principle that the first driving unit 610 and the second driving unit 620 amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the principle is similar when the voltage on the local data line LIO is less than the voltage on the complementary local data line LIOB, and will not be repeated here.
  • the switch unit 630 is used to control whether the first driving unit 610 and the second driving unit 620 can amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the switch unit 630 controls the first power terminal to be connected to the first driving unit 610 and controls the first power terminal to be connected to the second driving unit 620
  • the first driving unit 610 and the second driving unit 620 can amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the switch unit 630 controls the first power terminal to be disconnected from the first driving unit 610 and controls the first power terminal to be disconnected from the second driving unit 620, the first driving unit 610 and the second driving unit 620 cannot amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the switch unit 630 controls the first driving unit 610 to connect to the first power supply terminal and controls the second driving unit 620 to connect to the first power supply terminal after the local data line LIO and the complementary local data line LIOB are charged to the pre-charge voltage, so as to avoid the equalization circuit 500 being unable to charge the local data line LIO and the complementary local data line LIOB to the pre-charge voltage due to the first driving unit 610 and the second driving unit 620 being connected to the first power supply terminal all the time.
  • the switch unit 630 is set to control whether the first driving unit 610 and the second driving unit 620 can be connected to the first power supply end, so as to achieve isolation between the first power supply end and the second power supply end, thereby avoiding the situation where the first driving unit 610 and the second driving unit 620 always amplify the voltage difference between the local data line LIO and the complementary local data line LIOB, so that the equalization circuit 500 cannot charge the voltage of the local data line LIO and the complementary local data line LIOB to the pre-charge voltage, thereby causing the data to be unable to be accurately transmitted from the bit line BL to the local data line LIO.
  • the first driving unit 610 includes a first P-type transistor P1, a source of the first P-type transistor P1 is connected to the switch unit 630, a drain of the first P-type transistor P1 is connected to the local data line LIO, and a gate of the first P-type transistor P1 is connected to the complementary local data line LIOB.
  • the second driving unit 620 includes a second P-type transistor P2, a source of the second P-type transistor P2 is connected to the switch unit 630, a drain of the second P-type transistor P2 is connected to the complementary local data line LIOB, and a gate of the second P-type transistor P2 is connected to the local data line LIO.
  • the switch unit 630 includes a third P-type transistor P3, the source of the third P-type transistor P3 is connected to the first power supply terminal, the drain of the third P-type transistor P3 is connected to the source of the first P-type transistor P1, the drain of the third P-type transistor P3 is also connected to the source of the second P-type transistor P2, and the gate of the third P-type transistor P3 receives the first control signal RdEnN.
  • the third P-type transistor P3 is turned on, and the source of the first P-type transistor P1 is controlled to be connected to the first power supply terminal, and the source of the second P-type transistor P2 is connected to the first power supply terminal.
  • a voltage difference is generated on the local data line LIO and the complementary local data line LIOB, for example: the voltage on the local data line LIO is greater than the voltage on the complementary local data line LIOB, that is, the voltage on the local data line LIO is relatively large, and the voltage on the complementary local data line LIOB is relatively small.
  • the voltage on the complementary local data line LIOB is relatively small, and the driving ability of the first P-type transistor P1 to drive the local data line LIO upward is relatively strong.
  • the driving ability of the second P-type transistor P2 to drive the complementary local data line LIOB upward is relatively weak.
  • the driving ability of the first P-type transistor P1 to drive the local data line LIO upward is relatively strong, and the driving ability of the second P-type transistor P2 to drive the complementary local data line LIOB upward is relatively weak, the voltage on the local data line LIO will continue to be greater than the voltage on the complementary local data line LIOB, thereby amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the above uses the example that the voltage on the local data line LIO is greater than the voltage on the complementary local data line LIOB to illustrate the principle that the first P-type transistor P1 and the second P-type transistor P2 amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the principle is similar when the voltage on the local data line LIO is less than the voltage on the complementary local data line LIOB, and will not be repeated here.
  • the driving circuit 600 further includes a first control circuit 700, wherein a first output terminal of the first control circuit 700 is connected to a control terminal of the switch unit 630, and a second output terminal of the first control circuit 700 is connected to a control terminal of the secondary amplifier circuit 200.
  • a first input terminal of the first control circuit 700 receives a mode signal CTRLPin, and a second input terminal of the first control circuit 700 receives a reference signal RdEnPre.
  • the first control circuit 700 is configured to generate a first control signal RdEnN according to the mode signal CTRLPin and the reference signal RdEnPre, and to generate a second control signal RdEn according to the reference signal RdEnPre.
  • the first control signal RdEnN controls the driving circuit 600 to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB
  • the second control signal RdEn controls the secondary amplifying circuit 200 to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the first control signal RdEnN is low level effective, and the second control signal RdEn is high level effective.
  • the control driving circuit 600 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the control secondary amplifier circuit 200 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the first control signal RdEnN is in the valid state at the start time t2 Before the start time t3 when the second control signal RdEn is in the effective state, the control driving circuit 600 first amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB, and then the secondary amplification circuit 200 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the driving circuit 600 first amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB to compensate for the influence of the coupling capacitor on the voltage of the local data line LIO, and then the secondary amplification circuit 200 and the driving circuit 600 amplify the voltage difference between the local data line LIO and the complementary local data line LIOB together, and generate a voltage difference between the global data line GIO and the complementary global data line GIOB, shortening the time for the secondary amplification circuit 200 to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB, thereby improving the performance of the timing parameter tCCD of the memory.
  • the start time t2 at which the first control signal RdEnN is in a valid state is later than the end time t0 at which the equalization control signal EQLOB is in a valid state.
  • the equalization control signal EQLOB is in a valid state, the voltages of the local data line LIO and the complementary local data line LIOB are charged to a pre-charge voltage.
  • the equalization control signal EQLOB is a low-level active signal, that is, when the equalization control signal EQLOB is at a low level, the voltages of the local data line LIO and the complementary local data line LIOB are charged to a precharge voltage.
  • the control driving circuit 600 and the secondary amplifier circuit 200 amplify the voltage difference between the local data line LIO and the complementary local data line LIOB, thereby realizing accurate transmission of data between the bit line BL and the local data line LIO, and between the complementary bit line BLB and the complementary local data line LIOB.
  • the mode signal CTRLPin is used to adjust the start time t2 when the first control signal RdEnN is in the valid state, that is, to adjust the start time when the driving circuit 600 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the minimum value t2min of the start time when the first control signal RdEnN is in the valid state is the end time when the equalization control signal EQLOB is in the valid state
  • the maximum value t2max of the start time when the first control signal RdEnN is in the valid state is the start time when the second control signal RdEn is in the valid state.
  • the first control circuit 700 is used to determine the time step between the reference signal RdEnPre and the first control signal RdEnN according to the mode signal CTRLPin, and process the reference signal RdEnPre according to the time step to generate the first control signal RdEnN.
  • the time step can be a positive time step, marked as ⁇ . It can also be a negative time step, marked as - ⁇ .
  • a positive time step means that the starting time t2 of the first control signal RdEnN being in the effective state is later than the starting time t1 of the reference signal RdEnPre being in the effective state, and there is a difference ⁇ between t1 and t2.
  • a negative time step means that the starting time t2 of the first control signal RdEnN being in the effective state is earlier than the starting time t1 of the reference signal RdEnPre being in the effective state, and there is a difference ⁇ between t1 and t2.
  • the mode signal CTRLPin is a function of the first time interval, the process angle of the memory, the temperature of the memory, and the The first time interval is the time interval between adjacent row addressing and column addressing of the memory.
  • the mode signal CTRLPin is determined by a first time interval. The shorter the first time interval, the larger the time step corresponding to the mode signal CTRLPin, so that the starting time when the first control signal RdEnN is in a valid state is later.
  • the time step is a negative time step - ⁇
  • the smaller the absolute value of the negative time step - ⁇ the larger the negative time step.
  • the time step is a positive time step ⁇
  • the larger the absolute value of the positive time step ⁇ the larger the positive time step.
  • the mode signal CTRLPin is determined by any one or more parameters of the process angle of the memory, the temperature of the memory, and the working voltage of the memory.
  • the relationship between the process angle of the memory, the temperature of the memory, the working voltage of the memory, and the start time when the first control signal RdEnN is in the valid state can be determined by performing multiple tests on the memory, so as to achieve the purpose of reducing the noise introduced on the bit line BL and the complementary bit line BLB.
  • the start time for the driving circuit 600 to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB is adjusted, thereby reducing the noise introduced by the local data line LIO and the complementary local data line LIOB to the bit line BL and the complementary bit line BLB, thereby achieving accurate data transmission.
  • the reference signal RdEnPre is the column selection signal CSL.
  • the second control circuit 400 controls the connection or disconnection between the bit line BL and the local data line LIO, and is also used to control the connection or disconnection between the complementary bit line BLB and the complementary local data line LIOB.
  • the reference signal RdEnPre is not limited to the column selection signal CSL, but may be any other signal as long as the first control signal RdEnN satisfies the above timing relationship, which is not limited here.
  • the column selection signal CSL is at a low level
  • the bit line BL is disconnected from the local data line LIO
  • the complementary bit line BLB is disconnected from the complementary local data line LIOB.
  • the memory cell stores data "1”, and the memory cell shares charge with the bit line BL, generating a small voltage difference ⁇ BL1 between the bit line BL and the complementary bit line BLB.
  • the first-stage amplifier circuit 100 amplifies the small voltage difference ⁇ BL1 between the bit line BL and the complementary bit line BLB in the T1 phase, for example, to a voltage difference ⁇ BL2.
  • the column selection signal CSL is at a high level
  • the bit line BL is connected to the local data line LIO
  • the complementary bit line BLB is connected to the complementary local data line LIOB
  • the data on the bit line BL and the complementary bit line BLB are transmitted to the local data line LIO and the complementary local data line LIOB.
  • the local data lines LIO ⁇ 2> and LIO ⁇ 3> on both sides have a voltage jump due to the transmission of data "0", and the local data line LIO ⁇ 1> in the middle transmits data "1", that is, the voltage of the local data line LIO in the middle is close to the pre-charge voltage VintLP, then the local data lines LIO ⁇ 2> and LIO ⁇ 3> on both sides will affect the voltage on the middle local data line LIO ⁇ 0> due to the coupling capacitor.
  • the first control signal RdEnN is at a low level
  • the third P-type transistor P3 is turned on
  • the first P-type transistor P1 drives the voltage on the local data line LIO upward
  • the second P-type transistor P2 drives the voltage on the complementary local data line LIOB upward
  • the driving ability of the first P-type transistor P1 to pull the local data line LIO upward is greater than the driving ability of the second P-type transistor P2 to pull the complementary local data line LIOB upward, compensating for the influence of the local data lines LIO ⁇ 2> and LIO ⁇ 3> on the voltage of the middle local data line LIO ⁇ 0>
  • the complementary bit line BLB drives the voltage of the complementary local data line LIOB downward, compensating for the influence of the local data lines LIO ⁇ 2> and LIO ⁇ 3> on the voltage of the middle local data line LIO ⁇ 0>, and at the same time amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • the second control signal RdEn is at a high level, and the secondary amplifier circuit 200 starts to amplify the voltages on the local data line LIO and the complementary local data line LIOB.
  • the driving circuit 600 since the driving circuit 600 has amplified the voltage difference between the local data line LIO and the complementary local data line LIOB, the voltage difference ⁇ LIO2 is already relatively large.
  • the secondary amplifier circuit 200 and the driving circuit 600 amplify the voltage difference between the local data line LIO and the complementary local data line LIOB together, which can shorten the time for the secondary amplifier circuit 200 to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.
  • FIG. 7 takes the storage of data “1” in a storage unit as an example for explanation.
  • the storage of data “0” in a storage unit is similar to the storage of data “1”, and will not be described in detail here.
  • the start time when the first control signal RdEnN is in the valid state can be adjusted at the start time indicated by RdEnN1 and the start time indicated by RdEnN2 to adjust the magnitude of the noise introduced by the local data line LIO and the complementary local data line LIOB to the bit line BL and the complementary bit line BLB.

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Abstract

本公开提供一种存储器，包括一级放大电路，连接位线和互补位线，用于放大位线和互补位线上的电压差；二级放大电路，连接局部数据线和互补局部数据线，还连接全局数据线和互补全局数据线，在局部数据线与位线之间接通，以及互补局部数据线与互补位线之间接通后，放大局部数据线和互补局部数据线上的电压差，并在全局数据线和互补全局数据线上产生电压差；驱动电路，连接局部数据线和互补局部数据线，放大局部数据线和互补局部数据线上的电压差。通过如此设置，补偿由于耦合电容对局部数据线电压的影响，可以缩短放大局部数据线和互补局部数据线上的电压差的时间，提升存储器的时序参数性能。

Description

存储器
本申请要求于2022年11月04日提交中国专利局、申请号为202211376117.0、申请名称为“存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及但不限定于一种存储器。
背景技术
随着手机、平板、个人计算机等电子设备的普及，半导体存储器技术也得到了快速的发展。
在动态随机存取存储器(Dynamic Random Access Memory，DRAM)中，设有多级放大电路，通过多级放大电路放大电压差，实现对存储单元中读出或者写入数据。对于多级放大电路的改进可以提升存储器的性能。
发明内容
本公开提供一种存储器，包括：
一级放大电路，连接位线和互补位线，用于放大位线和互补位线上的电压差；
二级放大电路，连接局部数据线和互补局部数据线，还连接全局数据线和互补全局数据线，在局部数据线与位线之间接通，以及互补局部数据线与互补位线之间接通后，放大局部数据线和互补局部数据线上的电压差，并在全局数据线和互补全局数据线上产生电压差；
驱动电路，连接局部数据线和互补局部数据线，放大局部数据线和互补局部数据线上的电压差。
在一些实施例中，存储器还包括：
均衡电路，连接局部数据线和互补局部数据线，在局部数据线与位线之间接通，以及互补局部数据线与互补位线之间接通之前，将局部数据线和互补局部数据线的电压充电至预充电电压；
驱动电路用于在局部数据线和互补局部数据线的电压充电至预充电电压后，放大局部数据线和互补局部数据线上的电压差。
在一些实施例中，驱动电路放大局部数据线和互补局部数据线上的电压差的起始时刻，早于二级放大电路放大局部数据线和互补局部数据线上的电压差的起始时刻。
在一些实施例中，当第一时间间隔位于第一时间范围内时，第一起始时刻位于第一数值范围；
当第一时间间隔位于第二时间范围内时，第一起始时刻位于第二数值范围；
其中，第一时间间隔为存储器的相邻的行寻址到列寻址之间的时间间隔，第一起始时刻为驱动电路开始放大局部数据线和互补局部数据线上的电压差的起始时刻；
第一时间范围的上限值小于或等于第二时间范围的下限值，第一数值范围的上限值大于或等于第二数值范围的下限值。
在一些实施例中，驱动电路用于：
通过向上驱动局部数据线的电压和/或互补局部数据线的电压，实现放大局部数据线和互补局部数据线上的电压差；
其中，向上驱动局部数据线的驱动能力与互补局部数据线上的电压负相关，向上驱动互补局部数据线的驱动能力与局部数据线上的电压负相关。
在一些实施例中，驱动电路包括：
开关单元，与第一驱动单元和第二驱动单元连接，在第一控制信号的控制下控制第一驱动单元与第一电源端接通或者断开，以及在第一控制信号的控制下控制第二驱动单元与第一电源端接通或者断开；第一电源端提供电源电压；
第一驱动单元，连接局部数据线和互补局部数据线，在第一驱动单元接通第一电源端时根据互补局部数据线的电压向上驱动局部数据线的电压；
第二驱动单元，连接局部数据线和互补局部数据线，在第二驱动单元接通第一电源端时根据局部数据线的电压向上驱动互补局部数据线的电压。
在一些实施例中，第一驱动单元驱动局部数据线驱动能力与互补局部数据线的电压负相关；
第二驱动单元驱动互补局部数据线驱动能力与局部数据线的电压负相关。
在一些实施例中，第一驱动单元包括：
第一P型晶体管，源极连接开关单元，漏极连接局部数据线，栅极连接互补局部数据线；
第二驱动单元包括：
第二P型晶体管，源极连接开关单元，漏极连接互补局部数据线，栅极连接局部数据线。
在一些实施例中，开关单元包括：
第三P型晶体管，源极连接第一电源端，漏极连接第一P型晶体管的源极，漏极还连接第二P型晶体管的源极，栅极接收第一控制信号。
在一些实施例中，驱动电路还包括：
第一控制电路，第一输出端连接开关单元的控制端，第二输出端连接二级放大电路的控制端；第一输入端接收模式信号，第二输入端接收基准信号，用于根据模式信号和基准信号生成第一控制信号，并根据基准信号生成第二控制信号；
其中，第一控制信号为有效状态的起始时刻早于第二控制信号为有效状态的起始时刻，第二控制信号控制二级放大电路放大局部数据线和互补局部数据线上的电压差。
在一些实施例中，第一控制信号为有效状态的起始时刻晚于均衡控制信号为有效状态的终止时刻，均衡控制信号处于有效状态时将局部数据线和互补局部数据线的电压充电至预充电电压。
在一些实施例中，控制电路用于：
根据模式信号确定基准信号和第一控制信号之间的时间步长；
根据时间步长对基准信号进行处理生成第一控制信号。
在一些实施例中，模式信号是第一时间间隔、存储器的工艺角、存储器的温度和存储器的工作电压中任意一种或多种参数确定的；
其中，第一时间间隔为存储器的相邻的行寻址到列寻址之间的时间间隔。
在一些实施例中，基准信号为列选择信号，列选择信号用于控制位线和局部数据线之间接通或断开，以及还用于控制互补位线和互补局部数据线之间接通或断开。
在一些实施例中，存储器还包括：
第二控制电路，连接位线和互补位线，还连接局部数据线和互补局部数据线，用于接收列选择信号，在列选择信号的控制下控制位线和局部数据线之间接通或者断开，以及在列选择信号的控制下控制互补位线和互补局部数据线之间接通或者断开。
在一些实施例中，存储器还包括：
三级放大电路，连接全局数据线和互补全局数据线，用于放大全局数据线和互补全局数据线上的电压差。
本公开提供的存储器，包括一级放大电路、二级放大电路以及驱动电路，一级放大电路连接位线和互补位线，一级放大电路放大位线和互补位线上的电压差，驱动电路和二级放大电路均连接局部数据线和互补局部数据线，二级放大电路还连接全局数据线和互补全局数据线，在局部数据线和互补局部数据线上产生电压差后，二级放大电路放大局部数据线和互补局部数据线上的电压差，并在全局数据线和互补全局数据线上产生电压差，驱动电路也用于放大局部数据线和互补局部数据线上的电压差，补偿由于耦合电容对局部数据线电压的影响，可以缩短放大局部数据线和互补局部数据线上的电压差的时间，提升存储器的时序参数性能。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1为一种存储器的电路示意图；
图2为一种存储器中局部数据线的布线图；
图3为一种存储器中耦合电容对局部数据线电压影响的原理示意图；
图4为一种存储器中存在耦合电容对局部数据线电压影响时的工作原理图；
图5为本公开一实施例提供的存储器的电路示意图；
图6为本公开一实施例提供的存储器的工作时序图；
图7为本公开一实施例提供的存储器的工作原理图。
附图标记：
100、一级放大电路；200、二级放大电路；300、三级放大电路；400、第二控制
电路；500、均衡电路；600、驱动电路；700、第一控制电路；610、第一驱动单元；620、第二驱动单元；630、开关单元；BL、位线；BLB、互补位线；LIO、局部数据线；LIOB、互补局部数据线；GIO、全局数据线；GIOB、互补全局数据线；M1、第一晶体管；M2、第二晶体管；CSL、列选择信号；VintLP、第二电源端；RdEnN、第一控制信号；RdEn、第二控制信号；CTRLPin、模式信号；RdEnPre、基准信号；P1、第一P型晶体管；P2、第二P型晶体管；P3、第三P型晶体管；EQLOB、均衡控制信号。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
如图1所示，一种存储器包括一级放大电路100、二级放大电路200、三级放大电路300、第二控制电路400以及均衡电路500。一级放大电路100连接位线BL和互补位线BLB，一级放大电路100用于放大位线BL和互补位线BLB上的电压差。二级放大电路200连接局部数据线LIO和互补局部数据线LIOB，二级放大电路200还连接全局数据线GIO和互补全局数据线GIOB，二级放大电路200用于放大局部数据线LIO和互补局部数据线LIOB上的电压差，并在全局数据线GIO和互补全局数据线GIOB上产生电压差。三级放大电路300用于放大全局数据线GIO和互补全局数据线GIOB上的电压差。
第二控制电路400连接位线BL和互补位线BLB，第二控制电路400连接局部数据线LIO和互补局部数据线LIOB。第二控制电路400用于控制位线BL和局部数据线LIO之间的接通或者断开，第二控制电路400还用于控制互补位线BLB和互补局部数据线LIOB之间的接通或者断开。
均衡电路500连接局部数据线LIO和互补局部数据线LIOB。均衡电路500用于在位线BL和局部数据线LIO之间接通之前，以及互补位线BLB和互补局部数据线LIOB之间接通之前，将局部数据线LIO和互补局部数据线LIOB均充电至预充电电压VCC。
在位线BL和局部数据线LIO之间接通之前，以及互补位线BLB和互补局部数据线LIOB之间接通之前，存储单元与位线BL之间进行电荷共享，在位线BL和互补位线BLB上产生微小的电压差，一级放大电路100放大位线BL和互补位线BLB上微小的电压差。
在位线BL和局部数据线LIO之间接通，以及在互补位线BLB和互补局部数据线LIOB之间接通之后，位线BL和互补位线BLB在局部数据线LIO和互补局部数据线LIOB上产生电压差，二级放大电路200再放大局部数据线LIO和互补局部数据线LIOB上的电压差，实现数据从位线BL和互补位线BLB传输至局部数据线LIO和互补局部数据线LIOB。
图2为存储器中部分的局部数据线LIO的布线图，多个局部数据线LIO依次排列，两个局部数据线LIO之间会存在耦合电容，耦合电容上出现电压跳变时会对于局部数据线LIO上的电压有影响。
例如：将图2中4条局部数据线LIO从上到下依次标记为局部数据线LIO<2>，局部数据线LIO<0>，局部数据线LIO<3>和局部数据线LIO<1>。局部数据线LIO<2>和局部数据线LIO<3>之间存在耦合电容。
如图3，当局部数据线LIO<2>和局部数据线LIO<3>由于传输数据“0”，电压从预充电电压VCC下降成数据“0”对应电压，而局部数据线LIO<0>上传输数据“1”，电压仍接近预充电电压VCC。由于局部数据线LIO<2>和局部数据线LIO<3>上有电压跳变，局部数据线LIO<2>和局部数据线LIO<3>之间耦合电容影响会拉低局部数据线LIO<0>上电压。
如图4所示，在二级放大电路放大局部数据线LIO<0>和互补局部数据线LIOB<0>上电压差时，此时电压差ΔLIO1数值比较小，二级放大电路200将局部数据线LIO<0>和互补局部数据线LIOB<0>之间电压差放大至预设值的时间更长。存储器的时序参数tCCD是指上一个列地址选通脉冲和下一个列地址选通脉冲之间的时间间隔，二级放大电路200放大局部数据线LIO和互补局部数据线LIOB之间电压差变长时，会使存储器的时序参数tCCD变差。
如图5所示，本公开一实施例提供一种存储器，包括一级放大电路100、二级放大电路200以及驱动电路600。
其中，一级放大电路100连接位线BL和互补位线BLB，二级放大电路200连接局部数据线LIO和互补局部数据线LIOB，二级放大电路200还连接全局数据线GIO和互补全局数据线GIOB。驱动电路600连接局部数据线LIO和互补局部数据线LIOB。
局部数据线LIO与位线BL之间断开，以及互补局部数据线LIOB与互补位线BLB之间断开，存储单元与位线BL进行电荷共享，在位线BL和互补位线BLB上产生微小电压差，一级放大电路100用于放大位线BL和互补位线BLB上的微小电压差。
在局部数据线LIO与位线BL之间接通后，以及互补局部数据线LIOB与互补位线BLB之间接通后，位线BL驱动局部数据线LIO，互补位线BLB驱动互补局部数据线LIOB，在局部数据线LIO和互补局部数据线LIOB上产生电压差，二级放大电路200放大局部数据线LIO和互补局部数据线LIOB上的电压差，并在全局数据线GIO和互补全局数据线GIOB上产生电压差。在局部数据线LIO和互补局部数据线LIOB上产生电压差后，驱动电路600也放大局部数据线LIO和互补局部数据线LIOB上的电压差。
在上述技术方案中，设置连接局部数据线LIO和互补局部数据线LIOB的驱动电路600，在局部数据线LIO和互补局部数据线LIOB上产生电压差后，二级放大电路200放大局部数据线LIO和互补局部数据线LIOB上的电压差，驱动电路600也用于放大局部数据线LIO和互补局部数据线LIOB上的电压差，补偿由于耦合电容对局部数据线LIO电压的影响，可以缩短放大局部数据线LIO和互补局部数据线LIOB上的电压差的时间，提升存储器的时序参数tCCD。
在一些实施例中，继续参考图5，存储器还包括均衡电路500，均衡电路500连接局部数据线LIO和互补局部数据线LIOB。在局部数据线LIO与位线BL之间接通之前，以及互补局部数据线LIOB与互补位线BLB之间接通之前，均衡电路500将局部数据线LIO和互补局部数据线LIOB的电压充电至预充电电压。
在均衡电路500将局部数据线LIO和互补局部数据线LIOB的电压充电至预充电电压后，控制位线BL与局部数据线LIO之间接通，控制互补位线BLB和互补局部数据线LIOB之间接通，位线BL和互补位线BLB在局部数据线LIO和互补局部数据线LIOB之间产生电压差，驱动电路600放大局部数据线LIO和互补局部数据线LIOB上的电压差，二级放大电路200也放大局部数据线LIO和互补局部数据线LIOB上的电压差。
在一些实施例中，继续参考图5，均衡电路500连接第二电源端，第二电源端的电压VintLP是可调的，使预充电电压也是可调的，可根据存储器的时序参数调整第二电源端的提供电压VintLP，实现对局部数据线LIO和互补局部数据线LIOB上预充电电压的调整。
在一些实施例中，在局部数据线LIO和互补局部数据线LIOB被充电至预充电电压之后，在位线BL和局部数据线LIO之间接通之前，以及在互补位线BLB和互补局部数据线LIOB接通之前，使驱动电路600接通，处于等待状态，在位线BL和局部数据线LIO之间接通之后，以及在互补位线BLB和互补局部数据线LIOB接通之后，位线BL和互补位线BLB在局部数据线LIO和互补局部数据线LIOB之间产生电压差，驱动电路600放大局部数据线LIO和互补局部数据线LIOB之间电压差。
在一些实施例中，在位线BL和局部数据线LIO之间接通之后，以及在互补位线BLB和互补局部数据线LIOB接通之后，使驱动电路600接通，驱动电路600直接放大局部数据线LIO和互补局部数据线LIOB之间电压差，无需进入等待状态。
在上述技术方案中，在局部数据线LIO和互补局部数据线LIOB的电压充电至预充电电压后，控制驱动电路600和二级放大电路200放大局部数据线LIO和互补局部数据线LIOB上的电压差，实现数据在位线BL和局部数据线LIO之间，以及互补位线BLB和互补局部数据线LIOB之间准确传输。
在一些实施例中，继续参考图5，存储器还包括第二控制电路400，第二控制电路400连接位线BL和互补位线BLB，第二控制电路400还连接局部数据线LIO和互补局部数据线LIOB，第二控制电路400用于接收列选择信号CSL，第二控制电路400在列选择信号CSL的控制下控制位线BL和局部数据线LIO之间接通或者断开，以及在列选择信号CSL的控制下控制互补位线BLB和互补局部数据线LIOB之间接通或者断开。
在一些实施例中，继续参考图5，第二控制电路400包括第一晶体管M1和第二晶体管M2，第一晶体管M1的源极或者漏极连接位线BL，第一晶体管M1的漏极或者源极连接局部数据线LIO，第一晶体管M1的栅极连接列选择线，接收列选择信号CSL。第二晶体管M2的源极或者漏极连接互补位线BLB，第二晶体管M2的漏极或者源极连接互补局部数据线LIOB，第二晶体管M2的栅极连接列选择线，接收列选择信号CSL。
第一晶体管M1和第二晶体管M2在列选择信号CSL的控制下导通或截止，控制位线BL和局部数据线LIO之间接通或断开，互补位线BLB和互补局部数据线LIOB之间接通或断开。
在一些实施例中，第一晶体管M1和第二晶体管M2为N型晶体管，列选择信号CSL为高电平时控制第一晶体管M1和第二晶体管M2导通。
在一些实施例中，继续参考图5，存储器还包括三级放大电路300，三级放大电路300连接全局数据线GIO和互补全局数据线GIOB，三级放大电路300用于放大全局数据线GIO和互补全局数据线GIOB上的电压差。
在一些实施例中，驱动电路600放大局部数据线LIO和互补局部数据线LIOB上的电压差的起始时刻，早于二级放大电路200放大局部数据线LIO和互补局部数据线LIOB上的电压差的起始时刻。通过如此设置，在位线BL和互补位线BLB在局部数据线LIO和互补局部数据线LIOB上产生电压差后，由驱动电路600先放大局部数据线LIO和互补局部数据线LIOB上的电压差，补偿由于耦合电容对局部数据线LIO电压的影响，再由二级放大电路200和驱动电路600一起放大局部数据线LIO和互补局部数据线LIOB上的电压差，并在全局数据线GIO和互补全局数据线GIOB上产生电压差，缩短二级放大电路200放大局部数据线LIO和互补局部数据线LIOB上电压差的时间，提升存储器的时序参数tCCD的性能。
在一些实施例中，第一时间间隔为存储器的相邻的行寻址到列寻址之间的时间间隔tRCD，也就是，相邻的激活命令到读命令之间的时间间隔，或者是，相邻的激活命令到写命令之间的时间间隔。也就是，从开启字线到开启列选择线的时间间隔。
第一起始时刻为驱动电路600放大局部数据线LIO和互补局部数据线LIOB上的电压差的起始时刻。
当第一时间间隔位于第一时间范围内时，第一起始时刻位于第一数值范围。当第一时间间隔位于第二时间范围内时，第一起始时刻位于第二数值范围。第一时间范围的上限值小于或等于第二时间范围的下限值，第一数值范围的上限值大于或等于第二数值范围的下限值。
当第一时间间隔越短，驱动电路600放大局部数据线LIO和互补局部数据线LIOB上的电压差的起始时刻越晚。若第一时间间隔比较短，在位线BL和局部数据线LIO之间接通时，以及互补位线BLB和互补局部数据之间接通时，位线BL和互补位线BLB上的电压差越小，局部数据线LIO和互补局部数据线LIOB越容易向位线BL和互补位线BLB的引入噪声。通过延迟驱动电路600放大局部数据和互补局部数据线LIOB上电压差的起始时刻，可以减少局部数据线LIO和互补局部数据线LIOB对位线BL和互补位线BLB的影响，减少噪声引入。
在一些实施例中，第一起始时刻还可以存储器的工艺角、存储器的温度和存储器的工作电压中任意一种或多种参数进行调节，达到降低位线BL和互补位线BLB上噪声引入的目的。可通过对存储器进行多次测试，确定存储器的工艺角、存储器的温度和存储器的工作电压与第一起始时刻之间关系。
在一些实施例中，驱动电路600用于通过向上驱动局部数据线LIO的电压和/或向上驱动互补局部数据线LIOB的电压，实现放大局部数据线LIO和互补局部数据线LIOB上的电压差。其中，向上驱动局部数据线LIO或者互补局部数据线LIOB的驱动能力是指使驱动局部数据线LIO或者互补局部数据线LIOB电压升高的能力，可以 用电压变化速率衡量。向上驱动局部数据线LIO的驱动能力是与互补局部数据线LIOB上的电压负相关的，向上驱动互补局部数据线LIOB的驱动能力是与局部数据线LIO上的电压负相关的。
在局部数据线LIO和互补局部数据线LIOB上产生电压差后，例如：局部数据线LIO上电压大于互补局部数据线LIOB上的电压，也就是局部数据线LIO上电压比较大，互补局部数据线LIOB上电压比较小。局部数据线LIO上电压比较大时，驱动电路600向上驱动互补局部数据线LIOB的驱动能力较弱。互补局部数据线LIOB上电压比较小，驱动电路600向上驱动局部数据线LIO的驱动能力较强。在驱动电路600向上驱动互补局部数据线LIOB的驱动能力较弱，驱动电路600向上驱动局部数据线LIO的驱动能力较强时，则会使局部数据线LIO上电压继续大于互补局部数据线LIOB上的电压，实现放大局部数据线LIO和互补局部数据线LIOB上的电压差。
上面以局部数据线LIO上电压大于互补局部数据线LIOB上的电压为例说明，驱动电路600放大局部数据线LIO和互补局部数据线LIOB上的电压差的原理，局部数据线LIO上电压小于互补局部数据线LIOB上的电压时的原理相似，此处不再赘述。
在一些实施例中，驱动电路600包括开关单元630、第一驱动单元610以及第二驱动单元620。开关单元630与第一驱动单元610连接，开关单元630与第二驱动单元620连接。第一驱动单元610连接局部数据线LIO和互补局部数据线LIOB，第二驱动单元620连接局部数据线LIO和互补局部数据线LIOB。
开关单元630在第一控制信号RdEnN的控制下控制第一驱动单元610与第一电源端接通或者断开，开关单元630还在第一控制信号RdEnN的控制下控制第二驱动单元620与第一电源端接通或者断开，第一电源端提供电压为电源电压VCC。
第一驱动单元610在第一驱动单元610接通第一电源端时根据互补局部数据线LIOB的电压向上驱动局部数据线LIO的电压，第二驱动单元620在第二驱动单元620接通第一电源端时根据局部数据线LIO的电压向上驱动互补局部数据线LIOB的电压。
其中，第一驱动单元610驱动局部数据线LIO驱动能力与互补局部数据线LIOB的电压负相关，第二驱动单元620驱动互补局部数据线LIOB驱动能力与局部数据线LIO的电压负相关。
第一驱动单元610和第二驱动单元620用于放大局部数据线LIO和互补局部数据线LIOB上的电压差。在局部数据线LIO和互补局部数据线LIOB上产生电压差后，例如：局部数据线LIO上电压大于互补局部数据线LIOB上的电压，也就是局部数据线LIO上电压比较大，互补局部数据线LIOB上电压比较小。互补局部数据线LIOB上电压比较小，第一驱动单元610驱动电路600向上驱动局部数据线LIO的驱动能力较强。局部数据线LIO上电压比较大时，第二驱动单元620向上驱动互补局部数据线 LIOB的驱动能力较弱。在第一驱动单元610向上驱动局部数据线LIO的驱动能力较强，第二驱动单元620向上驱动互补局部数据线LIOB的驱动能力较弱时，则会使局部数据线LIO上电压继续大于互补局部数据线LIOB上的电压，实现放大局部数据线LIO和互补局部数据线LIOB上的电压差。
上面以局部数据线LIO上电压大于互补局部数据线LIOB上的电压为例说明第一驱动单元610和第二驱动单元620放大局部数据线LIO和互补局部数据线LIOB上的电压差的原理，局部数据线LIO上电压小于互补局部数据线LIOB上的电压时的原理相似，此处不再赘述。
开关单元630用于控制第一驱动单元610和第二驱动单元620是否能够放大局部数据线LIO和互补局部数据线LIOB上的电压差。
在开关单元630控制第一电源端与第一驱动单元610接通，以及控制第一电源端与第二驱动单元620接通时，第一驱动单元610和第二驱动单元620能够放大局部数据线LIO和互补局部数据线LIOB上的电压差。
在开关单元630控制第一电源端与第一驱动单元610断开，以及控制第一电源端与第二驱动单元620断开时，第一驱动单元610和第二驱动单元620无法放大局部数据线LIO和互补局部数据线LIOB上的电压差。
在一些实施例中，开关单元630在局部数据线LIO和互补局部数据线LIOB被充电至预充电电压后控制第一驱动单元610接通第一电源端，以及控制第二驱动单元620接通第一电源端，避免由于第一驱动单元610和第二驱动单元620一直接通第一电源端，而使均衡电路500无法将局部数据线LIO和互补局部数据线LIOB充电至预充电电压。
在上述技术方案中，通过设置开关单元630控制第一驱动单元610和第二驱动单元620是否能够接通第一电源端，实现第一电源端和第二电源端之间的隔离，避免由于使第一驱动单元610和第二驱动单元620一直放大局部数据线LIO和互补局部数据线LIOB上的电压差，而使均衡电路500无法将局部数据线LIO和互补局部数据线LIOB的电压充电至预充电压，进而导致数据无法从位线BL向局部数据线LIO准确传输。
在一些实施例中，第一驱动单元610包括第一P型晶体管P1，第一P型晶体管P1的源极连接开关单元630，第一P型晶体管P1的漏极连接局部数据线LIO，第一P型晶体管P1的栅极连接互补局部数据线LIOB。
第二驱动单元620包括第二P型晶体管P2，第二P型晶体管P2源极连接开关单元630，第二P型晶体管P2漏极连接互补局部数据线LIOB，第二P型晶体管P2栅极连接局部数据线LIO。
开关单元630包括第三P型晶体管P3，第三P型晶体管P3源极连接第一电源端，第三P型晶体管P3漏极连接第一P型晶体管P1的源极，第三P型晶体管P3漏极还连接第二P型晶体管P2的源极，第三P型晶体管P3栅极接收第一控制信号RdEnN。
P型晶体管的栅极电压越低，则P型晶体管的导通电流越大，P型晶体管对电压的向上拉动能力越强。
第三P型晶体管P3导通，控制第一P型晶体管P1的源极接通第一电源端，第二P型晶体管P2的源极接通第一电源端。在局部数据线LIO和互补局部数据线LIOB上产生电压差后，例如：局部数据线LIO上电压大于互补局部数据线LIOB上的电压，也就是局部数据线LIO上电压比较大，互补局部数据线LIOB上电压比较小。互补局部数据线LIOB上电压比较小，第一P型晶体管P1向上驱动局部数据线LIO的驱动能力较强。局部数据线LIO上电压比较大时，第二P型晶体管P2向上驱动互补局部数据线LIOB的驱动能力较弱。在第一P型晶体管P1向上驱动局部数据线LIO的驱动能力较强，第二P型晶体管P2向上驱动互补局部数据线LIOB的驱动能力较弱时，则会使局部数据线LIO上电压继续大于互补局部数据线LIOB上的电压，实现放大局部数据线LIO和互补局部数据线LIOB上的电压差。
上面以局部数据线LIO上电压大于互补局部数据线LIOB上的电压为例说明第一P型晶体管P1和第二P型晶体管P2放大局部数据线LIO和互补局部数据线LIOB上的电压差的原理，局部数据线LIO上电压小于互补局部数据线LIOB上的电压时的原理相似，此处不再赘述。
在一些实施例中，继续参考图5，驱动电路600还包括第一控制电路700，第一控制电路700的第一输出端连接开关单元630的控制端，第一控制电路700的第二输出端连接二级放大电路200的控制端。第一控制电路700第一输入端接收模式信号CTRLPin，第一控制电路700第二输入端接收基准信号RdEnPre，第一控制电路700用于根据模式信号CTRLPin和基准信号RdEnPre生成第一控制信号RdEnN，并根据基准信号RdEnPre生成第二控制信号RdEn。
第一控制信号RdEnN控制驱动电路600放大局部数据线LIO和互补局部数据线LIOB上的电压差，第二控制信号RdEn控制二级放大电路200放大局部数据线LIO和互补局部数据线LIOB上的电压差。
在一些实施例中，第一控制信号RdEnN为低电平有效，第二控制信号RdEn为高电平有效。第一控制信号RdEnN为低电平时，控制驱动电路600放大局部数据线LIO和互补局部数据线LIOB上的电压差。第二控制信号RdEn为高电平时，控制二级放大电路200放大局部数据线LIO和互补局部数据线LIOB上的电压差。
在一些实施例中，如图6所示，第一控制信号RdEnN为有效状态的起始时刻t2 早于第二控制信号RdEn为有效状态的起始时刻t3，控制驱动电路600先放大局部数据线LIO和互补局部数据线LIOB上的电压差，二级放大电路200后放大局部数据线LIO和互补局部数据线LIOB上的电压差。通过如此设置，由驱动电路600先放大局部数据线LIO和互补局部数据线LIOB上的电压差，补偿由于耦合电容对局部数据线LIO电压的影响，再由二级放大电路200和驱动电路600一起放大局部数据线LIO和互补局部数据线LIOB上的电压差，并在全局数据线GIO和互补全局数据线GIOB上产生电压差，缩短二级放大电路200放大局部数据线LIO和互补局部数据线LIOB上电压差的时间，提升存储器的时序参数tCCD的性能。
在一些实施例中，如图6所示，第一控制信号RdEnN为有效状态的起始时刻t2晚于均衡控制信号EQLOB为有效状态的终止时刻t0，均衡控制信号EQLOB处于有效状态时将局部数据线LIO和互补局部数据线LIOB的电压充电至预充电电压。
在一些实施例中，均衡控制信号EQLOB为低电平有效信号，也就是均衡控制信号EQLOB为低电平时将局部数据线LIO和互补局部数据线LIOB的电压充电至预充电电压。
通过如此设置，在局部数据线LIO和互补局部数据线LIOB的电压充电至预充电电压后，控制驱动电路600和二级放大电路200放大局部数据线LIO和互补局部数据线LIOB上的电压差，实现数据在位线BL和局部数据线LIO之间，以及互补位线BLB和互补局部数据线LIOB之间准确传输。
在一些实施例中，模式信号CTRLPin用于调节第一控制信号RdEnN为有效状态的起始时刻t2，也就是调节驱动电路600放大局部数据线LIO和互补局部数据线LIOB上的电压差的起始时刻。
在一些实施例中，第一控制信号RdEnN为有效状态的起始时刻的最小值t2min为均衡控制信号EQLOB为有效状态的终止时刻，第一控制信号RdEnN为有效状态的起始时刻的最大值t2max为第二控制信号RdEn为有效状态的起始时刻。
在一些实施例中，第一控制电路700用于根据模式信号CTRLPin确定基准信号RdEnPre和第一控制信号RdEnN之间的时间步长，根据时间步长对基准信号RdEnPre进行处理生成第一控制信号RdEnN。
时间步长可以为正时间步长，标记为Δτ。也可以为负时间步长，标记为-Δτ。正时间步长是指第一控制信号RdEnN为有效状态的起始时刻t2晚于基准信号RdEnPre为有效状态的起始时刻t1，且t1和t2之间相差Δτ。负时间步长是指第一控制信号RdEnN为有效状态的起始时刻t2早于基准信号RdEnPre为有效状态的起始时刻t1，t1和t2之间相差Δτ。
模式信号CTRLPin是第一时间间隔、存储器的工艺角、存储器的温度和存储器的 工作电压中任意一种或多种参数确定的。其中，第一时间间隔为存储器的相邻的行寻址到列寻址之间的时间间隔。
在一些实施例中，模式信号CTRLPin由第一时间间隔确定的，第一时间间隔越短，模式信号CTRLPin对应的时间步长越大，使得第一控制信号RdEnN为有效状态的起始时刻越晚。
其中，当时间步长为负时间步长-Δτ时，负时间步长-Δτ的绝对值越小，负时间步长越大。当时间步长为正时间步长Δτ时，正时间步长Δτ的绝对值越大，正时间步长越大。
在一些实施例中，模式信号CTRLPin由存储器的工艺角、存储器的温度和存储器的工作电压中任意一种或多种参数确定的。可通过对存储器进行多次测试，确定存储器的工艺角、存储器的温度和存储器的工作电压与第一控制信号RdEnN为有效状态的起始时刻之间关系，达到降低位线BL和互补位线BLB上噪声引入的目的。
通过如此设置，在存储器的时序参数较差时，通过调节驱动电路600放大局部数据线LIO和互补局部数据线LIOB上的电压差的起始时刻，减少局部数据线LIO和互补局部数据线LIOB对位线BL和互补位线BLB的噪声引入，实现数据准确传输。
在一些实施例中，基准信号RdEnPre为列选择信号CSL，第二控制电路400在列选择信号CSL的控制下，控制位线BL和局部数据线LIO之间接通或断开，以及还用于控制互补位线BLB和互补局部数据线LIOB之间接通或断开。
在一些实施例中，基准信号RdEnPre不限定为列选择信号CSL，也可以为其他任意信号，保证第一控制信号RdEnN满足上述时序关系即可，此处不做限定。
下面结合图7说明本公开实施例所描述的存储器的工作原理：
在T1阶段，列选择信号CSL为低电平，位线BL和局部数据线LIO之间断开，互补位线BLB和互补局部数据线LIOB之间断开。存储单元中存储数据“1”，存储单元与位线BL之间进行电荷共享，在位线BL和互补位线BLB上产生微小电压差ΔBL1。一级放大电路100在T1阶段放大位线BL和互补位线BLB上的微小电压差ΔBL1，例如：放大至电压差ΔBL2。
在T2阶段，列选择信号CSL为高电平，位线BL和局部数据线LIO之间接通，互补位线BLB和互补局部数据线LIOB之间接通，位线BL和互补位线BLB上的数据传输至局部数据线LIO和互补局部数据线LIOB上，此时，若位于两侧的局部数据线LIO<2>和LIO<3>上由于传输数据“0”出现电压跳变，而位于中间的局部数据线LIO<1>上传输数据“1”，也就是位于中间的局部数据线LIO的电压接近预充电电压VintLP，则两侧的局部数据线LIO<2>和LIO<3>会因为耦合电容而对中间局部数据线LIO<0>上的电压造成影响。
从T3阶段开始，第一控制信号RdEnN为低电平，第三P型晶体管P3导通，第一P型晶体管P1向上驱动局部数据线LIO上的电压，第二P型晶体管P2向上驱动互补局部数据线LIOB上的电压，且第一P型晶体管P1向上拉动局部数据线LIO的驱动能力大于第二P型晶体管P2向上拉动互补局部数据线LIOB的驱动能力，补偿两侧的局部数据线LIO<2>和LIO<3>对中间局部数据线LIO<0>上电压影响，而此时互补位线BLB向下驱动互补局部数据线LIOB的电压，实现补偿两侧的局部数据线LIO<2>和LIO<3>对中间局部数据线LIO<0>上电压影响，同时放大局部数据线LIO和互补局部数据线LIOB上的电压差。
从T4阶段开始，第二控制信号RdEn为高电平，二级放大电路200开始放大局部数据线LIO和互补局部数据线LIOB上的电压，此时由于驱动电路600已经将局部数据线LIO和互补局部数据线LIOB上的电压差进行放大，此时电压差△LIO2已经比较大，二级放大电路200和驱动电路600一起放大局部数据线LIO和互补局部数据线LIOB上的电压差，可以缩短二级放大电路200放大局部数据线LIO和互补局部数据线LIOB上的电压差的时间。
图7中以存储单元中存储数据“1”为例说明，存储单元中存储数据“0”的情况与存储数据“1”的情况相似，此处不再赘述。
继续参考图7，第一控制信号RdEnN为有效状态的起始时刻可以在RdEnN1所指示起始时刻和RdEnN2所指示起始时刻调节，用于调节局部数据线LIO和互补局部数据线LIOB向位线BL和互补位线BLB引入噪声的大小。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (15)

  1. 一种存储器，包括：
    一级放大电路，连接位线和互补位线，用于放大所述位线和所述互补位线上的电压差；
    二级放大电路，连接局部数据线和互补局部数据线，还连接全局数据线和互补全局数据线，在所述局部数据线与所述位线之间接通后，以及所述互补局部数据线与所述互补位线之间接通后，放大所述局部数据线和所述互补局部数据线上的电压差，并在所述全局数据线和所述互补全局数据线上产生电压差；
    驱动电路，连接所述局部数据线和所述互补局部数据线，放大所述局部数据线和所述互补局部数据线上的电压差。
  2. 根据权利要求1所述的存储器，其中，所述存储器还包括：
    均衡电路，连接所述局部数据线和所述互补局部数据线，在所述局部数据线与所述位线之间接通之前，以及所述互补局部数据线与所述互补位线之间接通之前，将所述局部数据线和所述互补局部数据线的电压充电至预充电电压；
    所述驱动电路用于在所述局部数据线和所述互补局部数据线的电压充电至预充电电压后，放大所述局部数据线和所述互补局部数据线上的电压差。
  3. 根据权利要求1或2所述的存储器，其中，所述驱动电路放大所述局部数据线和所述互补局部数据线上的电压差的起始时刻，早于所述二级放大电路放大所述局部数据线和所述互补局部数据线上的电压差的起始时刻。
  4. 根据权利要求1或2所述的存储器，其中，
    当第一时间间隔位于第一时间范围内时，第一起始时刻位于第一数值范围；
    当第一时间间隔位于第二时间范围内时，第一起始时刻位于第二数值范围；
    其中，所述第一时间间隔为存储器的相邻的行寻址到列寻址之间的时间间隔，所述第一起始时刻为所述驱动电路放大所述局部数据线和所述互补局部数据线上的电压差的起始时刻；
    所述第一时间范围的上限值小于或等于所述第二时间范围的下限值，所述第一数值范围的上限值大于或等于所述第二数值范围的下限值。
  5. 根据权利要求1所述的存储器，其中，所述驱动电路用于：
    通过向上驱动所述局部数据线的电压和/或所述互补局部数据线的电压，放大所述局部数据线和所述互补局部数据线上的电压差；
    其中，向上驱动所述局部数据线的驱动能力与所述互补局部数据线上的电压负相关，向上驱动所述互补局部数据线的驱动能力与所述局部数据线上的电压负相关。
  6. 根据权利要求5所述的存储器，其中，所述驱动电路包括：
    开关单元，与第一驱动单元和第二驱动单元连接，在第一控制信号的控制下控制所述第一驱动单元与第一电源端接通或者断开，以及在第一控制信号的控制下控制所述第二驱动单元与第一电源端接通或者断开；所述第一电源端提供电源电压；
    所述第一驱动单元，连接所述局部数据线和所述互补局部数据线，在所述第一驱动单元接通第一电源端时根据所述互补局部数据线的电压向上驱动所述局部数据线的电压；
    所述第二驱动单元，连接所述局部数据线和所述互补局部数据线，在所述第二驱动单元接通第一电源端时根据所述局部数据线的电压向上驱动所述互补局部数据线的电压；
    其中，所述第一驱动单元驱动所述局部数据线驱动能力与所述互补局部数据线的电压负相关；所述第二驱动单元驱动所述互补局部数据线驱动能力与所述局部数据线的电压负相关。
  7. 根据权利要求6所述的存储器，其中，
    所述第一驱动单元包括：
    第一P型晶体管，源极连接所述开关单元，漏极连接所述局部数据线，栅极连接所述互补局部数据线；
    所述第二驱动单元包括：
    第二P型晶体管，源极连接所述开关单元，漏极连接所述互补局部数据线，栅极连接所述局部数据线。
  8. 根据权利要求7所述的存储器，其中，所述开关单元包括：
    第三P型晶体管，源极连接所述第一电源端，漏极连接所述第一P型晶体管的源极，漏极还连接所述第二P型晶体管的源极，栅极接收所述第一控制信号。
  9. 根据权利要求6所述的存储器，其中，所述驱动电路还包括：
    第一控制电路，第一输出端连接所述开关单元的控制端，第二输出端连接所述二级放大电路的控制端；第一输入端接收模式信号，第二输入端接收基准信号，用于根据所述模式信号和所述基准信号生成第一控制信号，并根据所述基准信号生成第二控制信号；
    其中，所述第一控制信号为有效状态的起始时刻早于所述第二控制信号为有效状态的起始时刻，所述第二控制信号控制所述二级放大电路放大所述局部数据线和所述互补局部数据线上的电压差。
  10. 根据权利要求9所述的存储器，其中，所述第一控制信号为有效状态的起始时刻晚于均衡控制信号为有效状态的终止时刻，所述均衡控制信号处于有效状态时将所述局部数据线和所述互补局部数据线的电压充电至预充电电压。
  11. 根据权利要求9所述的存储器，其中，所述控制电路用于：
    根据所述模式信号确定所述基准信号和所述第一控制信号之间的时间步长；
    根据所述时间步长对所述基准信号进行处理生成所述第一控制信号。
  12. 根据权利要求11所述的存储器，其中，所述模式信号是第一时间间隔、存储器的工艺角、存储器的温度和存储器的工作电压中任意一种或多种参数确定的；
    其中，所述第一时间间隔为存储器的相邻的行寻址到列寻址之间的时间间隔。
  13. 根据权利要求9所述的存储器，其中，所述基准信号为列选择信号，所述列选择信号用于控制所述位线和所述局部数据线之间接通或断开，以及还用于控制所述互补位线和所述互补局部数据线之间接通或断开。
  14. 根据权利要求1所述的存储器，其中，所述存储器还包括：
    第二控制电路，连接所述位线和所述互补位线，还连接所述局部数据线和所述互补局部数据线，用于接收列选择信号，在所述列选择信号的控制下控制所述位线和所述局部数据线之间接通或者断开，以及在所述列选择信号的控制下控制所述互补位线和所述互补局部数据线之间接通或者断开。
  15. 根据权利要求1所述的存储器，其中，所述存储器还包括：
    三级放大电路，连接所述全局数据线和所述互补全局数据线，用于放大所述全局数据线和所述互补全局数据线上的电压差。
PCT/CN2023/074398 2022-11-04 2023-02-03 存储器 WO2024093037A1 (zh)

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CN101770806A (zh) * 2008-12-31 2010-07-07 台湾积体电路制造股份有限公司 用于sram的写操作中的灵敏放大器
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US20110199836A1 (en) * 2010-02-12 2011-08-18 Cheol Kim Bit-line sense amplifier, semiconductor memory device having the same, and method of testing bit-line micro-bridge defect
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CN101770806A (zh) * 2008-12-31 2010-07-07 台湾积体电路制造股份有限公司 用于sram的写操作中的灵敏放大器
US20110116334A1 (en) * 2009-11-18 2011-05-19 Yu Je-Min Semiconductor memory device
US20110199836A1 (en) * 2010-02-12 2011-08-18 Cheol Kim Bit-line sense amplifier, semiconductor memory device having the same, and method of testing bit-line micro-bridge defect
CN102347067A (zh) * 2010-07-07 2012-02-08 海力士半导体有限公司 预充电电路及包括所述预充电电路的半导体存储器件
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