WO2024093023A1

WO2024093023A1 - Semiconductor structure and forming method therefor

Info

Publication number: WO2024093023A1
Application number: PCT/CN2023/070881
Authority: WO
Inventors: 马梦茹; 马衎衎
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-11-01
Filing date: 2023-01-06
Publication date: 2024-05-10
Also published as: CN118042819A

Abstract

The present disclosure relates to a semiconductor structure and a forming method therefor. The semiconductor structure comprises: a substrate comprising a device area and a dummy-device area; active structures located in the device area, wherein the plurality of active structures are arranged at intervals in a first direction, and each of the active structures comprises a plurality of active areas, which are arranged in a second direction and are connected to each other; gate structures located in the device area, wherein the plurality of gate structures are arranged at intervals in the first direction, each of the gate structures comprises a first main body portion, a second main body portion and a connecting portion, each of the first main body portion and the second main body portion cover portions of two adjacent active structures close to each other and span the plurality of active structures in the second direction, the first main body portion is connected to the second main body portion by means of the connecting portion, and the connecting portion is located on first sides of the two adjacent active structures; and a dummy active structure, which is located in the dummy-device area and is located on second sides of the active structures. The present disclosure improves the integration level of the semiconductor structure, and reduces the loading effect of the semiconductor structure.

Description

Semiconductor structure and method of forming the same

Related Application Citations

This application claims priority to Chinese Patent Application No. 202211355369.5, filed on November 1, 2022, and entitled “Semiconductor Structure and Method for Forming the Same,” the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same.

Background technique

CSL (column select line) in semiconductor structures such as DRAM (Dynamic Random Access Memory) can control the specific information read from the bitline (BL) by the outside world. For example, after completing the operation of the sense phase, the bitline is in a stable logic 1 voltage state, and the bitline will charge the storage capacitor. After a certain period of time, the charge in the storage capacitor can be restored to the state before the read operation. Finally, through the control signal on the CSL, the outside world can read specific information from the bitline. In the semiconductor structure, the control transistor of the CSL is mostly designed with an "H" type structure. However, due to the continuous miniaturization of the size of the semiconductor structure, the control transistor of the "H" type structure occupies a large space, which leads to a long distance between adjacent devices, and there is no extra space outside the device area to place the dummy pattern structure. The load effect (Loading Effect) in the semiconductor structure manufacturing process has a large impact, and the uniformity of the device located at the junction or edge of the area is poor, thereby reducing the performance of the semiconductor structure.

Therefore, how to reduce the load effect inside the semiconductor structure and thus improve the performance of the semiconductor structure is a technical problem that needs to be solved urgently.

Summary of the invention

Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are used to reduce the load effect inside the semiconductor structure and improve the uniformity of devices inside the semiconductor structure, thereby improving the performance of the semiconductor structure.

According to some embodiments, the present disclosure provides a semiconductor structure, including:

A substrate, wherein the substrate includes a device region and a dummy device region;

An active structure, located in the device region, wherein a plurality of the active structures are arranged at intervals along a first direction, wherein the active structure comprises a plurality of active regions arranged along a second direction and connected to each other, wherein both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects with the second direction;

a gate structure, located in the device region, wherein a plurality of the gate structures are arranged at intervals along a first direction, wherein the gate structure comprises a first main body portion, a second main body portion and a connecting portion, wherein the first main body portion and the second main body portion respectively cover relatively close portions of two adjacent active structures and span across a plurality of active regions in the second direction, wherein the first main body portion is connected to the second main body portion through the connecting portion, and the connecting portion is located at a first side of two adjacent active structures;

The dummy active structure is located in the dummy device region and on a second side of the active structure, wherein the first side and the second side are the same side or two opposite sides of the active structure along the second direction.

In some embodiments, a plurality of the dummy active structures are arranged at intervals along the first direction, and the dummy active structure includes a plurality of dummy active regions arranged along the second direction and connected to each other.

In some embodiments, the connecting portion extends along the first direction, the first main body portion and the second main body portion both extend along the second direction, and the first main body portion and the second main body portion are located on the same side of the connecting portion along the second direction;

In two active structures adjacent to each other along the first direction, the first main body portion in one of the gate structures covers the active region in one of the active structures, and the second main body portion covers the active region in the other active structure.

In some embodiments, the active region includes a channel region, the active structure includes two active regions spaced apart along the second direction, and a connection region between the two active regions, and opposite ends of the connection region along the second direction respectively connect the channel regions in the two active regions;

In the two active structures adjacent to each other along the first direction, the first main body in one of the gate structures continuously covers the channel regions in the two active regions in one of the active structures, and the second main body continuously covers the channel regions in the two active regions in the other active structure.

In some embodiments, the first main body portion and the second main body portion are symmetrically distributed about an axis, and the axis extends along the second direction and passes through the center of the connecting portion.

In some embodiments, the first body portion includes a first portion covering the channel region in the active region, and a second portion covering the connection region and connected to the first portion;

A width of the first portion along the first direction is less than or equal to a width of the second portion along the first direction.

In some embodiments, the channel region includes a first channel region and a second channel region arranged along the first direction; the active region further includes:

a common source region, located between the first channel region and the second channel region;

A first drain region, located along the first direction on a side of the first channel region away from the common source region;

a second drain region, located along the first direction on a side of the second channel region away from the common source region;

The connection region includes a first connection region connecting the first channel regions in two active regions in the active structure and a second connection region connecting the second channel regions in two active regions in the active structure.

In some embodiments, for two gate structures adjacent to each other along the first direction, the first main body in one of the gate structures covers the first channel region in the active structure, and the second main body in the other gate structure covers the second channel region in the same active structure.

In some embodiments, it also includes:

a first isolation structure, located between the active structures adjacent to each other along the first direction;

The second isolation structure is located between the active regions adjacent to each other along the second direction in the active structure, and the width of the first isolation structure along the first direction is greater than the width of the second isolation structure along the second direction.

In some embodiments, the plurality of active regions in the active structure are aligned and arranged along the second direction;

A width of the second isolation structure along the second direction is less than 0.3 μm.

In some embodiments, the first side and the second side are two opposite sides of the active structure along the second direction; the semiconductor structure further includes:

The third isolation structure is located between the active structure and the dummy active structure.

In some embodiments, it also includes:

A first peripheral circuit is located outside the device region;

A gate lead has one end electrically connected to the first peripheral circuit and the other end electrically connected to the connecting portion in the gate structure.

In some embodiments, it also includes:

A gate lead port is located on the connecting portion and is used to be electrically connected to the gate lead. Along the second direction, the gate lead port is aligned with the center position of the first isolation structure.

According to some other embodiments, the present disclosure further provides a method for forming a semiconductor structure, comprising the following steps:

Providing a substrate, the substrate comprising a device region and a dummy device region;

An active structure is formed in the device region and a dummy active structure is formed in the dummy device region, wherein a plurality of the active structures are arranged at intervals along a first direction, the active structure comprises a plurality of active regions arranged along a second direction and connected to each other, the dummy active structure is located at a second side of the active structure, the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects with the second direction;

A gate structure is formed in the device area, and a plurality of the gate structures are arranged at intervals along the first direction. The gate structure includes a first main body, a second main body and a connecting portion. The first main body and the second main body respectively cover relatively close portions of two adjacent active structures and span a plurality of active areas in the second direction. The first main body is connected to the second main body through the connecting portion, and the connecting portion is located on a first side of two adjacent active structures, wherein the first side and the second side are the same side or opposite sides of the active structure along the second direction.

In some embodiments, the specific steps of providing a substrate, forming an active structure in the device region, and forming a dummy active structure in a dummy device region on the substrate include:

providing an initial substrate;

The initial substrate is patterned to form a plurality of active structures and a plurality of dummy active structures, wherein the plurality of dummy active structures are arranged at intervals along the first direction, the dummy active structures include a plurality of dummy active regions arranged along the second direction and connected to each other, the initial substrate remaining below the active structures and the dummy active structures serves as the substrate, the active region in the active structure includes a channel region, the active structure includes two active regions arranged at intervals along the second direction, and a connection region between the two active regions, and the opposite ends of the connection region along the second direction are respectively connected to the channel regions in the two active regions.

In some embodiments, the specific steps of forming a gate structure in the device region include:

Conductive material is deposited on the device area to form the first main body, the second main body and the connecting part, the connecting part extends along the first direction, the first main body and the second main body both extend along the second direction, and the first main body and the second main body are located on the same side of the connecting part along the second direction, and in two active structures adjacent to each other along the first direction, the first main body in one of the gate structures covers the active area in one of the active structures, and the second main body covers the active area in the other active structure.

In some embodiments, the channel region includes a first channel region and a second channel region arranged along the first direction; and the specific steps of forming a gate structure in the device region include:

Forming the first main body and the second main body respectively covering the first channel region and the second channel region above each of the active structures, and simultaneously forming a plurality of the connecting portions spaced apart along the first direction, to form a plurality of the gate structures;

For the two gate structures adjacent to each other along the first direction, the first main body in one of the gate structures covers the first channel region in the active structure, and the second main body in the other gate structure covers the second channel region in the same active structure.

In some embodiments, after forming the gate structure in the device region, the method further includes the following steps:

A gate lead is formed on the substrate, one end of the gate lead is electrically connected to a first peripheral circuit, and the other end of the gate lead is electrically connected to the connecting portion in the gate structure, and the first peripheral circuit is located outside the device region.

Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. By setting a plurality of active areas arranged along a second direction and interconnected in an active structure, the size of a device region including the plurality of active structures along the second direction can be reduced while ensuring that the number of active areas remains unchanged. On the one hand, this can improve the integration of the semiconductor structure; on the other hand, it can also provide space for setting a dummy device region outside the device region along the second direction, thereby reducing the load effect of the semiconductor structure, improving the uniformity of the active structure inside the device region, and improving the performance of the semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure;

FIG. 2 is a schematic diagram of the arrangement of active structures in the device region of a specific embodiment of the present disclosure;

FIG3 is a schematic diagram of the arrangement of the dummy active structure in the dummy device region according to a specific embodiment of the present disclosure;

FIG. 4 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;

5 to 7 are schematic diagrams of the main process structures in the process of forming a semiconductor structure according to a specific embodiment of the present disclosure.

Detailed ways

The specific implementation of the semiconductor structure and the method for forming the same provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

This specific embodiment provides a semiconductor structure, FIG1 is a schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure, FIG2 is a schematic diagram of the arrangement of active structures in a device region in a specific embodiment of the present disclosure, and FIG3 is a schematic diagram of the arrangement of dummy active structures in a dummy device region in a specific embodiment of the present disclosure. As shown in FIGS. 1-3, the semiconductor structure includes:

A substrate, wherein the substrate includes a device region 10 and a dummy device region 11;

An active structure 26, located in the device region 10, wherein a plurality of the active structures are arranged at intervals along a first direction D1, and the active structure 26 includes a plurality of active regions 12 arranged along a second direction D2 and connected to each other, wherein both the first direction D1 and the second direction D2 are parallel to the top surface of the substrate, and the first direction D1 intersects with the second direction D2;

A gate structure, located in the device region 10, wherein a plurality of the gate structures are arranged at intervals along the first direction D1, wherein the gate structure comprises a first main body portion 131, a second main body portion 132 and a connecting portion 14, wherein the first main body portion 131 and the second main body portion 132 respectively cover relatively close portions of two adjacent active structures 26 and span across a plurality of active regions 12 in the second direction D2, wherein the first main body portion 131 is connected to the second main body portion 132 via the connecting portion 14, and the connecting portion 14 is located at a first side of two adjacent active structures 26;

The dummy active structure 36 is located in the dummy device region 11 and on the second side of the active structure 26 , wherein the first side and the second side are the same side or two opposite sides of the active structure 26 along the second direction D2 .

Specifically, the semiconductor structure may be, but is not limited to, a DRAM. Taking the semiconductor structure as a DRAM as an example, the active region in the active structure 26 and the gate structure covering the active region may constitute a control transistor structure of a CSL. The substrate (not shown in the figure) may be, but is not limited to, a silicon substrate, and this specific embodiment is described by taking the substrate as a silicon substrate as an example. In other embodiments, the substrate may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The substrate is used to support the device structure above it. In one example, the active structure 26, the pseudo active structure 36 and the substrate are all made of silicon, so that the active structure 26, the pseudo active structure 36 and the substrate can be formed simultaneously by an etching process to simplify the process of the semiconductor structure. The material of the gate structure may be, but is not limited to, polycrystalline silicon. The top surface of the substrate refers to the surface of the substrate facing the active structure 26. The multiple described in this specific embodiment refers to more than two.

In some embodiments of this specific implementation method, the multiple active areas 12 arranged along the second direction D2 in the device area 10 are connected together to form the active structure 26, and the first main body 131 and the second main body 132 in the gate structure can be located on the same side of the connecting portion 14 along the second direction D2, so that the distance between the two adjacent active areas 12 along the second direction D2 is reduced, and the size of the entire gate structure (that is, the entirety composed of the connecting portion 14 and the first main body 131 and the second main body 132) along the second direction D2 is reduced, thereby reducing the width of the device area 10 along the second direction D2 and improving the integration of the device structure in the device area 10 and the semiconductor structure. Moreover, after the width of the device region 10 is reduced along the second direction D2, the dummy device region 11 can be arranged outside the device region 10 along the second direction D2 while keeping the area of the substrate unchanged. The dummy active structure 36 in the dummy device region 11 can reduce the load effect when etching the active structure 26 in the device region 10, thereby reducing the difference (for example, shape difference or feature size difference) between the active structures 26 in the device region 10, and reducing the difference (for example, shape difference or feature size difference) between the multiple active regions 12 arranged along the second direction D2 in the active structure 26, thereby improving the uniformity (including shape uniformity and feature size uniformity) between the active structures 26 in the device region 10, and improving the uniformity (including shape uniformity and feature size uniformity) between the active regions 12 in the active structure 26. A gate dielectric layer (not shown in the figure) is also arranged between the first main body 131 and the second main body 132 and the active region 12.

For example, as shown in FIG1 , the connection portion 14 in the gate structure is located outside the active structure 26, that is, the projection of the connection portion 14 on the top surface of the substrate does not overlap with the projection of the active structure 26 on the top surface of the substrate, so as to reduce the capacitive coupling effect between the connection portion 14 and the active region 12 in the active structure 26. The connection portion 14 and the dummy active structure 36 in the dummy device region 11 are distributed on opposite sides of the active structure 26 along the second direction D2, which can increase the process window when forming the connection portion 14 in the gate structure, thereby reducing the difficulty of manufacturing the semiconductor structure.

In other embodiments, the connection portion 14 and the dummy active structure 36 in the dummy device region 11 may also be located on the same side of the active structure 26 along the second direction D2 , thereby facilitating further reducing the size of the semiconductor structure.

In some embodiments, a plurality of the dummy active structures 36 are arranged at intervals along the first direction D1 , and the dummy active structures 36 include a plurality of dummy active regions 32 arranged along the second direction D2 and connected to each other.

In one example, the shape and size of the pseudo active area 32 (for example, the size along the first direction D1 and/or the size along the second direction D2) are the same as the shape and size of the active area 12 (for example, the size along the first direction D1 and/or the size along the second direction D2), and the shape and size of the pseudo active structure 36 (for example, the size along the first direction D1 and/or the size along the second direction D2) are the same as the shape and size of the active structure 26 (for example, the size along the first direction D1 and/or the size along the second direction D2), thereby further reducing the influence of the load effect when forming the device region 10 and further improving the performance of the semiconductor structure.

In other embodiments, a plurality of the dummy active structures 36 are arranged at intervals along the first direction D1, and the dummy active structure 36 includes only one dummy active region, so as to further simplify the manufacturing process of the semiconductor structure while reducing the load effect when etching to form the active structure 26 in the device region 10. In one example, the shape of the dummy active region may be the same as or different from the shape of the active region.

In order to further improve the integration of the semiconductor structure, in some embodiments, the connecting portion 14 extends along the first direction D1, the first main body portion 131 and the second main body portion 132 both extend along the second direction D2, and the first main body portion 131 and the second main body portion 132 are located on the same side of the connecting portion 14 along the second direction D2;

In two active structures 26 adjacent to each other along the first direction D1 , the first main body 131 in one gate structure covers the active region 12 in one of the active structures 26 , and the second main body covers the active region 12 in the other active structure.

In some embodiments, the active region 12 includes a channel region, the active structure 26 includes two active regions 12 arranged at intervals along the second direction D2, and a connection region located between the two active regions 12, and opposite ends of the connection region along the second direction D2 respectively connect the channel regions in the two active regions 12;

In two active structures 26 adjacent to each other along the first direction D1, the first main body 131 in one gate structure continuously covers the channel regions in the two active regions 12 in one of the active structures 26, and the second main body 132 continuously covers the channel regions in the two active regions 12 in the other active structure 26.

In some embodiments, the first main body portion 131 and the second main body portion 132 are symmetrically distributed about an axis, and the axis extends along the second direction D2 and passes through the center of the connecting portion 14 .

In some embodiments, the first body portion 131 includes a first portion covering the channel region in the active region 12, and a second portion covering the connection region and connected to the first portion;

A width of the first portion along the first direction D1 is smaller than or equal to a width of the second portion along the first direction D1.

In some embodiments, as shown in FIG. 2 , the channel region includes a first channel region 22 and a second channel region 23 arranged along the first direction D1; the active region 12 further includes:

A common source region 18, located between the first channel region 22 and the second channel region 23;

A first drain region 16, located along the first direction D1 on a side of the first channel region 22 away from the common source region 18;

A second drain region 17, located along the first direction D1 on a side of the second channel region 23 away from the common source region 12;

The connection region includes a first connection region 24 and a second connection region 25 . The first connection region 24 connects the first channel regions 22 in the two active regions 12 in the active structure 26 . The second connection region 25 connects the second channel regions 23 in the two active regions 12 in the active structure 26 .

For example, the active structure 26 includes two identical (for example, identical in shape and size) active regions 12. Each active region 12 includes the common source region 18, the first channel region 22 and the second channel region 23 distributed on opposite sides of the common source region 18 along the first direction D1, the first drain region 16 located on the side of the first channel region 22 away from the common source region 18 along the first direction D1, and the second drain region 17 located on the side of the second channel region 23 away from the common source region 12 along the first direction D1, so that two transistor structures can be formed in the active region 12, namely, a first transistor structure including the first drain region 16, the first channel region 22 and the common source region 18 and a second transistor structure including the second drain region 17, the second channel region 23 and the common source region 18.

The first channel regions 22 in the two active regions 12 in the active structure 26 are connected via the first connection region 24, and the second channel regions 23 in the two active regions 12 in the active structure 26 are connected via the second connection region 25. In one example, the first connection region 24, the second connection region 25 and the active region 12 are formed synchronously, that is, there is no contact interface between the first connection region 24 and the second connection region 25 in the same active structure 26 and the active region 12, thereby further simplifying the process of the semiconductor structure.

In some embodiments, as shown in FIG3 , the dummy active structure 36 includes two dummy active regions 32 arranged along the second direction D2, and a dummy connection region for connecting the two dummy active regions 32. Each of the dummy active regions 32 includes a first dummy channel region 33 and a second dummy channel region 37 arranged at intervals along the first direction D1, a dummy common source region 38 located between the first dummy channel region 33 and the second dummy channel region 37, a first dummy drain region 30 located on a side of the first dummy channel region 33 away from the dummy common source region 38 along the first direction D1, and a second dummy drain region 31 located on a side of the second dummy channel region 37 away from the dummy common source region 38 along the first direction D1. The dummy connection region includes a first dummy connection region 34 connecting the two first dummy channel regions 33, and a second dummy connection region 35 connecting the two second dummy channel regions 37.

In some embodiments, for two gate structures adjacent to each other along the first direction D1, the first main body 131 in one of the gate structures covers the first channel region 22 in the active structure 26, and the second main body 132 in the other gate structure covers the second channel region 23 in the same active structure 26.

For example, as shown in FIG1 , the first main body 131 and the second main body 132 in the gate structure are respectively connected to the two opposite ends of the connecting portion 14 along the first direction D1, the connecting portion 14 extends along the first direction D2, the first main body 131 and the second main body 132 both extend along the second direction D2, and the first main body 131 and the second main body 132 are located on the same side of the connecting portion 14 along the second direction D2, forming a C-shaped structure. For one active structure 26, the first main body 131 in one gate structure continuously covers the first channel regions 22 in the two active regions 12 in the active structure 26, and the first connection region 24 for connecting the two first channel regions 22, and the second main body 132 in another gate structure continuously covers the second channel regions 23 in the two active regions 12 in the active structure 26, and the second connection region 25 for connecting the two second channel regions 23. That is, the first channel region 22 and the second channel region 23 in one active region 12 are covered one by one by the two gate structures adjacent to each other along the first direction D1. For the two active structures 26 adjacent to each other along the first direction D1, the first main body 131 of the gate structure covers the first channel region 22 in one of the active structures 26, and the second main body 132 of the gate structure covers the second channel region 23 in the other active structure 26.

In some embodiments, the semiconductor structure further comprises:

a first isolation structure located between the active structures 26 adjacent to each other along the first direction D1;

The second isolation structure is located between the active regions 12 adjacent to each other along the second direction D2 in the active structure 26 . The width of the first isolation structure along the first direction D1 is greater than the width of the second isolation structure along the second direction D2 , so as to further reduce the size of the device region 10 along the second direction D2 .

In some embodiments, the plurality of active regions 12 in the active structure 26 are aligned and arranged along the second direction D2;

A width of the second isolation structure along the second direction D2 is less than 0.3 μm.

The multiple active regions 12 in the active structure 26 are aligned and arranged along the second direction D2, which means that the axes of the multiple active regions 12 in the active structure 26 extending along the second direction D2 are aligned, and the end faces of the multiple active regions 12 in the active structure 26 along the first direction D1 are also aligned. By setting the width L1 of the second isolation structure along the second direction D2 to be less than 0.3 μm, on the one hand, two adjacent active regions 12 in the active structure 26 can be effectively isolated to avoid signal crosstalk between adjacent active regions 12; on the other hand, it is also helpful to further reduce the size of the active structure 26 along the second direction D2. In one example, the width L1 of the second isolation structure along the second direction D2 is 0.12 μm.

In some embodiments, the length L2 of the portion where the projection of the first body portion 131 or the second body portion 132 on the top surface of the substrate overlaps with the projection of the active structure 26 on the top surface of the substrate along the second direction D2 is greater than or equal to 1 μm, thereby increasing the effective width of the device structure including the gate structure and the active structure 26, and further improving the performance of the semiconductor structure. In an example, the length L2 of the portion where the projection of the first body portion 131 or the second body portion 132 on the top surface of the substrate overlaps with the projection of the active structure 26 on the top surface of the substrate along the second direction D2 is 1.2 μm.

In some embodiments, the first side and the second side are two opposite sides of the active structure 26 along the second direction D2; the semiconductor structure further includes:

The third isolation structure is located between the active structure 26 and the dummy active structure 36 .

In some embodiments, the semiconductor structure further comprises:

A first peripheral circuit, located outside the device region 10;

The gate lead 15 has one end electrically connected to the first peripheral circuit and the other end electrically connected to the connection portion 14 in the gate structure.

In some embodiments, the semiconductor structure further comprises:

The gate lead port is located on the connecting portion 14 and is used to be electrically connected to the gate lead 15 . In the second direction D2 , the gate lead port is aligned with the center position of the first isolation structure.

Specifically, the semiconductor structure further includes the first peripheral circuit located outside the device region 10, and the gate lead 15 is used to transmit the gate control signal in the first peripheral circuit to the connection portion 14 in the gate structure, and then transmit the gate control signal to the first branch portion 131 and the second branch portion 132 in the gate structure through the connection portion 14. The gate lead port for electrically connecting the gate lead 15 is aligned with the center position of the first isolation structure located between two adjacent active structures 26 along the first direction D1. On the one hand, the window for forming the gate lead port can be enlarged to reduce damage to the active structure 26; on the other hand, the distances for transmitting the gate control signal from the gate lead 15 to the first main body portion 131 and the second main body portion 132 can be the same or similar, so that the signal delays in the first main body portion 131 and the second main body portion 132 are the same or similar, thereby further improving the electrical performance of the semiconductor structure.

In some embodiments, the semiconductor structure is further provided with a first drain lead 19 electrically connected to the first drain region 16, a second drain lead 20 electrically connected to the second drain region 17, and a source lead 21 electrically connected to the common source region 18, as shown in FIG1 . The first drain lead 19 is used to lead out or lead in a first drain signal of the first drain region 16, the second drain lead 20 is used to lead out or lead in a second drain signal of the second drain region 17, and the source lead 21 is used to lead out or lead in a common source signal of the common source region 18.

This specific embodiment also provides a method for forming a semiconductor structure. FIG4 is a flow chart of the method for forming a semiconductor structure in the specific embodiment of the present disclosure. FIG5-FIG7 are schematic diagrams of the main process structures in the process of forming a semiconductor structure in the specific embodiment of the present disclosure. The schematic diagrams of the semiconductor structure formed in this specific embodiment can be seen in FIG1-FIG3. As shown in FIG1-FIG7, the method for forming a semiconductor structure includes the following steps:

Step S41, forming an active structure 26 in the device region 10 on the substrate, and forming a dummy active structure 36 in the dummy device region 11 on the substrate, wherein a plurality of the active structures 26 are arranged at intervals along a first direction D1, the active structure 26 includes a plurality of active regions 12 arranged along a second direction D2 and connected to each other, the dummy active structure 36 is located on a second side of the active structure 26, the first direction D1 and the second direction D2 are both parallel to the top surface of the substrate, and the first direction D1 intersects with the second direction D2, as shown in FIGS. 2 , 3 and 5 ;

Step S42, forming a gate structure in the device area 10 on the substrate, wherein a plurality of the gate structures are arranged at intervals along the first direction D1, and the gate structure includes a first main body portion 131, a second main body portion 132 and a connecting portion 14, wherein the first main body portion 131 and the second main body portion 132 respectively cover relatively close portions of two adjacent active structures 26 and span a plurality of the active regions 12 in the second direction D2, and the first main body portion 131 is connected to the second main body portion 132 through the connecting portion 14, and the connecting portion 14 is located on a first side of two adjacent active structures 26, wherein the first side and the second side are the same side or opposite sides of the active structure 26 along the second direction D2, as shown in FIG. 6.

In some embodiments, the specific steps of forming the active structure 26 in the device region 10 on the substrate and forming the dummy active structure 36 in the dummy device region 11 on the substrate include:

providing an initial substrate;

The initial substrate is patterned to form a plurality of active structures 26 and a plurality of dummy active structures 36, wherein the plurality of dummy active structures 36 are arranged at intervals along the first direction D1, and the dummy active structure 36 includes a plurality of dummy active regions 32 arranged along the second direction D2 and connected to each other, and the initial substrate remaining below the active structures 26 and the dummy active structures 36 serves as the substrate, and the active region 12 in the active structure 26 includes a channel region, and the active structure 26 includes two active regions 12 arranged at intervals along the second direction D2, and a connection region between the two active regions 12, and the connection region at opposite ends along the second direction D2 respectively connects the channel regions in the two active regions 12.

In some embodiments, the specific steps of forming a gate structure in the device region 10 on the substrate include:

Conductive material is deposited on the device region 10 to form the first main body 131, the second main body 132 and the connecting portion 14, the connecting portion 14 extends along the first direction D1, the first main body 131 and the second main body 132 both extend along the second direction D2, and the first main body 131 and the second main body 132 are located on the same side of the connecting portion 14 along the second direction D2, and in two active structures 26 adjacent to each other along the first direction D1, the first main body 131 in one of the gate structures covers the active area 12 in one of the active structures 26, and the second main body 132 covers the active area in the other active structure 26.

In some embodiments, the channel region includes a first channel region 22 and a second channel region 23 arranged along the first direction D1; the specific steps of forming a gate structure in the device region 10 on the substrate include:

The first main body 131 and the second main body 132 are formed above each of the active structures 26 to cover the first channel region 22 and the second channel region 23 respectively, and a plurality of the connecting portions 14 are formed to be arranged at intervals along the first direction D1 to form a plurality of the gate structures;

For two gate structures adjacent to each other along the first direction D1 , the first main body 131 in one of the gate structures covers the first channel region 22 in the active structure, and the second main body 132 in the other gate structure covers the second channel region 23 in the same active structure 26 .

In some embodiments, after forming a gate structure in the device region 10 on the substrate, the following steps are further included:

A gate lead 15 is formed on the substrate, one end of the gate lead 15 is electrically connected to a first peripheral circuit and the other end is electrically connected to the connection portion 14 in the gate structure. The first peripheral circuit is located outside the device region 10, as shown in FIG. 7 .

Specifically, after forming a plurality of the gate structures, the gate lead 15, the first drain lead 19 electrically connected to the first drain region 16, the second drain lead 20 electrically connected to the second drain region 17, and the source lead 21 electrically connected to the common source region 18 can be formed simultaneously, as shown in FIG. 7 .

The semiconductor structure and the method for forming the same provided in some embodiments of the present specific implementation manner can reduce the size of the device region including the multiple active structures along the second direction while ensuring that the number of active regions remains unchanged by setting a plurality of active regions arranged along the second direction in the active structure. On the one hand, this can improve the integration of the semiconductor structure; on the other hand, it can also provide space for setting a dummy device region outside the device region along the second direction, thereby reducing the load effect of the semiconductor structure, improving the uniformity of the active structure inside the device region, and improving the performance of the semiconductor structure.

The above is only a preferred embodiment of the present disclosure. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

A semiconductor structure comprising:

A substrate, wherein the substrate includes a device region and a dummy device region;

An active structure, located in the device region, wherein a plurality of the active structures are arranged at intervals along a first direction, wherein the active structure comprises a plurality of active regions arranged along a second direction and connected to each other, wherein both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects with the second direction;

A gate structure, located in the device region, wherein a plurality of the gate structures are arranged at intervals along a first direction, wherein the gate structure comprises a first main body portion, a second main body portion, and a connecting portion, wherein the first main body portion and the second main body portion respectively cover relatively close portions of two adjacent active structures and span across a plurality of the active regions in the second direction, wherein the first main body portion is connected to the second main body portion through the connecting portion, and the connecting portion is located on a first side of two adjacent active structures;

The dummy active structure is located in the dummy device region and on a second side of the active structure, wherein the first side and the second side are the same side or two opposite sides of the active structure along the second direction.
The semiconductor structure according to claim 1, wherein a plurality of the dummy active structures are arranged at intervals along the first direction, and the dummy active structure comprises a plurality of dummy active regions arranged along the second direction and connected to each other.
The semiconductor structure according to claim 1, wherein the connecting portion extends along the first direction, the first main portion and the second main portion both extend along the second direction, and the first main portion and the second main portion are located on the same side of the connecting portion along the second direction;

In two active structures adjacent to each other along the first direction, the first main body portion in one of the gate structures covers the active region in one of the active structures, and the second main body portion covers the active region in the other active structure.
The semiconductor structure according to claim 3, wherein the active region comprises a channel region, the active structure comprises two active regions spaced apart along the second direction, and a connection region between the two active regions, and opposite ends of the connection region along the second direction respectively connect the channel regions in the two active regions;

In the two active structures adjacent to each other along the first direction, the first main body in one of the gate structures continuously covers the channel regions in the two active regions in one of the active structures, and the second main body continuously covers the channel regions in the two active regions in the other active structure.
The semiconductor structure according to claim 4, wherein the first main body portion and the second main body portion are symmetrically distributed about an axis, and the axis extends along the second direction and passes through the center of the connecting portion.
The semiconductor structure according to claim 5, wherein the first main body portion includes a first portion covering the channel region in the active region, and a second portion covering the connection region and connected to the first portion;

A width of the first portion along the first direction is less than or equal to a width of the second portion along the first direction.
The semiconductor structure according to claim 5, wherein the channel region comprises a first channel region and a second channel region arranged along the first direction; and the active region further comprises:

a common source region, located between the first channel region and the second channel region;

A first drain region, located along the first direction on a side of the first channel region away from the common source region;

a second drain region, located along the first direction on a side of the second channel region away from the common source region;

The connection region includes a first connection region connecting the first channel regions in two active regions in the active structure and a second connection region connecting the second channel regions in two active regions in the active structure.
The semiconductor structure according to claim 7, wherein, for two gate structures adjacent to each other along the first direction, the first main body in one of the gate structures covers the first channel region in the active structure, and the second main body in the other gate structure covers the second channel region in the same active structure.
The semiconductor structure according to claim 1, further comprising:

a first isolation structure, located between the active structures adjacent to each other along the first direction;

The second isolation structure is located between the active regions adjacent to each other along the second direction in the active structure, and the width of the first isolation structure along the first direction is greater than the width of the second isolation structure along the second direction.
The semiconductor structure according to claim 9, wherein the plurality of active regions in the active structure are aligned and arranged along the second direction;

A width of the second isolation structure along the second direction is less than 0.3 μm.
The semiconductor structure according to claim 9, wherein the first side and the second side are two opposite sides of the active structure along the second direction; the semiconductor structure further comprises:

The third isolation structure is located between the active structure and the dummy active structure.
The semiconductor structure according to claim 10, further comprising:

A first peripheral circuit is located outside the device region;

A gate lead has one end electrically connected to the first peripheral circuit and the other end electrically connected to the connecting portion in the gate structure.
The semiconductor structure according to claim 12, further comprising:

A gate lead port is located on the connecting portion and is used to be electrically connected to the gate lead. Along the second direction, the gate lead port is aligned with the center position of the first isolation structure.
A method for forming a semiconductor structure comprises the following steps:

Providing a substrate, the substrate comprising a device region and a dummy device region;

An active structure is formed in the device region and a dummy active structure is formed in the dummy device region, wherein a plurality of the active structures are arranged at intervals along a first direction, the active structure comprises a plurality of active regions arranged along a second direction and connected to each other, the dummy active structure is located at a second side of the active structure, the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects with the second direction;

A gate structure is formed in the device area, and a plurality of the gate structures are arranged at intervals along the first direction. The gate structure includes a first main body, a second main body and a connecting portion. The first main body and the second main body respectively cover relatively close portions of two adjacent active structures and span a plurality of active areas in the second direction. The first main body is connected to the second main body through the connecting portion, and the connecting portion is located on a first side of two adjacent active structures, wherein the first side and the second side are the same side or opposite sides of the active structure along the second direction.
The method for forming a semiconductor structure according to claim 14, wherein the specific steps of providing a substrate, forming an active structure in the device region, and forming a dummy active structure in the dummy device region include:

providing an initial substrate;

The initial substrate is patterned to form a plurality of active structures and a plurality of dummy active structures, wherein the plurality of dummy active structures are arranged at intervals along the first direction, the dummy active structures include a plurality of dummy active regions arranged along the second direction and connected to each other, the initial substrate remaining below the active structures and the dummy active structures serves as the substrate, the active region in the active structure includes a channel region, the active structure includes two active regions arranged at intervals along the second direction, and a connection region between the two active regions, and the opposite ends of the connection region along the second direction are respectively connected to the channel regions in the two active regions.
The method for forming a semiconductor structure according to claim 15, wherein the specific step of forming a gate structure in the device region comprises:

Conductive material is deposited on the device area to form the first main body, the second main body and the connecting part, the connecting part extends along the first direction, the first main body and the second main body both extend along the second direction, and the first main body and the second main body are located on the same side of the connecting part along the second direction, and in two active structures adjacent to each other along the first direction, the first main body in one of the gate structures covers the active area in one of the active structures, and the second main body covers the active area in the other active structure.
The method for forming a semiconductor structure according to claim 16, wherein the channel region includes a first channel region and a second channel region arranged along the first direction; and the specific step of forming a gate structure in the device region includes:

Forming the first main body and the second main body respectively covering the first channel region and the second channel region above each of the active structures, and simultaneously forming a plurality of the connecting portions spaced apart along the first direction, to form a plurality of the gate structures;

For the two gate structures adjacent to each other along the first direction, the first main body in one of the gate structures covers the first channel region in the active structure, and the second main body in the other gate structure covers the second channel region in the same active structure.
The method for forming a semiconductor structure according to claim 14, wherein after forming a gate structure in the device region, the method further comprises the following steps:

A gate lead is formed on the substrate, one end of the gate lead is electrically connected to a first peripheral circuit, and the other end of the gate lead is electrically connected to the connecting portion in the gate structure, and the first peripheral circuit is located outside the device region.