WO2024087932A1 - 控制方法、设备及计算设备 - Google Patents

控制方法、设备及计算设备 Download PDF

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Publication number
WO2024087932A1
WO2024087932A1 PCT/CN2023/118996 CN2023118996W WO2024087932A1 WO 2024087932 A1 WO2024087932 A1 WO 2024087932A1 CN 2023118996 W CN2023118996 W CN 2023118996W WO 2024087932 A1 WO2024087932 A1 WO 2024087932A1
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Prior art keywords
virtual
bmc chip
bmc
cpus
interface
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PCT/CN2023/118996
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English (en)
French (fr)
Inventor
毛阿利
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超聚变数字技术有限公司
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Publication of WO2024087932A1 publication Critical patent/WO2024087932A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of data processing technology, and in particular to a control method, device and computing device.
  • the baseboard management controller (BMC) chip can manage the server.
  • the BMC chip can manage the information of components such as the battery, fan, memory, and hard disk in the server.
  • multiple single-CPU servers can be set in the chassis, and the multiple single-CPU servers can share a set of shared components.
  • two single-CPU servers can be set in the chassis, and the two single-CPU servers can share a set of fans and power supplies.
  • each single-CPU server needs to be equipped with a BMC chip for management, which leads to high server costs. How to reduce the cost of the server has become an urgent problem to be solved.
  • the present application provides a control method, device and computing device for solving the technical problem of high cost of servers in the prior art.
  • the present application provides a control method, which is applied to a control system, wherein the control system includes a BMC chip and multiple CPUs, and the BMC chip is connected to the multiple CPUs.
  • the method includes:
  • the BMC chip obtains a first identifier of each CPU in the multiple CPUs
  • the BMC chip generates a plurality of virtual BMCs based on the plurality of first identifiers, and the plurality of virtual BMCs and the plurality of CPUs have a one-to-one correspondence;
  • the BMC chip manages multiple CPUs based on the multiple virtual BMCs.
  • the control method provided by the present application may include the following beneficial effects: a virtual BMC is generated for multiple CPUs through a BMC chip, and each CPU is managed through an independent virtual BMC, so that multiple CPUs can be managed through one BMC chip, saving server costs.
  • the BMC chip generates multiple virtual BMCs based on the multiple first identifiers, including:
  • the BMC chip determines, based on the multiple first identifiers, multiple configuration information of the multiple virtual BMCs, where the configuration information of the multiple virtual BMCs is different;
  • the BMC chip generates the multiple virtual BMCs based on the multiple configuration information, and the number of the virtual BMCs is the same as the number of the first identifiers.
  • the control method provided by the present application may include the following beneficial effects: since the BMC chip can determine the configuration information of the virtual BMC according to the first identifier of each CPU, the BMC chip can generate mutually independent virtual BMCs through the configuration information, and then multiple independent CPUs can be managed through multiple independent virtual BMCs, thereby reducing the cost of the server.
  • the BMC chip determines the configuration information of the virtual BMC based on the first identifier, including:
  • the BMC chip generates a virtual network port and a virtual external interface of the virtual BMC based on the first identifier, the IP address of the virtual network port is associated with the first identifier, and the virtual external interface is a virtual interface for data transmission with an external device;
  • the BMC chip determines configuration information of the virtual BMC based on the virtual network port and the virtual external interface.
  • the control method provided by the present application may include the following beneficial effects: since the BMC chip can determine the virtual network port and the virtual external interface of the virtual BMC through the first identifier, multiple virtual BMCs are independent of each other, and each virtual BMC has the function of the BMC chip managing the CPU, so that only one BMC chip is needed in the control system to manage multiple CPUs, thereby saving server costs.
  • the BMC chip manages multiple CPUs based on the multiple virtual BMCs, including:
  • the BMC chip obtains a connection mode between the BMC chip and the multiple CPUs
  • the BMC chip manages multiple CPUs based on the connection mode.
  • the control method provided by the present application may include the following beneficial effects: the BMC chip can obtain component information through the connection method. Since the connection methods between the BMC chip and multiple CPUs are different, the methods in which the BMC chip obtains component information are also different, which can improve the flexibility of obtaining component information.
  • the BMC chip manages multiple CPUs based on the connection mode, including:
  • connection mode is that the BMC chip is connected to the multiple CPUs respectively through M groups of management interfaces
  • the BMC chip manages the corresponding CPU based on each group of management interfaces, and the M is the same as the number of the CPUs;
  • the BMC chip obtains the interface type of each group of management interfaces and manages the multiple CPUs based on the interface type, the interface type is a non-shared type or a shared type, and N is less than the number of the CPUs.
  • the control method provided by the present application may include the following beneficial effects: the BMC chip may determine the method for obtaining component information by managing the interface type of the interface, thereby improving the flexibility of obtaining component information.
  • managing multiple CPUs based on the interface type includes:
  • the interface type of the management interface group is a non-shared type, managing the corresponding CPU based on the management interface;
  • the interface type of the management interface group is a shared interface type
  • the corresponding CPU is managed based on a time-sharing access method.
  • the control method provided by the present application may include the following beneficial effects: when the interface type of the management interface is a shared interface type, the BMC chip can obtain the component information of the server by time-sharing access, so that multiple CPUs can be managed through one management interface of the BMC chip, thereby saving the interface resources of the BMC chip and reducing the cost of the server.
  • the method further includes:
  • the BMC chip obtains shared component information based on any virtual BMC, and the shared component information is Information about hardware devices shared by multiple CPUs;
  • the BMC chip sends the shared component information to other virtual BMCs.
  • the control method provided by the present application may include the following beneficial effects: because the acquired shared component information can be shared between multiple virtual BMCs, this can save system resources and improve the reliability of data acquisition.
  • the present application provides a control device, which is applied to a control system, wherein the control system includes a BMC chip and multiple CPUs, and the BMC chip is connected to the multiple CPUs.
  • the control device may include a first acquisition module, a generation module, and a management module, wherein:
  • the first acquisition module is used to acquire a first identifier of each CPU in the multiple CPUs
  • the generating module is used to generate a plurality of virtual BMCs based on a plurality of first identifiers, wherein the plurality of virtual BMCs and the plurality of CPUs have a one-to-one correspondence;
  • the management module is used to manage multiple CPUs based on the multiple virtual BMCs.
  • the control device provided by the present application can include the following beneficial effects: a virtual BMC is generated for multiple CPUs through a BMC chip, and each CPU is managed through an independent virtual BMC, so that multiple CPUs can be managed through one BMC chip, saving server costs.
  • the generating module is specifically used for:
  • the plurality of virtual BMCs are generated, and the number of the virtual BMCs is the same as the number of the first identifiers.
  • the control device provided by the present application may include the following beneficial effects: since the BMC chip can determine the configuration information of the virtual BMC according to the first identifier of each CPU, the BMC chip can generate mutually independent virtual BMCs through the configuration information, and then multiple independent CPUs can be managed through multiple independent virtual BMCs, thereby reducing the cost of the server.
  • the generating module is specifically used for:
  • a virtual network port and a virtual external interface of the virtual BMC are generated, wherein the IP address of the virtual network port is associated with the first identifier, and the virtual external interface is a virtual interface for performing data transmission with an external device;
  • configuration information of the virtual BMC is determined.
  • the control device provided by the present application can include the following beneficial effects: since the BMC chip can determine the virtual network port and virtual external interface of the virtual BMC through the first identifier, multiple virtual BMCs are independent of each other, and each virtual BMC has the function of the BMC chip managing the CPU, so that only one BMC chip is needed in the control system to manage multiple CPUs, thereby saving server costs.
  • the management module is specifically used to:
  • a plurality of CPUs are managed based on the connection manner.
  • the control device provided by the present application may include the following beneficial effects: the BMC chip can obtain component information through the connection method. Since the connection methods between the BMC chip and multiple CPUs are different, the methods in which the BMC chip obtains component information are also different, which can improve the flexibility of obtaining component information.
  • the management module is specifically used to:
  • connection mode is that the BMC chip is connected to the multiple CPUs respectively through M groups of management interfaces, then the corresponding CPU is managed based on each group of management interfaces, and the M is the same as the number of the CPUs;
  • connection mode is that the BMC chip is connected to the multiple CPUs through N groups of management interfaces
  • the interface type of each group of management interfaces is obtained, and the multiple CPUs are managed based on the interface type, the interface type is a non-shared type or a shared type, and N is less than the number of the CPUs.
  • the control device provided by the present application may include the following beneficial effects: the BMC chip may determine the method of obtaining component information by managing the interface type of the interface, thereby improving the flexibility of obtaining component information.
  • the management module is specifically used to:
  • the interface type of the management interface group is a non-shared type, managing the corresponding CPU based on the management interface;
  • the interface type of the management interface group is a shared interface type
  • the corresponding CPU is managed based on a time-sharing access method.
  • the control device provided by the present application may include the following beneficial effects: when the interface type of the management interface is a shared interface type, the BMC chip can obtain the component information of the server by time-sharing access. In this way, multiple CPUs can be managed through one management interface of the BMC chip, thereby saving the interface resources of the BMC chip and reducing the cost of the server.
  • control device further includes a second acquisition module, where the second acquisition module is configured to:
  • the BMC chip acquires shared component information based on any one of the virtual BMCs, where the shared component information is information about hardware devices shared by the multiple CPUs;
  • the BMC chip sends the shared component information to other virtual BMCs.
  • the control device provided by the present application may have the following beneficial effects: because the acquired shared component information can be shared between multiple virtual BMCs, system resources can be saved and the reliability of data acquisition can be improved.
  • the present application provides a BMC chip, wherein the BMC chip includes at least one group of management interfaces, the BMC chip is connected to multiple CPUs through at least one group of management interfaces, and the BMC chip transmits data with the CPUs through the management interfaces.
  • the BMC chip provided by the present application may include the following beneficial effects: the BMC chip may be connected to multiple CPUs, thereby managing multiple CPUs through one BMC chip, thereby reducing the cost of the server.
  • control device including a processor and a memory
  • the memory is used to store computer programs
  • the processor is used to execute the computer program stored in the memory so that the control device executes the method described in the first aspect above.
  • the present application provides a computing device, comprising the BMC chip described in the third aspect, or the control device described in the fourth aspect.
  • the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions.
  • the computer-readable storage medium stores computer-executable instructions.
  • an embodiment of the present disclosure provides a computer program product, including a computer program, which, when executed by a processor, implements the method described in the first aspect and various possible methods involved in the first aspect.
  • the present application provides a control method, device and computing device, which are applied to a control system, wherein the control system includes a BMC chip and multiple CPUs, the BMC chip and the multiple CPUs are connected, the method includes the BMC chip obtaining a first identifier of each CPU in the multiple CPUs, the BMC chip generating multiple virtual BMC, wherein multiple virtual BMCs and multiple CPUs have a one-to-one correspondence, and the BMC chip manages multiple CPUs according to the multiple virtual BMCs.
  • the BMC chip can be connected to multiple CPUs and an independent virtual BMC is generated for each CPU, the BMC chip can manage the corresponding CPUs through multiple virtual BMCs, and then manage multiple CPUs through one BMC chip, thereby reducing the cost of the server.
  • FIG1 is a schematic diagram of the structure of a control system provided in an embodiment of the present application.
  • FIG2A is a schematic diagram of a connection method between a BMC chip and a CPU provided in an embodiment of the present application;
  • FIG2B is a schematic diagram of another connection method between a BMC chip and a CPU provided in an embodiment of the present application;
  • FIG3 is a schematic diagram of an application scenario provided by an embodiment of the present application.
  • FIG4 is a schematic flow chart of a control method provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of a CPU management process provided by an embodiment of the present application.
  • FIG6 is a method for managing multiple CPUs provided by an embodiment of the present application.
  • FIG7 is a schematic diagram of a method for obtaining shared component information provided by an embodiment of the present application.
  • FIG8 is a schematic diagram of a process for obtaining shared component information provided by an embodiment of the present application.
  • FIG9 is a schematic diagram of the structure of a control device provided in an embodiment of the present application.
  • FIG10 is a schematic diagram of the structure of another control device provided in an embodiment of the present application.
  • FIG. 11 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application.
  • the BMC chip can be a management chip in the server.
  • the BMC chip can be a baseboard management controller.
  • the BMC chip is a small operating system independent of the server system.
  • the BMC chip can manage the information of components such as batteries, fans, hard disks, and memory in the server.
  • the BMC chip can include physical interfaces and external interfaces.
  • the BMC chip can include a physical interface connected to the CPU, through which the BMC chip can access the CPU.
  • the BMC chip also includes an external interface connected to external devices.
  • the BMC chip can It can be connected to network cables and terminal devices through external interfaces.
  • the external interface may be a network port, which may be connected to a network cable, or a web interface, through which the BMC chip may provide a visual operation interface, or other interfaces, which are not limited in the embodiments of the present application.
  • Virtual BMC has the management function of BMC chip.
  • virtual BMC can have the function of managing server component information in BMC chip.
  • virtual BMC can also manage component information such as battery, fan, hard disk and memory in the server.
  • Virtual BMC can have all the functions of BMC chip.
  • each CPU is an independent system, therefore, each CPU requires an independent BMC for management (that is, one BMC chip can only manage one CPU), while the BMC chip in this application can generate a virtual BMC for each CPU, and each virtual BMC can independently manage a CPU connected to the BMC chip, thereby saving server costs.
  • servers are generally composed of a central processing unit (CPU), memory, hard disk, network card and other devices.
  • CPU central processing unit
  • memory volatile and non-volatile memory
  • a server usually needs a BMC chip.
  • the BMC chip manages all the hardware in the entire server chassis, such as CPU, memory, hard disk, power supply, fan, etc.
  • An independent software system runs on the BMC chip, which provides management functions for server hardware. This software can also be called BMC software.
  • multiple single-CPU servers can be set in the chassis, and multiple single-CPU servers can share a set of shared components.
  • two single-CPU servers can be set in the chassis, and the two single-CPU servers can share a set of fans and power supplies.
  • each single-CPU server needs to be equipped with a BMC chip for management.
  • the chassis includes three single-CPU servers, three BMC chips need to be set in the chassis. This leads to a higher cost of the server, and how to reduce the cost of the server is a problem that needs to be solved urgently.
  • the embodiment of the present application provides a control method, which is applied to a control system, wherein the control system may include a BMC chip and multiple CPUs, the BMC chip is connected to the multiple CPUs, the BMC chip can obtain the first identifier of each CPU in the multiple CPUs, and generate a virtual BMC for each CPU according to the multiple first identifiers, and the BMC chip can manage multiple CPUs according to the multiple virtual BMCs.
  • the control system may include a BMC chip and multiple CPUs
  • the BMC chip is connected to the multiple CPUs
  • the BMC chip can obtain the first identifier of each CPU in the multiple CPUs, and generate a virtual BMC for each CPU according to the multiple first identifiers
  • the BMC chip can manage multiple CPUs according to the multiple virtual BMCs.
  • Figure 1 is a schematic diagram of the structure of a control system provided by an embodiment of the present application. Please refer to Figure 1, Figure 1 may include a BMC chip, CPU1, CPU2, CPU3 and CPU4, and the BMC chip may be connected to CPU1, CPU2, CPU3 and CPU4 respectively, so that the BMC chip can configure a virtual BMC for each CPU, and then obtain the data of each CPU chip through the virtual BMC, thereby reducing the cost of the control system.
  • BMC chip CPU1, CPU2, CPU3 and CPU4
  • the BMC chip may be connected to CPU1, CPU2, CPU3 and CPU4 respectively, so that the BMC chip can configure a virtual BMC for each CPU, and then obtain the data of each CPU chip through the virtual BMC, thereby reducing the cost of the control system.
  • FIG. 1 is only an exemplary illustration of the control system of the present application.
  • the control system may include any number of CPUs (such as 1, 2 or 3, etc., which are not limited to the embodiments of the present application), and multiple CPUs may be controlled by one BMC chip.
  • the embodiment of the present application includes a BMC chip, the BMC chip includes at least one group of management interfaces, the BMC The chip can be connected to multiple CPUs through at least one set of management interfaces, and the BMC chip can transmit data with the CPU through the management interface.
  • the BMC chip can be connected to multiple CPUs through one set of management interfaces, or the BMC chip can be connected to multiple CPUs through multiple sets of management interfaces.
  • connection method between the BMC chip and the CPU according to the embodiment of the present application is described below.
  • FIG2A is a schematic diagram of a connection method between a BMC chip and a CPU provided in an embodiment of the present application.
  • the number of management interface groups of the BMC chip is the same as the number of CPUs.
  • the BMC chip includes two groups of management interfaces. Among them, each group of management interfaces includes an I3C interface, a PECI interface, and a PCIE interface.
  • the BMC chip is connected to server 1 through a group of management interfaces, and the BMC chip is connected to server 2 through another group of management interfaces.
  • Server 1 includes CPU1, and server 2 includes CPU2. In this way, the BMC chip can generate a virtual BMC1 for server 1 and a virtual BMC2 for server 2.
  • the virtual BMC1 can transmit data with CPU1 by connecting to the management interface group of server 1, and the virtual BMC2 can transmit data with CPU2 by connecting to the management interface group of server 2. In this way, multiple CPUs can be managed by one BMC chip, reducing the cost of the server.
  • Fig. 2B is a schematic diagram of another BMC chip and CPU connection method provided in an embodiment of the present application.
  • the number of management interface groups of the BMC chip is less than the number of CPUs, please refer to Fig. 2B, the BMC chip includes 2 groups of management interfaces, wherein each group of management interfaces can include an I3C interface, a PECI interface and a PCIE interface (not shown in Fig. 2B), the BMC chip is connected to server 1 through a group of management interfaces, and the BMC chip is connected to server 2 and server 3 through another group of management interfaces, wherein server 1 includes CPU1, server 2 includes CPU2, and server 3 includes CPU3.
  • the BMC chip can generate a virtual BMC1 for server 1, a virtual BMC2 for server 2, and a virtual BMC3 for server 3, and the virtual BMC1 can be connected to a group of management interfaces of server 1 for data transmission with CPU1, and the virtual BMC2 and virtual BMC3 can be connected to another group of management interfaces of server 2 and server 3, and time-sharingly transmit data with CPU2 and CPU3.
  • a group of management interfaces in the embodiment of the present application may include all interfaces for BMC to access the CPU.
  • a group of management interfaces may include an I3C interface, a PECI interface, and a PCIE interface.
  • both groups of management interfaces may include an I3C interface, a PECI interface, and a PCIE interface.
  • one group of management interfaces in the BMC chip may include an I3C interface and a PECI interface
  • another group of management interfaces may include a PECI interface and a PCIE interface.
  • the virtual BMC can manage the corresponding CPUs through time-sharing access.
  • the BMC chip includes a group of management interfaces, and the group of management interfaces is connected to CPU1 and CPU2, the BMC chip can generate a virtual BMC1 corresponding to CPU1 and a virtual BMC2 corresponding to CPU2, wherein both virtual BMC1 and virtual BMC2 manage the corresponding CPUs through the group of management interfaces.
  • virtual BMC1 accesses CPU1 through the group of management interfaces
  • virtual BMC2 accesses CPU2 through the group of management interfaces.
  • the embodiments of the present application can also determine the time-sharing access method through other methods, and the embodiments of the present application are not limited to this. In this way, when the management interface resources are less, one BMC chip can also manage multiple CPUs, thereby improving the resource utilization of the BMC chip.
  • FIG3 is a schematic diagram of an application scenario provided by an embodiment of the present application.
  • FIG3 may include a 2P server (a server including two single CPUs), wherein the 2P server may include a BMC chip, CPU1 and CPU2.
  • the BMC chip is connected to CPU1 and CPU2 respectively.
  • CPU1 can also be connected to hard disk 1 and memory 1, and CPU2 can also be connected to hard disk 2 and memory 2.
  • the BMC chip can manage CPU1 and CPU2.
  • the BMC chip can obtain the temperature of CPU1, the remaining space of hard disk 1, the temperature of CPU2, and the remaining space of hard disk 2. In this way, only one BMC chip needs to be set in the 2P server to manage CPU1 and CPU2, without setting a BMC chip for each CPU, thereby reducing the cost of the 2P server.
  • FIG. 3 is only an illustrative example of the application scenario of the embodiment of the present application, and is not a limitation on the application scenario of the embodiment of the present application.
  • FIG4 is a flow chart of a control method provided in an embodiment of the present application. Referring to FIG4 , the method may include:
  • the execution subject of the embodiment of the present application may be a BMC chip.
  • the control system includes a BMC chip and multiple CPUs, and the BMC chip is connected to the multiple CPUs respectively.
  • the control system may include 1 BMC chip and 2 servers, and the server may be a single-CPU server, and the BMC chip is connected to the CPUs in the 2 servers respectively.
  • the control system may also include 1 BMC chip and 4 single-CPU servers, and the BMC chip is connected to the CPUs in the 4 single-CPU servers respectively.
  • the embodiment of the present application is not limited to this.
  • the BMC chip is used to manage all hardware in the control system.
  • the BMC chip can manage components, boards, power supplies, fans, etc. in a multi-P server.
  • a multi-P server can be a server composed of multiple CPUs.
  • a server can include components such as a CPU, memory, hard disk, and network card.
  • the server includes two sets of the above components, so that the server can be two independent physical servers (2P server).
  • an independent system can be run on the BMC chip, and the hardware of the server can be managed through the independent system.
  • the BMC chip can obtain information such as the power of the server and the speed of the fan through the management system in the chip.
  • the BMC chip can control components in the server. For example, when an alarm occurs in a component in the server, the BMC chip can control the alarm component in the server through the running independent system. For example, the BMC chip can eliminate the alarm information in the server, etc.
  • the first identifier may be the identity identification number of the CPU.
  • the first identifier may be the ID of the CPU
  • the BMC chip may obtain the first identifier of the CPU based on the configuration information of each CPU.
  • the control system may include CPU1 and CPU2. If the ID of CPU1 is 1 and the ID of CPU2 is 2, the first identifier of CPU1 obtained by the BMC chip is 1, and the first identifier of CPU2 obtained by the BMC chip is 2.
  • the first identifier of the CPU may be a pre-set identifier. For example, when assembling a multi-P server, the corresponding ID may be pre-configured for each CPU.
  • the BMC chip may obtain the first identification of the CPU according to the following feasible implementation method: sending a query instruction to the CPU.
  • the query instruction may be used to query the first identification of the CPU.
  • the BMC chip may send an identification query instruction to multiple connected CPUs.
  • the BMC chip may obtain multiple first identifications.
  • the BMC chip may determine whether to obtain the first identifier of the CPU according to the state of the virtual control switch, wherein the virtual control switch is used to control whether the BMC chip is turned on or off. Enable the function of virtual BMC. For example, if the virtual control switch is in the on state, the BMC chip can obtain the first identification of multiple CPUs. If the virtual control switch is in the off state, the BMC chip does not need to obtain the first identification of the CPU. It should be noted that the virtual control switch can be visualized in the terminal device through the web interface, and then the state of the virtual control switch can be controlled in the terminal device. The embodiment of the present application can also control the virtual control switch in other ways, and the embodiment of the present application is not limited to this.
  • S402 Generate multiple virtual BMCs based on multiple first identifiers.
  • the virtual BMC has the functions of a BMC chip, and multiple virtual BMCs and multiple CPUs have a one-to-one correspondence.
  • the virtual BMC can be a virtualized BMC.
  • the CPU is the CPU of a cloud server in the cloud
  • the virtual BMC can also be a BMC generated in the cloud
  • each virtual BMC can be an independent BMC management system.
  • BMC software can be installed in the BMC chip, and the BMC software can generate a virtual BMC for each CPU, and then obtain the component information of the CPU through the virtual BMC.
  • a multi-P server includes CPU1 and CPU2
  • the BMC chip can generate virtual BMC1 and virtual BMC2.
  • Virtual BMC1 is used to obtain the component information of CPU1
  • virtual BMC2 is used to obtain the component information of CPU2. Since CPU1 and CPU2 in the multi-P server are independent of each other, virtual BMC1 and virtual BMC2 are both independent BMCs.
  • the BMC chip can generate multiple virtual BMCs according to the following feasible implementation method: based on multiple first identifiers, multiple configuration information of multiple virtual BMCs are determined, and based on the multiple configuration information, multiple virtual BMCs are generated.
  • the configuration information may include multiple parameters required to generate the virtual BMC, and the BMC chip can generate the corresponding virtual BMC through the configuration information.
  • the configuration information may include a virtual network port and a virtual external interface, and the BMC chip can generate a virtual BMC through the virtual network port and the virtual external interface.
  • the number of virtual BMCs is the same as the number of first identifiers. For example, if the multi-P server includes 2 CPUs, the BMC chip can obtain 2 first identifiers, and then determine 2 configuration information based on the 2 first identifiers, and generate 2 virtual BMCs based on the 2 configuration information.
  • the configuration information of multiple virtual BMCs is different.
  • the BMC chip can determine the configuration information 1 of the virtual BMC1 according to the first identifier of CPU1, and determine the configuration information 2 of the virtual BMC2 according to the first identifier of CPU2, wherein, since the first identifier of CPU1 is different from the first identifier of CPU2, the configuration information 1 and the configuration information 2 are also different.
  • the BMC chip can determine the configuration information of the virtual BMC according to the following feasible implementation method: based on the first identifier, generate the virtual network port and virtual external interface of the virtual BMC, and determine the configuration information of the virtual BMC based on the virtual network port and the virtual external interface.
  • the IP address of the virtual network port is associated with the first identifier.
  • the BMC chip can initialize the network port according to the CPU ID, and can virtualize multiple network port devices (such as eth0:1, eth0:2 or eth0:3, etc.) through the operating system network protocol stack.
  • the IP address of the virtual network port can be automatically arranged according to the first identifier of the CPU.
  • a multi-P server may include CPU1 and CPU2, wherein the first identifier of CPU1 is 1, the first identifier of CPU2 is 2, the IP address of the virtual network port of CPU1 generated by the BMC chip can be 888.888.8.881 (1 is the first identifier of CPU1), and the IP address of the virtual network port of CPU2 generated by the BMC chip can be 888.888.8.882 (2 is the first identifier of CPU2).
  • the virtual external interface is a virtual interface for data transmission with an external device.
  • the virtual external interface may include a web interface (providing a visual operation page), a cli interface (providing a command line operation page), etc., through which data can be transmitted with an external device.
  • multiple virtual external interfaces can be bound to different virtual network ports.
  • a virtual web interface and a virtual cli interface can be bound to different IP addresses (IP addresses of each virtual network port). In this way, each virtual network port can be bound to multiple virtual external interfaces.
  • the BMC chip can determine the virtual network port and the virtual external interface as the configuration information of the virtual BMC. For example, after the BMC chip generates the virtual network port and the virtual external interface according to the first identifier, the BMC chip can determine the information of the virtual network port and the virtual external interface as the configuration information of the virtual BMC.
  • the BMC chip can generate a virtual BMC based on the configuration information. For example, after the BMC chip determines the virtual network port and the virtual external interface, a virtual BMC can be generated, the virtual BMC includes an independent IP address, a full set of virtual external interfaces, and the virtual BMC can be a management system for a CPU.
  • the BMC chip can obtain CPU information, server information, etc. based on multiple virtual BMCs, and then manage the CPU.
  • the BMC chip can obtain CPU information, memory information, hard disk information, network card information, battery information, hard disk remaining space, memory utilization, fan speed, etc. in the server based on multiple virtual BMCs.
  • the BMC chip can manage multiple CPUs through multiple virtual BMCs.
  • the BMC chip is connected to CPU1 and CPU2, the BMC chip generates virtual BMC1 and virtual BMC2, and obtains CPU1 information through virtual BMC1, and obtains CPU2 information through virtual BMC2.
  • a multi-P server includes 3 CPUs, the BMC chip can generate 3 virtual BMCs, and obtain information about the 3 CPUs through the 3 virtual BMCs.
  • FIG5 is a schematic diagram of a CPU management process provided by an embodiment of the present application.
  • the BMC software can generate a virtual BMC1 according to the ID of the CPU1 of server 1, and generate a virtual BMC2 according to the ID of the CPU2 of server 2.
  • the BMC software can obtain the component information of the management resources of server 1 through the virtual BMC1, and obtain the component information of the management resources of server 2 through the virtual BMC2.
  • the virtual network port and virtual external interface in this application are different from the management interface group in this application.
  • the virtual BMC can access the CPU through the management interface group, and managing the CPU requires an actual physical interface. Therefore, the BMC chip in this application needs to include at least one group of management interface groups (such as I3C, PECI, etc.), and the BMC chip also includes a network port and an external interface (such as web, cli, etc.) for interacting with external devices. Therefore, when generating a virtual BMC, it is also necessary to generate a virtual network port and a virtual external interface according to the functions of the network port and the external interface.
  • management interface groups such as I3C, PECI, etc.
  • the embodiment of the present application provides a control method, which is applied to a control system.
  • the control system may include a BMC chip and multiple CPUs.
  • the BMC chip has a connection relationship with the multiple CPUs.
  • the BMC chip can obtain the first identifier of each CPU in the multiple CPUs, and generate a virtual network port and a virtual external interface of the virtual BMC according to the first identifier. According to the virtual network port and the virtual external interface, the configuration information of the virtual BMC is determined.
  • the BMC chip can generate multiple virtual BMCs according to multiple configuration information, and manage multiple CPUs through multiple virtual BMCs. In the above method, since the BMC chip can manage multiple independent CPUs through multiple virtual BMCs, multiple single-CPU servers only need one BMC chip, thereby reducing the cost of the server.
  • FIG6 is a method for managing multiple CPUs provided by an embodiment of the present application. Referring to FIG6 , the method flow includes:
  • Case 1 The BMC chip is connected to multiple CPUs through M groups of management interfaces, where M is the same as the number of CPUs.
  • the BMC chip can configure a set of management interfaces for each CPU, and then manage multiple CPUs in parallel through multiple sets of management interfaces.
  • a multi-P server includes CPU1, CPU2, and a BMC chip.
  • the BMC chip can be connected to CPU1 through a set of management interfaces, and the BMC chip can be connected to CPU2 through another set of management interfaces.
  • the BMC chip can manage CPU1 through one set of management interfaces, and the BMC chip can manage CPU2 through another set of management interfaces.
  • Case 2 The BMC chip is connected to multiple CPUs through N groups of management interfaces, where N is smaller than the number of CPUs.
  • a multi-P server includes CPU1, CPU2, CPU3 and a BMC chip
  • the BMC chip may include management interface group A and management interface group B.
  • the BMC chip can be connected to CPU1 through management interface group A, and the BMC chip can be connected to CPU2 and CPU3 through management interface group B.
  • the BMC chip can manage the CPU through management interface group A, and the BMC chip can manage CPU2 and CPU3 through management interface group B.
  • the BMC chip manages multiple CPUs based on the connection mode. There are two cases:
  • Case 1 The BMC chip is connected to multiple CPUs through group M management interfaces.
  • a multi-P server includes CPU1, CPU2 and a BMC chip, where the BMC chip includes management interface group A and management interface group B. If the BMC chip is connected to CPU1 through management interface group A and connected to CPU2 through management interface group B, the BMC chip can manage CPU1 through management interface group A and manage CPU2 through management interface group B.
  • Case 2 The BMC chip is connected to multiple CPUs through N groups of management interfaces.
  • the interface type of each group of management interfaces is obtained, and multiple CPUs are managed according to the interface type, where N is less than the number of CPUs.
  • the interface type can be a non-shared type or a shared type.
  • a non-shared type management interface group can independently connect to a CPU, and a shared type management interface group can connect to at least two CPUs.
  • the BMC chip includes management interface group A and management interface group B.
  • the interface type of management interface group A is a non-shared type
  • the interface type of management interface group B is a shared type
  • multiple CPUs are managed based on the interface type, specifically: if the interface type of the management interface group is a non-shared type, the corresponding CPU is managed through the management interface group.
  • the interface type of the management interface group is a non-shared type, it means that the management interface group is independently connected to a CPU, so the BMC chip can obtain component information of the connected CPU through the management interface group.
  • the interface type of the management interface group is a shared interface type
  • the corresponding CPU is managed through time-sharing access.
  • the interface type of the management interface group is a shared type, it means that the management interface group is connected to multiple CPUs at the same time. Therefore, the BMC chip cannot manage multiple CPUs connected to the management interface group at the same time through the management interface group.
  • the BMC chip can manage multiple CPUs through time-sharing access. For example, if the management interface group is connected to CPU1 and CPU2 at the same time, the BMC chip can manage CPU1 through the management interface group in one cycle, and manage CPU2 through the management interface group in the next cycle.
  • the embodiment of the present application provides a control method for obtaining the connection mode between the BMC chip and multiple CPUs. If the connection mode is that the BMC chip is connected to multiple CPUs respectively through M groups of management interfaces, then multiple CPUs are managed through each group of management interfaces. If the connection mode is that the BMC chip is connected to multiple CPUs through N groups of management interfaces, then the interface type of each group of management interfaces is obtained, and multiple CPUs are managed based on the interface type. In this way, when the BMC chip is connected to each CPU respectively through multiple groups of management interfaces, the BMC chip can independently manage the corresponding CPU through each group of management interfaces.
  • the BMC chip When the BMC chip is connected to multiple CPUs through a group of management interfaces, the BMC chip can manage multiple CPUs connected to the management interface group through the group of management interfaces in a time-sharing manner, thereby improving the flexibility of CPU management. Moreover, since one BMC chip can manage multiple CPUs through multiple virtual BMCs, there is no need to set up a BMC chip for each CPU, thereby reducing the cost of the server.
  • the above control method also includes a method for obtaining shared component information.
  • the method for obtaining shared component information is described below in conjunction with FIG. 7 .
  • FIG7 is a schematic diagram of a method for obtaining shared component information provided by an embodiment of the present application. Referring to FIG7 , the method flow includes:
  • S701 Acquire shared component information based on any virtual BMC.
  • the shared component information is information about hardware devices shared by the multiple CPUs.
  • the shared component information may include power supply information, fan information, network information, etc., and multiple CPUs may share hardware devices such as a fan and a power supply.
  • the BMC chip can obtain the shared component information through any virtual BMC.
  • the BMC chip can obtain the shared component information through virtual BMC1, and the BMC chip can also obtain the shared component information through virtual BMC2.
  • the BMC chip can also obtain shared component information through multiple virtual BMCs, and verify the shared component information obtained by the multiple virtual BMCs.
  • the BMC chip can obtain shared component information 1 through virtual BMC1, obtain shared component information 2 through virtual BMC2, and compare shared component information 1 with shared component information 2. If shared component information 1 is the same as shared component information 2, it is determined that the shared component information verification is successful. If shared component information 1 is different from shared component information 2, it is determined that the shared component information verification fails. This can improve the reliability of data and thus improve the security of the server.
  • the BMC chip after the BMC chip obtains the shared component information through any virtual BMC, it can send the shared component information to other virtual BMCs, which can avoid repeated acquisition of the shared component information and further save system resources of the control system.
  • FIG8 is a schematic diagram of a process for obtaining shared component information provided by an embodiment of the present application.
  • the shared components include components such as fans and power supplies.
  • the BMC software can generate a virtual BMC1 based on the ID of CPU1 of server 1, and generate a virtual BMC2 based on the ID of CPU2 of server 2.
  • the BMC chip can obtain the shared component information through the virtual BMC1 and send the shared component information to the virtual BMC2. In this way, the obtained shared component information can be shared between multiple virtual BMCs, saving system resources and improving the reliability of data acquisition.
  • FIG9 is a schematic diagram of the structure of a control device provided in an embodiment of the present application.
  • the control device 900 may include a first acquisition module 901, a generation module 902, and a management module 903, wherein:
  • the first acquisition module 901 is used to acquire a first identifier of each CPU in the multiple CPUs;
  • the generating module 902 is used to generate a plurality of virtual BMCs based on a plurality of first identifiers, wherein the plurality of virtual BMCs and the plurality of CPUs have a one-to-one correspondence;
  • the management module 903 is used to manage multiple CPUs based on the multiple virtual BMCs.
  • the generating module 102 is specifically configured to:
  • the plurality of virtual BMCs are generated, and the number of the virtual BMCs is the same as the number of the first identifiers.
  • the generating module 902 is specifically configured to:
  • a virtual network port and a virtual external interface of the virtual BMC are generated, wherein the IP address of the virtual network port is associated with the first identifier, and the virtual external interface is a virtual interface for performing data transmission with an external device;
  • configuration information of the virtual BMC is determined.
  • the management module 903 is specifically configured to:
  • a plurality of CPUs are managed based on the connection manner.
  • the management module 903 is specifically configured to:
  • connection mode is that the BMC chip is connected to the multiple CPUs respectively through M groups of management interfaces, then the corresponding CPU is managed based on each group of management interfaces, and the M is the same as the number of the CPUs;
  • connection mode is that the BMC chip is connected to the multiple CPUs through N groups of management interfaces
  • the interface type of each group of management interfaces is obtained, and the multiple CPUs are managed based on the interface type, the interface type is a non-shared type or a shared type, and N is less than the number of the CPUs.
  • the management module 903 is specifically configured to:
  • the interface type of the management interface group is a non-shared type, managing the corresponding CPU based on the management interface;
  • the interface type of the management interface group is a shared interface type
  • the corresponding CPU is managed based on a time-sharing access method.
  • control device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.
  • FIG10 is a schematic diagram of the structure of another control device provided in an embodiment of the present application. Based on the embodiment shown in FIG9 , please refer to FIG10 , the control device further includes a second acquisition module 904, and the second acquisition module 904 is used to:
  • the shared component information is sent to other virtual BMCs.
  • control device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.
  • FIG11 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application. Referring to FIG11 , it shows a schematic diagram of the structure of a computing device 1100 suitable for implementing an embodiment of the present disclosure.
  • the computing device 1100 may include a processing unit;
  • the computing device 1100 is a computer (e.g., a central processing unit, a graphics processing unit, etc.) 1101, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1102 or the program loaded from the storage device 1108 to the random access memory (RAM) 1103.
  • Various programs and data required for the operation of the computing device 1100 are also stored in the RAM 1103.
  • the processing device 1101, the ROM 1102, and the RAM 1103 are connected to each other via a bus 1104.
  • An input/output (I/O) interface 1105 is also connected to the bus 1104.
  • the following devices may be connected to the I/O interface 1105: input devices 1106 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 1107 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 1108 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 1109.
  • the communication devices 1109 may allow the computing device 1100 to communicate wirelessly or wired with other devices to exchange data.
  • FIG. 11 shows a computing device 1100 with various devices, it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or have alternatively.
  • an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program code for executing the method shown in the flowchart.
  • the computer program can be downloaded and installed from the network through the communication device 1109, or installed from the storage device 1108, or installed from the ROM 1102.
  • the processing device 1101 the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.
  • the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two.
  • the computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above.
  • Computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.
  • a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device.
  • a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried.
  • This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above.
  • the computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device.
  • the program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.
  • the present application provides a BMC chip, wherein the BMC chip includes at least one set of management interfaces, and the BMC chip is connected to multiple CPUs through the at least one set of management interfaces.
  • the present application also provides a control device, including a processor and a memory; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory, so that the control device executes the method described in the embodiments of the present application.
  • the computing device may include the above-mentioned control device or the above-mentioned BMC chip.
  • the computer readable medium may be included in the computing device; or may exist independently without being installed. into the computing device.
  • the computer-readable medium carries one or more programs.
  • the computing device executes the method shown in the above embodiment.
  • Computer program code for performing the operations of the present disclosure may be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, C++, and conventional procedural programming languages such as "C" or similar programming languages.
  • the program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server.
  • the remote computer may be connected to the user's computer via any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).
  • LAN Local Area Network
  • WAN Wide Area Network
  • each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function.
  • the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved.
  • each square box in the block diagram and/or flow chart, and the combination of the square boxes in the block diagram and/or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.
  • the units involved in the embodiments described in the present disclosure may be implemented by software or hardware.
  • the name of a unit does not limit the unit itself in some cases.
  • the first acquisition unit may also be described as a "unit for acquiring at least two Internet Protocol addresses".
  • exemplary types of hardware logic components include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), and the like.
  • FPGAs field programmable gate arrays
  • ASICs application specific integrated circuits
  • ASSPs application specific standard products
  • SOCs systems on chip
  • CPLDs complex programmable logic devices
  • a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment.
  • a machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • a machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing.
  • a more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
  • RAM random access memory
  • ROM read-only memory
  • EPROM or flash memory erasable programmable read-only memory
  • CD-ROM portable compact disk read-only memory
  • CD-ROM compact disk read-only memory
  • magnetic storage device or any suitable combination of the foregoing.

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Abstract

一种控制方法、设备及计算设备，应用于控制系统，控制系统包括一个BMC芯片和多个CPU，BMC芯片与多个CPU具有连接关系，方法包括：BMC芯片获取多个CPU中每个CPU的第一标识；BMC芯片基于多个第一标识生成多个虚拟BMC，多个虚拟BMC和多个CPU具有一一对应的关系；BMC芯片基于多个虚拟BMC管理多个CPU。

Description

控制方法、设备及计算设备
本申请要求于2022年10月28日提交中国专利局、申请号为202211335526.6、申请名称为“控制方法、设备及计算设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据处理技术领域，尤其涉及一种控制方法、设备及计算设备。
背景技术
基板管理控制器(Baseboard management controller，BMC)芯片可以对服务器进行管理。例如，BMC芯片可以管理服务器中的电池、风扇、内存和硬盘等部件的信息。
目前，为了提高机箱内的空间利用率，可以在机箱中设置多个单CPU的服务器，多个单CPU的服务器可以共用一套共享部件。例如，机箱中可以设置2个单CPU的服务器，且2个单CPU的服务器可以共用一套风扇和电源。
然而，每个单CPU的服务器都需要设置一个BMC芯片进行管理，进而导致服务器的成本较高，如何降低服务器的成本成为一个亟待解决的问题。
发明内容
本申请提供一种控制方法、设备及计算设备，用于解决现有技术中服务器的成本较高的技术问题。
第一方面，本申请提供一种控制方法，应用于控制系统，所述控制系统包括一个BMC芯片和多个CPU，所述BMC芯片与所述多个CPU具有连接关系，所述方法包括：
所述BMC芯片获取所述多个CPU中每个CPU的第一标识；
所述BMC芯片基于多个第一标识生成多个虚拟BMC，所述多个虚拟BMC和所述多个CPU具有一一对应的关系；
所述BMC芯片基于所述多个虚拟BMC管理多个CPU。
本申请提供的控制方法可以包括以下有益效果：通过BMC芯片为多个CPU生成虚拟BMC，进而通过独立的虚拟BMC对每个CPU进行管理，这样可以通过一个BMC芯片管理多个CPU，节约服务器的成本。
在一种可能的实施方式中，所述BMC芯片基于所述多个第一标识，生成多个虚拟BMC，包括：
所述BMC芯片基于所述多个第一标识，确定所述多个虚拟BMC的多个配置信息，所述多个虚拟BMC的配置信息不同；
所述BMC芯片基于所述多个配置信息，生成所述多个虚拟BMC，所述虚拟BMC的数量与所述第一标识的数量相同。
本申请提供的控制方法可以包括以下有益效果：由于BMC芯片可以根据每个CPU的第一标识确定虚拟BMC的配置信息，因此，BMC芯片通过配置信息可以生成相互独立的虚拟BMC，进而可以通过多个独立的虚拟BMC，管理多个独立的CPU，降低服务器的成本。
在一种可能的实施方式中，针对于任意一个虚拟BMC；所述BMC芯片基于所述第一标识，确定所述虚拟BMC的配置信息，包括：
所述BMC芯片基于所述第一标识，生成所述虚拟BMC的虚拟网口和虚拟外部接口，所述虚拟网口的IP地址与所述第一标识相关联，所述虚拟外部接口为与外部设备进行数据传输的虚拟接口；
所述BMC芯片基于所述虚拟网口和所述虚拟外部接口，确定所述虚拟BMC的配置信息。
本申请提供的控制方法可以包括以下有益效果：由于BMC芯片可以为通过第一标识，确定虚拟BMC的虚拟网口和虚拟外部接口，因此，多个虚拟BMC是相互独立的，并且每个虚拟BMC都具备BMC芯片管理CPU的功能，这样控制系统中只需要一个BMC芯片即可管理多个CPU，进而节约服务器的成本。
在一种可能的实施方式中，所述BMC芯片基于所述多个虚拟BMC管理多个CPU，包括：
所述BMC芯片获取所述BMC芯片与所述多个CPU的连接方式；
所述BMC芯片基于所述连接方式管理多个CPU。
本申请提供的控制方法可以包括以下有益效果：BMC芯片可以通过连接方式，获取部件信息，由于BMC芯片与多个CPU的连接方式不同，因此，BMC芯片获取部件信息的方式也不同，这样可以提高获取部件信息的灵活度。
在一种可能的实施方式中，所述BMC芯片基于所述连接方式管理多个CPU，包括：
若所述连接方式为所述BMC芯片通过M组管理接口分别与所述多个CPU相连，则所述BMC芯片基于每组管理接口管理对应的CPU，所述M与所述CPU的数量相同；
若所述连接方式为所述BMC芯片通过N组管理接口与所述多个CPU相连，则所述BMC芯片获取每组管理接口的接口类型，并基于所述接口类型管理多个CPU，所述接口类型为非共用类型或共用类型，所述N小于所述CPU的数量。
本申请提供的控制方法可以包括以下有益效果：BMC芯片可以通过管理接口的接口类型，确定获取部件信息的方法，进而提高部件信息获取的灵活度。
在一种可能的实施方式中，基于所述接口类型管理多个CPU，包括：
若所述管理接口组的接口类型为非共用类型，则基于所述管理接口管理对应的CPU；
若所述管理接口组的接口类型为共用接口类型，则基于分时访问的方式管理对应的CPU。
本申请提供的控制方法可以包括以下有益效果：在管理接口的接口类型为共用接口类型时，BMC芯片可以通过分时访问的方式获取服务器的部件信息，这样，通过BMC芯片的一个管理接口，管理多个CPU，进而节约BMC芯片的接口资源，降低服务器的成本。
在一种可能的实施方式中，所述多个CPU之间存在共享部件，所述方法还包括：
所述BMC芯片基于任意一个虚拟BMC获取共享部件信息，所述共享部件信息为所述 多个CPU共用的硬件设备的信息；
所述BMC芯片向其它虚拟BMC发送所述共享部件信息。
本申请提供的控制方法可以包括以下有益效果：由于多个虚拟BMC之间可以分享获取的共享部件信息，因此，这样可以节约系统资源，提高数据获取的可靠性。
第二方面，本申请提供一种控制装置，应用于控制系统，所述控制系统包括一个BMC芯片和多个CPU，所述BMC芯片与所述多个CPU具有连接关系，该控制装置可以包括第一获取模块、生成模块和管理模块，其中：
所述第一获取模块用于，获取所述多个CPU中每个CPU的第一标识；
所述生成模块用于，基于多个第一标识生成多个虚拟BMC，所述多个虚拟BMC和所述多个CPU具有一一对应的关系；
所述管理模块用于，基于所述多个虚拟BMC管理多个CPU。
本申请提供的控制装置可以包括以下有益效果：通过BMC芯片为多个CPU生成虚拟BMC，进而通过独立的虚拟BMC对每个CPU进行管理，这样可以通过一个BMC芯片管理多个CPU，节约服务器的成本。
在一种可能的实施方式中，所述生成模块具体用于：
基于所述多个第一标识，确定所述多个虚拟BMC的多个配置信息，所述多个虚拟BMC的配置信息不同；
基于所述多个配置信息，生成所述多个虚拟BMC，所述虚拟BMC的数量与所述第一标识的数量相同。
本申请提供的控制装置可以包括以下有益效果：由于BMC芯片可以根据每个CPU的第一标识确定虚拟BMC的配置信息，因此，BMC芯片通过配置信息可以生成相互独立的虚拟BMC，进而可以通过多个独立的虚拟BMC，管理多个独立的CPU，降低服务器的成本。
在一种可能的实施方式中，所述生成模块具体用于：
基于所述第一标识，生成所述虚拟BMC的虚拟网口和虚拟外部接口，所述虚拟网口的IP地址与所述第一标识相关联，所述虚拟外部接口为与外部设备进行数据传输的虚拟接口；
基于所述虚拟网口和所述虚拟外部接口，确定所述虚拟BMC的配置信息。
本申请提供的控制装置可以包括以下有益效果：由于BMC芯片可以为通过第一标识，确定虚拟BMC的虚拟网口和虚拟外部接口，因此，多个虚拟BMC是相互独立的，并且每个虚拟BMC都具备BMC芯片管理CPU的功能，这样控制系统中只需要一个BMC芯片即可管理多个CPU，进而节约服务器的成本。
在一种可能的实施方式中，所述管理模块具体用于：
获取所述BMC芯片与所述多个CPU的连接方式；
基于所述连接方式管理多个CPU。
本申请提供的控制装置可以包括以下有益效果：BMC芯片可以通过连接方式，获取部件信息，由于BMC芯片与多个CPU的连接方式不同，因此，BMC芯片获取部件信息的方式也不同，这样可以提高获取部件信息的灵活度。
在一种可能的实施方式中，所述管理模块具体用于：
若所述连接方式为所述BMC芯片通过M组管理接口分别与所述多个CPU相连，则基于每组管理接口管理对应的CPU，所述M与所述CPU的数量相同；
若所述连接方式为所述BMC芯片通过N组管理接口与所述多个CPU相连，则获取每组管理接口的接口类型，并基于所述接口类型管理多个CPU，所述接口类型为非共用类型或共用类型，所述N小于所述CPU的数量。
本申请提供的控制装置可以包括以下有益效果：BMC芯片可以通过管理接口的接口类型，确定获取部件信息的方法，进而提高部件信息获取的灵活度。
在一种可能的实施方式中，所述管理模块具体用于：
若所述管理接口组的接口类型为非共用类型，则基于所述管理接口管理对应的CPU；
若所述管理接口组的接口类型为共用接口类型，则基于分时访问的方式管理对应的CPU。
本申请提供的控制装置可以包括以下有益效果：在管理接口的接口类型为共用接口类型时，BMC芯片可以通过分时访问的方式获取服务器的部件信息，这样，通过BMC芯片的一个管理接口，管理多个CPU，进而节约BMC芯片的接口资源，降低服务器的成本。
在一种可能的实施方式中，控制装置还包括第二获取模块，所述第二获取模块用于：
所述BMC芯片基于任意一个虚拟BMC获取共享部件信息，所述共享部件信息为所述多个CPU共用的硬件设备的信息；
所述BMC芯片向其它虚拟BMC发送所述共享部件信息。
本申请提供的控制装置可以包括以下有益效果：由于多个虚拟BMC之间可以分享获取的共享部件信息，因此，这样可以节约系统资源，提高数据获取的可靠性。
第三方面，本申请提供一种BMC芯片，所述BMC芯片中包括至少一组管理接口，所述BMC芯片通过至少一组管理接口与多个CPU连接，所述BMC芯片通过所述管理接口与所述CPU进行数据传输。
本申请提供的BMC芯片可以包括以下有益效果：BMC芯片可以与多个CPU连接，进而通过一个BMC芯片管理多个CPU，降低服务器的成本。
第四方面，本申请提供一种控制设备，包括处理器和存储器；
所述存储器用于，存储计算机程序；
所述处理器用于，执行所述存储器中存储的计算机程序，以使得所述控制设备执行上述第一方面所述的方法。
第五方面，本申请提供一种计算设备，包括第三方面所述的BMC芯片，或如第四方面所述的控制设备。
第六方面，本申请提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，实现如上第一方面以及第一方面各种可能涉及的所述的方法。
第七方面，本公开实施例提供一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行时实现如上第一方面以及第一方面各种可能涉及的所述的方法。
本申请提供一种控制方法、设备及计算设备，应用于控制系统，其中，控制系统包括一个BMC芯片和多个CPU，BMC芯片与多个CPU具有连接关系，该方法包括BMC芯片获取多个CPU中每个CPU的第一标识，BMC芯片根据多个第一标识，生成多个虚拟 BMC，其中，多个虚拟BMC和多个CPU具有一一对应的关系，BMC芯片根据多个虚拟BMC管理多个CPU。在上述方法中，由于BMC芯片可以与多个CPU连接，并且为每个CPU生成独立的虚拟BMC，因此，BMC芯片可以通过多个虚拟BMC管理对应的CPU，进而通过一个BMC芯片管理多个CPU，降低服务器的成本。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一共控制系统的结构示意图；
图2A为本申请实施例提供的一种BMC芯片与CPU的连接方式的示意图；
图2B为本申请实施例提供的另一种BMC芯片与CPU的连接方式的示意图；
图3为本申请实施例提供的一种应用场景示意图；
图4为本申请实施例提供的一种控制方法的流程示意图；
图5为本申请实施例提供的一种管理CPU的过程示意图；
图6为本申请实施例提供的一种管理多个CPU的方法；
图7为本申请实施例提供的一种获取共享部件信息的方法示意图；
图8为本申请实施例提供的一种获取共享部件信息的过程示意图；
图9为本申请实施例提供的一种控制装置的结构示意图；
图10为本申请实施例提供的另一种控制装置的结构示意图；
图11为本申请实施例提供的一种计算设备的结构示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
为了便于理解，下面，对本申请实施例涉及的概念进行说明。
BMC芯片：BMC芯片可以为服务器中的管理芯片。例如，BMC芯片可以为基板管理控制器，BMC芯片是独立于服务器系统之外的小型操作系统，BMC芯片可以管理服务器中的电池、风扇、硬盘和内存等部件的信息。可选的，BMC芯片中可以包括物理接口和外部接口。例如，BMC芯片可以包括与CPU连接的物理接口，BMC芯片可以通过该接口访问CPU，BMC芯片也包括与外部设备连接的外部接口，BMC芯片可 以通过外部接口与网线、终端设备连接。
需要说明的是，外部接口可以为网口，该网口可以与网线进行连接，外部接口也可以为web接口，BMC芯片通过该web接口可以提供可视化操作界面，外部接口也可以为其它接口，本申请实施例对此不作限定。
虚拟BMC：虚拟BMC具备BMC芯片的管理功能。例如，虚拟BMC可以具备BMC芯片中的管理服务器的部件信息的功能。例如，虚拟BMC也可以管理服务器中的电池、风扇、硬盘和内存等部件信息。虚拟BMC可以具备BMC芯片的所有功能。例如，在实际应用过程中，每个CPU都为一个独立的系统，因此，每个CPU都需要一个独立BMC进行管理(即，一个BMC芯片只能管理一个CPU)，而本申请中的BMC芯片可以为每个CPU生成一个虚拟BMC，每个虚拟BMC都可以独立的管理一个BMC芯片连接的CPU，进而节约服务器的成本。
目前，服务器一般由中央处理器(Central Processing Unit，CPU)、内存、硬盘、网卡等设备组成，在一块主板支持2个独立服务器的场景，由2套以上部件组成，可看做是2台独立的物理服务器；同理，多套以上部件组成的独立运行系统可看做多台独立的物理服务器。
其中，一台服务器通常需要一颗BMC芯片，BMC芯片作为管理系统管理着整个服务器机箱里的所有硬件，如CPU、内存、硬盘、电源、风扇等。BMC芯片上运行着一个独立的软件系统，由这套软件提供对服务器硬件的管理功能，这套软件也可称为BMC软件。
在一些实施例中，为了提高机箱内的空间利用率，可以在机箱中设置多个单CPU的服务器，多个单CPU的服务器可以共用一套共享部件。例如，机箱中可以设置2个单CPU的服务器，且2个单CPU的服务器可以共用一套风扇和电源。但是，每个单CPU的服务器都需要设置一个BMC芯片进行管理，例如，若机箱内包括3个单CPU的服务器，则机箱中需要设置3个BMC芯片。这样导致服务器的成本较高，如何降低服务器的成本称为一个亟待解决的问题。
为了解决相关技术中的技术问题，本申请实施例提供一种控制方法，该控制方法应用于控制系统，其中，控制系统可以包括BMC芯片和多个CPU，BMC芯片与多个CPU具有连接，BMC芯片可以获取多个CPU中每个CPU第一标识，并根据多个第一标识，为每个CPU生成一个虚拟BMC，BMC芯片可以根据多个虚拟BMC管理多个CPU。在上述方法中，由于BMC芯片可以通过多个虚拟BMC管理多个独立的CPU所在的服务器，因此，多个单CPU的服务器只需要一个BMC芯片即可，进而降低服务器的成本。
下面，结合图1，对本申请实施例的控制系统的结构进行说明。
图1为本申请实施例提供的一种控制系统的结构示意图。请参见图1，图1中可以包括BMC芯片、CPU1、CPU2、CPU3和CPU4，BMC芯片可以分别与CPU1、CPU2、CPU3和CPU4连接，这样BMC芯片可以为每个CPU配置一个虚拟BMC，进而通过虚拟BMC获取每个CPU芯片的数据，降低控制系统的成本。
需要说明的是，图1只是示例性的示意本申请的控制系统，在实际应用过程中，控制系统中可以包括任意数量的CPU(如，1个、2个或3个等，本申请实施例对此不作限定)，并通过一个BMC芯片控制多个CPU。
可选的，本申请实施例包括一种BMC芯片，BMC芯片包括至少一组管理接口，BMC 芯片可以通过至少一组管理接口与多个CPU连接，BMC芯片可以通过管理接口与CPU进行数据传输。例如，BMC芯片可以通过一组管理接口与多个CPU连接，BMC芯片也可以通过多组管理接口与多个CPU连接。
下面，结合图2A-图2B，对本申请实施例的BMC芯片与CPU的连接方式进行说明。
图2A为本申请实施例提供的一种BMC芯片与CPU的连接方式的示意图。在图2A所示的实施例中，BMC芯片的管理接口组的数量与CPU的数量相同，请参见图2A，BMC芯片包括两组管理接口。其中，每组管理接口中都包括I3C接口、PECI接口和PCIE接口。BMC芯片通过一组管理接口与服务器1连接，BMC芯片通过另一组管理接口与服务器2连接，服务器1中包括CPU1，服务器2中包括CPU2。这样，BMC芯片可以为服务器1生成虚拟BMC1，为服务器2生成虚拟BMC2，虚拟BMC1可以通过连接服务器1的管理接口组与CPU1进行数据传输，虚拟BMC2可以通过连接服务器2的管理接口组与CPU2进行数据传输，这样，通过一个BMC芯片管理多个CPU，降低服务器的成本。
图2B为本申请实施例提供的另一种BMC芯片与CPU的连接方式的示意图。在图2B所示的实施例中，BMC芯片的管理接口组的数量小于CPU的数量，请参见图2B，BMC芯片包括2组管理接口，其中，每组管理接口都可以包括I3C接口、PECI接口和PCIE接口(图2B中未示出)，BMC芯片通过一组管理接口与服务器1连接，BMC芯片通过另一组管理接口与服务器2和服务器3连接，其中，服务器1中包括CPU1，服务器2中包括CPU2，服务器3中包括CPU3。这样，BMC芯片可以为服务器1生成虚拟BMC1，为服务器2生成虚拟BMC2，为服务器3生成虚拟BMC3，虚拟BMC1可以通过连接服务器1的一组管理接口与CPU1进行数据传输，虚拟BMC2和虚拟BMC3可以通过连接服务器2和服务器3的另一组管理接口，分时与CPU2和CPU3进行数据传输。
需要说明的是，本申请实施例中的一组管理接口可以包括BMC对CPU进行访问的所有接口。例如，一组管理接口中可以包括I3C接口、PECI接口和PCIE接口。例如，若BMC芯片中包括两组管理接口，则两组管理接口中都可以包括I3C接口、PECI接口和PCIE接口。
需要说明的是，多组管理接口中包括的接口可以相同，也可以不同，本申请实施例对此不作限定。例如，BMC芯片中的一组管理接口可以包括I3C接口和PECI接口，另一组管理接口可以包括PECI接口和PCIE接口。
可选的，在一组管理接口与多个CPU连接时，虚拟BMC可以通过分时访问的方式管理对应的CPU。例如，若BMC芯片中包括一组管理接口，该组管理接口与CPU1和CPU2连接，则BMC芯片可以生成CPU1对应的虚拟BMC1，生成CPU2对应的虚拟BMC2，其中，虚拟BMC1和虚拟BMC2都通过该组管理接口管理对应的CUP，在第一个周期，虚拟BMC1通过该组管理接口访问CPU1，在下一个周期，虚拟BMC2通过该组管理接口访问CPU2，需要说明的是，本申请实施例也可以通过其它的方法确定分时访问的方式，本申请实施例对此不作限定，这样，在管理接口资源较少时，一个BMC芯片也可以管理多个CPU，提高BMC芯片的资源利用率。
下面，结合图3，对本申请实施例的应用场景进行说明。
图3为本申请实施例提供的一种应用场景示意图。请参见图3，图3中可以包括2P服务器(包括2个单CPU的服务器)，其中，2P服务器中可以包括BMC芯片、CPU1和CPU2， BMC芯片分别与CPU1和CPU2连接。CPU1还可以和硬盘1和内存1连接，CPU2还可以和硬盘2和内存2连接。BMC芯片可以管理CPU1和CPU2。例如，BMC芯片可以获取CPU1的温度、硬盘1的剩余空间、CPU2的温度和硬盘2的剩余空间，这样，2P服务器中只需要设置1个BMC芯片，即可管理CPU1和CPU2，无需分别为每个CPU设置一个BMC芯片，进而降低2P服务器的成本。
需要说明的是，图3只是示例性的示意本申请实施例的应用场景，并非对本申请实施例的应用场景的限定。
下面以具体地实施例对本公开的技术方案以及本公开的技术方案如何解决上述技术问题进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本公开的实施例进行描述。
图4为本申请实施例提供的一种控制方法的流程示意图。请参见图4，该方法可以包括：
S401、获取多个CPU的多个第一标识。
本申请实施例的执行主体可以为BMC芯片。可选的，控制系统包括BMC芯片和多个CPU，BMC芯片分别与多个CPU连接。例如，控制系统中可以包括1个BMC芯片和2个服务器，服务器可以为单CPU服务器，该BMC芯片分别与2个服务器中的CPU连接，控制系统中也可以包括1个BMC芯片和4个单CPU服务器，该BMC芯片分别与4个单CPU服务器中的CPU连接，本申请实施例对此不作限定。
可选的，BMC芯片用于管理控制系统中的所有硬件。例如，BMC芯片可以管理多P服务器中的部件、板卡、电源和风扇等。可选的，多P服务器可以为多个CPU组成的服务器。例如，服务器中可以包括CPU、内存、硬盘和网卡等部件组成，在一块主板支持2个独立的服务器时，该服务器中包括2套上述部件，这样该服务器可以为2台独立的物理服务器(2P服务器)。
可选的，BMC芯片上可以运行独立的系统，通过该独立的系统可以对服务器的硬件进行管理。例如，BMC芯片可以通过芯片中的管理系统，获取服务器的电量、风扇的转速等信息。可选的，BMC芯片可以控制服务器中的部件。例如，在服务器中的部件发生报警时，BMC芯片可以通过运行的独立的系统对服务器中的报警部件进行控制。例如，BMC芯片可以消除服务器中的报警信息等。
可选的，第一标识可以为CPU的身份标识号。例如，第一标识可以为CPU的ID，BMC芯片可以根据每个CPU的配置信息，获取CPU的第一标识。例如，控制系统中可以包括CPU1和CPU2，若CPU1的ID为1，CPU2的ID为2，则BMC芯片获取的CPU1的第一标识为1，BMC芯片获取的CPU2的第一标识为2。需要说明的是，CPU的第一标识可以为预先设置的标识，例如，在组装多P服务器时，可以预先为每个CPU配置对应的ID。
可选的，BMC芯片可以根据如下可行的实现方式，获取CPU的第一标识：向CPU发送查询指令。其中，查询指令可以用于查询CPU的第一标识。接收CPU发送的第一标识。例如，在BMC芯片启动时，BMC芯片可以向已连接的多个CPU发送标识查询指令，在BMC芯片接收到多个CPU发送的标识时，BMC芯片可以得到多个第一标识。
可选的，在BMC芯片获取CPU的第一标识之前，BMC芯片可以根据虚拟控制开关的状态，确定是否获取CPU的第一标识，其中，虚拟控制开关用于控制BMC芯片是否开 启虚拟BMC的功能。例如，若该虚拟控制开关为打开状态，则BMC芯片可以获取多个CPU的第一标识，若虚拟控制开关为关闭状态，则BMC芯片无需获取CPU的第一标识。需要说明的，该虚拟控制开关可以通过web接口可视化在终端设备中，进而在终端设备中控制虚拟控制开关的状态，本申请实施例也可以通过其它方式控制虚拟控制开关，本申请实施例对此不作限定。
S402、基于多个第一标识，生成多个虚拟BMC。
可选的，虚拟BMC具备BMC芯片的功能，多个虚拟BMC和多个CPU具有一一对应的关系。例如，虚拟BMC可以为虚拟化的BMC，若CPU为云端中的云服务器的CPU，则虚拟BMC也可以为在云端中生成的BMC，每个虚拟BMC都可以为独立的一个BMC管理系统。例如，BMC芯片中可以安装BMC软件，BMC软件可以为每个CPU生成一个虚拟BMC，进而通过虚拟BMC获取CPU的部件信息。例如，若多P服务器中包括CPU1和CPU2，则BMC芯片可以生成虚拟BMC1和虚拟BMC2，虚拟BMC1用于获取CPU1的部件信息，虚拟BMC2用于获取CPU2的部件信息，由于多P服务器中的CPU1和CPU2相互独立，因此，虚拟BMC1和虚拟BMC2都为独立的BMC。
可选的，BMC芯片可以根据如下可行的实现方式，生成多个虚拟BMC：基于多个第一标识，确定多个虚拟BMC的多个配置信息，基于多个配置信息，生成多个虚拟BMC。可选的，配置信息可以包括生成虚拟BMC所需的多个参数，BMC芯片通过配置信息，可以生成对应的虚拟BMC。例如，配置信息可以包括虚拟网口和虚拟外部接口，BMC芯片通过虚拟网口和虚拟外部接口可以生成虚拟BMC。可选的，虚拟BMC的数量与第一标识的数量相同。例如，若多P服务器中包括2个CPU，则BMC芯片可以获取2个第一标识，进而根据2个第一标识，确定2个配置信息，并根据2个配置信息生成2个虚拟BMC。
可选的，多个虚拟BMC的配置信息不同。例如，若控制系统中包括CPU1和CPU2，则BMC芯片可以根据CPU1的第一标识，确定虚拟BMC1的配置信息1，根据CPU2的第一标识，确定虚拟BMC2的配置信息2，其中，由于CPU1的第一标识与CPU2的第一标识不同，因此，配置信息1和配置信息2也不同。
可选的，针对任意一个虚拟BMC，BMC芯片可以根据如下可行的实现方式，确定虚拟BMC的配置信息：基于第一标识，生成虚拟BMC的虚拟网口和虚拟外部接口，基于虚拟网口和虚拟外部接口，确定虚拟BMC的配置信息。可选的，虚拟网口的IP地址与第一标识相关联。例如，BMC芯片可以根据CPU的ID初始化网口，通过操作系统网络协议栈可以虚拟多个网口设备(如，eth0：1、eth0：2或eth0：3等)。
可选的，虚拟网口的IP地址可以根据CPU的第一标识进行自动排列。例如，多P服务器中可以包括CUP1和CPU2，其中，CPU1的第一标识为1，CPU2的第一标识为2，BMC芯片生成的CPU1的虚拟网口的IP地址可以为888.888.8.881(1为CPU1的第一标识)，BMC芯片生成的CPU2的虚拟网口的IP地址可以为888.888.8.882(2为CPU2的第一标识)。
可选的，虚拟外部接口为与外部设备进行数据传输的虚拟接口。例如，虚拟外部接口可以包括web接口(提供可视化操作页面)、cli接口(提供命令行操作页面)等，通过虚拟外部接口可以与外部设备进行数据传输。可选的，多个虚拟外部接口可以与不同的虚拟网口绑定。例如，虚拟web接口和虚拟cli接口可以与不同的IP地址(每个虚拟网口的IP 地址都不同)绑定，这样，每个虚拟网口都可以绑定多个虚拟外部接口。
可选的，BMC芯片可以将虚拟网口和虚拟外部接口确定为虚拟BMC的配置信息。例如，BMC芯片根据第一标识生成虚拟网口和虚拟外部接口之后，BMC芯片可以将虚拟网口的信息和虚拟外部接口的信息确定为该虚拟BMC的配置信息。可选的，BMC芯片可以基于配置信息生成虚拟BMC。例如，BMC芯片确定虚拟网口和虚拟外部接口之后，可以生成虚拟BMC，该虚拟BMC包括独立的IP地址、全套的虚拟外部接口，该虚拟BMC可以为一个CPU的管理系统。
S403、基于多个虚拟BMC管理多个CPU。
可选的，BMC芯片可以基于多个虚拟BMC，获取CPU的信息、服务器的信息等，进而管理CPU。例如，BMC芯片可以基于多个虚拟BMC获取服务器内的CPU信息、内存信息、硬盘信息、网卡信息、电池信息、硬盘剩余空间、内存利用率和风扇转速等。BMC芯片可以通过多个虚拟BMC管理多个CPU。例如，BMC芯片与CPU1和CPU2连接，BMC芯片生成虚拟BMC1和虚拟BMC2，并通过虚拟BMC1获取CPU1的信息，通过虚拟BMC2获取CPU2的信息。例如，多P服务器中包括3个CPU，BMC芯片可以生成3个虚拟BMC，并通过3个虚拟BMC获取3个CPU的信息。
下面，结合图5，对根据多个虚拟BMC管理多个CPU的过程进行说明。
图5为本申请实施例提供的一种管理CPU的过程示意图。请参见图5，图5中可以包括BMC芯片对应的BMC软件、服务器1(单CPU的服务器)的管理资源(CPU1、内存1和硬盘1)和服务器2(单CPU的服务器)的管理资源(CPU2、内存2和硬盘2)。BMC软件可以根据服务器1的CPU1的ID生成虚拟BMC1，根据服务器2的CPU2的ID生成虚拟BMC2。BMC软件可以通过虚拟BMC1获取服务器1的管理资源的部件信息，通过虚拟BMC2获取服务器2的管理资源的部件信息。
需要说明的是，本申请中的虚拟网口和虚拟外部接口与本申请中的管理接口组不同，虚拟BMC可以通过管理接口组访问CPU，而管理CPU需要实际的物理接口，因此，本申请中的BMC芯片需要包括至少一组管理接口组(如，I3C、PECI等)，而BMC芯片还包括与外部设备交互的网口和外部接口(如，web、cli等)，因此，在生成虚拟BMC时，还需要针对网口和外部接口的功能，生成虚拟网口和虚拟外部接口。
本申请实施例提供一种控制方法，应用于控制系统，该控制系统可以包括一个BMC芯片和多个CPU，BMC芯片与多个CPU具有连接关系，BMC芯片可以获取多个CPU中每个CPU的第一标识，并根据第一标识，生成虚拟BMC的虚拟网口和虚拟外部接口，根据虚拟网口和虚拟外部接口，确定虚拟BMC的配置信息，BMC芯片可以根据多个配置信息，生成多个虚拟BMC，并通过多个虚拟BMC管理多个CPU。在上述方法中，由于BMC芯片可以通过多个虚拟BMC管理多个独立的CPU，因此，多个单CPU的服务器只需要一个BMC芯片即可，进而降低服务器的成本。
在图4所示的实施例的基础上，下面，结合图6，对上述控制方法中，根据多个虚拟BMC管理多个CPU的方法进行详细的说明。
图6为本申请实施例提供的一种管理多个CPU的方法。请参见图6，该方法流程包括：
S601、获取BMC芯片与多个CPU的连接方式。
可选的，BMC芯片与多个CPU的连接方式，有如下两种情况：
情况1：BMC芯片通过M组管理接口分别与多个CPU相连，M与CPU的数量相同。
可选的，在该种情况中，BMC芯片可以为每个CPU都配置一组管理接口，进而通过多组管理接口，并行的管理多个CPU。例如，多P服务器中包括CPU1、CPU2和BMC芯片，BMC芯片可以通过一组管理接口与CPU1连接，BMC芯片可以通过另一组管理接口与CPU2连接，BMC芯片可以通过一组管理接口管理CPU1，BMC芯片可以通过另一组管理接口管理CPU2。
情况2：BMC芯片通过N组管理接口与多个CPU相连，N小于CPU的数量。
可选的，在该种情况中，由于BMC芯片中的管理接口的组数小于CPU的数量，因此，至少存在两个CPU与同一组管理接口连接，BMC芯片可以通过N组管理接口管理多个CPU。例如，多P服务器中包括CPU1、CPU2、CPU3和BMC芯片，BMC芯片中可以包括管理接口组A和管理接口组B，BMC芯片可以通过管理接口组A与CPU1连接，BMC芯片可以通过管理接口组B与CPU2和CPU3连接，BMC芯片可以通过管理接口组A管理CPU，BMC芯片可以通过管理接口组B管理CPU2和CPU3。
S602、基于连接方式管理多个CPU。
可选的，BMC芯片基于连接方式管理多个CPU，有如下两种情况：
情况1：连接方式为BMC芯片通过M组管理接口分别与多个CPU相连。
可选的，若连接方式为BMC芯片通过M组管理接口分别与多个CPU相连，则通过每组管理接口管理对应的CPU，其中，M与CPU的数量相同。例如，多P服务器中包括CPU1、CPU2和BMC芯片，其中，BMC芯片中包括管理接口组A和管理接口组B，若BMC芯片通过管理接口组A与CPU1连接，通过管理接口组B与CPU2连接，则BMC芯片可以通过管理接口组A管理CPU1，通过管理接口组B管理CPU2。
情况2：连接方式为BMC芯片通过N组管理接口与多个CPU相连。
可选的，若连接方式为BMC芯片通过N组管理接口与多个CPU相连，则获取每组管理接口的接口类型，并根据接口类型管理多个CPU，其中，N小于CPU的数量。可选的，接口类型可以为非共用类型或共用类型。可选的，非共用类型的管理接口组可以独立连接一个CPU，共用类型的管理接口组可以连接至少两个CPU。例如，BMC芯片中包括管理接口组A和管理接口组B，若BMC芯片通过管理接口组A与CPU1连接，通过管理接口B组与CPU2和CPU3连接，则管理接口组A的接口类型为非共用类型，管理接口组B的接口类型为共用类型。
可选的，基于接口类型管理多个CPU，具体为：若管理接口组的接口类型为非共用类型，则通过管理接口组管理对应的CPU。例如，若管理接口组的接口类型为非共用类型，则说明该管理接口组独立连接一个CPU，因此，BMC芯片可以通过该管理接口组获取连接的CPU的部件信息。
若管理接口组的接口类型为共用接口类型，则通过分时访问的方式管理对应的CPU。例如，若管理接口组的接口类型为共用类型，则说明该管理接口组同时连接多个CPU，因此，BMC芯片无法通过该管理接口组同时管理该管理接口组连接的多个CPU，BMC芯片可以通过分时访问的方式管理多个CPU。例如，若管理接口组同时连接CPU1和CPU2，则BMC芯片可以在一个周期内通过该管理接口组管理CPU1，在下一个周期内通过该管理接口组管理CPU2。
本申请实施例提供一种控制方法，获取BMC芯片与多个CPU的连接方式，若连接方式为BMC芯片通过M组管理接口分别与多个CPU相连，则通过每组管理接口管理多个CPU，若连接方式为BMC芯片通过N组管理接口与多个CPU相连，则获取每组管理接口的接口类型，并基于接口类型管理多个CPU。这样，在BMC芯片通过多组管理接口分别与每个CPU链接时，BMC芯片可以通过每组管理接口独立的管理对应的CPU，在BMC芯片通过一组管理接口与多个CPU连接时，BMC芯片可以通过该组管理接口，分时管理该管理接口组连接的多个CPU，进而提高CPU管理的灵活度，并且，由于一个BMC芯片可以通过多个虚拟BMC管理多个CPU，因此，无需为每个CPU设置一个BMC芯片，进而降低服务器的成本。
在上述任意一个实施例的基础上，多个CPU之间存在共享部件，上述控制方法中还包括共享部件信息的获取方法，下面，结合图7，对获取共享部件信息的方法进行说明。
图7为本申请实施例提供的一种获取共享部件信息的方法示意图。请参见图7，该方法流程包括：
S701、基于任意一个虚拟BMC获取共享部件信息。
可选的，共享部件信息为所述多个CPU共用的硬件设备的信息。例如，共享部件信息可以包括电源信息、风扇信息和网络信息等，多个CPU可以共用一个风扇和电源等硬件设备。
可选的，BMC芯片可以通过任意一个虚拟BMC获取共享部件信息。例如，若BMC芯片生成虚拟BMC1和虚拟BMC2，则BMC芯片可以通过虚拟BMC1获取共享部件信息，BMC芯片也可以通过虚拟BMC2获取共享部件信息。
可选的，BMC芯片也可以通过多个虚拟BMC获取共享部件信息，并对多个虚拟BMC获取的共享部件信息进行验证。例如，BMC芯片可以通过虚拟BMC1获取共享部件信息1，通过虚拟BMC2获取共享部件信息2，并将共享部件信息1和共享部件信息2进行对比，若共享部件信息1与共享部件信息2相同，则确定共享部件信息验证成功，若共享部件信息1与共享部件信息2不同，则确定共享部件信息验证失败，这样可以提高数据的可靠性，进而提高服务器的安全性。
S702、向其它虚拟BMC发送共享部件信息
可选的，BMC芯片通过任意一个虚拟BMC获取到共享部件信息之后，可以向其它的虚拟BMC发送共享部件信息，这样可以避免共享部件信息的重复获取，进而可以节约控制系统的系统资源。
下面，结合图8，对获取共享部件信息的过程进行说明。
图8为本申请实施例提供的一种获取共享部件信息的过程示意图。请参见图8，图8中可以包括BMC芯片对应的BMC软件、服务器1的管理资源(CPU1、内存1和硬盘1)和服务器2的管理资源(CPU2、内存2和硬盘2)。共享部件中包括风扇、电源等部件。BMC软件可以根据服务器1的CPU1的ID生成虚拟BMC1，根据服务器2的CPU2的ID生成虚拟BMC2。BMC芯片可以通过虚拟BMC1获取共享部件信息，并向虚拟BMC2发送共享部件信息。这样，多个虚拟BMC之间可以分享获取的共享部件信息，节约系统资源，提高数据获取的可靠性。
图9为本申请实施例提供的一种控制装置的结构示意图。请参见图9，该控制装置900， 该控制装置900可以包括第一获取模块901、生成模块902和管理模块903，其中：
所述第一获取模块901用于，获取所述多个CPU中每个CPU的第一标识；
所述生成模块902用于，基于多个第一标识生成多个虚拟BMC，所述多个虚拟BMC和所述多个CPU具有一一对应的关系；
所述管理模块903用于，基于所述多个虚拟BMC管理多个CPU。
在一种可能的实施方式中，所述生成模块102具体用于：
基于所述多个第一标识，确定所述多个虚拟BMC的多个配置信息，所述多个虚拟BMC的配置信息不同；
基于所述多个配置信息，生成所述多个虚拟BMC，所述虚拟BMC的数量与所述第一标识的数量相同。
在一种可能的实施方式中，所述生成模块902具体用于：
基于所述第一标识，生成所述虚拟BMC的虚拟网口和虚拟外部接口，所述虚拟网口的IP地址与所述第一标识相关联，所述虚拟外部接口为与外部设备进行数据传输的虚拟接口；
基于所述虚拟网口和所述虚拟外部接口，确定所述虚拟BMC的配置信息。
在一种可能的实施方式中，所述管理模块903具体用于：
获取所述BMC芯片与所述多个CPU的连接方式；
基于所述连接方式管理多个CPU。
在一种可能的实施方式中，所述管理模块903具体用于：
若所述连接方式为所述BMC芯片通过M组管理接口分别与所述多个CPU相连，则基于每组管理接口管理对应的CPU，所述M与所述CPU的数量相同；
若所述连接方式为所述BMC芯片通过N组管理接口与所述多个CPU相连，则获取每组管理接口的接口类型，并基于所述接口类型管理多个CPU，所述接口类型为非共用类型或共用类型，所述N小于所述CPU的数量。
在一种可能的实施方式中，所述管理模块903具体用于：
若所述管理接口组的接口类型为非共用类型，则基于所述管理接口管理对应的CPU；
若所述管理接口组的接口类型为共用接口类型，则基于分时访问的方式管理对应的CPU。
本申请实施例提供的控制装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此处不再进行赘述。
图10为本申请实施例提供的另一种控制装置的结构示意图。在图9所示的实施例的基础上，请参见图10，该控制装置还包括第二获取模块904，所述第二获取模块904用于：
基于任意一个虚拟BMC获取共享部件信息，所述共享部件信息为所述多个CPU共用的硬件设备的信息；
向其它虚拟BMC发送所述共享部件信息。
本申请实施例提供的控制装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此处不再进行赘述。
图11为本申请实施例提供的一种计算设备的结构示意图。请参见图11，其示出了适于用来实现本公开实施例的计算设备1100的结构示意图，计算设备1100可以包括处理装 置(例如中央处理器、图形处理器等)1101，其可以根据存储在只读存储器(Read Only Memory，简称ROM)1102中的程序或者从存储装置1108加载到随机访问存储器(Random Access Memory，简称RAM)1103中的程序而执行各种适当的动作和处理。在RAM 1103中，还存储有计算设备1100操作所需的各种程序和数据。处理装置1101、ROM 1102以及RAM 1103通过总线1104彼此相连。输入/输出(I/O)接口1105也连接至总线1104。
通常，以下装置可以连接至I/O接口1105：包括例如触摸屏、触摸板、键盘、鼠标、摄像头、麦克风、加速度计、陀螺仪等的输入装置1106；包括例如液晶显示器(Liquid Crystal Display，简称LCD)、扬声器、振动器等的输出装置1107；包括例如磁带、硬盘等的存储装置1108；以及通信装置1109。通信装置1109可以允许计算设备1100与其他设备进行无线或有线通信以交换数据。虽然图11示出了具有各种装置的计算设备1100，但是应理解的是，并不要求实施或具备所有示出的装置。可以替代地实施或具备更多或更少的装置。
特别地，根据本公开的实施例，上文参考流程图描述的过程可以被实现为计算机软件程序。例如，本公开的实施例包括一种计算机程序产品，其包括承载在计算机可读介质上的计算机程序，该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信装置1109从网络上被下载和安装，或者从存储装置1108被安装，或者从ROM 1102被安装。在该计算机程序被处理装置1101执行时，执行本公开实施例的方法中限定的上述功能。
需要说明的是，本公开上述的计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本公开中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。而在本公开中，计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读信号介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：电线、光缆、RF(射频)等等，或者上述的任意合适的组合。
可选的，本申请提供一种BMC芯片，所述BMC芯片中包括至少一套管理接口，所述BMC芯片通过至少一套管理接口与多个CPU连接。
可选的，本申请还提供一种控制设备，包括处理器和存储器；所述存储器用于，存储计算机程序；所述处理器用于，执行所述存储器中存储的计算机程序，以使得所述控制设备执行本申请实施例中所述的方法。
可选的，计算设备可以包括上述控制设备或上述BMC芯片。
上述计算机可读介质可以是上述计算设备中所包含的；也可以是单独存在，而未装配 入该计算设备中。
上述计算机可读介质承载有一个或者多个程序，当上述一个或者多个程序被该计算设备执行时，使得该计算设备执行上述实施例所示的方法。
可以以一种或多种程序设计语言或其组合来编写用于执行本公开的操作的计算机程序代码，上述程序设计语言包括面向对象的程序设计语言—诸如Java、Smalltalk、C++，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络——包括局域网(Local Area Network，简称LAN)或广域网(Wide Area Network，简称WAN)—连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。
附图中的流程图和框图，图示了按照本公开各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，该模块、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
描述于本公开实施例中所涉及到的单元可以通过软件的方式实现，也可以通过硬件的方式来实现。其中，单元的名称在某种情况下并不构成对该单元本身的限定，例如，第一获取单元还可以被描述为“获取至少两个网际协议地址的单元”。
本文中以上描述的功能可以至少部分地由一个或多个硬件逻辑部件来执行。例如，非限制性地，可以使用的示范类型的硬件逻辑部件包括：现场可编程门阵列(FPGA)、专用集成电路(ASIC)、专用标准产品(ASSP)、片上系统(SOC)、复杂可编程逻辑设备(CPLD)等等。
在本公开的上下文中，机器可读介质可以是有形的介质，其可以包含或存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的程序。机器可读介质可以是机器可读信号介质或机器可读储存介质。机器可读介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。机器可读存储介质的更具体示例会包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或快闪存储器)、光纤、便捷式紧凑盘只读存储器(CD-ROM)、光学储存设备、磁储存设备、或上述内容的任何合适组合。
需要注意，本公开中提及的“一个”、“多个”的修饰是示意性而非限制性的，本领域技术人员应当理解，除非在上下文另有明确指出，否则应该理解为“一个或多个”。
以上描述仅为本公开的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的公开范围，并不限于上述技术特征的特定组合而成的技术方案， 同时也应涵盖在不脱离上述公开构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。
此外，虽然采用特定次序描绘了各操作，但是这不应当理解为要求这些操作以所示出的特定次序或以顺序次序执行来执行。在一定环境下，多任务和并行处理可能是有利的。同样地，虽然在上面论述中包含了若干具体实现细节，但是这些不应当被解释为对本公开的范围的限制。在单独的实施例的上下文中描述的某些特征还可以组合地实现在单个实施例中。相反地，在单个实施例的上下文中描述的各种特征也可以单独地或以任何合适的子组合的方式实现在多个实施例中。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。

Claims (10)

  1. 一种控制方法，其特征在于，应用于控制系统，所述控制系统包括一个BMC芯片和多个CPU，所述BMC芯片与所述多个CPU具有连接关系，所述方法包括：
    所述BMC芯片获取所述多个CPU中每个CPU的第一标识；
    所述BMC芯片基于多个第一标识生成多个虚拟BMC，所述多个虚拟BMC和所述多个CPU具有一一对应的关系；
    所述BMC芯片基于所述多个虚拟BMC管理多个CPU。
  2. 根据权利要求1所述的方法，其特征在于，所述BMC芯片基于所述多个第一标识，生成多个虚拟BMC，包括：
    所述BMC芯片基于所述多个第一标识，确定所述多个虚拟BMC的多个配置信息，所述多个虚拟BMC的配置信息不同；
    所述BMC芯片基于所述多个配置信息，生成所述多个虚拟BMC，所述虚拟BMC的数量与所述第一标识的数量相同。
  3. 根据权利要求2所述的方法，其特征在于，针对于任意一个虚拟BMC；所述BMC芯片基于所述第一标识，确定所述虚拟BMC的配置信息，包括：
    所述BMC芯片基于所述第一标识，生成所述虚拟BMC的虚拟网口和虚拟外部接口，所述虚拟网口的IP地址与所述第一标识相关联，所述虚拟外部接口为与外部设备进行数据传输的虚拟接口；
    所述BMC芯片基于所述虚拟网口和所述虚拟外部接口，确定所述虚拟BMC的配置信息。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，所述BMC芯片基于所述多个虚拟BMC管理多个CPU，包括：
    所述BMC芯片获取所述BMC芯片与所述多个CPU的连接方式；
    所述BMC芯片基于所述连接方式管理多个CPU。
  5. 根据权利要求4所述的方法，其特征在于，所述BMC芯片基于所述连接方式管理多个CPU，包括：
    若所述连接方式为所述BMC芯片通过M组管理接口分别与所述多个CPU相连，则所述BMC芯片基于每组管理接口管理对应的CPU，所述M与所述CPU的数量相同；
    若所述连接方式为所述BMC芯片通过N组管理接口与所述多个CPU相连，则所述BMC芯片获取每组管理接口的接口类型，并基于所述接口类型管理多个CPU，所述接口类型为非共用类型或共用类型，所述N小于所述CPU的数量。
  6. 根据权利要求5所述的方法，其特征在于，基于所述接口类型管理多个CPU，包括：
    若所述管理接口组的接口类型为非共用类型，则基于所述管理接口管理对应的CPU；
    若所述管理接口组的接口类型为共用接口类型，则基于分时访问的方式管理对应的CPU。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，所述多个CPU之间存在共享部件，所述方法还包括：
    所述BMC芯片基于任意一个虚拟BMC获取共享部件信息，所述共享部件信息为所述多个CPU共用的硬件设备的信息；
    所述BMC芯片向其它虚拟BMC发送所述共享部件信息。
  8. 一种BMC芯片，其特征在于，所述BMC芯片中包括至少一组管理接口，所述BMC芯片通过至少一组管理接口与多个CPU连接，所述BMC芯片通过所述管理接口与所述CPU进行数据传输。
  9. 一种控制设备，其特征在于，包括处理器和存储器；
    所述存储器用于，存储计算机程序；
    所述处理器用于，执行所述存储器中存储的计算机程序，以使得所述控制设备执行上述权利要求1-7任一项所述的方法。
  10. 一种计算设备，其特征在于，包括如权利要求8所述的BMC芯片，或如权利要求9所述的控制设备。
PCT/CN2023/118996 2022-10-28 2023-09-15 控制方法、设备及计算设备 WO2024087932A1 (zh)

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