WO2024087145A1 - Dispositif de mémoire et procédé d'adressage associé - Google Patents

Dispositif de mémoire et procédé d'adressage associé Download PDF

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Publication number
WO2024087145A1
WO2024087145A1 PCT/CN2022/128149 CN2022128149W WO2024087145A1 WO 2024087145 A1 WO2024087145 A1 WO 2024087145A1 CN 2022128149 W CN2022128149 W CN 2022128149W WO 2024087145 A1 WO2024087145 A1 WO 2024087145A1
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WIPO (PCT)
Prior art keywords
memory
memory cells
columns
data
enable
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PCT/CN2022/128149
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English (en)
Inventor
Jianping Li
Xiang FU
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Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
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Priority to CN202280005055.4A priority Critical patent/CN118266029A/zh
Priority to PCT/CN2022/128149 priority patent/WO2024087145A1/fr
Publication of WO2024087145A1 publication Critical patent/WO2024087145A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

Definitions

  • the present disclosure relates to memory devices and addressing methods thereof.
  • I/O speed is an important indicator of the performance of a memory device.
  • its cell operation time i.e., writing time and reading time, is decided by the physical properties of the memory cell.
  • the I/O speed is proportional to and limited by the I/O width of the memory device.
  • Phase-change memory (PCM) cells are non-volatile memory devices that store data using a phase-change material.
  • PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials, e.g., chalcogenide alloys, based on heating and quenching of the phase-change materials electrothermally.
  • a memory device including a plurality of memory banks.
  • the memory device further includes an enable module coupled to the memory cells and/or the data controllers and configured to enable p columns of the k columns from each group in each bank, where 0 ⁇ p ⁇ k.
  • the addressing module includes an address register configured to store address commands, an address controller configured to determine address data based on an input signal and the address commands, and an address decoder configured to output i address values corresponding to the i groups of memory cells, and assign each address value to the columns of memory cells in a same group.
  • a number of the memory cells in each column is M
  • a number of the data controllers in each set is M
  • M is a positive integer
  • each of the data controllers is configured to operate i memory cells from each of the i groups.
  • each of the data controllers is configured to store data with one bit
  • the data controllers are configured to store data with k ⁇ M bits
  • the memory bank is configured to operate data with p ⁇ M bits in a clock cycle.
  • the enable module includes an enable register configured to store enable commands, an enable controller configured to determine an enable data based on an input signal and the enable commands, and an enable decoder configured to output k enable signals corresponding to the k columns of memory cells in a same group, and each of the k enable signals is configured to control i columns from each of the i groups.
  • a number of the memory cells in each group is k ⁇ M
  • the memory cells in each group correspond to the data controllers one by one
  • the enable module is further configured to enable p columns of the k columns from each of the i groups by enabling p ⁇ M memory cells and disabling (k-p) ⁇ M memory cells in each of the i groups.
  • a number of the memory cells in each group is k ⁇ M
  • the memory cells in each of the i groups correspond to the data controllers one by one
  • the enable module is further configured to enable p columns of the k columns from each of the i groups by enabling p ⁇ M data controllers and disabling (k-p) ⁇ M data controllers.
  • each of the k enable signals is binary data with one bit.
  • p enable signals of k enable signals are 1, and (k-p) enable signals of k enable signals are 0.
  • a column of memory cells is on when the enable signal is 1 and off when the enable signal is 0.
  • one of the i groups of memory cells is selected and operated in a clock cycle.
  • i 2 x
  • the address data is binary data with x bit, where x is a positive integer.
  • a maximum value of x is
  • a memory system including a memory device including a plurality of memory banks and a memory controller coupled to the memory device and configured to control the memory device.
  • Each of the memory banks configured to store data includes an array of memory cells with N columns, where N is a positive integer, an addressing module configured to divide the memory cells into i groups by assigning i addresses to the N columns, where a plurality of data controllers configured to operate one of the i groups of memory cells, and an enable module coupled to the memory cells and/or the data controllers and configured to enable part of the k columns from each of the i groups in each bank.
  • a number of the memory cells in each column is M
  • a number of the columns of memory cells enabled by the enable module from each group is p
  • a number of the data controllers is k ⁇ M
  • a number of the memory cells in each group is k ⁇ M
  • the memory cells in each group correspond to the data controllers one by one.
  • each of the data controllers is configured to operate i memory cells from each of the i groups.
  • each of the data controllers is configured to store data with one bit
  • the k ⁇ M data controllers are configured to store data with k ⁇ M bits
  • the memory bank is configured to operate data with p ⁇ M bits in a clock cycle.
  • the addressing module includes an address register configured to store address commands, an address controller configured to determine address data based on an input signal and the address commands, and an address decoder configured to output i address values corresponding to the i groups of memory cells, and assign each address value to the columns of memory cells in a same group.
  • the enable module includes an enable register configured to store enable commands, an enable controller configured to determine an enable data based on an input signal and the enable commands, and an enable decoder configured to output k enable signals corresponding to the k columns of memory cells in a same group, and each of the k enable signals is configured to control i columns from each of the i groups.
  • the enable module is configured to enable p of the k columns from each of the i groups by enabling p ⁇ M memory cells and disabling (k-p) ⁇ M memory cells in each of the i groups.
  • the enable module is configured to enable p of the k columns from each group by enabling p ⁇ M data controllers and disabling (k-p) ⁇ M data controllers.
  • a method for addressing a memory device including a plurality of memory banks each of the memory banks includes an array of memory cells with N columns, where N is a positive integer.
  • a number of the memory cells in each column is M
  • operating the selected group by data controllers corresponding with the memory cells in the selected group includes operating the memory cells in the selected group according to the data stored in the corresponding data controllers to proceed a write or read operation, and the memory cells in each group corresponding to the data controllers one by one.
  • p ⁇ M bits of data are operated within an operation cycle in each of the memory banks, and k ⁇ M bits of data are operated within an operation cycle in each of the memory banks at most.
  • enabling p columns of the k columns from each group in each bank includes enabling p ⁇ M memory cells and disabling (k-p) ⁇ M memory cells in each of the i groups.
  • enabling p columns of the k columns from each group in each bank includes enabling p ⁇ M data controllers and disabling (k-p) ⁇ M data controllers.
  • enabling p columns of the k columns from each group in each bank includes outputting k enable signals to enable or disable the k columns from each group in each bank, and the enable signals are binary data with one bit.
  • p enable signals of the k enable signals are 1, (k-p) enable signals of k enable signals are 0, and a column of memory cells is on when the enable signal is 1 and off when the enable signal is 0.
  • FIG. 1 illustrates a block diagram of an exemplary system having a memory device, according to some aspects of the present disclosure.
  • FIG. 2 illustrates a schematic diagram of an exemplary memory device including peripheral circuits, according to some aspects of the present disclosure.
  • FIG. 3 illustrates a schematic diagram of an exemplary memory device including a phase-change memory (PCM) cell, according to some aspects of the present disclosure.
  • PCM phase-change memory
  • FIG. 4 illustrates a block diagram of an exemplary memory device including a memory cell array and peripheral circuits, according to some aspects of the present disclosure.
  • FIG. 5 illustrates a block diagram of an exemplary memory device including a plurality of memory banks.
  • FIG. 6 illustrates a block diagram of an exemplary memory bank including a plurality of memory cells.
  • FIG. 7 illustrates a block diagram of an exemplary memory device including a plurality of memory banks, according to some aspects of the present disclosure.
  • FIG. 8A illustrates a block diagram of an exemplary memory bank including a plurality of memory cells, according to some aspects of the present disclosure.
  • FIG. 8B illustrates a block diagram of an exemplary addressing module including an address register, an address controller, and an address decoder, according to some aspects of the present disclosure.
  • FIG. 9A illustrates a block diagram of an exemplary memory device including a plurality of memory banks, according to some aspects of the present disclosure.
  • FIG. 9B illustrates a block diagram of an exemplary enable module including an address register, an address controller, and an address decoder, according to some aspects of the present disclosure.
  • FIG. 9C illustrates a truth table of the enable module in FIG. 9B, according to some aspects of the present disclosure.
  • FIG. 9D illustrates a schematic diagram of an exemplary logic circuit, according to some aspects of the present disclosure.
  • FIG. 10A illustrates a block diagram of an exemplary memory bank including a plurality of memory cells, according to some aspects of the present disclosure.
  • FIG. 10B illustrates a block diagram of an exemplary memory bank including a plurality of memory cells, according to some aspects of the present disclosure.
  • FIG. 11A illustrates a block diagram of an exemplary memory bank including a plurality of memory cells, according to some aspects of the present disclosure.
  • FIG. 11B illustrates a block diagram of an exemplary memory bank including a plurality of memory cells, according to some aspects of the present disclosure.
  • FIG. 12A illustrates a block diagram of an exemplary memory bank including a plurality of columns of memory cells, according to some aspects of the present disclosure.
  • FIG. 12B illustrates a block diagram of an exemplary memory bank including a plurality of columns of memory cells, according to some aspects of the present disclosure.
  • FIG. 12C illustrates a truth table of the enable module of FIG. 12B, according to some aspects of the present disclosure.
  • FIG. 12D illustrates a block diagram of an exemplary memory bank including a plurality of columns of memory cells, according to some aspects of the present disclosure.
  • FIG. 12E illustrates a schematic diagram of an exemplary memory bank including a plurality of columns of memory cells, according to some aspects of the present disclosure.
  • FIG. 12F illustrates a block diagram of an exemplary memory bank including a plurality of columns of memory cells, according to some aspects of the present disclosure.
  • FIG. 13A illustrates a block diagram of an exemplary memory bank including a plurality of columns of memory cells, according to some aspects of the present disclosure.
  • FIG. 13B illustrates a block diagram of an exemplary memory bank including a plurality of columns of memory cells, according to some aspects of the present disclosure.
  • FIG. 13C illustrates a block diagram of an exemplary memory bank including a plurality of columns of memory cells, according to some aspects of the present disclosure.
  • FIG. 13D illustrates a block diagram of an exemplary memory bank including a plurality of columns of memory cells, according to some aspects of the present disclosure.
  • FIG. 14 illustrates a flowchart of an exemplary method for operating a memory device, according to some aspects of the present disclosure.
  • FIG. 15 illustrates a flowchart of an exemplary method for operating a memory device, according to some aspects of the present disclosure.
  • terminology may be understood at least in part from usage in context.
  • the term “one or more” as used herein, depending at least in part upon context may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense.
  • terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.
  • the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.
  • Phase-change memory (PCM) cells are non-volatile memory devices that store data using a phase-change material.
  • PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials, e.g., chalcogenide alloys, based on heating and quenching of the phase-change materials electrothermally.
  • the input/output (I/O) speed is decided by the number of banks in the device and the addressable data size in each bank.
  • the mainstream 3D PCM memory is configured with 16 banks to balance the I/O speed, capacity, and cost.
  • An array addressable data size of each bank is 16 bytes.
  • the present disclosure introduces a solution in which a memory device and a method for addressing thereof are provided. Neither the array addressable data size of each bank nor the number of the banks in a memory device can be increased because the area of the device will be increased greatly with the two approaches.
  • the present disclosure provides a new approach to at least double the array addressable data size with a small area increase.
  • two or more columns of memory cells share the same address.
  • the array addressable data size of each bank is at least doubled compared to the original circuit design without adding extra banks or cells.
  • the number of data controllers configured to operate the memory cells is increased proportionally to couple the memory cells sharing the same address.
  • the addressing module is redesigned to match the new structure of the memory cells.
  • the size increment of the memory device is less than 10%of the device memory while the array addressable data size of the memory device is at least doubled, so that the accessible data size could be consistent with the average particle size of data disposal of the system and the data disposal efficiency would be improved significantly.
  • FIG. 1 illustrates a block diagram of an exemplary system 100 having a memory device, according to some aspects of the present disclosure.
  • System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein.
  • system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106.
  • Host 108 can be a processor of an electronic device, such as a central processing unit (CPU) , or a system-on-chip (SoC) , such as an application processor (AP) .
  • host 108 can be configured to send or receive data to or from memory devices 104.
  • the host can be a user logic, or a user interface such that the user may give instructions to the host and transmit the instructions to the memory devices or the memory cell array.
  • Memory device 104 can be any memory device disclosed in the present disclosure. As disclosed below in detail, memory device 104, such as phase change random access memory (PCRAM) , dynamic random access memory (DRAM) , or NAND Flash memory device, can include a clock input, a command bus, a control logic, an address register, a row decoder/word line driver, a memory cell array having memory cells, a voltage generator, a page buffer/sense amplifier, a column decoder/bit line driver, an input/output circuit (I/O circuit) /read data latch, and a data register/data I/O, according to some implementations.
  • PCRAM phase change random access memory
  • DRAM dynamic random access memory
  • NAND Flash memory device can include a clock input, a command bus, a control logic, an address register, a row decoder/word line driver, a memory cell array having memory cells, a voltage generator, a page buffer/sense amplifier, a column decoder/bit line driver, an input/output circuit (
  • Memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104, according to some implementations. Memory controller 106 can manage the data stored in memory device 104 and communicate with host 108. In some implementations, memory controller 106 is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller 106 is designed for operating in a high duty-cycle environment solid-state drives (SSDs) or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays.
  • SSDs solid-state drives
  • eMMCs embedded multi-media-cards
  • Memory controller 106 can be configured to control operations of memory device 104, such as read, erase, and write operations. Memory controller 106 can also be configured to manage various functions with respect to the data stored or to be stored in memory device 104 including, but not limited to bad-cell management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller 106 is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device 104. Any other suitable functions may be performed by memory controller 106 as well, for example, formatting memory device 104. Memory controller 106 can communicate with an external device (e.g., host 108) according to a particular communication protocol.
  • ECCs error correction codes
  • memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.
  • interface protocols such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.
  • memory controller 106 can also be configured to control operations of memory device 104 to perform methods in accordance with
  • memory controller 106 can determine an initial read voltage V read_1 based on a set threshold voltage distribution of PCM cells 208 in a memory cell array. In some implementations, memory controller 106 can determine whether the read voltage V read is higher than a threshold voltage V th of one of the plurality of memory cells. In some implementations, memory controller 106 can determine that the state of the memory cell is a “set” state in response to the read voltage V read being higher than the threshold voltage V th . In some implementations, memory controller 106 can set the read voltage V read as the initial read voltage V read_1 plus a step size voltage V dac .
  • memory controller 106 can determine that the state of the memory cell is a “reset” state in response to the read voltage V read being equal to or higher than the maximum read voltage V read_max . In some implementations, memory controller 106 can repeatedly or iteratively apply the read voltage V read to one of the plurality of PCM cells 208 in response to that the read voltage V read is lower than the maximum read voltage V read_max . It is noted that one or more of these operations of memory device 104 may also be performed partially or fully by control logic in accordance with some implementations of the present disclosure.
  • FIG. 2 illustrates a schematic circuit diagram of an exemplary memory device 200 including peripheral circuits, according to some aspects of the present disclosure.
  • Memory device 200 can be an example of memory device 104 in FIG. 1.
  • Memory device 200 can include a memory cell array 201 and peripheral circuits 202 coupled to memory cell array 201.
  • Memory cell array 201 can include word lines 214, bit lines 216, and memory cells formed between word lines 214 and bit lines 216.
  • each memory cell can include a PCM element (not shown) in series with a selector (not shown) .
  • the memory cells are PCM cells.
  • memory cells can also be DRAM cells, each of which includes a paired transistor and capacitor.
  • a word line voltage (V w ) can be applied to each word line 214
  • V b bit line voltage
  • FIG. 3 illustrates a side view of a cross-section of a memory device 300 having a PCM element in series with a selector.
  • Memory device 300 includes a plurality of parallel bit lines 304 (i.e., corresponding to bit line 216 in FIG. 2) above a substrate 302 and a plurality of parallel word lines 316 (i.e., corresponding to word line 214 in FIG. 2) above bit lines 304.
  • Memory device 300 also includes a plurality of PCM cells 301 (e.g., corresponding to PCM cell 208 in FIG. 2) each disposed at an intersection of a respective pair of bit line 304 and word line 316. Adjacent PCM cells 301 are separated by an insulating structure 322.
  • Each PCM cell 301 includes a selector 308 and a PCM element 312 above selector 308.
  • Each PCM cell 301 further includes three electrodes 306, 310, and 314 vertically between a respective bit line 304, selector 308, PCM element 312, and a respective word line 316, respectively.
  • a read operation of a memory cell may reduce the lifespan of the memory cell. This phenomenon is observed particularly in a PCM cell (e.g., 301) having a PCM element (e.g., 312) in series with a selector (e.g., 308) because the PCM cell is more sensitive to read voltage and may have a higher chance to get stuck in a “reset” state when the read voltage is too high.
  • PCM element 312 can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally.
  • phase-change element can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that cells the current path) repeatedly between the two phases to store data.
  • Selector 308 may include an ovonic threshold switch (OTS) selector having an OTS material, such as zinc telluride (ZnTe) , which exhibits a field-dependent volatile resistance switching behavior (known as “OTS phenomenon” ) when an external bias voltage (Va) is higher than the threshold voltage is applied (Vth) .
  • OTS phenomenon a field-dependent volatile resistance switching behavior
  • Va external bias voltage
  • Vth threshold voltage
  • Ioff off-state current
  • the OTS selector undergoes the OTS phenomenon and switches to the on-state with low resistance; thus, the current through the OTS selector in the on-state (Ion) increases.
  • the volatile on-state is maintained as long as high voltage is supplied.
  • FIG. 4 illustrates a block diagram of an exemplary memory device 400 (e.g., corresponding to 104 in FIG. 1) including a memory cell array 401 (e.g., corresponding to 201 in FIG. 2) and peripheral circuits, according to some aspects of the present disclosure.
  • a memory cell of memory cell array 401 includes PCM cell 301, as shown in FIG. 3.
  • page buffer/sense amplifier 404 can be configured to read and program (write) data from and to memory cell array 401 according to the control signals from control logic 412.
  • page buffer/sense amplifier 404 may store one page of program data (write data) to be programmed into one page of memory cell array 201 (e.g., in FIG. 2) .
  • page buffer/sense amplifier 404 may perform program verify operations to ensure that the data has been properly programmed into PCM cells 208 coupled to selected word lines 214.
  • page buffer/sense amplifier 404 may also sense the low power signals from bit line 216 that represents a data bit stored in PCM cells 208 and amplify the small voltage swing to recognizable logic levels in a read operation.
  • page buffer/sense amplifier 404 may include a comparator (e.g., a voltage comparator) to compare a voltage signal (e.g., a read voltage) with a reference voltage signal (e.g., a pre-determined threshold voltage of a memory cell under “set” state) .
  • a comparator e.g., a voltage comparator to compare a voltage signal (e.g., a read voltage) with a reference voltage signal (e.g., a pre-determined threshold voltage of a memory cell under “set” state) .
  • Column decoder/bit line driver/data latch 406 can be configured to be controlled by control logic 412 and select one or more PCM cells 208 and bit lines 216. Column decoder/bit line driver/data latch 406 can be further configured to drive the selected bit line 216. Column decoder/bit line driver/data latch 406 can be further configured to drive bit lines 216 using bit line voltages generated from voltage generator 410. Column decoder/bit line driver/data latch 406 can be a temporary binary data storage facility to store bits. In some implementations, column decoder/bit line driver/data latch 406 may include a read data latch to store read data temporarily.
  • Data register can be coupled to page buffer/sense amplifier 404 and/or column decoder/bit line driver/data latch 406 and can be configured to direct (route) the data input from data bus 423 to the desired PCM cells 208 of memory cell array 201, as well as the data output from the desired PCM cells 208 to data bus 423.
  • Row decoder/word line driver 408 can be configured to be controlled by control logic 412 and select one or more PCM cells 208 of memory cell array 201 and a word line 214. Row decoder/word line driver 408 can be further configured to drive the selected word line 214. Row decoder/word line driver 408 can be further configured to drive word lines 214 using word line voltages generated from voltage generator 410.
  • Voltage generator 410 can be configured to be controlled by control logic 412 according to the control signals from control logic 412 and generate the word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verification voltage, etc. ) , bit line voltages, and source line voltages to be supplied to memory cell array 401.
  • voltage generator 410 is configured to generate the read voltage V read to one of the PCM cells 208 in the memory cell array 401, and in response to the new, incremental read voltage V read is lower than a maximum read voltage V read_max , repeatedly generating another read voltage V read to the memory cell in the memory cell array 401.
  • Control logic 412 can be coupled to each peripheral circuit described above and configured to control the operations of each peripheral circuit.
  • Control logic 412 is configured to receive a clock signal, a command signal, an address signal, and a data signal from a host (e.g., 108 in FIG. 1) .
  • the command signal is received via a command bus 421.
  • the data signal is received via a data bus 423.
  • control logic 412 can be implemented by microprocessors, microcontrollers (a.k.a.
  • control logic 412 is configured to direct one or more incremental read voltages into one of PCM cells 208 in memory cell array 401. That is, control logic 412 may instruct voltage generator 410 to generate one or more incremental read voltages and direct word line driver 408 to apply the one or more incremental read voltages to the one of the PCM cells 208 in memory cell array 401.
  • control logic 412 is also configured to receive a feedback signal from data register 416 to determine whether to direct another incremental read voltage into the one of PCM cells 208 in memory cell array 401.
  • the feedback signal based on whether a state of the one of the PCM cells 208 in memory cell array 401 has been determined can be processed by control logic 412.
  • Address registers 414 can be coupled to control logic 412 or included in control logic 412.
  • Address registers 414 can include state registers, command registers, and address registers for storing state information, command operation codes (OP codes) , and command addresses for controlling the operations of each peripheral circuit.
  • a PCM device usually includes a plurality of memory cell areas (e.g., memory banks, a.k.a. memory cell columns or memory cell groups) .
  • FIG. 5 illustrates a block diagram of an exemplary memory device 500 including 16 memory banks. The memory banks are numbered from Bank 0 to Bank 15, respectively. The 16 memory banks can perform concurrent data I/O operations to write or read 128 pieces of data (e.g., 16 bytes) to or from communication interface I/F 510. The writing or reading commands are sent to communication interface I/F 510 as a data queue DQ.
  • the width of the data queue could be defined as needed, such as 2, 4, 8, 16, 32, etc. In the present example, the width of the data queue is 8.
  • the width of the data queue to the data interface I/F 510 in each example is set as 8. It is understood that the width of the data queue can be any other suitable value as needed, and the example of the present disclosure are for illustrative purposed only.
  • FIG. 6 illustrates a block diagram of an exemplary memory bank 600 including a plurality of memory cells.
  • Memory bank 600 is an example of any bank from Bank 0 to Bank 15 in FIG. 5.
  • the memory cells in memory bank 600 is arranged in a format of a matrix with several rows and columns.
  • the memory cells in the matrix are numbered in a format of Memory cell N-M, where N represents the column in which the memory cell is positioned, and M represents the row in which the memory cell is positioned.
  • the coordinates of each memory cell in the format Memory cell N-M are the same as the physical coordinates of the memory cell (N, M) .
  • the matrix is formed by 4 columns and 128 rows.
  • N ranges from 0 to 3
  • M ranges from 0 to 127.
  • Memory cell 0-0 means the memory cell is positioned at the first row and the first column of the matrix
  • Memory cell 2-88 means the memory cell is positioned at the third column and the 89 th row of the matrix
  • N and M are positive integers and are multiples of 2.
  • the matrix could be configured with other formats, such as 8 ⁇ 256 or 16 ⁇ 128 according to actual needs, and the values of N and M would be designed accordingly.
  • the memory cells in the same row are driven by a corresponding data controller.
  • the number of the data controllers in memory bank 600 equals the number of the rows. For example, example the number of the data controllers is 128, and each of the data controller is numbered from 0 to 127 corresponding to the 128 rows one by one.
  • Each of the data controllers is configured to operate 4 memory cells, while only one of the 4 memory cells in the same row will be selected and operated in each operation cycle.
  • the memory cells in the same column share the same address and are operated in the same operation cycle.
  • Each memory cell is configured to store one piece of data, i.e., one bit.
  • memory bank 600 can access data with 128 bits at most.
  • Addressing module 610 is configured to select one from the 4 columns of memory cells to be operated.
  • Addressing module 610 includes an address register and an address decoder.
  • the address register is configured to store address commands.
  • the address decoder is configured to output a binary value to select a column of memory cells for operation based on an input signal, and the address commands stored in the address register.
  • Four columns are set in the present example, and addressing module 610 is configured to output binary data with two bits which could generate 4 different values corresponding to the 4 columns of memory cells. For example, [0, 0] corresponds to the first column, [0, 1] corresponds to the second column, [1, 0] corresponds to the third column, and [1, 1] corresponds to the fourth column.
  • addressing module 610 outputs one of the four values to select one from the 4 columns for a writing or reading operation, i.e., only one column of memory cells is addressed and operated in an operation cycle, and memory bank 600 can operate 128 pieces of data at most.
  • memory device 500 having 16 memory banks can perform concurrent data I/O operations to write or read 128 ⁇ 16 pieces of data, i.e., 2K bits.
  • the above-mentioned configuration is employed, i.e., the mainstream memory devices are configured to have 16 memory banks, the addressable data size of the memory device is 2K bits (128 bits ⁇ 16) .
  • the average particle size of data disposal of popular systems is 4K bits, thus, the data disposal efficiency of a system employing the 3D PCM device is halved compared to a memory device with 4K Bits accessible date. Increasing the number of banks in a PCM device could improve the size of the accessible data with a great sacrifice of the area of the memory device, which is unacceptable in practice.
  • FIG. 7 illustrates a block diagram of an exemplary memory device 700 including 16 memory banks according to a first aspect of the present disclosure.
  • FIG. 8A shows the detailed structure of a memory bank 800
  • memory bank 800 is one of the 16 memory banks illustrated in FIG. 7.
  • FIG. 8B is a detailed block diagram of an addressing module 810 in FIG.
  • Memory bank 800 further includes k sets of data controllers, each set of data controllers is configured to operate i columns of memory cells. The number of the memory cells in each column is M, the number of the data controllers in each set is M, (M is a positive integer) and each of the data controllers is configured to operate i memory cells from each of the i groups.
  • Each of the data controllers is configured to store a data with one bit, and the k ⁇ M data controllers are configured to store a data with k ⁇ M bits.
  • the number of the memory cells in each group is k ⁇ M
  • the k ⁇ M memory cells in each group correspond to the k ⁇ M data controllers one by one, meaning that the memory cells in the same group are configured to be controlled bya corresponding data controller and assigned with same address, and the k ⁇ M memory cells in the same group can be accessed at the same time in an operation cycle.
  • the array addressable data size is at least doubled compared to memory device 500 in which M memory cells can be operated in the same operation cycle at most.
  • the memory cells are arranged as a N ⁇ M matrix with N rows and M columns of memory cells, the memory cells are numbered in a different way in contrast to the memory device shown in FIG. 5 and FIG. 6.
  • the memory cells in the are numbered in a format of where N represents the column in which the memory cell is positioned, and M represents the row in which the memory cell is positioned.
  • the coordinates of each memory cell in the format is different from the physical coordinates of the memory cell (N, M) .
  • the former represents the functional position of the memory cell in a logic circuit, while the latter one represents the physical location of the memory cell in the memory cell array.
  • the k ⁇ M memory cells in different columns of the same group are numbered consecutively.
  • the memory cells in a first column of each group are numbered from 0 to (M-1)
  • the memory cells in a second column of the k columns are numbered from M to (2M-1)
  • the memory cells in a k th column of the k columns are numbered from (k-1) M to (k ⁇ M-1)
  • the k ⁇ M data controllers are numbered from 0 to (k ⁇ M-1) corresponding to the memory cells.
  • Memory cell 0-0 means the memory cell is the first memory cell in the first group, and is positioned at the first row and the first column of the matrix
  • Memory cell 1-88 means the memory cell is the 89 th memory cell in the second group, and is positioned at the second column and the 89 th row of the matrix
  • Memory cell 1-241 means the memory cell is the 242 th memory cell in the second group, and is positioned at the fourth column and the 242 th row of the matrix; and so on.
  • Memory cell 0-0 means the memory cell is the first memory cell in the first group, and is positioned at the first row and the first column of the matrix
  • Memory cell 1-88 means the memory cell is the 89 th memory cell in the second group, and is positioned at the second column and the 89 th row of the matrix
  • Memory cell 1-241 means the memory cell is the 242 th memory cell in the second group, and is positioned at the fourth column and the
  • each memory cell in different columns of the same group share a same address and are operated in a same operation cycle.
  • Each memory cell is configured to store one piece of data, i.e., one bit.
  • memory bank 800 can access data with 256 bits at most.
  • the number of data controllers in the present example is 256, which equals the number of memory cells in each group, and is twice the number of data controllers of the memory device in FIG. 6.
  • Each data controller is configured to control and operate two memory cells from each group, and only one group of memory cells is selected to be operated in an operation cycle.
  • Addressing module 810 is configured to divide the memory cells into two groups by assigning two addresses to the four columns, each group including two columns. As shown in FIG. 8B, addressing module 810 includes an address register 802, an address controller 804, and an address decoder 806. Address register 802 is configured to store address commands, address controller 804 is configured to determine address data based on an input signal and the address commands, and address decoder 806 is configured to output i address values corresponding to the i groups of memory cells and assign each address values to the columns of memory cells in a same group.
  • the values of k and x are dependent on the values of N, M, and i, and will be different in other examples when the values of N, M, and i change. It is understood that the examples in the present disclosure are for illustrative purposed only.
  • the four columns in the present example are divided into two groups, each of the two groups includes two columns of memory cells sharing a same address and are operated at the same time.
  • Addressing module 810 is configured to output binary data with one bit, which could generate two different values corresponding to the two groups of memory cells. For example, 0 corresponds to the two columns in the first group, and 1 corresponds to the two columns in the second group.
  • addressing module 810 outputs one of the two values to select one from the two groups for a writing or reading operation, i.e., two columns of memory cells are addressed and operated in an operation cycle, and memory bank 800 can operate 256 pieces of data at most.
  • the memory device 700 having 16 memory banks can perform concurrent data I/O operations to write or read 256 ⁇ 16 pieces of data, i.e., 4K bits.
  • the array addressable data size is doubled with a size increase less than 7%, which is a cost for the extra data controllers.
  • the array addressable data size of 4K bits is consistent with the average particle size of data disposal of the popular system. Thus, the data disposal efficiency of the bus in the system is at least doubled.
  • a memory device 900 includes a plurality of memory banks is provided, as shown in FIGs. 9A-11B.
  • FIG. 9A illustrates a block diagram of an exemplary memory device 900 including a plurality of memory banks according to a second aspect of the present disclosure
  • FIG. 9B illustrates a block diagram of an enable module 910 in FIG. 9A
  • FIG. 9C illustrates a truth table of the enable module 910 according to FIG. 9B
  • FIG. 9D illustrates a schematic diagram of an exemplary logic circuit according to the truth table of FIG. 9C.
  • FIGs 10A-11B illustrate the block diagram of an exemplary memory bank according to four examples of the second aspect of the present disclosure.
  • Memory bank 1000 includes a plurality of memory banks and an enable module 910.
  • Memory bank 1000 further includes k sets of data controllers, each set of data controllers is configured to operate i columns of memory cells. The number of the memory cells in each column is M, the number of the data controllers in each set is M, where M is a positive integer, and each of the data controllers is configured to operate i memory cells from each of the i groups.
  • the number of the memory cells in each group is k ⁇ M, and the memory cells in each group correspond to the data controllers one by one.
  • Each of the memory cells in a same group are configured with a corresponding data controller and assigned with a same address, and the memory cells in a same group can be accessed at the same time in an operation cycle.
  • Each of the data controllers is configured to store data with one bit, and the data controllers are configured to store data with k ⁇ M bits, and the memory bank 1000 is configured to operate data with p ⁇ M bits in a clock cycle, where p is adjustable according to an input signal by the enable module 910.
  • Memory device 900 and memory bank 1000 in the second example have a similar structure to memory device 700 and memory bank 800 in the first example, and the structure in common will not be repeated here.
  • the difference between the first and second aspects of the present disclosure is the setting of enable module 910, which is not configured in the first examples, and will be illustrated in detail in the following description.
  • the configuration of the memory device in FIG. 7 and FIG. 8A are employed to illustrate the present example easily and clearly.
  • the memory cells in different columns of a same group share a same address and are operated in a same operation cycle. Each memory cell is configured to store one piece of data, i.e., one bit.
  • memory bank 1000 can access data with 256 bits at most.
  • the number of data controllers in the present example is 256, which equals the number of memory cells in each group.
  • Each data controller is configured to control and operate two memory cells from each group, and only one group of memory cells is selected to be operated in an operation cycle.
  • Enable module 910 is configured to enable p of the k columns from each group in each bank, where p ⁇ k. As shown in FIG. 9B, the enable module 910 includes an enable register 902, an enable controller 904, and an enable decoder 906. Enable register 902 is configured to store enable commands. Enable controller 904 is configured to determine enable data based on an input signal and the enable commands. Enable decoder 906 is configured to output k enable signals corresponding to the k columns of memory cells in a group, and each of the k enable signals is configured to control i columns from each of the i groups.
  • Each of the k enable signals is a binary data with one bit, where p of k enable signals are 1, and (k-p) of k enable signals are 0, a column of memory cells is on when the enable signal is 1 and off when the enable signal is 0.
  • the accessible data size of the memory bank 1000 changes between M, 2M, whil, k ⁇ M.
  • FIG. 9C illustrates a truth table of enable module 910 according to FIG. 9B.
  • Memory device 900 has two modes: in Mode 1, the addressable data size of the memory device is 2K bits, and in Mode 2, the addressable data size of the memory device is 4K bits. Mode 1 and Mode 2 switch according to the input signal.
  • Enable controller 904 outputs a reference Mode Option representing the two modes of memory device 900.
  • Mode Option is a binary data with 1 bits, where “0” represents Mode 1, and “1” represents Mode 2.
  • FIG. 9D illustrates a schematic diagram of an exemplary logic circuit according to the truth table of FIG.
  • the data disposal efficiency of memory device 700 is increased greatly by combining the memory cells in different columns into a group sharing a same address, while other performances of memory device 700 are sacrificed. For example, an inrush current being generated during state switching at the beginning of a write or read operation will be at least doubled. When hundreds of cells are operated at the same time, a large peak current will occur and lead to a sharp voltage drop, and the total write voltage will drop largely due to the transient peak current. For cells at the far end of the array, when the real cell operation voltages are marginal compared to the cell required values, the voltage drop will result in insufficient write voltage, and inadequate write current and will lead to an unsuccessful write operation.
  • the increase of the I/O speed dominates the performance of the memory device and outperforms the sacrifices in other aspects.
  • the increase of the I/O speed will be meaningless because the I/O efficiency is limited by the average particle size of data disposal of the memory device. Adjusting the addressable data size of the memory device allowed the memory device to be coupled with different memory systems with better performance.
  • FIG. 10A illustrates a block diagram of an exemplary memory bank 1000 including a plurality of memory cells according to some aspects of the present disclosure.
  • the first group of memory cells includes the first and third columns of the memory cell array, and the memory cells in the first group are numbered from Memory cell 0-0 to Memory cell 0-255.
  • the second group of memory cells includes the second and fourth columns of the memory cell array, and the memory cells in the second group are numbered from Memory cell 1-0 to Memory cell 1-255.
  • Two sets of data controllers are configured to control the two groups of memory cells. Each data controller corresponds to two memory cells from each of the 2groups respectively.
  • the number of the data controllers is 256, the first set of the data controllers are numbered from Data Controller 0 to Data Controller 127, and the second set of the data controllers are numbered from Data Controller 128 to Data Controller 255 , Data Controller 0 is configured to control Memory Cell 0-0 and Memory Cell 1-0, Data Controller 1 is configured to control Memory Cell 0-1 and Memory Cell 1-1, Data Controller 128 is configured to control Memory Cell 0-120 and Memory Cell 1-128, and so on.
  • Enable Signal 1 controls the first column in the first group and the second column in the second group
  • Enable Signal 2 controls the third column in the first group and the fourth column in the second group.
  • FIG. 10B illustrates a block diagram of an exemplary memory bank 1000 including a plurality of memory cells according to a second example of the second aspect of the present disclosure.
  • the difference between the first and second examples is the values of the Enable Signals.
  • both the first and second groups have 256 memory cells
  • the addressable data size of memory device 900 is 4K bits.
  • FIG. 11A illustrates a block diagram of an exemplary memory bank 1100 including a plurality of memory cells according to a third example of the second aspect of the present disclosure.
  • the first group of memory cells includes the first and third columns of the memory cell array, and the memory cells in the first group are numbered from Memory cell 0-0 to Memory cell 0-255.
  • the second group of memory cells includes the second and fourth columns of the memory cell array, and the memory cells in the second group are numbered from Memory cell 1-0 to Memory cell 1-255.
  • Two sets of data controllers are configured to control the two groups of memory cells. Each data controller corresponds to two memory cells from each of the 2 groups, respectively.
  • the number of the data controllers is 256, the first set of the data controllers are numbered from Data Controller 0 to Data Controller 127, and the second set of the data controllers are numbered from Data Controller 128 to Data Controller 255, Data Controller 0 is configured to control Memory Cell 0-0 and Memory Cell 1-0, Data Controller 1 is configured to control Memory Cell 0-1 and Memory Cell 1-1, Data Controller 128 is configured to control Memory Cell 0-120 and Memory Cell 1-128, and so on.
  • Enable Signal 1 controls the first set of the data controllers
  • Enable Signal 2 controls the second set of the data controllers
  • the addressable data size of memory device is 2K bits.
  • FIG. 11B illustrates a block diagram of an exemplary memory bank 1100 including a plurality of memory cells according to a second example of the second aspect of the present disclosure.
  • the difference between the first and second examples is the values of the Enable Signals.
  • FIGs 12A-13D illustrate memory devices using other configurations with different values of N, M, i, and k.
  • a new symbol is introduced to represent columns of memory cells in FIGs 12A-13D, memory cells in FIGs 12A-13D are simplified and included in the column symbols for ease of description.
  • FIG. 12A illustrates a block diagram of an exemplary memory bank 1210 including a plurality of columns of memory cells according to a first aspect of the present disclosure.
  • No enable module is configured in the first aspect.
  • memory bank 1210 includes an array of memory cells with 8 columns, and an addressing module 810 configured to divide the memory cells into 2 groups by assigning 2 addresses to the 8 columns, each group including 4 columns.
  • Memory bank 1210 further includes 4 sets of data controllers, each set of data controllers is configured to operate 2 columns of memory cells.
  • the number of the memory cells in each column is 128, the number of the data controllers in each set is 128, and each of the data controllers is configured to operate 2 memory cells from each of the 2 groups.
  • Each of the data controllers is configured to store data with one bit
  • the 512 data controllers are configured to store data with 512 bits.
  • the number of the memory cells in each group is 512
  • the 512 memory cells in each group correspond to the 512 data controllers one by one.
  • Each of the memory cells in a same group is configured with a corresponding data controller and assigned with a same address, and the 512 memory cells in a same group can be accessed at the same time in an operation cycle.
  • the array addressable data size is four times of memory device 500 in which 128 memory cells can be operated in the same operation cycle at most.
  • FIG. 12B illustrates a block diagram of an exemplary memory bank 1220 including a plurality of columns of memory cells according to a second aspect of the present disclosure, enable module 910mis configured in the second aspect.
  • memory bank 1220 includes an array of memory cells with 8 columns, and an addressing module 810 configured to divide the memory cells into 2 groups by assigning 2 addresses to the 8 columns, each group including 4 columns.
  • Memory bank 1210 further includes 4 sets of data controllers, each set of data controllers is configured to operate 2 columns of memory cells, where the first set of data controllers are configured to control the first and second columns of memory cells, the second set of data controllers are configured to control the third and fourth columns of memory cells, the third set of data controllers are configured to control the fifth and sixth columns of memory cells, and the fourth set of data controllers are configured to control the seventh and eighth columns of memory cells.
  • the number of the memory cells in each column is 128, the number of the data controllers in each set is 128, and each of the data controllers is configured to operate 2 memory cells from each of the 2 groups.
  • Each of the data controllers is configured to store data with one bit, and the 512 data controllers are configured to store data with 512 bits.
  • the number of the memory cells in each group is 512, and the 512 memory cells in each group correspond to the 512 data controllers one by one.
  • Each of the memory cells in a same group is configured with a corresponding data controller and assigned with a same address, and the 512 memory cells in a same group can be accessed at the same time in an operation cycle at most.
  • Enable module 910 is configured to enable p of the 4 columns from each group in each bank. The structure of enable module 910 has been described in detail combined with FIG. 9Band thus, will not be repeated here.
  • Enable module 910 is configured to output 4 enable signals corresponding to the 4 columns of memory cells in a group, and each of the 4 enable signals is configured to control 2 columns from 2 each of the 2 groups.
  • Each of the 4 enable signals is a binary data with one bit, where p of 4 enable signals are 1, and (4-p) of k enable signals are 0, a column of memory cells is on when the enable signal is 1 and off when the enable signal is 0.
  • the addressable data size of the memory device configured with memory banks 1220 changes between 2K bits, 4K bits, and 8K bits.
  • FIG. 12C illustrates a truth table of the enable module 910 according to FIG. 12B.
  • Memory bank 1220 has four modes, where in Mode 1, Mode 2, and Mode 3, the addressable data sizes of the memory device configured with memory banks 1220 are 2K bits, 4K bits, and 8K bits, respectively. Mode 4 is invalid because no memory cell is enabled at this mode. Mode 1 to Mode 3 switch according to the input signal.
  • Enable controller 904 outputs a reference Mode Option representing the four modes of the memory device 900.
  • Mode Option is a binary data with 2 bits, where (1, 1) represents Mode 1, (1, 0) represents Mode 2, and (0, 1) represents Mode 3.
  • Enable Signal 1 is electrically connected to Column 1 and Column 2
  • Enable Signal 2 is electrically connected to Column 3 and Column 4
  • Enable Signal 3 is electrically connected to Column 5 and Column 6
  • Enable Signal 4 is electrically connected to Column 7 and Column 8.
  • Mode Option is (1, 1)
  • memory bank 1220 is performed in Mode 1 with an 8K bits addressable data size.
  • the Enable Signals can also be electronically connected to the four sets of data controllers respectively.
  • the Mode Option is (1, 1)
  • all four sets of data controllers are enabled.
  • the Enable Signals can also be electronically connected to the four sets of data controllers respectively. When the Mode Option is (1, 0) , the first and second sets of data controllers are enabled, the third and fourth sets of data controllers are disabled, and memory bank 1220 is performed in Mode 2 with a 4K bits addressable data size.
  • Enable Signal 1 is “1” , where Column 1 of the memory cells in the first group and Column 2 of the memory cells in the second group are enabled and in a state of on.
  • Enable Signals 2, 3, and 4 are “0” , where Columns 3, 5, and 7 of the memory cells in the first group, and Columns 4, 6, and 8 of the memory cells in the second group, are disabled in the Off state.
  • Memory bank 1220 is performed in Mode 3 with a 2K bits addressable data size.
  • the Enable Signals can also be electronically connected to the four sets of data controllers respectively.
  • the Mode Option is (0, 1) , the first set of data controllers are enabled, the second, third, and fourth sets of data controllers are disabled, memory device employing memory banks 1220 is performed in Mode 2 with a 2K bits addressable data size.
  • the addressable data size of the memory device employing memory banks 1220 is changing from 2K bits, 4K bits, and 8K bits. For each memory device, the best performance would be obtained when its addressable data size equals the average particle size of data disposal of the mainstream memory system.
  • the introduction of the enable module 910 realize an automatic adjustment of the addressable data size of the memory device to match memory systems with different data disposal particle size and obtain the best performance of the whole memory device and the system. With the increase of the values of p and N, a bigger range of the addressable data size can be gained.
  • FIG. 13A illustrates a block diagram of an exemplary memory bank 1310 including a plurality of columns of memory cells according to a first aspect of the present disclosure.
  • No enable module is configured in the first aspect.
  • memory bank 1310 includes an array of memory cells with 8 columns, and an addressing module 810 configured to divide the memory cells into 4 groups by assigning 4 addresses to the 8 columns, each group including 2 columns.
  • Memory bank 1310 further includes 2 sets of data controllers, each set of data controllers is configured to operate 4 columns of memory cells.
  • the number of the memory cells in each column is 128, the number of the data controllers in each set is 128, and each of the data controllers is configured to operate 2 memory cells from each of the 2 groups.
  • Each of the data controllers is configured to store data with one bit
  • the 256 data controllers are configured to store data with 256 bits.
  • a number of the memory cells in each group is 256
  • the 256 memory cells in each group correspond to the 256 data controllers one by one.
  • Each of the memory cells in a same group are configured with a corresponding data controller and assigned with a same address, and the 256 memory cells in a same group can be accessed at the same time in an operation cycle.
  • the array addressable data size is two times of memory device 500 in which 128 memory cells can be operated in a same operation cycle at most.
  • FIG. 13B illustrates a block diagram of an exemplary memory bank 1320 including a plurality of columns of memory cells according to a second aspect of the present disclosure, enable module 910 is configured in the second aspect.
  • memory bank 1320 includes an array of memory cells with 8 columns, and an addressing module 810 configured to divide the memory cells into 4 groups by assigning 4 addresses to the 8 columns, each group including 2 columns.
  • Memory bank 1320 further includes 2 sets of data controllers, each set of data controllers is configured to operate 4 columns of memory cells, where the first set of data controllers is configured to control the first to fourth columns of memory cells, the second set of data controllers are configured to control the fifth to eighth columns of memory cells.
  • the number of the memory cells in each column is 128, the number of the data controllers in each set is 128, and each of the data controllers is configured to operate 4 memory cells from each of the 4 groups.
  • Each of the data controllers is configured to store data with one bit
  • the 256 data controllers are configured to store data with 256 bits.
  • the number of the memory cells in each group is 256
  • the 256 memory cells in each group corresponds to the 256 data controllers one by one.
  • Each of the memory cells in a same group are configured with a corresponding data controller and assigned with a same address, and the 256 memory cells in a same group can be accessed at the same time in an operation cycle at most.
  • Enable module 910 is configured to enable p of the 2 columns from each group in each bank.
  • the structure of enable module 910 has been described in detail combined with FIG. 9B and thus, will not be repeated here.
  • Enable module 910 is configured to output 2 enable signals corresponding to the 2 columns of memory cells in a group, and each of the 2 enable signals is configured to control 4 columns from 4 different groups.
  • Each of the 2 enable signals is a binary data with one bit, where p of 2 enable signals are 1, and (2-p) of k enable signals are 0, a column of memory cells is on when the enable signal is 1 and off when the enable signal is 0.
  • the addressable data size of the memory bank 1320 changes between 2K bits and 4K bits.
  • Mode 1 the addressable data size of the memory device is 2K bits
  • Mode 2 the addressable data size of the memory device is 4K bits.
  • Mode 1 and Mode 2 switch according to the input signal.
  • Enable controller 904 outputs a reference Mode Option representing the two modes of the memory device 900.
  • Mode Option is binary data with 1 bit, where “0” represents Mode 1, and “1” represents Mode 2.
  • Mode Option When the Mode Option is “0” , Enable Signal 1 is “1, ” and Enable Signal 2 is “0” , where only one of the two columns in a same group of the memory cells is in a state of on, and the other one of the two columns is in a state of off, the memory device 900 is performed in Mode 1 with a 2K bits addressable data size.
  • Mode Option is “1”
  • both Enable Signal 1 and 2 are “1” , where all the two columns in a same group of the memory cells are in a state of on, the memory device 900 is performed in Mode 2 with a 4K bits addressable data size.
  • FIG. 13C illustrates a block diagram of an exemplary memory bank 1320 including a plurality of memory cells.
  • the first group of memory cells includes the first and fifth columns of the memory cell array
  • the second group of memory cells includes the second and sixth columns of the memory cell array
  • the third group of memory cells includes the third and seventh columns of the memory cell array
  • the fourth group of memory cells includes the fourth and eighth columns of the memory cell array.
  • Two sets of data controllers are configured to control the two groups of memory cells, and each data controller corresponds to four memory cells from each of the 4 groups, respectively.
  • the number of the data controllers is 256.
  • Enable Signal 1 controls the first column in the first group, the second column in the second group, the third column in the third group, the fourth column in the fourth group, and the first set of data controllers.
  • Enable Signal 2 controls the fifth column in the first group, the sixth column in the second group, the seventh column in the third group, the eighth column in the fourth group, and the second set of data controllers.
  • FIG. 13D illustrates a block diagram of an exemplary memory bank 1320 including a plurality of memory cells according to a second example of the second aspect of the present disclosure.
  • the difference between the first and second examples is the values of the Enable Signals.
  • all the four groups have 256 memory cells
  • the addressable data size of memory device 900 is 4K bits.
  • a memory system includes a memory device configured to store data, and a memory controller coupled to the memory device and configured to control the memory device.
  • the memory device includes a plurality of memory banks.
  • Each of the memory banks includes an array of memory cells with N columns, where N is a positive integer, an addressing module, and a plurality of data controllers.
  • the addressing module is configured to divide the memory cells into i groups by assigning i addresses to the N coulums, where The data controllers are configured to operate one of the i groups of memory cells.
  • the number of the memory cells in each column is M
  • the number of the data controllers is k ⁇ M
  • the number of the memory cells in each group is k ⁇ M.
  • the k ⁇ M memory cells in each group correspond to the k ⁇ M data controllers one by one.
  • Each of the data controllers is configured to operate i memory cells from each of the i groups.
  • the addressing module includes an address controller, an address register, and an address decoder.
  • the address register is configured to store address commands.
  • the address controller is configured to determine address data based on an input signal, and the address commands.
  • the address decoder is configured to output i address values corresponding to the i groups of memory cells based on the address data.
  • a memory system includes a memory device configured to store data, and a memory controller coupled to the memory device and configured to control the memory device.
  • the memory device includes a plurality of memory banks.
  • Each of the memory banks includes an array of memory cells with N columns, where N is a positive integer, an addressing module, a plurality of data controllers, and an enable module.
  • the addressing module is configured to divide the memory cells into i groups by assigning i addresses to the N columns, where The plurality of data controllers is configured to operate one of the i groups of memory cells.
  • the number of the memory cells in each column is M
  • the number of the columns of memory cells enabled by the enable module from each group is p
  • the number of the data controllers is k ⁇ M
  • the number of the memory cells in each group is k ⁇ M.
  • the k ⁇ M memory cells in each group correspond to the k ⁇ M data controllers one by one.
  • Each of the data controllers is configured to operate i memory cells from each of the i groups.
  • Each of the data controllers is configured to store data with one bit
  • the data controllers are configured to store data with k ⁇ M bits
  • the memory bank is configured to operate data with p ⁇ M bits in a clock cycle.
  • the addressing module includes an address controller, an address register, and an address decoder.
  • the address register is configured to store address commands.
  • the address controller is configured to determine address data based on an input signal and the address commands.
  • the address decoder is configured to output i address values corresponding to the i groups of memory cells and assign each address value to the columns of memory cells in a same group.
  • the enable module includes an enable register, an enable controller, and an enable decoder.
  • the enable register is configured to store enable commands
  • the enable controller is configured to determine enable data based on an input signal and the enable commands.
  • the enable decoder is configured to output k enable signals corresponding to the k columns of memory cells in a group, and each of the k enable signals is configured to control i columns from each of the i groups.
  • the enable module is configured to enable p of the k columns from each group by enabling p ⁇ M memory cells and disabling (k-p) ⁇ M memory cells in each group, and/or to enable p of the k columns from each group by enabling p ⁇ M data controllers and disabling (k-p) ⁇ M data controllers.
  • FIG. 14 illustrates a flowchart of an exemplary method 1400 for operating a memory device, according to some aspects of the present disclosure.
  • the memory device may be any suitable memory device disclosed herein.
  • Method 1400 may be implemented partially or fully by control logic 412 as in FIG. 4. It is understood that the operations shown in method 1400 may not be exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 14.
  • the memory device includes a plurality of memory banks.
  • Each of the memory banks includes an array of memory cells with N columns, where N is a positive integer, an addressing module, and a plurality of data controllers.
  • the addressing module is configured to divide the memory cells into i groups by assigning i addresses to the N coulums, where The data controllers are configured to operate one of the i groups of memory cells.
  • the number of the memory cells in each column is M
  • a number of the data controllers is k ⁇ M
  • the number of the memory cells in each group is k ⁇ M.
  • the k ⁇ M memory cells in each group correspond to the k ⁇ M data controllers one by one.
  • Each of the data controllers is configured to operate i memory cells from each of the i groups.
  • Method 1400 proceeds to operation 1402, as illustrated in FIG. 14, in which the memory cells are divided into i groups by assigning i addresses to the N columns by the addressing module.
  • Each of the i groups includes k columns of memory cells.
  • Dividing the memory cells into i groups by assigning i addresses to the N columns includes determining address data based on an input signal and address commands, outputting i address values corresponding to the i groups of memory cells; and assigning each address value to the columns of memory cells in a same group.
  • At least two columns of memory cells are combined into a group and share the same address.
  • Each of the memory cells in a same group could be addressed and operated by a corresponding data controller.
  • Method 1400 proceeds to operation 1404, as shown in FIG. 14, selecting one from the i groups of memory cells.
  • Operation 1404 includes selecting and outputting one from the i address values, and enabling a group of memory cells corresponding to the selected address value.
  • operation 1404 is performed by the addressing module.
  • the addressing module includes an address controller, an address register, and an address decoder.
  • the address register is configured to store address commands.
  • the address controller is configured to determine address data based on an input signal and the address commands.
  • the address decoder is configured to output i address values corresponding to the i groups of memory cells based on the address data. Only one group of memory cells can be addressed and operated in an operation cycle.
  • Each memory cell is configured to store a piece of data, i.e., one bit.
  • the accessible data size of each bank is k ⁇ M.
  • Method 1400 proceeds to operation 1406, as shown in FIG. 14, operating the selected group by data controllers corresponding with the memory cells in the selected group.
  • k ⁇ M memory cells can be accessed at most in an operation cycle.
  • the array addressable data size is at least doubled compared to the memory device in which M memory cells can be operated in a same operation cycle at most.
  • the addressing module outputs one of the i values to select one from the i groups for a writing or reading operation, i.e., k columns of memory cells are operated in an operation cycle, and each memory bank can operate k ⁇ M pieces of data at least.
  • k ⁇ M ⁇ 16 pieces of data can be written or read through concurrent data I/O operations.
  • the array addressable data size is at least doubled with a size increase of less than 10%, which is a cost for the extra data controllers. The efficiency of I/O operation is improved.
  • FIG. 15 illustrates a flowchart of an exemplary method 1500 for operating a memory device, according to some aspects of the present disclosure.
  • the memory device may be any suitable memory device disclosed herein.
  • Method 1500 may be implemented partially or fully by control logic 412 as in FIG. 4. It is understood that the operations shown in method 1500 may not be exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 15.
  • the memory device includes a plurality of memory banks.
  • Each of the memory banks includes an array of memory cells with N columns, where N is a positive integer, an addressing module, a plurality of data controllers, and an enable module.
  • the addressing module is configured to divide the memory cells into i groups by assigning i addresses to the N columns, where The plurality of data controllers is configured to operate one of the i groups of memory cells.
  • Method 1500 proceeds to operation 1502, as shown in FIG. 15, in which the memory cells are divided into i groups by assigning i addresses to the N columns by the addressing module.
  • Each of the i groups includes k columns of memory cells.
  • operation 1402 at least two columns of memory cells are combined into a group and share a same address.
  • Each of the memory cells in a same group could be operated by a corresponding data controller.
  • operation 1502 operating the memory cells in the selected group according to the data stored in the corresponding data controllers to proceed a write or read operation, and the memory cells in each group corresponding to the data controllers one by one.
  • p ⁇ M bits of data are operated within an operation cycle in each of the memory banks
  • k ⁇ M bits of data are operated within an operation cycle in each of the memory banks at most.
  • Method 1500 proceeds to operation 1504, as shown in FIG. 15, the addressing module includes an address controller, an address register, and an address decoder.
  • the address register is configured to store address commands.
  • the address controller is configured to determine address data based on an input signal and the address commands.
  • the address decoder is configured to output i address values corresponding to the i groups of memory cells based on the address data. Only one group of memory cells can be addressed and operated in an operation cycle. Each memory cell is configured to store a piece of data, i.e., one bit. Thus, the accessible data size of each bank is k ⁇ M.
  • Method 1500 proceeds to operation 1506, as shown in FIG. 15, enabling p of the k columns from each group in each bank by enable module 910, where p ⁇ k.
  • Operation 1506 could be performed by enabling p ⁇ M memory cells and disabling (k-p) ⁇ M memory cells in each of the i group or enabling p ⁇ M data controllers and disabling (k-p) ⁇ M data controllers.
  • Enabling p columns of the k columns from each group in each bank includes outputting k enable signals to enable or disable the k columns from each group in each bank, and the enable signals are binary data with one bit.
  • enable module 910 includes an enable register 902, an enable controller 904, and an enable decoder 906.
  • Enable register 902 is configured to store enable commands.
  • Enable controller 904 is configured to determine enable data based on an input signal and the enable commands.
  • Enable decoder 906 is configured to output k enable signals corresponding to the k columns of memory cells in a group, and each of the k enable signals is configured to control i columns from each of the i groups.
  • Each of the k enable signals is a binary data with one bit, where p of k enable signals are 1, and (k-p) of k enable signals are 0, a column of memory cells is on when the enable signal is 1 and off when the enable signal is 0.
  • the accessible data size of the memory bank 1000 changes between M, 2M, whil, k ⁇ M.
  • Method 1500 proceeds to operation 1508, as shown in FIG. 15, operating the enabled p of the k columns of the selected group by data controllers corresponding with the memory cells in the selected group.
  • the enable signal is determined by the memory system based on the performance of the memory system, mainly referring to the average disposal particle size of the memory system. The performance of the memory system will be the best when the addressable data size of the memory device equals the average disposal particle size of the memory system.

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Abstract

L'invention concerne un dispositif de mémoire et un procédé d'adressage associé. Le dispositif de mémoire comprend une pluralité de banques de mémoire. Chacune des banques de mémoire comprend un réseau de cellules de mémoire avec N colonnes, N étant un nombre entier positif, un module d'adressage configuré pour diviser les cellules de mémoire en i groupes en attribuant i adresses aux N colonnes, chaque groupe comprenant k colonnes, k ensembles de contrôleurs de données, chaque ensemble de contrôleurs de données étant configuré pour actionner i colonnes de cellules de mémoire, et un module d'activation couplé aux cellules de mémoire et/ou aux contrôleurs de données et configuré pour activer p colonnes des k colonnes de chaque groupe dans chaque banque.
PCT/CN2022/128149 2022-10-28 2022-10-28 Dispositif de mémoire et procédé d'adressage associé WO2024087145A1 (fr)

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CN202280005055.4A CN118266029A (zh) 2022-10-28 2022-10-28 存储器设备及其寻址方法
PCT/CN2022/128149 WO2024087145A1 (fr) 2022-10-28 2022-10-28 Dispositif de mémoire et procédé d'adressage associé

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Citations (4)

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US20090196103A1 (en) * 2008-02-04 2009-08-06 Mosaid Technologies Incorporated Non-volatile memory device having configurable page size
US20150309743A1 (en) * 2014-04-28 2015-10-29 Samsung Electronics Co., Ltd. Semiconductor memory devices and memory systems including the same
US20150364191A1 (en) * 2013-01-31 2015-12-17 Hewlett-Packard Development Company, L.P. Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency
CN109559779A (zh) * 2017-09-26 2019-04-02 三星电子株式会社 半导体存储器装置及操作半导体存储器装置的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090196103A1 (en) * 2008-02-04 2009-08-06 Mosaid Technologies Incorporated Non-volatile memory device having configurable page size
US20150364191A1 (en) * 2013-01-31 2015-12-17 Hewlett-Packard Development Company, L.P. Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency
US20150309743A1 (en) * 2014-04-28 2015-10-29 Samsung Electronics Co., Ltd. Semiconductor memory devices and memory systems including the same
CN109559779A (zh) * 2017-09-26 2019-04-02 三星电子株式会社 半导体存储器装置及操作半导体存储器装置的方法

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