WO2024085727A1 - Board for electronic parts, method for manufacturing board for electronic parts, and display device and semiconductor device including same - Google Patents

Abstract

The present invention relates to a board for electronic parts, a method for manufacturing the board for electronic parts, and a display and a semiconductor device which include the board, the board comprising: a substrate including at least one through via; and a tight-adhesion enhancement layer on the surface of the substrate and in the through via, wherein the through via has, at at least one of the upper and lower surfaces, a hole diameter that is greater than the hole diameter at a site inside the hole. Due to the inclusion of the tight-adhesion enhancement layer, the tight adhesion of a metal plating layer is improved, thus preventing the occurrence of defects and also simplifying manufacturing processes as compared to conventional boards for electronic parts.

Description

Substrate for electronic components, method of manufacturing the substrate for electronic components, and display devices and semiconductor devices including the same

The present invention relates to a substrate for electronic components including a substrate having a through-type core via, a method of manufacturing the substrate for electronic components, and a display device and semiconductor device including the same.

The substrate, which is the base material for various electronic devices such as semiconductor devices and display devices, aims to stack multiple chips in a small area using 2.5D or 3D integrated circuit technology, making semiconductor devices ultra-small. A method to simplify and systematize the process is required.

Through-core vias (through-board vias, via holes, etc.) provide electrical connections between layers in a physical electronic circuit or chip. For example, in a three-dimensional stacked integrated circuit, through-core vias can integrate electronic components vertically and horizontally. Typically, through-core vias are used in silicon substrates. Republic of Korea Patent Publication No. 10-1459597 discloses a method of manufacturing a through-type silicon via (TSV) substrate. However, because glass is economically cheaper than silicon, glass substrates have recently become more widely used in electronic devices. Glass substrates can also offer improved electromagnetic loss properties, improved dielectric properties, tailored thermal expansion coefficients and the ability to come in scalable form factors.

In Republic of Korea Patent Publication No. 10-1685578, providing an electroless palladium plating solution; Injecting an inert gas into the electroless palladium plating solution; Immersing the substrate in the electroless palladium plating solution; And an electroless palladium plating method is provided, including the step of electroless plating the substrate using the plating solution. However, even if the above plating method is applied, a problem may arise in which sufficient adhesion and reliability of the plating film cannot be secured. This affects the transmission of electrical signals and power, which can ultimately be directly related to the performance of the device. This improves plating adhesion, reduces the rate of defects in the process, increases yield, and prevents electrode lifting even under harsh conditions. Rather, there is a need to develop a substrate for electronic components with a simplified manufacturing process and a manufacturing method thereof.

In order to solve the above-mentioned problems, the purpose of the present invention is to provide a substrate for electronic components with improved plating adhesion in the process of plating a substrate having a through-type core via, and a method for manufacturing the same.

The present invention provides a substrate for electronic components and a method of manufacturing the same, in which the thickness of the plating layer can be adjusted, electrode lifting does not occur even under harsh conditions, and the manufacturing process can be simplified compared to conventional electronic component substrates. It is for the purpose of invention.

Another object of the present invention is to provide a display device and a semiconductor device including the above electronic component substrate.

However, the problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

The present invention provides a substrate comprising one or more through core vias; and an adhesion enhancement layer on the surface of the substrate and the through-type core via, wherein the through-type core via has a hole diameter of at least one of the upper and lower surfaces larger than the hole diameter of a point inside the hole. It concerns boards for components.

In the present invention, the through-type core via is a line connecting a point of the core via on the upper or lower surface in a vertical cross-section and a point with the smallest hole diameter inside the via; And the angle of a line connected in the vertical direction from a point of the core via on the upper or lower surface may be 1° to 25° or less.

In the present invention, the through core via may have a symmetric or asymmetric vertical cross section.

In the present invention, the inner wall surface of the through-type core via may have a shape including irregularities.

The present invention may be characterized in that the substrate is glass or quartz.

In the present invention, the adhesion enhancing layer may include at least one member selected from the group consisting of a UV curable resin having an acrylic group and a polyimide-based thermosetting resin, or may be a film coated with a metal, oxide, or ceramic oxide.

In the present invention, the thickness of the adhesion enhancing layer may be 250 to 6000 Å.

In the present invention, the average hole diameter of at least one of the upper and lower surfaces of each through-type via of the substrate may be 5 to 190㎛.

The present invention includes the steps of (a) forming an adhesion enhancement layer on the surface of a substrate including one or more through-type core vias; and (b) plating metal on the surface of the substrate on which the adhesion enhancement layer is formed, wherein the hole diameter of at least one of the upper and lower surfaces of the through-type core via is larger than the hole diameter of a point inside the hole. , The plating step of (b) relates to a method of manufacturing a substrate for electronic components, wherein the plating step is performed through one or more methods selected from electrolytic plating and electroless plating.

In the present invention, step (a) may further include a surface modification process.

In the present invention, the surface modification may be performed by one or more methods selected from the group consisting of saponification treatment, plasma treatment, corona treatment, and primer treatment methods.

The present invention is to adjust the etching rate of the upper and lower surfaces of the substrate before step (a), thereby manufacturing a through-core via in which the hole diameter of at least one of the upper and lower surfaces is larger than the hole diameter of a point inside the hole. It may involve more processes.

In the present invention, step (b) may be performed one or more times.

Additionally, the present invention may relate to a display device and a semiconductor device including the electronic component substrate.

According to the electronic component substrate and its manufacturing method according to the present invention, in the production of a substrate having a through-type core via, the adhesion of the metal plating layer is improved by including an adhesion enhancement layer formed through a wet coating method to prevent defects. Thus, high quality substrates for electronic components can be provided.

In addition, according to the electronic component substrate and its manufacturing method according to the present invention, the thickness of the plating layer can be adjusted through an additional process, and the manufacturing process can be simplified compared to the conventional electronic component substrate.

According to the electronic component substrate and its manufacturing method according to the present invention, the through-type core via may have a hole diameter of at least one of the upper and lower surfaces that is larger than the hole diameter of a point inside the hole, and accordingly, the through-type core via When the volume of the metal inside the via hole expands/contracts, it is possible to prevent shock from being concentrated on the metal plated inside the core via in either the upper or lower direction of the hole, thereby preventing electrode lifting under harsh conditions.

By applying the substrate for electronic components according to the present invention, display devices and semiconductor devices with excellent reliability can be provided.

1 is a cross-sectional view showing a substrate including a through-type core via according to an embodiment of the present invention. (Hourglass-shaped through-type core via hole not shown)

Figure 2 is a cross-sectional view of the substrate for electronic components of the present invention on which an adhesion enhancement layer is formed. (Hourglass-shaped through-type core via hole not shown)

Figure 3 is a cross-sectional view of a substrate for electronic components of the present invention on which an adhesion enhancement layer and a metal electrode layer are formed. (Hourglass-shaped through-type core via hole not shown)

Figure 4 is a cross-sectional view showing a substrate including a through-type core via according to an embodiment of the present invention. (Hourglass-shaped through-core via hole shown)

Figure 5 is a cross-sectional view of the substrate for electronic components of the present invention on which an adhesion enhancement layer is formed. (Hourglass-shaped through-core via hole shown)

Figure 6 is a cross-sectional view of a substrate for electronic components of the present invention on which an adhesion enhancement layer and a metal electrode layer are formed. (Hourglass-shaped through-core via hole shown)

Figure 7 is a road showing a vertical cross-section of the through-type core via of the present invention, and the hole diameter on the upper surface, the hole diameter at a point inside the hole, and the hole diameter on the lower surface are respectively indicated.

Figure 8 is a road showing a vertical cross-section of a through-type core via of the present invention, a line connecting a point of the core via on the upper or lower surface and a point with the smallest hole diameter inside the via; And the angle of a line connected in the vertical direction from a point of the core via on the upper or lower surface is indicated.

Figure 9 is a road showing a vertical cross-section of the through-type core via of the present invention, and the inner wall of the through-type core via is illustrated with irregularities.

Figure 10 is a vertical cross-sectional photograph of a through-core via of the present invention according to Example 1.

Figure 11 is a vertical cross-sectional photograph and an enlarged view of the inner wall of the through-type core via of the present invention according to Example 1.

12A and 12B are vertical cross-sectional photographs of the through-core via of the present invention according to Example 3.

13 is a vertical cross-sectional photograph of a through-core via of the present invention according to Example 4.

14 is a vertical cross-sectional photograph of a through-core via of the present invention according to Example 1.

In the drawing, what each symbol represents is as follows.

10: substrate

20: Adhesion promotion layer

30: Metal electrode layer

The present invention provides a substrate comprising one or more through core vias; and an adhesion enhancement layer on the surface of the substrate and the through-type core via, wherein the through-type core via has a hole diameter of at least one of an upper surface and a lower surface that is larger than the hole diameter of a point inside the hole. It relates to a substrate for electronic components, a method of manufacturing the substrate for electronic components, and a display device and semiconductor device including the same.

More specifically, (a) forming an adhesion enhancement layer on the surface of a substrate including one or more through-core vias; and (b) plating metal on the surface of the substrate on which the adhesion enhancement layer is formed, wherein the hole diameter of at least one of the upper and lower surfaces of the through-type core via is larger than the hole diameter of a point inside the hole. , The plating step of (b) is performed through one or more methods selected from electrolytic plating and electroless plating, thereby relating to a method of manufacturing a substrate for electronic components in which plating adhesion is improved. According to the present invention, the adhesion enhancement layer may be formed through a wet coating method, and thus, a more uniform thin film can be formed inside the core via compared to a general sputtering method, and the incidence of defects when forming metal wiring can be reduced. It has an advantage insofar as it can reduce production costs and maintenance costs.

According to the electronic component substrate and its manufacturing method according to the present invention, the through-type core via may have a hole diameter of at least one of the upper and lower surfaces that is larger than the hole diameter of a point inside the hole, and accordingly, the through-type core via When the volume of the metal inside the via hole expands/contracts, it is possible to prevent shock from being concentrated on the metal plated inside the core via in either the upper or lower direction of the hole, thereby preventing electrode lifting under harsh conditions.

Through one or more embodiments of the present invention, a display device and a semiconductor device including the electronic component substrate are described, but the present invention is not limited thereto, and a number of devices to which the electronic component substrate and its manufacturing method can be applied are provided. It can be used without restrictions in any field.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings. However, the following drawings attached to this specification illustrate preferred embodiments of the present invention, and serve to further understand the technical idea of the present invention along with the contents of the above-described invention, so the present invention is described in such drawings. It should not be interpreted as limited to the specifics.

As used herein, comprises and/or comprising and/or having means one or more other components, steps, operations and/or elements other than the mentioned components, steps, operations and/or elements. /or is used in the sense that it does not exclude the presence or addition of elements. Like reference numerals refer to like elements throughout the specification.

Spatially relative terms such as “bottom”, “bottom”, “bottom”, “top”, “top”, “top”, etc. refer to one element or component and other elements or components as shown in the drawing. It can be used to easily describe correlations with others. Spatially relative terms should be understood as terms that include different directions of the element during use or operation in addition to the direction shown in the drawings. For example, when an element shown in a drawing is turned over, an element described as “below” or “below” another element may be placed “above” the other element. Accordingly, the illustrative term “down” may include both downward and upward directions. Elements can also be oriented in other directions, so spatially relative terms can be interpreted according to orientation.

Additionally, what is described as “surface” may not only include the top and bottom of an object spatially, but may also refer to all of the externally exposed parts. For example, 'the surface of a substrate including a through-type core via' can be interpreted as a term that includes both the top and bottom surfaces of the substrate as well as the inner (or inner) wall of the hole of the core via.

As used herein, “substantially” can be interpreted to include not only physically completely identical or identical, but also within the error range of measurement or manufacturing process, for example, error range of 0.1%. It can be interpreted as follows.

<Substrate for electronic components>

The present invention provides a substrate comprising one or more through core vias; and an adhesion enhancement layer on the surface of the substrate and the through-type core via, and is for a substrate for electronic components. In particular, the substrate may include one selected from glass or quartz, and the substrate for electronic components manufactured according to an embodiment of the present invention may have a plating adhesion of 4B or more as a result of an adhesion test according to the international standard ASTM D3359. It is not limited to this. The substrate for electronic components of the present invention may further include a metal plating layer on the adhesion enhancement layer.

The through-type core via according to the present invention may have a hole diameter of at least one of the upper and lower surfaces that is larger than the hole diameter at a point inside the hole, and the volume of the metal inside the through-type core via hole expands/contracts accordingly. In this case, it is possible to prevent shock from being concentrated on the metal plated inside the core via in either the upper or lower direction of the hole, thereby preventing electrode lifting under harsh conditions.

Preferably, the substrate for electronic components of the present invention may be manufactured by the method described in <Method for manufacturing a substrate for electronic components>, which will be described later.

Board

As a substrate for electronic components of the present invention, materials with weak conductivity such as glass, quartz, and polyimide can be used. In particular, it is preferable to use glass or quartz as a substrate because of its excellent chemical durability and optical properties, and from the same point of view, It is more desirable to choose glass material rather than quartz.

1 is a cross-sectional view showing a substrate including a through-type core via according to an embodiment of the present invention. Figure 2 is a cross-sectional view of the substrate for electronic components of the present invention on which an adhesion enhancement layer is formed. Figure 3 is a cross-sectional view of a substrate for electronic components of the present invention on which an adhesion enhancement layer and a metal electrode layer are formed. (In FIGS. 1 to 3, the hourglass-shaped through-core via hole described later is not shown)

According to one embodiment of the present invention, it is more preferable that the substrate is a glass substrate 10 including one or more through-type core vias as shown in FIG. 1. The glass substrate has excellent versatility and durability, and the composition for manufacturing the glass substrate is not particularly limited and can be selected depending on the desired use. For example, the glass substrate may be formed from a glass suitable for electronic device applications, including WILLOW ^® glass manufactured by Corning, Eagle XG ^TM glass, NSG soda lime glass, NEG Glass, or code 2318 glass. However, it is not limited to this and other types of ion-exchangeable glass or fused silica can be used to form the glass substrate.

Additionally, a substrate having a through-type core via can be manufactured by applying a process commonly used in the art to drill a through-type core via into the substrate. The shape and size of the substrate, such as square or circular, are not limited, but a square shape may be advantageous in terms of processing. In addition, the average thickness of the substrate can be selectively used without limitation as needed, but in the case of UTG (ultra thin glass), it may be 30㎛ or more and 100㎛ or less, and for communication, display, and semiconductor substrates, the thickness can be up to 1100㎛. ㎛, preferably 250 to 700 ㎛. When the thickness of the substrate satisfies the above range, it is preferable in terms of durability.

The through-type core via may be of a through-type type with holes formed on both the top and bottom surfaces and have side walls, and may have a horizontal cross-section of a circle, ellipse, or polygon, but is not limited thereto. Additionally, the shape of the horizontal cross section of the upper and/or lower surfaces may be the same as or different from the horizontal cross section inside the hole. Preferably, the through-type core via may have circular upper and lower surfaces and an internal horizontal cross-section of the hole. Additionally, the through-type core via of the present invention may be designed to maintain electrical properties by allowing the hole of the core via to be filled with an electrically conductive material such as copper or another metal without inserting a component. The through core via may be formed in the substrate by any suitable method, for example by drilling into the substrate using a pulsed laser. The average hole diameter of at least one of the upper and lower surfaces of each of the through-type core vias may be 5 to 190 ㎛, and is most preferably 20 to 50 ㎛. When the above range is satisfied, the plating layer can be formed uniformly and electrical interference can be prevented. In the present invention, the 'hole diameter' of a through-type core via means the diameter if the via in the horizontal cross-section is circular. If the via is not circular, it may be the length of the longest line among the lines connecting any two points in the horizontal cross-section of the via. . In the present invention, the 'cross-sectional area' of a through-type core via may mean the area of the horizontal cross-section of the via.

Figure 4 is a cross-sectional view showing a substrate including a through-type core via according to an embodiment of the present invention. Figure 5 is a cross-sectional view of the substrate for electronic components of the present invention on which an adhesion enhancement layer is formed. Figure 6 is a cross-sectional view of a substrate for electronic components of the present invention on which an adhesion enhancement layer and a metal electrode layer are formed. (Showing an hourglass-shaped through-core via hole) Figure 7 is a road showing a vertical cross-section of a through-type core via of the present invention, showing the hole diameter on the upper surface, the hole diameter at a point inside the hole, and the hole diameter on the lower surface, respectively. It is done. The core via of the present invention may be composed of an upper surface, a lower surface, and the inside of a hole (same meaning as 'inside') connecting the upper surface and the lower surface. In one example of the present invention, referring to FIGS. 4 to 7, the through-type core via has a hole diameter of the core via at one point inside the hole larger than the hole diameter of the core via on the upper surface and the hole diameter of the core via on the lower surface. It can be small. Alternatively, in one example of the present invention, the cross-sectional area of the core vias on the upper and lower surfaces may be larger than the cross-sectional area of one point inside the hole. More specifically, the cross-sectional area or diameter of the hole of the core via may become smaller from the top and bottom surfaces toward the inside of the hole. As a point with a small cross-sectional area or hole diameter is located inside the hole, when physical shock is applied from the outside to the substrate of the present invention or the volume of the metal inside the through-core via hole expands/contracts depending on temperature/humidity, By preventing impact from being concentrated on the metal plated inside the core via in either the upper or lower direction of the hole, it is possible to prevent the metal from being separated from the core via. Specifically, when external physical shock is applied to the substrate or the volume of the metal inside the hole expands/contracts depending on temperature/humidity, in the case of a conventional structure in which force is concentrated in either the upper or lower surface, electrode separation may occur. On the other hand, in the substrate of the present invention, the impact is distributed in both directions to the upper and lower surfaces centered on a point with a small cross-sectional area or hole diameter inside the hole, thereby preventing metal from being separated from the core via.

In one embodiment of the present invention, the through-type core via of the present invention may have a symmetrical or asymmetrical vertical cross-section. In one embodiment of the present invention, the through core via of the present invention may have a vertical cross-section shaped like an hourglass, and the hourglass may be symmetrical or asymmetrical.

In the case where the core via of the present invention is symmetrical, in the present invention, when the upper surface of the line connecting the upper and lower surfaces of the core via is set to 0% and the lower surface is set to 100%, the point where the cross-sectional area or hole diameter of the hole in the core via is smallest is 40 It may be located at the 60% point, but is not limited thereto. In the case where the core via of the present invention is asymmetric, in the present invention, when the upper surface of the line connecting the upper and lower surfaces of the core via is set to 0% and the lower surface is set to 100%, the point where the cross-sectional area or hole diameter of the hole of the core via is smallest is 15 It may be located at 35% to 65% or 65% to 75%, but is not limited thereto.

More specifically, Figure 8 is a road showing a vertical cross-section of a through-type core via of the present invention, a line connecting a point of the core via on the upper or lower surface and a point with the smallest hole diameter inside the via; And the angle of a line connected in the vertical direction from a point of the core via on the upper or lower surface is indicated. Referring to FIG. 8, the through-type core via of the present invention has a line connecting a point of the core via on the upper or lower surface in a vertical cross-section and a point with the smallest hole diameter inside the via; And it may include a form in which the angle of a line connected in the vertical direction from a point of the core via on the upper or lower surface is 1° to 25°, preferably 3° to 20°, and most preferably 5° to 18°. . In this case, it is most advantageous for achieving the purpose of the present invention.

In the present invention, as described above, a symmetrical/asymmetrical through-type core via in which a point with a small cross-sectional area or hole diameter is located inside the hole is formed by adjusting the etching rate or rate of the upper and lower surfaces when manufacturing the core via. can do. For example, when forming a through-core via by etching the upper and lower surfaces of the substrate, when etching is performed simultaneously on both the upper and lower surfaces, the intensity of the etching exposure becomes weaker as it moves from the upper and lower surfaces toward the inside of the substrate, resulting in symmetrical sand It is possible to form a clock-shaped core via. At this time, the etching may use a known etchant for etching the substrate. For example, an etchant composition containing hydrofluoric acid may be used, but is not particularly limited. As an example, the etchant composition may include hydrofluoric acid, nitric acid, sulfuric acid, a surfactant as an additive, an anti-foaming property control additive, and/or distilled water.

Additionally, in another example of the present invention, when the etching time for one of the upper and lower surfaces is lengthened, it is possible to form an asymmetric hourglass-shaped core via.

The etching time varies depending on the thickness of the substrate, but can be performed for about 3 to 4 hours based on a 400Å to 500Å thick substrate, but is not limited to this.

Regarding the formation of a symmetrical or non-symmetrical hourglass-shaped core via depending on the etching time, according to an example of the present invention, a symmetrical hourglass-shaped core via is formed during etching so that the upper and lower surfaces are exposed simultaneously. This is possible.

Additionally, in order to form an asymmetric hourglass-shaped core via, the exposure of the etchant composition to the upper and lower surfaces of the substrate can be adjusted. For example, the asymmetric ratio of the hourglass shape can be adjusted by exposing the substrate to the etchant composition in a horizontal direction on the surface where the distance to the section with the smallest hole diameter between the upper and lower surfaces is set to be shorter. In other words, a method of floating the substrate in the etchant composition and adjusting the etchant composition and the substrate to be horizontally opposed is applicable.

In addition, the method is not particularly limited, but in order to differently adjust the degree to which the etchant composition is exposed to the upper and lower surfaces of the substrate, an acid-resistant jig (Teflon, etc.) is applied to one of the upper and lower surfaces, Exposure to the etchant composition can be physically blocked.

In the core via of the present invention, the hole diameter of the core via on the upper surface and the hole diameter of the core via on the lower surface may be the same or different. Additionally, when the substrate of the present invention includes a plurality of core vias, the shape of each core via or the diameter of the hole may be the same or different. As an example, it may be designed in consideration of the contact area of elements or wiring located on the upper and/or lower side of the substrate of the present invention, the RDL or PAD, and the connection terminal, etc. For example, when a large electrical contact area on the top surface is required or when the electrical contact area is small, the shape of the core via can be adjusted accordingly.

Figure 9 is a road showing a vertical cross-section of the through-type core via of the present invention, and the inner wall of the through-type core via is illustrated with irregularities. Specifically, the inner wall of the through-type core via of the present invention may have a large surface area and, for example, may have a shape including repetitive or non-repetitive irregularities. Accordingly, by applying a three-dimensional anchoring effect to the metal plated inside the through core via of the present invention, adhesion can be improved. That is, in the present invention, the roughness inside the through-type core via is increased to increase the specific surface area, and by forming irregularities inside the through-type core via, the interface of the increased (generated) area due to the irregularities increases the metal electrode. When formed, it has the effect of increasing the contact area. The anchoring effect using the waviness of the surface irregularities and the lay also help improve the adhesion desired in the present invention.

More preferably, the inner wall of the through-type core via of the present invention may have a specific surface area increased by 10 to 300%, preferably 50 to 300%, compared to the inner wall of a conventional core via that does not contain irregularities. , thereby providing an interface that can adhere to the metal formed inside the core. If the specific surface area is excessively increased beyond the above range, the surface of the substrate may become porous and the mechanical strength of the substrate may decrease.

In order to form the above-mentioned irregularities on the inner wall of the through-type core via of the present invention, a known method can be used. For example, by adjusting the etching rate using an ultrasonic cleaning method, the inside of the through-type core via is formed. The illuminance of the wall surface can be adjusted.

More specifically, in order to form the above-mentioned irregularities on the inner wall of the through-type core via of the present invention, ultrasonic vibration is applied to the sample at a certain time interval using an ultrasonic cleaning method, and the shape control and surface roughness to be etched as process variables are adjusted. It can be increased. Ultrasonic cleaning is a form of repeated on/off operation with a time difference, and the concentration can be adjusted by controlling the circulation of the etchant composition inside and the time at which the composition is in equilibrium. Etching according to this concentration occurs immediately, and when the concentration is lowered, the concentration of the etchant composition can be adjusted to occur at a certain rate by assisting the circulation of the solution outside the etched area where the high-concentration etchant composition exists. The creation of irregularities as described above on the inner wall of the through-type core via can be adjusted by using the time at which etched sludge, etc., is removed as a process factor to appropriately adjust the time when ultrasonic waves are turned on and off.

Specifically, the higher the aspect ratio of the average thickness of the substrate to the average hole diameter of the core via, the more the integrated circuit performance of the semiconductor device can be improved and the packaging size and stress effects can be reduced. However, the higher the aspect ratio, the more difficult it is to metallize the sidewall of the core via, and if the hole diameter of the core via is too small, there is a disadvantage that voids may occur during the process of filling the core via with a conductive material. Therefore, in one embodiment according to the present invention, the aspect ratio is most preferably 1:10 to 1:30 in terms of ease of processing and performance of the semiconductor device.

It is preferable to use a number of core vias of 1 to 5,000 per 1 cm ² of the substrate in terms of application to a substrate for electronic components that has sufficient conductivity while maintaining low resistance, but is not limited to this and may be used without limitation as needed. A substrate on which vias are formed can be used. For example, when the density of the core vias is low, there may be more than 1 but less than 400 per 1 cm ² of the substrate.

Adhesion promotion layer

An example of a substrate on which an adhesion enhancing layer according to the present invention is formed is shown in Figure 2. As shown in FIG. 2, the adhesion enhancing layer 20 may be formed in direct contact with the surface of the substrate 10, and may be intended to improve the adhesion of the metal plating layer formed through a subsequent plating process. there is. The adhesion enhancing layer may be a polymer material containing at least one selected from the group consisting of UV curable resin having an acrylic group and polyimide thermosetting resin, which may be polymerized by appropriate light or heat. The adhesion enhancing layer of the present invention includes a film coated with metal, oxide, and/or ceramic oxide. In this case, the material included in the adhesion enhancing layer is not limited to specific materials such as organic materials, inorganic materials, metals, and oxides, but may be composed of organic materials and/or inorganic materials continuously laminated. In addition, the adhesion enhancing layer of the present invention may be a thin film deposited by a method such as sputtering or CVD, and the thin film may include ITO, IZO, AZO, IGZO, CuO and/or TiO ₂ You can.

As the UV curable resin, any material known in the art to be used in negative photoresist can be used without limitation. However, UV curable resin having an acrylic group has excellent adhesion to the substrate surface and is suitable for use with metals included in the metal plating layer. Since it is possible to secure interfacial adhesion with the adhesion promotion layer, it is more desirable in terms of excellent adhesion between the upper and lower coating films based on the adhesion promotion layer.

The polyimide-based thermosetting resin is more preferable than the UV curing resin for forming an adhesion enhancement layer of a substrate for electronic components because the cured product has good heat resistance, solvent resistance, chemical resistance, mechanical properties, and electrical insulation. The weight average molecular weight (GPC measurement) of the polyimide is not greatly limited, but may be, for example, 1,000 g/mol or more and 200,000 g/mol or less, or 10,000 g/mol or more and 200,000 g/mol or less.

In addition, the adhesion enhancement layer may be manufactured by applying a composition further containing a photopolymerizable compound, a photopolymerization initiator, a heat curing agent, a solvent and/or an additive, etc. to the polymer material and then curing the polymer material.

The photopolymerizable compound is a compound that can be polymerized by the action of the following photopolymerization initiator, and may be a monofunctional monomer or a difunctional or higher monomer, preferably a bifunctional or higher polyfunctional monomer.

Specific examples of the monofunctional monomer include nonylphenylcarbitol acrylate, 2-hydroxy-3-phenoxypropyl acrylate, 2-ethylhexylcarbitol acrylate, 2-hydroxyethyl acrylate, or N-vinylpy. Lolidon, etc., but is not limited thereto.

Specific examples of the above bifunctional or higher monomers include 1,6-hexanediol di(meth)acrylate, ethylene glycol di(meth)acrylate, neopentyl glycol di(meth)acrylate, and triethylene glycol di. (meth)acrylate, bis(acryloyloxyethyl) ether of bisphenol A, or 3-methylpentanediol di(meth)acrylate, etc., and trimethylolpropane tri(meth)acrylate, trifunctional or higher monomer. Toxylated trimethylolpropane tri(meth)acrylate, propoxylated trimethylolpropane tri(meth)acrylate, pentaerythritol tri(meth)acrylate, pentaerythritol tetra(meth)acrylate, dipentaerythritol penta( Meta)acrylate, ethoxylated dipentaerythritol hexa(meth)acrylate, propoxylated dipentaerythritol hexa(meth)acrylate, or dipentaerythritol hexa(meth)acrylate, etc., but are limited to these. no.

The photopolymerizable compound may be included in an amount of more than 30% by weight and less than 95% by weight based on 100% by weight of the total composition. Preferably, when included in the range of more than 40% by weight and less than 90% by weight, light conversion efficiency, degree of curing, and dispersion stability are improved, providing desirable advantages in terms of strength and smoothness of the pixel portion. If the photopolymerizable compound is included less than the above range, it becomes difficult to secure fluidity for ink jetting, and if the photopolymerizable compound is included more than the above range, it may cause problems with poor adhesion, so it is preferable that the photopolymerizable compound be contained within the above range.

The photopolymerization initiator can be used without particular restrictions as long as it can polymerize the photopolymerizable compound. For example, the photopolymerization initiator is an acetophenone-based compound, a benzophenone-based compound, a triazine-based compound, a biimidazole-based compound, an oxime-based compound, It is preferable to use at least one compound selected from the group consisting of oxanthone-based compounds and phosphine oxide compounds.

For example, using an oxime-based compound or a phosphine oxide compound can secure better physical properties in terms of cured density and surface roughness of the cured film. Specific examples of the oxime compounds include o-ethoxycarbonyl-α-oxyimino-1-phenylpropan-1-one, and representative commercial products include Irgacure OXE 01 and OXE 02 from BASF.

Specific examples of the phosphine oxide compound include trimethylbenzoylphenylphosphine oxide, Darocur TPO from BASF, Lucirin TPO, and diphenyl (2,4,6-trimethylbenzoyl)phosphine oxide from TCI.

The photopolymerization initiator may be included in an amount of 0.1 to 10% by weight, preferably 0.5 to 8% by weight, based on 100% by weight of the total composition. When the photopolymerization initiator is contained within the above range, sufficient curing can be achieved by light or heat to form an adhesion enhancing layer with excellent physical properties such as hardness, and the composition can be highly sensitive and the exposure time can be shortened, thereby improving productivity. It is desirable because it exists.

The photopolymerization initiator may further include a photopolymerization initiation auxiliary agent in order to improve the sensitivity of the composition according to the present invention. When the photopolymerization initiation aid is included, sensitivity is further increased and productivity is improved. The photopolymerization initiation aid may be, for example, one or more compounds selected from the group consisting of amine compounds, carboxylic acid compounds, and organic sulfur compounds having a thiol group, but is not limited thereto. The photopolymerization initiation aid can be added appropriately as long as it does not impair the effect of the present invention.

The thermosetting agent is activated by heat, for example, phenol novolak resin, trifunctional phenol novolak resin, cresol novolak resin, bisphenol A novolak resin, xylene novolak resin, triphenyl novolak resin, B Phenyl-based novolak resin, dicyclopentadiene novolak resin, naphthalene-based novolak resin, phenol p-xylene resin, phenol 4,4'-dimethylbiphenylene resin, phenol dicyclopentadiene novolak resin, dicyclo Phenolic resin curing agents such as pentadiene-phenol novolac (DCPD-phenol), xylok (modified p-xylene), triazine-based compounds, dihydroxy naphthalene, and dihydroxy benzene; Aliphatic acid anhydrides such as dodecenyl succinic anhydride (DDSA), poly azelaic poly anhydride, hexahydrophthalic anhydride (HHPA), and methyl tetrahydrophthalic Alicyclic acid anhydrides such as anhydride (methyl tetrahydrophthalic anhydride, MeTHPA), methylnadic anhydride (MNA), trimellitic anhydride (TMA), and pyromellitic dianhydride (pyromellitic acid anhydride). Acid anhydride curing agents such as aromatic acid anhydrides such as acid dianhydride (PMDA) and benzophenonetetracarboxylic dianhydride (BTDA); 4,4'-Dimethylaniline (diamino diphenyl methane, DAM or DDM), diamino diphenyl sulfone (DDS), and dicyandiamide (DICY) Amine curing agents, etc., but are not limited thereto, and the content of the thermosetting agent may be appropriately selected according to the amount generally used in this technical field, and is not particularly limited.

The solvent is not particularly limited as long as the curable resin has an appropriate viscosity, can easily dissolve the remaining components, and does not damage the substrate, and various organic solvents used in the field of manufacturing substrates for electronic components can be used.

Specific examples of the solvent include ethylene glycol monoalkyl ethers such as ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, ethylene glycol monopropyl ether, and thylene glycol monobutyl ether; Diethylene glycol dialkyl ethers such as diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol dipropyl ether, and ethylene glycol dibutyl ether; Ethylene glycol alkyl ether acetates such as methyl cellosolve acetate and ethyl cellosolve acetate; Propylene glycol dialkyl ethers such as propylene glycol monomethyl ether; alkylene glycol alkyl ether acetates such as propylene glycol monomethyl ether acetate, propylene glycol monoethyl ether acetate, propylene glycol monopropyl ether acetate, methoxybutyl acetate, and methoxypentyl acetate; Aromatic hydrocarbons such as benzene, toluene, xylene, and mesitylene; Ketones such as methyl ethyl ketone, acetone, methyl amyl ketone, methyl isobutyl ketone, and cyclohexanone; alcohols such as ethanol, propanol, butanol, hexanol, cyclohexanol, ethylene glycol, and glycerin; esters such as ethyl 3-ethoxypropionate and methyl 3-methoxypropionate; Cyclic esters such as γ-butyrolactone; etc. can be mentioned.

Among the above solvents, organic solvents having a boiling point of 100 to 200° C. are preferred in terms of applicability and drying properties, and more preferably alkylene glycol alkyl ether acetates, ketones, ethyl 3-ethoxypropionate or 3- esters such as methyl methoxypropionate, and more preferably propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate, propylene glycol monoethyl ether acetate, cyclohexanone, 3-ethoxyethyl propionate, 3- and methyl methoxypropionate.

Additionally, the solvent may include an aprotic solvent, for example, acetone, acetonitrile, m-cresol, tetrahydrofuran (THF), N-methyl-2- Pyrrolidone (NMP), N,N-dimethylformamide (DMF), N,N-dimethylacetamide (DMAc), dimethyl sulfoxide (DMSO) and diethyl acetate It is preferable to include at least one polar aprotic solvent selected from among.

The above solvents can be used alone or in a mixture of two or more types, and when contained in an amount of 30 to 70% by weight based on 100% by weight of the composition, they can be used in roll coaters, spin coaters, slit and spin coaters, dip coaters, and slit coaters (slot die) It is preferable because it provides the effect of improving applicability when applied with a coating device such as an inkjet (sometimes referred to as a coater).

In addition to this, in order to improve the flatness or adhesion of the adhesion enhancing layer, additives commonly used in the art may be further included without departing from the purpose of the present invention. Specifically, it may further include a leveling agent, anti-foaming agent, surfactant, adhesion enhancer, ultraviolet absorber, anti-agglomeration agent, and/or dispersant, and the additive may be appropriately adjusted by those skilled in the art to the extent that it does not impair the effect of the present invention. It can be used by adding.

The surfactant may further include a fluorine-based surfactant, and when the surfactant is included, there is an advantage that the flatness of the coating film can be improved. In addition, when using a mixture of two or more types of surfactants with different particle sizes and structures, there is an advantage of uniform spraying during inkjet spraying, and it can provide the effect of protecting the substrate from oxygen or moisture from penetrating during the process. It is more advantageous in that respect. For example, the fluorine-based surfactants include BM-1000, BM-1100 (BM Chemie), Prolide FC-135/FC-170C/FC-430 (Sumitomo 3M Co., Ltd.), SH-28PA/-190/-8400/SZ- 6032 (Dore Silicon Co., Ltd.), Megaface F-554/ Megaface F-559/ Megaface F-563 (DIC Co., Ltd.), etc. can be used, but are not limited thereto.

The dispersant is a type of surfactant that is used to ensure optimal dispersibility in the process by uniformly dispersing solids in the solvent to ensure high density flowability, and can be included without limitation as long as it is commonly used in the art. .

The adhesion enhancer may be added to increase adhesion to the substrate and may include a silane coupling agent having a reactive substituent selected from the group consisting of carboxyl group, methacryloyl group, isocyanate group, epoxy group, and combinations thereof. It is not limited. Specifically, vinyltrimethoxysilane, vinyltriethoxysilane, vinyltris(2-methoxyethoxy)silane, N-(2-aminoethyl)-3-aminopropylmethyldimethoxysilane, N-(2 -Aminoethyl)-3-aminopropyltrimethoxysilane, 3-aminopropyltriethoxysilane, 3-glycidoxypropyltrimethoxysilane, 3-glycidoxypropylmethyldimethoxysilane, 2-(3, 4-Epoxycyclohexyl) ethyltrimethoxysilane, 3-chloropropylmethyldimethoxysilane, 3-chloropropyltrimethoxysilane, 3-methacryloyloxypropyltrimethoxysilane, 3-mercaptopropyltrimeth Toxysilane, etc. may be used, but are not limited thereto.

The additive may be used in an amount of 0.01 to 10% by weight, specifically 0.02 to 8% by weight, and more specifically 0.03 to 5% by weight based on 100% by weight of the total composition, but is not limited thereto. When the additive is included within the above range, it is preferable because the coating properties, flatness, adhesion, etc. of the composition can be improved.

In one embodiment, the thickness of the adhesion enhancing layer 20 may be 250 to 6000 Å, preferably 500 to 3000 Å, and more preferably 1000 to 1500 Å. It is preferable that the thickness of the adhesion enhancement layer satisfies the above range in terms of improving the adhesion of the plating layer provided on the adhesion enhancement layer.

By applying the adhesion enhancing layer between the metal plating layer and the glass substrate, the adhesion of the metal plating layer to the glass substrate can be improved. This has the effect of ensuring the reliability of the electrode by improving the adhesion between the electrode and the glass substrate when forming the electrode with a substrate containing through-type vias, preventing distortion and substrate deformation due to thermal shock and/or thermal deformation during the process, and It is effective in improving the durability of the substrate by increasing physical adhesion and preventing corrosion due to moisture and/or gas. It is preferable that the plating adhesion of the electronic component substrate of the present invention is 4B or more. If the plating adhesion of the metal plating layer is less than the above range, problems may occur in the durability of the electronic component substrate and the semiconductor package including the same. The plating adhesion may be 4B or more, and 5B is more preferable in terms of durability, and may be evaluated according to the standards of ASTM D3359, an international standard method. According to the evaluation criteria of the international standard, the adhesion of the metal plating layer according to an embodiment of the present invention may be such that no peeling phenomenon is observed during evaluation, or peeling may be observed in an area of less than 5% of the target area.

metal plating layer

Referring to Figure 3, the substrate for electronic components according to an embodiment of the present invention may have a metal plating layer formed on the surface of the adhesion enhancement layer.

The plating layer is not particularly limited as long as it contains a conductive metal, but it is preferable to be manufactured from metal ink in terms of low cost, productivity, and ease of process such as maintenance. Specifically, when forming the metal plating layer including the metal ink, the production time can be shortened compared to the case of including a general metal to form a sufficient plating layer thickness, low resistance can be realized, and general plating layer such as core vias can be formed. It is suitable for forming metal layers even in complex structures where photolithography is difficult to apply. The metal ink is made by dispersing metal nanoparticles of consistent size and shape in an alcohol and/or hydrocarbon-based solvent, and the metal nanoparticles are preferably contained in an amount of 3 to 50 wt% based on the total weight of the dispersion. The metal nanoparticles may be conductive silver, gold, nickel, copper, or a combination thereof, but copper is more preferable because it is advantageous in economic terms and has superior electrical conductivity compared to other metals. The metal nanoparticles may have a particle size of 100 nm or less, and a particle size of 30 to 60 nm is preferred in terms of ease of process. The solvent may include common solvents used in the art, and more preferably alcohol-based compounds such as methanol, ethanol, isopropanol, butanol, and propylene glycol methoxy alcohol; and hydrocarbon-based compounds such as hexane, heptane, benzene, toluene, xylene, ethylene-based, and acetate-based; These may be used alone or in combination of two or more types.

< Manufacturing method of substrate for electronic components >

The method of manufacturing a substrate for electronic components of the present invention includes the steps of (a) forming an adhesion enhancement layer on the surface of a substrate including one or more through-type vias, and (b) plating a metal on the surface of the adhesion enhancement layer. In addition, the plating step of (b) is characterized in that it is performed through one or more methods selected from electrolytic plating and electroless plating.

In addition, the method of manufacturing a substrate for electronic components according to the present invention may further include a photo process (step (c)) for implementing a circuit after step (b), and step (b) is performed once. There may be more to do than this.

A method of manufacturing a substrate for electronic components according to one or more embodiments of the present invention includes the steps of (a) forming an adhesion enhancement layer on the surface of a substrate including one or more through-type core vias; And (b) plating a metal on the surface of the substrate on which the adhesion enhancement layer is formed, the adhesion of the metal plating layer may be improved, and the through-type core via has a hole diameter of at least one of the upper and lower surfaces inside the hole. It may be larger than the hole diameter at one point. In addition, step (c) as an additional process after steps (a) and (b); It may further include a subsequent step including a photo process, and before performing steps (a), (b), and (c) of the present invention, a step of drilling a through-core via in the substrate through a preparation process. may have been added. In particular, a process of manufacturing a through-core via in which the hole diameter of at least one of the upper and lower surfaces is larger than the hole diameter of a point inside the hole by adjusting the etching rate of the upper and lower surfaces of the substrate before step (a). It may further include. The above preparation process is omitted since the content described for the substrate of <Substrate for Electronic Components> can be applied as is.

(a) forming an adhesion enhancement layer on the surface of a substrate including one or more through-type core vias

The step of forming an adhesion enhancing layer of the present invention may be performed by coating a composition for forming an adhesion enhancing layer.

The composition for forming an adhesion enhancement layer of the present invention may be a composition containing the resin and solvent described in the above-mentioned <Adhesion Enhancement Layer> section.

According to one or more embodiments of the present invention, the substrate forming the adhesion enhancement layer may be made of a material selected from glass or quartz, as described in <Substrate for Electronic Components> , and may have coating properties, optical properties, In terms of chemical stone durability, etc., it is preferable to select glass material.

In addition, the above coating methods include, for example, spin coat method, roller coat method, bar coat method, dip coat method, gravure coat method, curtain coat method, die coat method, spray coat method, doctor coat method, and kneader coat method. coat process, etc.; Printing processes such as screen printing, spray printing, inkjet printing, iron plate printing, intaglio printing, and flat printing; There are deposition processes such as IML (In-Mold Labeling) injection method, CVD (chemical vapor deposition), PVD (physical vapor deposition), and PECVD (plasma enhanced chemical vapor deposition). According to one embodiment of the present invention, a coating liquid is applied to form an adhesion enhancing layer to form a uniform coating film. Among the above methods, slot die coating, spin coating, and dip coating are used. A variety of wet coating methods such as coating, bar coating, and spray coating can be applied without limitation, and it is especially preferable to perform slot die coating or spin coating in terms of applicability and fairness. do. The present invention has the advantage of forming an adhesion enhancing layer using wet coating, thereby improving production speed and securing productivity compared to the conventional sputtering method, and enabling a low-cost, high-efficiency process.

According to one embodiment of the present invention, a surface modification process may be further included for the purpose of preliminary treatment before applying the adhesion enhancing layer. The surface modification includes saponification treatment, plasma treatment, corona treatment, primer treatment, etc., and it is preferable to perform corona treatment in terms of ease of process. Thereafter, the coating film is dried by heating at a temperature of 50°C or higher and 150°C or lower, or 50°C or higher and 100°C or lower using a heating means such as a hot plate, hot air circulation furnace, or infrared furnace to volatilize the solvent. In order to harden the dried coating film by heat treatment, it can be treated by appropriately applying heat or light depending on the type of polymer material included, that is, UV curable resin or thermosetting resin. The light treatment may use g-line (wavelength: 436 nm), h-line, i-line (wavelength: 365 nm), etc. The irradiation amount of ultraviolet rays can be appropriately selected as needed, and is not limited to this in the present invention. The heat treatment can be performed by a heating means such as a hot plate, hot air circulation furnace, infrared furnace, etc., and can be appropriately selected at a temperature of 200 ℃ or higher, preferably 200 ℃ or higher and 300 ℃ or lower, and the present invention does not limit this.

(b) plating metal on the surface of the substrate on which the adhesion enhancement layer is formed

The plating step of the present invention may be performed by a wet coating method. In one embodiment of the present invention, this step may be performed using metallic ink. The contents described in the above-mentioned <metal plating layer> section may be applied to the metal ink without limitation.

According to one embodiment of the present invention, a seed layer can first be formed through a coating and sintering process of metal ink commonly used in the industry, and then a metal plating layer can be formed by applying electroplating and non-electrolytic plating methods, which will be described later. there is. By performing the above process step by step, a metal plating layer that is uniform and has excellent adhesion can be formed not only on the upper and lower surfaces of a glass substrate having a through-type core via, but also on the inner wall of the core via.

Specifically, this step may be performed through one or more methods selected from electrolytic plating and electroless plating. In particular, since the present invention includes an adhesion enhancement layer on the substrate, metal plating is possible with uniformly high adhesion even in the through-type core via portion of the substrate even when only metal ink is used without applying current in the plating step. . Additionally, it goes without saying that an electrolytic plating method that applies current is applicable to the present invention.

The electrolytic plating is applied without particular limitation as long as it is a method recognized as an electrolytic plating method known in the art, such as in the electrical and electronic circuits, semiconductor field, and/or communication field. Specifically, the electrolytic plating step may be performed by wet coating metal ink on the surface of the substrate on which the adhesion enhancement layer is formed and then applying electric current. When the metal ink is wet-coated on the surface of the substrate on which the adhesion enhancement layer is formed, a metal seed may be formed on the adhesion enhancement layer. The metal ink may be coated using a method such as spin coating.

Electroplating can be performed by adding a current to the substrate on which the metal seed is formed by coating the metal ink in an electrolyte solution. The electrolyte solution is not particularly limited as long as it contains electrolyte materials such as chlorine ions, lithium ions, CuSO ₄ , and H ₂ SO ₄ . The current is preferably 0.5 to 20 ASD (amps/dm ² ). If it is less than the above range, the plating crystal grains become coarse and the adhesion of the metal plating layer deteriorates. If it exceeds the above range, the excess plating current is applied to the edge portion. There is a possibility that work may not work smoothly due to the edge burning phenomenon that occurs when concentration occurs.

The electroless plating method may be performed through a wet coating method using metal ink on the surface of the substrate on which the adhesion enhancement layer is formed, and may be performed without additional electrolyte treatment and/or application of current. In the case of a substrate on which an adhesion enhancement layer is not formed, the adhesion is low, and plating with secured adhesion and uniformity on the upper surface of the glass substrate is impossible using only the electroless plating method. However, in the present invention, as an adhesion enhancement layer is introduced on the substrate, Uniform, high-adhesion plating is possible using only electroless wet plating without applying current.

In the present invention, step (b) may be performed repeatedly one or more times. When step (b) is repeated multiple times, a multi-layer laminate can be formed, and in this case, an insulating film may be further included between the multi-layer laminate. With regard to the multi-layer laminate and/or the insulating film, any configuration or technology commonly used in the art may be applied together with the present invention without limitation. Accordingly, the film thickness of the metal plating layer can be adjusted in a desired manner. Specifically, by performing step (b) one more time, a metal plating layer with a thickness of about 10㎛ can be manufactured, and the recovery and final thickness of the metal plating layer may vary depending on the content of metal ink and/or coating method. You can.

(c) Subsequent steps

The method of manufacturing a substrate for electronic components of the present invention may further include a photo process for implementing a circuit after step (b). The photo process can apply a known method for forming a pattern on a metal plating layer, for example, a PCB (Printed Circuit Board), COG (chip on glass) for micro LED, or FEM (Front end module) substrate for high frequency RF, etc. Examples include sputtering processes such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), and PECVD (Plasma Enhanced Chemical Vapor Deposition), screen printing, gravure, and gravure offset ( Methods such as direct printing processes such as gravure offset or inkjet, coating processes, and wet or dry plating processes can be applied. In particular, to implement the desired pattern shape, it is desirable to apply a photo etching method.

The photoetching method involves applying photoresist on the layer that is the target of patterning, selectively curing the applied photoresist using a mask, developing and removing the uncured photoresist, and then etching to form a pattern. This is a method of forming a pattern through a series of processes known in the art to remove the cured photoresist. Photoresists can be divided into positive-type photoresists and negative-type photoresists. The positive type is a photoresist that becomes soluble in the developer when exposed to UV, and the negative type is a photoresist that is insoluble in the developer when exposed to UV. It is a photoresist. Therefore, when using the positive type, the part exposed to UV is developed and a pattern can be formed through a subsequent process, and when using the negative type, the part not exposed to UV is developed and a pattern can be formed through a subsequent process. You can. Conditions for curing the photoresist are not particularly limited, and for example, 0.01 to 10 J/cm ² of UV may be irradiated for 1 to 500 seconds, and preferably 0.05 to 1 J/cm ² of UV may be irradiated for 1 to 1 second. Can be investigated for 120 seconds.

<Display device and semiconductor device including the above electronic component substrate>

In addition to the above electronic component substrate, the present invention includes a display device and/or a semiconductor device manufactured through a post-process including a known process for manufacturing a display device and/or a semiconductor device.

The display device and semiconductor device are not particularly limited as long as they are manufactured using known methods used in the art. In addition, display devices manufactured including the electronic component substrate include, for example, LCD (Liquid Crystal Display), PDP (Plasma Display Panel), FED (Field Emission Display), ELD (Electro-Luminescent Display), and OLED (Organic Display). Light Emitting Diode), etc., but it also includes various image display devices such as electroluminescence display devices, plasma display devices, and field emission display devices, as well as ordinary liquid crystal display devices. Semiconductor packages, semiconductor devices, and display devices manufactured including the electronic component substrate have excellent integration and excellent electrical characteristics, so they can be applied to various devices commonly used in the field and exhibit excellent performance.

Hereinafter, examples of the present invention will be described in detail. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. The present embodiments are merely provided to ensure that the disclosure of the present invention is complete and to be understood by those skilled in the art. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims. “%” and “part” in the examples are mass% and mass part, respectively, unless otherwise specified.

<Manufacture of substrates for electronic components>

Example 1 Angle 5 to 10 ° , hourglass shape, three-dimensional effect (specific surface area increase type)

(1) Preparation process - manufacturing process of the substrate on which the core via is formed

A glass substrate with a flat surface (BDA-E, 0.5 mm thick, Nippon Electric Glass Co., Ltd) was prepared, and the substrate was washed with 2.5 vol% of PK-LCG225X-1 detergent at 70 °C for 8 min in an ultrasonic bath. It has been done. Organic residues are then removed by rinsing with deionized water, and defects are formed on the glass surface at predetermined locations for core via formation. Specifically, the manufacture of core vias on a glass substrate was carried out through the following process. A 30W laser with a wavelength of 904 to 1065 nm in the IR region was selectively irradiated to the core via etching position of the glass substrate. Afterwards, the glass substrate was etched in a hydrofluoric acid etchant using a deeping method, washed with ultrapure water, and dried to produce a glass substrate with a through-core via.

The number of core vias was 4,000 per cm ² , the maximum outer diameter of the core via was 87.3㎛, and the smallest diameter inside the via hole was 45㎛. In addition, the substrate with the core via manufactured in this way is scribed on the glass using CNC laser equipment or using a diamond glass cutter and then broken to expose the vertical cross section, and then used by microscope manufacturer OLYMPUS, model name STM7- Observation with MFA is shown in Figures 10, 11, and 14. It was confirmed that the hourglass-shaped angle inside the core via was 5 to 10°, and the inner wall with an increased specific surface area was confirmed.

(2) Formation of adhesion enhancement layer (step (a): wet coating)

Next, the surface of the glass substrate on which the through-type core via was formed was subjected to corona treatment using a corona treatment device (CTW series, WEDGE CO., LTD) for surface modification. Specifically, it was conducted once under the conditions of output (processing intensity) of 0.3kW and processing speed of 3m/min.

Afterwards, spin coating (1H-DX2, MIKASA) was performed on the glass substrate at 2000 RPM for 20 seconds with an adhesion enhancing layer material containing Pd filler particles and polyimide-based resin so that the final film thickness was 1.5㎛, and then applied on a hot plate. It was cured at a temperature of 120°C for 30 minutes. As a result of measuring the thickness of the adhesion enhancement layer formed using FE-SEM (HITACHI, SU-8010), the thickness of the adhesion enhancement layer formed on the upper and lower surfaces of the glass substrate was measured to be 5,300°C on average.

(3) Metal plating process (step (b): electrolytic plating)

A copper ink mixture is prepared by adding 40 wt% of copper nanoparticles (average particle diameter 50 nm) to an acetate-based solvent containing some butyl carbitol acetate and then dispersing. Thereafter, the copper ink mixture was spin-coated on the glass substrate on which the via was formed using a spin coater (1H-DX2, MIKASA) at 2000 RPM for 20 seconds, and then heated and dried (baked) in an oven at 80 ° C. for 5 minutes. Then, using a xenon lamp (PulseForge 1300, NovaCentrix), light was irradiated onto the dried copper ink pattern and sintered. At this time, the driving voltage of the light source was 650V, the intensity was about 8.91J/cm2, and the irradiation pulse time was 1000μsec.

The substrate was cleaned for 10 seconds at room temperature with a mixture of EVP 221C (Dupont, 5 vol%) and 47% H ₂ SO ₄ (14.0 vol%). Afterwards, it was washed with DI water for about 2 minutes at room temperature, and acid washed with 47% H ₂ SO ₄ (28.0 vol%) for 10 seconds. Next, electroplating was performed to form a copper plating film on the surface of the glass substrate and inside the core via. Specifically, the plating solution contained CuSO _4. 5H ₂ O (75 g/L), H ₂ SO ₄ (190 g/L), Cl- (50 mg/L), and ST-901C (0.5 vol%), and was incubated at room temperature for 35 minutes. Plating was performed with 2ASD (Amps/dm ² ).

D.I. the plated sample for about 2 minutes at room temperature. Washed with water and treated with OXIBAN 60 (0.5 vol%) for 30 seconds for rust prevention. Afterwards, D.I. again at room temperature for about 1 minute. After washing with water and drying, it was annealed in a convection oven at 120°C for 30 minutes.

Example 2 Angle 12 to 18 ° , hourglass shape, three-dimensional effect (increased specific surface area)

The number of core vias was 4,000 per 1 cm ² , the outer diameter of the core via was up to 80㎛, and the smallest diameter inside the via hole was 56㎛. Using the above-described method, it was confirmed that the hourglass-shaped angle inside the core via was 12 to 18°, and the inner wall with an increased specific surface area was confirmed.

Example 3 Angle 10 to 15 ° , asymmetric hourglass shape, three-dimensional effect (specific surface area increase type)

The number of core vias was 4,000 per 1 cm ² , and the diameter of the upper surface of the core via was 190㎛, the diameter of the lower surface was 49㎛, and the diameter of the smallest diameter inside the via hole was 35㎛. In addition, the substrate with the core via manufactured in this way was cut in the same manner as above to expose the vertical cross section, and then observed in the above-described manner as shown in FIGS. 12A and 12B. It was confirmed that the hourglass-shaped angle inside the core via was asymmetrical at 10 to 15°, and the inner wall with an increased specific surface area was confirmed.

Example 4 Angle 25 ° , specific surface area not adjusted

The number of core vias was 4,000 per 1 cm ² , the outer diameter of the core via was up to 80㎛, and the smallest diameter inside the via hole was 56㎛.

The vertical cross-section of the substrate with the core via formed in this way was exposed by the above-described method, and then observed by the above-described method, as shown in FIG. 13. It was confirmed that the hourglass-shaped angle inside the core via was symmetrical at 25°, and the inner wall was confirmed to have no increase in specific surface area.

Comparative Example 1

The electronic component substrate of Comparative Example 1 was manufactured by applying the same method as the method of manufacturing the electronic component substrate according to Example 1, except that step (a), which is the adhesion enhancement layer forming process, was omitted.

Comparative Example 2

Method for manufacturing a substrate for electronic components according to Example 1, except that step (a), which is the adhesion enhancement layer forming process, is omitted and the following stuffing method (step (b')) is applied instead of step (b). The electronic component substrate of Comparative Example 2 was manufactured by applying the same method as above.

Step (b'): Plating process - stuffing method

After cleaning the glass substrate with the adhesion enhancement layer using a standard cleaning process, Ti is applied to the front and back of the glass substrate twice in total using a DC Magnetron Sputter to form a layer. Then, an Ar partial pressure of 10 sccm, a sputtering pressure of 3 mTorr, and a DC power of 100 W were applied to form a film with a film thickness of 500 Å. The film thickness was confirmed by SEM. After completing the Ti layer, Cu is applied in the same manner as above to form a layer at the level of 10,000 Å.

The substrate was cleaned for 10 seconds at room temperature with a mixture of EVP 221C (Dupont, 5 vol%) and 47% H ₂ SO ₄ (14.0 vol%). Afterwards, it was washed with DI water for about 2 minutes at room temperature, and acid washed with 47% H ₂ SO ₄ (28.0 vol%) for 10 seconds.

Next, electroplating was performed to form a copper plating film on the surface of the glass substrate and inside the hole of the core via. Specifically, the plating solution contained CuSO _4.5 H ₂ O (75 g/L), H ₂ SO ₄ (190 g/L), Cl- (50 mg/L), and ST-901C (0.5 vol%), and 2ASD for 35 minutes at room temperature. Plating was performed at (Amps/dm ² ).

D.I. the plated sample for about 2 minutes at room temperature. Washed with water and treated with OXIBAN 60 (0.5 vol%) for 30 seconds for rust prevention. Afterwards, D.I. again at room temperature for about 1 minute. After washing with water and drying, it was annealed in a convection oven at 120°C for 30 minutes.

Comparative Example 3 Angle 0 - Cylindrical

The number of core vias was 4,000 per 1 cm ² , and the outer diameter of the top/bottom surfaces of the core via and the inner diameter of the via hole were 56㎛.

Experiment example

(1) Evaluation of plating adhesion

An adhesion test was performed on the surface of the electronic component substrate manufactured according to the above examples and comparative examples in accordance with ASTM D3359, an international standard cross cut method. Specifically, among 100 1 mm * 1 mm grid scales formed on the surface of a substrate for electronic components, the degree of peeling off portions was observed after the tape adhesion test, and the degree of adhesion was evaluated with a value from 0B to 5B, and the results are shown in the table below. It is shown in 1.

<Evaluation criteria>

5B: No delamination occurs in the entire area of the test specimen.

4B: A state in which peeling occurs in less than 5% of the total area of the specimen.

3B: A state in which peeling occurs in an area of 5% to 15% of the total area of the specimen.

2B: A state in which peeling occurs in an area of 15% to 35% of the total area of the specimen.

1B: A state in which peeling occurs in an area greater than 35% but less than 65% of the total area of the specimen.

0B: A state in which peeling occurs in more than 65% of the total area of the specimen.

In addition, the results were judged according to the criteria below and are listed in Table 1 below.

<Judgment criteria>

OK: Plating adhesion 4B or more

NG: Plating adhesion less than 4B

(2) Average thickness of plating layer

The average thickness of the plating layer confirmed by SEM was measured and listed in Table 1 below.

	Example 1	Example 4	Comparative Example 1	Comparative example 2
Plating adhesion	5B	5B	0B	2B
Judgment	OK	OK	NG	NG
Plating layer thickness (㎛)	4.6	9.6	9.8	4.5

(3) Reliability evaluation

The reliability of each Example and Comparative Example was evaluated according to the following KS test method and is shown in Table 2.

If electrode lifting and/or electrode corrosion were confirmed, it was recorded as NG, otherwise it was recorded as OK.

< KS test method >

High temperature and humidity 500HR 60/93: IEC60068-2-3 (high temperature and humidity test), KS C 0222 (high temperature and humidity test)

Low temperature test 240HR: IEC60068-2-1 (low temperature test), KS C 0220 (low temperature test)

High temperature test 240HR: IEC60068-2-2 (high temperature test), KS C 0221 (high temperature test)

Temperature and humidity cycle test -20~60℃ 72HR: IEC60068-2-30 (temperature and humidity cycle test), Ks C 0227 (temperature and humidity cycle test)

Salt spray: IEC600682.11 (salt spray test), KS C 0223 (salt spray test)

	Comparative Example 3	Example 1	Example 2	Example 3	Example 4
High temperature and humidity 500HR 60/93	NG (electrode excitation)	OK	OK	OK	NG (electrode excitation)
Low temperature test 240HR	NG	OK	OK	OK	OK
High temperature test 240HR	NG	OK	OK	OK	OK
Temperature and humidity cycle test -20~60℃, 72HR	NG (electrode excitation)	OK	OK	OK	NG (electrode excitation)
salt spray	NG Electrode corrosion and lifting	OK	OK	OK	NG Electrode corrosion and lifting

According to the experimental data in Table 1, the electronic component substrate manufactured according to the embodiment of the present invention showed excellent plating adhesion, while a comparative example in which copper ink was plated using a general sputtering method rather than a wet coating method In the case of Comparative Example 1 and Comparative Example 2 where the adhesion enhancing layer was not applied, the plating adhesion did not meet the criteria and peeling was observed in a large area. In addition, according to the experimental data in Table 2, according to Examples 1 to 4 of the present invention The manufactured electronic component substrate containing a through-type core via in which the hole diameter of at least one of the upper and lower surfaces is larger than the hole diameter of a point inside the hole did not show electrode lifting phenomenon under harsh conditions of high and low temperatures. In particular, the electronic component substrates of Examples 1 to 3, in which the inside of the core via was shaped like an hourglass and the specific surface area of the inner wall was increased, showed electrode lifting phenomenon even under all harsh conditions such as high temperature/high humidity, high temperature, low temperature, salt water, etc. This did not appear, confirming that it had a superior effect. In contrast, the electronic substrate of Comparative Example 3 including a cylindrical core via showed poor results in which the electrode was lifted under all conditions.

According to the electronic component substrate and its manufacturing method according to the present invention, in the production of a substrate having a through-type core via, the adhesion of the metal plating layer is improved by including an adhesion enhancement layer formed through a wet coating method to prevent defects. Thus, high quality substrates for electronic components can be provided.

Claims (15)

1. A substrate comprising one or more through-core vias; and

   It includes an adhesion enhancement layer on the surface of the substrate and the surface of the through-type core via,

   In the through-type core via, the hole diameter of at least one of the upper and lower surfaces is larger than the hole diameter of a point inside the hole,

   Substrate for electronic components.
2. In claim 1,

   The through-type core via is a line connecting a point of the core via on the upper or lower surface in a vertical cross-section and a point with the smallest hole diameter inside the via; and a board for electronic components, wherein the angle of a line connected in the vertical direction from a point of the core via on the upper or lower surface is 1° to 25° or less.
3. In claim 1,

   A substrate for electronic components, wherein the through-type core via has a symmetric or asymmetric vertical cross-section.
4. In claim 1,

   A substrate for electronic components, characterized in that the inner wall of the through-type core via has a shape containing irregularities.
5. In claim 1,

   A substrate for electronic components, characterized in that the substrate is glass or quartz.
6. In claim 1,

   The adhesion enhancing layer includes at least one selected from the group consisting of a UV curable resin having an acrylic group and a polyimide-based thermosetting resin, or is a film coated with a metal, oxide, or ceramic oxide.
7. In claim 1,

   A substrate for electronic components wherein the thickness of the adhesion enhancing layer is 250 to 6000 Å.
8. In claim 1,

   A substrate for electronic components, wherein the average hole diameter of at least one of the upper and lower surfaces of each through-type core via of the substrate is 5 to 190㎛.
9. (a) forming an adhesion enhancement layer on the surface of a substrate including one or more through-core vias; and

   (b) plating metal on the surface of the substrate on which the adhesion enhancement layer is formed,

   In the through-type core via, the hole diameter of at least one of the upper and lower surfaces is larger than the hole diameter of a point inside the hole,

   A method of manufacturing a substrate for electronic components, wherein the plating step of (b) is performed through one or more methods selected from electrolytic plating and electroless plating.
10. In claim 9,

    The step (a) is a method of manufacturing a substrate for electronic components, further comprising a surface modification process.
11. In claim 10,

    A method of manufacturing a substrate for electronic components, wherein the surface modification is performed by one or more methods selected from the group consisting of saponification treatment, plasma treatment, corona treatment, and primer treatment.
12. In claim 9,

    Before step (a), by adjusting the etching rate of the upper and lower surfaces of the substrate, a process of manufacturing a through-core via in which the hole diameter of at least one of the upper and lower surfaces is larger than the hole diameter of a point inside the hole is further performed. Including, a method of manufacturing a substrate for electronic components.
13. In claim 9,

    A method of manufacturing a substrate for electronic components, wherein step (b) is further performed one or more times.
14. A display device comprising the substrate for electronic components according to any one of claims 1 to 8.
15. A semiconductor device comprising the electronic component substrate according to any one of claims 1 to 8.

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