WO2024082747A1 - Routeur ayant une mémoire cache, système de réseau de routage et de commutation, puce et procédé de routage - Google Patents

Routeur ayant une mémoire cache, système de réseau de routage et de commutation, puce et procédé de routage Download PDF

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Publication number
WO2024082747A1
WO2024082747A1 PCT/CN2023/108912 CN2023108912W WO2024082747A1 WO 2024082747 A1 WO2024082747 A1 WO 2024082747A1 CN 2023108912 W CN2023108912 W CN 2023108912W WO 2024082747 A1 WO2024082747 A1 WO 2024082747A1
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output port
routing
buffer pool
router
output
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PCT/CN2023/108912
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English (en)
Chinese (zh)
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刘明
石昊明
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声龙(新加坡)私人有限公司
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Publication of WO2024082747A1 publication Critical patent/WO2024082747A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/60—Router architectures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3027—Output queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of integrated circuit technology, and in particular to a router with cache, a routing switching network system, a chip, and a routing method.
  • Routers and arbiters are generally used in on-chip routing switching networks.
  • a router is a circuit structure in an integrated circuit, which generally has one or more input ports and multiple output ports. Its function is to transfer data to the appropriate output port according to established rules.
  • An arbiter is a circuit structure in an integrated circuit, which generally has multiple input ports and one or more output ports. Its function is to transfer data arriving from multiple input ports to the appropriate output port according to established rules.
  • the Proof of Work (POW) mechanism requires a large number of hash operations to find a hash value that meets the conditions under a specific difficulty value. Distributing the computing tasks on multiple computing units can increase the computing speed of the Proof of Work. However, since each computing task needs to access multiple storage units through the on-chip routing switching network, the throughput of the routing switching network becomes an important factor affecting the computing speed of the Proof of Work.
  • the present disclosure provides a router with a cache, comprising:
  • M 1 input port, M output ports, a first buffer pool, M first-in first-out FIFO queues corresponding one-to-one to the M output ports, an input port processing module, and M output port processing modules corresponding one-to-one to the M output ports;
  • M is a positive integer;
  • the input port processing module is configured to receive a routing request through an input port of a router, wherein the routing request includes routing data and routing port information; when there is an idle storage location in the first buffer pool of the router, select an idle storage location as a target location, and store the routing data in the routing request into the target location; determine a target output port of the router according to the routing port information in the routing request, and store the index information of the target location in a FIFO queue of the target output port; wherein each output port corresponds to a FIFO queue;
  • the output port processing module is configured to read the index information of the first output position from the FIFO queue of the output port after the output port obtains an output indication, determine the target position in the first cache pool according to the index information, read the routing data from the target position and output it to the output port.
  • the present disclosure provides a routing method, applied to a router with a cache, comprising:
  • routing request includes routing data and routing port information
  • the router When there is an idle storage location in the first buffer pool of the router, select an idle storage location as a target location, and store the routing data in the routing request into the target location; determine the target output port of the router according to the routing port information in the routing request, and save the index information of the target location in the FIFO queue of the target output port; wherein the router includes an input port and M output ports, each output port corresponds to a FIFO queue, and M is a positive integer;
  • the index information of the first output position is read from the FIFO queue of the output port, the target position in the first cache pool is determined according to the index information, and the routing data is read from the target position and output to the output port.
  • the present disclosure provides a routing switching network system, including M arbitrators and N The above routers with cache; N and M are positive integers;
  • Any router with cache includes 1 input port and M output ports;
  • Any arbiter has N input ports and one output port;
  • the M output ports of any router with cache are connected one by one to the input ports of the M arbitrators respectively;
  • the N input ports of any arbitrator are connected one by one to the output ports of N routers with caches.
  • the present disclosure provides a chip, comprising the above-mentioned routing switching network system.
  • FIG1 is a schematic diagram of the structure of a router with cache provided by an embodiment of the present disclosure
  • FIG2 is a schematic diagram of the structure of another router with cache provided in an embodiment of the present disclosure.
  • FIG3 is a schematic diagram of the structure of an input port processing module provided by an embodiment of the present disclosure.
  • FIG4 is a schematic diagram of the structure of an output port processing module provided by an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a second buffer pool provided in an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of the structure of a 1*4 router with cache provided in an embodiment of the present disclosure
  • FIG7 is a flow chart of a routing method provided by an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of the structure of a routing switching network system provided by an embodiment of the present disclosure.
  • the present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art.
  • the embodiments, features, and elements disclosed in the present disclosure may also be combined with any conventional features or elements to form a unique invention scheme defined by the appended claims.
  • Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the appended claims. Therefore, it should be understood that any feature shown and/or discussed in the present disclosure may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the appended claims and their equivalents, the embodiments are not subject to other limitations.
  • various modifications and changes may be made within the scope of protection of the appended claims.
  • an embodiment of the present disclosure provides a router with a cache, including:
  • M 1 input port, M output ports, a first buffer pool, M first-in first-out FIFO queues corresponding one-to-one to the M output ports, an input port processing module, and M output port processing modules corresponding one-to-one to the M output ports;
  • M is a positive integer;
  • the input port processing module is configured to receive a routing request through an input port of the router, wherein the routing request includes routing data and routing port information; when there is an idle storage location in the first buffer pool of the router, select an idle storage location as a target location, and store the routing data in the routing request in the target location; determine the target output port of the router according to the routing port information in the routing request, and store the index information of the target location in the target location; In the FIFO queue of the output port, each output port corresponds to a FIFO queue;
  • the output port processing module is configured to read the index information of the first output position from the FIFO queue of the output port after the output port obtains an output indication, determine the target position in the first cache pool according to the index information, read the routing data from the target position and output it to the output port.
  • the router with cache provided in the above embodiment includes 1 input port, M output ports, a first cache pool, M first-in first-out FIFO queues corresponding to the M output ports, an input port processing module, and M output port processing modules corresponding to the M output ports.
  • the routing forwarding efficiency can be improved and resources can be saved by sharing the first cache pool by multiple output ports, the routing forwarding efficiency of each output port can be improved by setting a corresponding FIFO queue for each output port, and the index information of the routing data is stored in the FIFO queue instead of the routing data, which can save resources.
  • the object (index information) stored first in the FIFO queue will be taken out first. Each time an object is taken out, the object that was stored after the taken out object will automatically become the object at the first output position during the next take-out operation.
  • the router with cache further includes: a first cache pool recording module
  • the first buffer pool recording module is configured to record the occupancy information of each storage location in the first buffer pool through a first recording registers, wherein a is the depth of the first buffer pool, that is, the total number of storage locations in the first buffer pool, and a is a positive integer.
  • the first cache pool recording module is configured to, after routing data is stored in a storage location in the first cache pool, set the value of the first record register corresponding to the storage location to indicate occupancy; after routing data in a storage location in the first cache pool is read out, set the value of the first record register corresponding to the storage location to indicate free.
  • the input port processing module includes: an input port control unit, a first buffer pool addressing unit, a first buffer pool write control unit, and a FIFO queue write control unit;
  • An input port control unit is configured to receive a routing request from an input port, wherein the routing request Contains routing data and routing port information, sends the routing data to the first buffer pool write control unit, and sends the routing port information to the FIFO queue write control unit;
  • a first buffer pool addressing unit is configured to determine whether there is an idle storage location in the first buffer pool, and if so, select an idle storage location as a target location, and send index information of the target location to the first buffer pool write control unit and the FIFO queue write control unit;
  • a first buffer pool write control unit configured to store the routing data in the routing request into the target location in the first buffer pool
  • the FIFO queue write control unit is configured to determine the target output port of the router according to the routing port information, and store the index information of the target position in the FIFO queue of the target output port; wherein each output port corresponds to a FIFO queue.
  • the first cache pool addressing unit is configured to determine whether there is a free storage location in the first cache pool in the following manner: obtaining record information of a first record registers of the first cache pool record module, and determining whether there is a free storage location in the first cache pool based on the record information.
  • the first cache pool write control unit is further configured to, after storing the routing data in the routing request into the target location in the first cache pool, notify the first cache pool recording module to set the value of the first recording register corresponding to the target location to indicate occupancy.
  • the output port processing module corresponding to the i-th output port includes: an output port control unit, a first buffer pool read control unit, and a FIFO queue read control unit; 1 ⁇ i ⁇ M;
  • An output port control unit is configured to obtain an output indication from the i-th output port and notify the FIFO queue read control unit;
  • a FIFO queue read control unit is configured to read the index information of the first output position from the FIFO queue (FIFO queue i) corresponding to the i-th output port, and send the index information to the first buffer pool read control unit;
  • the first buffer pool read control unit is configured to read routing data from the first buffer pool according to the index information and output the routing data to the corresponding i-th output port.
  • the first cache pool read control unit is further configured to read After the routing data is read from the first buffer pool according to the index information, the first buffer pool recording module is notified to set the value of the first recording register corresponding to the storage position of the read routing data in the first buffer pool to indicate idle.
  • the input port control unit is further configured to, after receiving a routing request through the input port of the router, return a response message to the superior module through the input port indicating that the router is ready to receive routing data when there is a free storage location in the first cache pool of the router; and return a response message to the superior module through the input port indicating that the router is not ready to receive routing data when there is no free storage location in the first cache pool of the router.
  • the output port control unit is configured to obtain an output indication from the i-th output port in the following manner: a data output request is sent to a lower-level module through the i-th output port, and when a response signal of authorized output is returned by the lower-level module, it is determined that an output indication is obtained.
  • the length of the FIFO queue corresponding to each output port of the router is equal to the depth of the first buffer pool. For example, if the depth of the first buffer pool is 16, the length of the FIFO queue corresponding to each output port of the router is also 16. Setting the length of the FIFO queue corresponding to each output port of the router to the depth of the first buffer pool can cope with the situation where multiple routing requests are concentratedly sent to the same output port in a short period of time.
  • the router with cache further includes: a second cache pool; the sum of the depth of the second cache pool and the length of the FIFO queue of any output port is greater than or equal to the depth of the first cache pool;
  • the second buffer pool is configured to cache index information of a storage location of routing data of any output port in the first buffer pool
  • the input port processing module is configured to determine the target output port of the router according to the routing port information in the routing request, and then determine whether the FIFO queue of the target output port is full. If it is full, the index information of the storage position of the routing data in the first buffer pool and the information of the target output port are stored in the second buffer pool together; if it is not full, the index information of the storage position is stored in the FIFO queue of the target output port.
  • the depth of the second buffer pool is greater than the sum of the lengths of the FIFO queues of any output port. For example, if the depth of the first buffer pool is 16, the length of the FIFO queue of any output port of the router is 4, and the depth of the second buffer pool can be set to 20.
  • the output port processing module is further configured to read the index information of the first output position from the FIFO queue of the output port, and then query whether the index information of the output port exists in the second cache pool, and if so, save the index information of the target position of the routing data of the output port that is first stored in the second cache pool in the FIFO queue of the output port.
  • the second buffer pool is implemented by a register file or by a plurality of registers.
  • a router with a cache having 1 input port and 4 output ports is taken as an example.
  • the router includes: an input port, 4 output ports, an addressing arbitration module, a cache pool empty and full recording module, a gating module, 4 FIFO queues, a cache pool, a cache pool write control module, 4 cache pool read control modules, and 4 FIFO queue read control modules.
  • the depth of the cache pool is 8.
  • the cache pool empty and full recording module includes 8 first recording registers.
  • the router When a router receives a routing request from an input port, it will receive data signals, handshake signals, and routing port signals at the same time.
  • the data signal bit width can be very large, much larger than the bit width of the FIFO queue.
  • the handshake signal is an interactive signal between the upper module and the router, such as a pair of handshake signals wvalid and wready. wvalid (sent from the upper module to the router) indicates that a routing request has arrived, and wready (sent from the router to the upper module) indicates that there is cache space in the current router to receive the routing request.
  • the routing port signal is a pair of handshake signals rvalid and grant sent between the output port of the router to which the routing data needs to be sent and the lower module (such as the arbitrator).
  • rvalid (sent from the router to the lower module) indicates that there is a routing request to the lower module in the router
  • grant (sent from the lower module to the router) indicates that the lower module has responded to the routing request and authorized the router to output at the corresponding output port.
  • the addressing arbitration module is configured to receive a routing request through an input port of a router, wherein the routing request includes routing data and routing port information; obtain the record information of the eight first record registers of the buffer pool empty and full record module, determine whether there is an idle storage location in the buffer pool according to the record information, and if so, select an idle storage location as a target location, and send the index information of the target location to the buffer pool write control module and the selection module.
  • the cache pool write control module is configured to store the routing data in the routing request into the target location in the cache pool.
  • the gating module is configured to determine the target output port of the router according to the routing port information, and store the index information of the target position in the FIFO queue of the target output port; wherein each output port corresponds to a FIFO queue.
  • the cache pool read control module corresponding to output port i is configured to send a data output request to the lower-level module through output port i.
  • a response signal of authorized output returned by the lower-level module is received, it is determined that an output indication is obtained; the index information of the first output position is read from the FIFO queue (FIFO queue i) corresponding to output port i, and the index information is sent to the cache pool read control module; 1 ⁇ i ⁇ 4.
  • the cache pool read control module is configured to read routing data from the cache pool according to the index information and output the data to the corresponding output port i; 1 ⁇ i ⁇ 4.
  • routing data 1 is output port 1
  • the destination port of routing data 2 is output port 2
  • the destination port of routing data 3 is output port 3.
  • Positions 1, 2, and 3 of the buffer pool store routing data 1, routing data 2, and routing data 3, respectively.
  • the FIFO queue (FIFO1) of output port 1 stores the index information of the storage position of routing data 1 in the buffer pool
  • the FIFO queue (FIFO2) of output port 2 stores the index information of the storage position of routing data 2 in the buffer pool
  • the FIFO queue (FIFO3) of output port 3 stores the index information of the storage position of routing data 3 in the buffer pool.
  • a routing request to output port 1 arrives at the router.
  • the addressing arbitration module obtains an index signal that can map the free address in the buffer pool by querying the buffer pool empty and full record module (for example, the 4th register indicates the position 4 of the buffer pool), and sends the index signal to the buffer pool write control module and the gating module.
  • the gating module determines whether the destination port is the output port according to the routing port information.
  • Output port 1 sends the index signal of the storage location of the routing data to the FIFO queue (FIFO queue 1) of output port 1.
  • the buffer pool write control module writes the routing data into the buffer pool according to the index signal sent by the addressing arbitration module, and notifies the buffer pool empty and full recording module to set the value of the fourth register (indicating whether the position 4 of the buffer pool is occupied) to indicate occupation.
  • a routing request to output port 2 arrives at the router.
  • the addressing arbitration module obtains an index signal that can map the free address in the buffer pool by querying the buffer pool empty and full record module (for example, the 5th register indicates the position 5 of the buffer pool), and sends the index signal to the buffer pool write control module and the selection module.
  • the selection module determines that the destination port is output port 2 based on the routing port information, and sends the index signal of the storage location of the routing data to the FIFO queue (FIFO queue 2) of output port 2.
  • the buffer pool write control module writes the routing data into the buffer pool according to the index signal sent by the addressing arbitration module, and notifies the buffer pool empty and full record module to set the value of the 5th register (indicating whether the position 5 of the buffer pool is occupied) to indicate occupation.
  • output port 1 and output port 2 receive the authorization output signal from the lower-level module, that is, the grant1 and grant2 signals are high (high level is valid), FIFO queue 1 outputs the index information currently at the front of the queue (register 1 indicates position 1 of the buffer pool), and FIFO queue 2 outputs the index information currently at the front of the queue (register 2 indicates position 2 of the buffer pool).
  • Buffer pool read control module 1 obtains the index information output by FIFO queue 1, reads routing data 1 from the buffer pool according to the index information and sends it to output port 1, notifies the buffer pool empty and full record module to set the value of register 1 to indicate idle.
  • Buffer pool read control module 2 obtains the index information output by FIFO queue 2, reads routing data 2 from the buffer pool according to the index information and sends it to output port 2, notifies the buffer pool empty and full record module to set the value of register 2 to indicate idle.
  • an embodiment of the present disclosure provides a routing method, which is applied to a router with a cache, including:
  • Step S10 receiving a routing request through an input port of a router; wherein the routing request includes routing data and routing port information;
  • Step S20 when there is an idle storage location in the first buffer pool of the router, select an idle storage location as a target location, store the routing data in the routing request into the target location; determine the target output port of the router according to the routing port information in the routing request, The index information of the target position is stored in the FIFO queue of the target output port; wherein the router includes an input port and M output ports, each output port corresponds to a FIFO queue, and M is a positive integer;
  • Step S30 after the output port of the router obtains an output indication, reads the index information of the first output position from the FIFO queue of the output port, determines the target position in the first cache pool according to the index information, reads the routing data from the target position and outputs it to the output port.
  • the routing method provided in the above embodiment and applied to a router with a cache can improve the routing forwarding efficiency and save resources by having multiple output ports share the first cache pool.
  • the routing forwarding efficiency of each output port can be improved, and storing index information of routing data in the FIFO queue instead of routing data can save resources.
  • the first buffer pool is implemented by a register file or by multiple registers. As long as the first buffer pool is not full, it can always receive routing data from the input port, so the larger the first buffer pool is, the greater the network throughput is, but the more resources are occupied.
  • the register file or multiple registers can be read concurrently, so the routing forwarding efficiency can be maximized.
  • a register file is a circuit structure in the field of computer chips. It refers to a customized combination of registers in a cluster. It has the application characteristics of one-port writing and multiple-port reading, and there is no extra space between the internal registers. Therefore, compared with the circuit implemented by the same number of multiple registers, the circuit using a register file occupies a smaller area.
  • the method further comprises:
  • the occupancy information of each storage location in the first buffer pool is recorded through a first recording registers; wherein a is the depth of the first buffer pool, that is, the total number of storage locations in the first buffer pool, and a is a positive integer.
  • the occupancy information of each storage location in the first buffer pool is recorded by a first record register, including: after the routing data is stored in a storage location in the first buffer pool, the value of the first record register corresponding to the storage location is set to indicate occupancy; after the routing data of a storage location in the first buffer pool is read out, the value of the first record register corresponding to the storage location is set to indicate occupancy; The value of a record register is set to indicate idle.
  • the method further includes: when there is an idle storage location in a first cache pool of the router, the router returns a response message to a superior module through the input port indicating that the router is ready to receive routing data.
  • the method further includes: when there is no free storage location in a first cache pool of the router, the router returns a response message to a superior module through the input port indicating that the router is not ready to receive routing data.
  • the output port of the router obtains the output indication, including: sending a data output request to a lower-level module through the output port of the router, and when a response signal of authorized output returned by the lower-level module is received, determining that the output indication is obtained.
  • the bit width of the index information of the storage location of the first cache pool is determined by the depth of the first cache pool, and the bit width of the index information is smaller than the bit width of the routing data cached in any storage location.
  • the bit width of the routing data can be as high as 1024 bits.
  • the depth of the first cache pool is 16
  • the first cache pool includes 16 storage locations
  • the index information of the storage location of the first cache pool is 0 to 15, that is, the bit width of the index information of the storage location of the first cache pool can be 4 bits, which is much smaller than the bit width of the routing data.
  • the length of the FIFO queue corresponding to each output port of the router is equal to the depth of the first buffer pool. For example, if the depth of the first buffer pool is 16, the length of the FIFO queue corresponding to each output port of the router is also 16. Setting the length of the FIFO queue corresponding to each output port of the router to the depth of the first buffer pool can cope with the situation where multiple routing requests are concentratedly sent to the same output port in a short period of time.
  • the method when the length of the FIFO queue corresponding to each output port of the router is less than the depth of the first buffer pool, the method further includes:
  • the target output port of the router After determining the target output port of the router according to the routing port information in the routing request, determining whether the FIFO queue of the target output port is full, and if it is full, storing the index information of the storage location of the routing data in the first buffer pool and the information of the target output port in the second buffer pool together. In the storage pool, if it is not full, the index information of the storage location is stored in the FIFO queue of the target output port;
  • the second buffer pool is used to cache the index information of the storage location of the routing data of any output port in the first buffer pool; the sum of the depth of the second buffer pool and the length of the FIFO queue of any output port is greater than or equal to the depth of the first buffer pool.
  • the method further includes: querying whether the index information of the output port exists in the second cache pool, and if so, saving the index information of the target position of the routing data of the output port that is first stored in the second cache pool in the FIFO queue of the output port.
  • an embodiment of the present disclosure provides a routing switching network system, including M arbitrators and the above-mentioned N routers with caches; N and M are positive integers;
  • Any router with cache includes 1 input port and M output ports;
  • Any arbiter has N input ports and one output port;
  • the M output ports of any router with cache are connected one by one to the input ports of the M arbitrators respectively;
  • the N input ports of any arbitrator are connected one by one to the output ports of N routers with caches.
  • the routing switching network system includes N routers with cache and M arbiters.
  • Each router with cache can improve routing forwarding efficiency and save resources by sharing the first cache pool through multiple output ports.
  • the routing forwarding efficiency of each router output port can be improved, and storing index information of routing data instead of routing data in the FIFO queue can save resources.
  • a router generally has one input port and multiple output ports, and its function is to transfer data to the appropriate output port according to established rules.
  • An arbitrator generally has multiple input ports and one output port, and its function is to transfer data arriving from multiple input ports to the appropriate output port according to established rules.
  • the input port of a router can be connected to an upper-level module (such as a computing module, etc.).
  • the output port of an arbitrator can be connected to a lower-level module (such as a storage controller, an on-chip bus controller, etc.).
  • the embodiment of the present disclosure also provides a chip, including the above-mentioned routing switching network system.
  • the chip supports applications based on the Ethereum proof-of-work mechanism.
  • the functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof.
  • the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation.
  • Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit.
  • Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium).
  • computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data).
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer.
  • communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

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Abstract

Sont divulgués un routeur ayant une mémoire cache, un système de réseau de routage et de commutation, ainsi qu'une puce et un procédé de routage. Le routeur doté d'une mémoire cache comprend un port d'entrée, M ports de sortie, un premier pool de cache, M files d'attente FIFO en correspondance biunivoque avec les M ports de sortie, un module de traitement de port d'entrée et M modules de traitement de port de sortie en correspondance biunivoque avec les M ports de sortie. Le module de traitement de port d'entrée est configuré pour sélectionner une position de stockage inactive du premier pool de cache en tant que position cible pour stocker des données de routage, puis stocker les informations d'index de la position cible dans la file d'attente FIFO d'un port de sortie du routeur. Les modules de traitement de port de sortie sont chacun configurés pour lire les informations d'index disposées à la première position de sortie dans la file d'attente FIFO d'un port de sortie, déterminer la position cible dans le premier pool de cache selon les informations d'index, lire les données de routage à partir de la position cible et transmettre les données de routage au port de sortie.
PCT/CN2023/108912 2022-10-18 2023-07-24 Routeur ayant une mémoire cache, système de réseau de routage et de commutation, puce et procédé de routage WO2024082747A1 (fr)

Applications Claiming Priority (2)

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