WO2024082732A1 - 一种集成参考电压产生的模数转换器及校准方法 - Google Patents

一种集成参考电压产生的模数转换器及校准方法 Download PDF

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Publication number
WO2024082732A1
WO2024082732A1 PCT/CN2023/108062 CN2023108062W WO2024082732A1 WO 2024082732 A1 WO2024082732 A1 WO 2024082732A1 CN 2023108062 W CN2023108062 W CN 2023108062W WO 2024082732 A1 WO2024082732 A1 WO 2024082732A1
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Prior art keywords
capacitor
ptat
analog
diode
signal
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PCT/CN2023/108062
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English (en)
French (fr)
Inventor
唐中
刘禹延
谭年熊
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杭州万高科技股份有限公司
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Priority to EP23805849.9A priority Critical patent/EP4391389A1/en
Publication of WO2024082732A1 publication Critical patent/WO2024082732A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing

Definitions

  • the invention belongs to the technical field of analog-to-digital conversion, and in particular relates to an analog-to-digital converter with integrated reference voltage generation and a calibration method.
  • the application field of high-precision sensors requires a high-precision analog-to-digital converter (ADC) to realize input signal acquisition, and also requires a high-precision reference source that does not change with the environment such as temperature and power supply as the reference signal of the ADC.
  • ADC analog-to-digital converter
  • an additional reference signal driver is also required.
  • the reference signal generation module, driver, and analog-to-digital converter are often designed separately, which inevitably has disadvantages such as high power consumption, large area, and large errors.
  • each component needs to be calibrated separately, which increases the correction cost.
  • the technical problem to be solved by the present invention is to provide an analog-to-digital converter and a calibration method with integrated reference voltage generation in view of the deficiencies in the prior art.
  • a first aspect discloses an analog-to-digital converter with integrated reference voltage generation, including a sample-and-hold circuit, a capacitor digital-to-analog converter and a quantizer.
  • the sample-and-hold circuit is used to sample and hold the analog input signal to obtain a first signal
  • the capacitance digital-to-analog converter is used to generate a reference signal, and to generate a second signal proportional to the reference signal according to the fed-back digital output signal; the first signal and the second signal are subtracted to obtain an error signal;
  • the quantizer is used to digitize the error signal to obtain a digital output signal.
  • a loop filter may be added before the quantizer, and the loop filter is used for noise shaping to improve resolution.
  • the capacitance digital-to-analog converter includes a CTAT circuit based on a capacitance bias diode and a PTAT circuit based on a capacitance bias diode, the CTAT circuit based on a capacitance bias diode and the PTAT circuit based on a capacitance bias diode jointly generate the reference signal, and the reference signal is independent of temperature.
  • the CTAT circuit based on the capacitor biased diode generates a CTAT voltage V D which decreases as the temperature increases
  • the PTAT circuit based on the capacitor biased diode generates a PTAT voltage ⁇ V D which increases as the temperature increases.
  • the capacitor-biased diode-based CTAT circuit includes a first CTAT circuit switch S CTAT1 , a CTAT diode branch and a CTAT capacitor branch, one end of the first CTAT circuit switch S CTAT1 is respectively connected to one end of the CTAT diode branch and one end of the CTAT capacitor branch, the other end of the CTAT diode branch and the other end of the CTAT capacitor branch are both grounded; the other end of the first CTAT circuit switch S CTAT1 is connected to a power supply.
  • the PTAT circuit based on capacitor biased diode includes a first capacitor biased diode circuit and a second capacitor biased diode circuit
  • the first capacitor biased diode circuit includes a first PTAT circuit switch S PTAT1 , a first PTAT diode branch and a first PTAT capacitor branch, one end of the first PTAT circuit switch S PTAT1 is respectively connected to one end of the first PTAT diode branch and one end of the first PTAT capacitor branch, and the other end of the first PTAT diode branch and the other end of the first PTAT capacitor branch are both grounded; the other end of the first PTAT circuit switch S PTAT1 is connected to a power supply;
  • the second capacitor biased diode circuit includes a second PTAT circuit switch S PTAT2 , a second PTAT diode branch and a second PTAT capacitor branch, one end of the second PTAT circuit switch S PTAT2 is respectively connected to one end of the second PTAT diode branch and
  • the CTAT diode branch includes a first diode D1 and a second CTAT circuit switch S CTAT2 connected to the first diode D1 .
  • the CTAT capacitor branch includes a second reference capacitor C REF2 .
  • the CTAT capacitor branch includes N second capacitor branches connected in parallel, and the second capacitor branch includes a second reference capacitor C REF2 and a second reference switch S REF2 connected to the second reference capacitor C REF2 .
  • the first PTAT diode branch includes a second diode D2 and a third PTAT circuit switch S PTAT3 connected to the second diode D2 .
  • the second PTAT diode branch includes a fourth PTAT circuit switch S PTAT4 and a PTAT diode combination connected to the fourth PTAT circuit switch S PTAT4 , and the PTAT diode combination includes a plurality of third diodes D3 connected in parallel.
  • the first PTAT capacitor branch and the second PTAT capacitor branch both include a first reference capacitor C REF1 .
  • the first PTAT capacitor branch and the second PTAT capacitor branch both include N parallel first capacitor branches, and the first capacitor branch includes a first reference capacitor C REF1 and a first reference switch S REF1 connected to the first reference capacitor C REF1 .
  • the second reference capacitor C REF2 is first pre-charged to the power supply voltage V DD through the first CTAT circuit switch S CTAT1 , and then the first CTAT circuit switch S CTAT1 is opened, and the second CTAT circuit switch S CTAT2 is closed, and the second reference capacitor C REF2 is discharged through the first diode D1; if the discharge time is fixed, the residual voltage on the second reference capacitor C REF2 decreases as the temperature increases, and the residual voltage is the CTAT voltage V D .
  • the first reference capacitor C REF1 of the first capacitor biased diode circuit is first pre-charged to the power supply voltage V DD through the first PTAT circuit switch S PTAT1 , and then the first PTAT circuit switch S PTAT1 is opened, and the third PTAT circuit switch S PTAT3 is closed, and the first reference capacitor C REF1 of the first capacitor biased diode circuit is discharged through the second diode D2 to obtain a first residual voltage V D1 .
  • first reference capacitor C REF1 of the second capacitor biasing diode circuit is first pre-charged to the power supply voltage V DD through the second PTAT circuit switch S PTAT2 , and then the second PTAT circuit switch S PTAT2 is opened, and the fourth PTAT circuit switch S PTAT4 is closed, and the first reference capacitor C REF1 of the second capacitor biasing diode circuit is discharged through the PTAT diode combination to obtain a second residual voltage V D2 .
  • a voltage difference V D1 -V D2 between the first residual voltage V D1 and the second residual voltage V D2 increases as the temperature increases, and the voltage difference is a PTAT voltage ⁇ V D .
  • control timings of the first CTAT circuit switch S CTAT1 , the first PTAT circuit switch S PTAT1 , and the second PTAT circuit switch S PTAT2 are the same.
  • control timings of the second CTAT circuit switch S CTAT2 , the third PTAT circuit switch S PTAT3 and the fourth PTAT circuit switch S PTAT4 are the same, and the ratio of the area of the second diode D2 to the area of the PTAT diode combination is set to 1:p, where p>1.
  • control timing of the second CTAT circuit switch S CTAT2 and the third PTAT circuit switch S PTAT3 is the same, the area of the second diode D2 is equal to the area of the PTAT diode combination, the starting time of closing of the third PTAT circuit switch S PTAT3 and the fourth PTAT circuit switch S PTAT4 is the same, and the ratio of the closing time is 1:p, p>1.
  • the analog-to-digital converter is a delta-sigma analog-to-digital converter
  • the delta-sigma analog-to-digital converter includes a delta-sigma modulator
  • the delta-sigma modulator includes the capacitor digital-to-analog converter and a first-stage integrator
  • the capacitor digital-to-analog converter generates a CTAT voltage V D and a PTAT voltage ⁇ V D
  • the first-stage integrator includes an integration capacitor C INT
  • the control timing of the delta-sigma modulator includes: the input signal V IN implements signal sampling in the sampling period ⁇ 1, and implements signal transfer and integration in the integration period ⁇ 2; for the reference signal branch, the sampling period ⁇ 1 is divided into two parts: rst and ⁇ 3, wherein in the rst state, the first reference capacitor CREF1 and the second reference capacitor CREF2 are pre-charged to the power supply voltage; in the ⁇ 3 state, the second reference capacitor CREF2 is discharged through the first diode D1, and the first reference capacitor CREF1 is discharged through the second diode D2 and the PTAT diode combination, and the reference signal is sampled on the first reference capacitor CREF1 and the second reference capacitor CREF2 at the end of ⁇ 3 and ⁇ 1; in the integration phase ⁇ 2, the charges on the first reference capacitor CREF1 and the second reference capacitor CREF2 are transferred to the integration capacitor C INT
  • +/-V REF is generated according to the output 1-bit BS code stream for achieving balance with the input signal V IN , and the average value of the BS code stream is V IN /V REF .
  • the analog-to-digital converter is a charge-sharing successive approximation analog-to-digital converter, which includes an input capacitor CIN, the capacitor digital-to-analog converter and a comparator.
  • the capacitor analog-to-digital converter samples a temperature-independent reference signal on an N-bit first reference capacitor C REF1 and a second reference capacitor C REF2 during a sampling phase, and generates a feedback control signal proportional to the reference signal according to a comparator result during a comparison phase.
  • one end of the first CTAT circuit switch S CTAT1 of the CTAT circuit based on the capacitor biasing diode is further connected to a sixth CTAT circuit switch S CTAT6 , when the digital output signal is an N-bit digital output, N>1, the CTAT capacitor branch includes N second capacitor branches connected in parallel, the second capacitor branch includes a second reference capacitor C REF2 and a second reference switch S REF2 connected to the second reference capacitor C REF2 , and also includes a fourth reference switch S REF4 connected to the second reference capacitor C REF2 , the fourth reference switch S REF4 is connected to the MSB or the LSB;
  • one end of the first PTAT circuit switch S PTAT1 is further connected to a seventh PTAT circuit switch S PTAT7 .
  • One end of the second PTAT circuit switch S PTAT2 is connected to the seventh PTAT circuit switch S PTAT7 .
  • the first PTAT capacitor branch and the second PTAT capacitor branch both include N first capacitor branches connected in parallel.
  • the first capacitor branch includes a first reference capacitor C REF1 and a first reference switch S REF1 connected to the first reference capacitor C REF1 , and also includes a third reference switch S REF3 connected to the first reference capacitor C REF1 .
  • the third reference switch S REF3 is connected to the MSB or the LSB.
  • the second PTAT capacitor branch also includes an eighth PTAT circuit switch S PTAT8 .
  • One end of the eighth PTAT circuit switch S PTAT8 is connected to the N first capacitor branches connected in parallel, and the other end of the eighth PTAT circuit switch S PTAT8 is grounded.
  • One end of the eighth PTAT circuit switch S PTAT8 is also connected to the sixth CTAT circuit switch S CTAT6 .
  • control timing of the charge sharing successive approximation analog-to-digital converter includes: the input signal is sampled and held on the input capacitor CIN, the reference voltage of the reference signal is held on the first reference capacitor C REF1 and the second reference capacitor C REF2 ; the differential input signals INP and INN are sampled and held on the input capacitor CIN when the sampling phase Fs is high, and for the reference signal branch, the first reference capacitor C REF1 is connected to the circuit through the first reference switch S REF1 and the third reference switch S REF3 in the sampling phase Fs, and the second reference capacitor C REF2 is connected to the circuit through the second reference switch S REF2 and the fourth reference switch S REF4 in the sampling phase Fs to generate a reference signal.
  • the sampling phase Fs can be divided into two parts: the ⁇ 1 phase and the ⁇ 2 phase, the ⁇ 1 phase realizes the generation of the PTAT voltage signal ⁇ V D which is positively correlated with the temperature and the CTAT voltage signal V D which is negatively correlated with the temperature; the ⁇ 2 phase realizes the proportional addition of the PTAT voltage signal ⁇ V D and the CTAT voltage signal V D to obtain a reference signal ⁇ V D +V D which is independent of the temperature.
  • the ⁇ 1 phase is further divided into two sub-phases: rst and ⁇ d/ ⁇ d1,2.
  • the first reference capacitor CREF1 and the second reference capacitor CREF2 are precharged to the power supply voltage VDD; in the ⁇ d state, the second reference capacitor CREF2 is discharged through the first diode D1, and in the ⁇ d1 and ⁇ d2 states, the first reference capacitor CREF1 is discharged through the combination of the second diode D2 and the third diode D3.
  • the PTAT voltage signal ⁇ V D and the CTAT voltage signal V D are sampled on the first reference capacitor CREF1 and the second reference capacitor CREF2 respectively; in the phase ⁇ 2, the eighth PTAT circuit switch S PTAT8 is opened, the sixth CTAT circuit switch S PTAT6 and the seventh PTAT circuit switch S PTAT7 are closed, so as to realize the addition of the PTAT voltage signal ⁇ V D and the CTAT voltage signal V D , and generate a reference signal independent of temperature on the first reference capacitor CREF1 and the second reference capacitor CREF2 .
  • the comparison quantization phase ⁇ SAR is entered.
  • the first reference capacitor C REF1 , the second reference capacitor C REF2 and the input capacitor CIN share charges to obtain the comparator input voltage.
  • the result obtained by the comparator comparison is used to control the working state of the next capacitance digital-to-analog converter; multiple successive approximation comparisons are performed to obtain the final converted output signal.
  • the analog-to-digital converter is a pipeline analog-to-digital converter
  • the pipeline structure analog-to-digital converter includes conversion modules connected in series step by step, and each conversion module includes the sampling and holding circuit and the capacitor digital-to-analog converter, the sampling and holding circuit samples and holds the analog input signal to obtain a first signal; the capacitor digital-to-analog converter generates a reference signal, and generates a second signal proportional to the reference signal based on the feedback digital output signal; the first signal and the second signal are subtracted to obtain an error signal.
  • a second aspect discloses a calibration method for an analog-to-digital converter with integrated reference voltage generation, which is applied to the above-mentioned analog-to-digital converter with integrated reference voltage generation, and is characterized by comprising:
  • Step 1 inputting an analog input signal into the analog-to-digital converter generated by the integrated reference voltage to obtain a digital output signal;
  • Step 2 subtracting the digital output signal from the ideal value to obtain a difference value
  • Step 3 adjusting the reference capacitance or the discharge time of the capacitance digital-to-analog converter according to the difference, so as to calibrate the digital output signal.
  • the ideal value in step 2 is the ratio of the analog input signal value to the desired designed reference signal value.
  • step 3 includes:
  • the first reference capacitor C REF1 or the second reference capacitor C REF2 is increased until the difference is zero;
  • the first reference capacitor C REF1 or the second reference capacitor C REF2 is reduced until the difference is zero.
  • step 3 includes:
  • the analog-to-digital converter proposed in this application has a high-precision reference source inside, that is, the reference signal is directly sampled in the capacitor digital-to-analog converter of the analog-to-digital converter, without the need for an additional reference signal generation circuit and reference signal driver, thereby fundamentally solving the shortcomings of the traditional architecture such as power consumption, area, and large errors.
  • the analog-to-digital converter can be used for various switched capacitor ADCs, such as delta-sigma ADC, SAR ADC, and Pipelined ADC.
  • a calibration method for the ADC with integrated reference voltage generation is also proposed.
  • the output of the analog-to-digital converter is measured by inputting a voltage, and the capacitance of the analog-to-digital converter is calibrated according to the output to achieve output calibration of the digital-to-analog converter.
  • FIG1 is a schematic diagram of a traditional ADC architecture.
  • FIG. 2 is a schematic diagram of an analog-to-digital converter architecture provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of the CBD circuit structure and working principle.
  • FIG. 4 is a schematic diagram of a circuit structure for generating PTAT and CTAT voltages by CBD.
  • FIG5 is a schematic diagram of a CDAC architecture based on the CBD principle in an analog-to-digital converter provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of a delta-sigma modulator circuit of an integrated reference voltage generating circuit provided in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a charge-sharing SAR ADC circuit with an integrated reference voltage generating circuit provided in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of the Pipelined ADC circuit including CBD CDAC provided in an embodiment of the present application.
  • Figure 1 shows the traditional switched capacitor analog-to-digital converter architecture and its peripheral modules, which mainly include an analog-to-digital converter ADC, a reference signal generation circuit, and a reference signal driver.
  • the input signal VIN is passed through the sample-and-hold circuit S&H and then the difference is obtained by the feedback reference signal to obtain the error signal, which is then passed through the loop filter and quantizer to obtain the digital output.
  • the digital output is also used for feedback control of the digital-to-analog converter (DAC), and is combined with the external input reference signal VREF to generate a feedback reference signal.
  • DAC digital-to-analog converter
  • the inventor of the present invention has found that in this traditional architecture, the ADC and the reference signal generating circuit and the reference signal driver need to be designed separately. Even if each module is well optimized, the combination often cannot achieve the optimal overall signal of the system. In particular, in order to drive the ADC, the reference signal driver requires a large power consumption and area, and also introduces additional errors, such as DC offset, noise, etc. In system applications, in order to achieve high precision, each module needs to be calibrated separately, and the calibration method is different, which further increases the system cost. For example, to calibrate the reference signal, an additional pin is required, and the reference signal output is measured and calibrated by a high-precision multimeter.
  • the capacitive digital to analog converter (CDAC) of the analog-to-digital converter with integrated reference voltage generation directly has a reference signal generation function, so that no additional reference signal generating circuit and reference signal driving circuit are required.
  • the area and power consumption of the analog-to-digital converter with integrated reference voltage generation are greatly reduced, and possible sources of errors are reduced.
  • the calibration of the analog-to-digital converter architecture provided in the embodiment of the present application only requires one calibration, that is, given the input signal VIN, the ADC output is directly measured to achieve integrated calibration of the entire signal path.
  • the analog-to-digital converter for generating an integrated reference voltage includes a sampling and holding circuit S&H, a capacitor digital-to-analog converter CDAC and a quantizer, wherein the sampling and holding circuit S&H is used to sample and hold the analog input signal VIN to obtain a first signal; the capacitor digital-to-analog converter CDAC is used to generate a reference signal, and according to the feedback digital output signal, a second signal that is proportional to the reference signal is generated, for example, the second signal is the product of the reference signal and the feedback digital output signal; the first signal and the second signal are subtracted to obtain an error signal; the quantizer is used to digitize the error signal to obtain a digital output signal.
  • the sampling and holding circuit S&H is used to sample and hold the analog input signal VIN to obtain a first signal
  • the capacitor digital-to-analog converter CDAC is used to generate a reference signal, and according to the feedback digital output signal, a second signal that is proportional to the reference signal is generated, for example, the second
  • the digital output signal supports N-bit digital output, where N ⁇ 1.
  • N N ⁇ 1
  • analog-to-digital converters such as delta-sigma analog-to-digital converters
  • a loop filter can be added before the quantizer, and the loop filter is used for noise shaping to improve resolution.
  • the capacitor digital-to-analog converter includes a CTAT (complementary to absolute temperature) circuit based on a capacitor bias diode and a PTAT (proportional to absolute temperature) circuit based on a capacitor bias diode.
  • the CTAT circuit based on a capacitor bias diode and the PTAT circuit based on a capacitor bias diode jointly generate the reference signal, and the reference signal is independent of temperature.
  • the CTAT circuit based on the capacitor bias diode generates a CTAT voltage V D that decreases as the temperature increases
  • the PTAT circuit based on the capacitor bias diode generates a PTAT voltage ⁇ V D that increases as the temperature increases.
  • the CTAT voltage V D and the PTAT voltage ⁇ V D are combined and added to generate the reference
  • the value of the proportional factor ⁇ makes the reference voltage V REF independent of temperature.
  • the capacitor-biased diode-based CTAT circuit includes a first CTAT circuit switch S CTAT1 , a CTAT diode branch, and a CTAT capacitor branch, one end of the first CTAT circuit switch S CTAT1 is respectively connected to one end of the CTAT diode branch and one end of the CTAT capacitor branch, the other end of the CTAT diode branch and the other end of the CTAT capacitor branch are both grounded; the other end of the first CTAT circuit switch S CTAT1 is connected to a power supply.
  • the first CTAT circuit switch S CTAT1 can be implemented using a common PMOS switch.
  • the CTAT diode branch includes a first diode D1 and a second CTAT circuit switch S CTAT2 connected to the first diode D1.
  • the first diode D1 can use a P+/Nwell diode or a Pwell/N+ diode.
  • the second CTAT circuit switch S CTAT2 can use a switch with a gate voltage bootstrap switch or a switch with a dummy tube.
  • the first diode D1 in the CTAT diode branch can be replaced by a diode-connected transistor (short-circuiting the base and collector of the transistor) or other devices such as DTMOST (dynamic threshold MOS transistor).
  • the transistor can be PNP or NPN, and short-circuiting the base and collector to form an equivalent diode can achieve better diode performance.
  • the CTAT capacitor branch when the digital output signal is a 1-bit digital output, the CTAT capacitor branch includes a second reference capacitor C REF2 .
  • the second reference capacitor C REF2 can use a MIM (Metal-Insulator-Metal) capacitor or a MOM (Metal-Oxide-Metal) capacitor.
  • the CTAT capacitor branch includes N parallel second capacitor branches
  • the second capacitor branch includes a second reference capacitor C REF2 and a second reference switch S REF2 connected to the second reference capacitor C REF2 , that is, the second reference capacitor C REF2 can be split into N-bit for digital control as needed to form an N-bit capacitor digital-to-analog converter.
  • the second reference capacitor C REF2 can use a MIM capacitor or a MOM capacitor
  • the second reference switch S REF2 can use an ordinary NMOS switch.
  • the capacitor-biased diode-based PTAT circuit includes a first capacitor-biased diode circuit and a second capacitor-biased diode circuit, and the voltage difference generated by the two circuits is the PTAT voltage ⁇ V D .
  • the first capacitor bias diode circuit includes a first PTAT circuit switch S PTAT1 , a first PTAT diode branch and a first PTAT capacitor branch, one end of the first PTAT circuit switch S PTAT1 is respectively connected to one end of the first PTAT diode branch and one end of the first PTAT capacitor branch, the other end of the first PTAT diode branch and the other end of the first PTAT capacitor branch are both grounded; the other end of the first PTAT circuit switch S PTAT1 is connected to a power supply.
  • the first PTAT circuit switch S PTAT1 can be implemented using a common PMOS switch.
  • the second capacitor biasing diode circuit includes a second PTAT circuit switch S PTAT2 , a second PTAT diode branch, and a second PTAT capacitor branch.
  • One end of the second PTAT circuit switch S PTAT2 is respectively connected to one end of the second PTAT diode branch and one end of the second PTAT capacitor branch, and the other end of the second PTAT diode branch and the other end of the second PTAT capacitor branch are both grounded.
  • the other end of the second PTAT circuit switch S PTAT2 is connected to a power supply.
  • the second PTAT circuit switch S PTAT2 can be implemented using a common PMOS switch.
  • the first PTAT diode branch includes a second diode D2 and a third PTAT circuit switch S PTAT3 connected to the second diode D2.
  • the second diode D2 can use a P+/Nwell diode or a Pwell/N+ diode.
  • the third PTAT circuit switch S PTAT3 can use a switch with a gate voltage bootstrap switch or a switch with a dummy tube.
  • the second PTAT diode branch includes a fourth PTAT circuit switch S PTAT4 and a PTAT diode combination connected to the fourth PTAT circuit switch S PTAT4 , and the PTAT diode combination includes a plurality of third diodes D3 connected in parallel.
  • the fourth PTAT circuit switch S PTAT4 can use a switch with a gate voltage bootstrap switch or a switch with a dummy tube
  • the third diode D3 can use a P+/Nwell diode or a Pwell/N+ diode.
  • the second diode D2 in the first PTAT diode branch and the third diode D3 in the PTAT diode combination can be replaced by a diode-connected transistor (short-circuiting the base and collector of the transistor) or other devices such as DTMOST.
  • the transistor can be PNP or NPN, and short-circuiting the base and collector to form an equivalent diode can achieve better diode performance.
  • the first PTAT capacitor branch and the second PTAT capacitor branch each include a first reference capacitor C REF1 .
  • the first reference capacitor C REF1 can use a MIM capacitor or a MOM capacitor and needs to be of the same type as the second reference capacitor C REF2 .
  • the digital output signal is an N-bit digital output, N>1, the first PTAT capacitor branch and the second PTAT capacitor branch each include N first capacitor branches connected in parallel, the first capacitor branch includes a first reference capacitor C REF1 and a first reference switch S REF1 connected to the first reference capacitor C REF1 , That is, the first reference capacitor C REF1 can be split into N-bit for digital control as needed to form an N-bit capacitor digital-to-analog converter.
  • the first reference capacitor C REF1 can use a MIM capacitor or a MOM capacitor, which needs to be the same type as the second reference capacitor C REF2 .
  • the first reference switch S REF1 can use an ordinary NMOS switch.
  • the second reference capacitor C REF2 is first pre-charged to the power supply voltage V DD through the first CTAT circuit switch S CTAT1 , and then the first CTAT circuit switch S CTAT1 is disconnected, and the second CTAT circuit switch S CTAT2 is closed, and the second reference capacitor C REF2 is discharged through the first diode D1; the residual voltage on the capacitor decreases with time, and after a period of time (nanosecond level), the residual voltage on the capacitor has nothing to do with its initial voltage, but is only determined by the diode characteristics. If the discharge time is fixed, the residual voltage on the second reference capacitor C REF2 decreases as the temperature increases, and the residual voltage is the CTAT voltage V D , and the expression of V D is as follows:
  • V D VT ( VT * C REF2 /t/Is)
  • T represents the current temperature
  • k represents the Boltzmann constant
  • q represents the charge constant
  • t represents the duration of closing the second CTAT circuit switch SCTAT2
  • Is represents the saturation current of the diode or transistor.
  • the diode voltage (Diode Voltage) is also the CTAT voltage VD , and the CTAT voltage VD decreases with time, and as the temperature increases, the CTAT voltage VD decreases.
  • the first reference capacitor C REF1 of the first capacitor biased diode circuit is first pre-charged to the power supply voltage V DD through the first PTAT circuit switch S PTAT1 , and then the first PTAT circuit switch S PTAT1 is opened, and the third PTAT circuit switch S PTAT3 is closed, and the first reference capacitor C REF1 of the first capacitor biased diode circuit is discharged through the second diode D2 to obtain a first residual voltage V D1 .
  • the first reference capacitor C REF1 of the second capacitor biased diode circuit is first pre-charged to the power supply voltage V DD through the second PTAT circuit switch S PTAT2 , and then the second PTAT circuit switch S PTAT2 is opened, and the fourth PTAT circuit switch S PTAT4 is closed, and the first reference capacitor C REF1 of the second capacitor biased diode circuit is discharged through the PTAT diode combination to obtain a second residual voltage V D2 .
  • the voltage difference V D1 -V D2 between the first residual voltage V D1 and the second residual voltage V D2 increases as the temperature increases.
  • the voltage difference is a PTAT voltage ⁇ V D .
  • the expression of ⁇ V D is as follows:
  • p represents the ratio of the area of the second diode D2 to the area of the PTAT diode combination, or the ratio of the closing durations of the third PTAT circuit switch S PTAT3 and the fourth PTAT circuit switch S PTAT4 when the closing start time is the same.
  • control timings of the first CTAT circuit switch S CTAT1 , the first PTAT circuit switch S PTAT1 , and the second PTAT circuit switch S PTAT2 are the same.
  • control timing of the second CTAT circuit switch S CTAT2 , the third PTAT circuit switch S PTAT3 and the fourth PTAT circuit switch S PTAT4 is the same, and the area ratio of the second diode D2 to the area ratio of the PTAT diode combination is set to 1:p, where p>1.
  • the third diode D3 in the PTAT diode combination can be the same as the second diode D2, and the PTAT diode combination includes p third diodes D3, or the third diode D3 can be different from the second diode D2, as long as the area ratio of the second diode D2 to the area ratio of the PTAT diode combination is set to 1:p, which does not affect the implementation of the embodiment of the present application.
  • a current density proportional relationship is formed, thereby generating a PTAT voltage ⁇ V D that increases with increasing temperature.
  • control timing of the second CTAT circuit switch S CTAT2 and the third PTAT circuit switch S PTAT3 is the same, the area of the second diode D2 is equal to the area of the PTAT diode combination, the start time of closing the third PTAT circuit switch S PTAT3 and the fourth PTAT circuit switch S PTAT4 is the same, and the ratio of the closing time is 1:p, p>1.
  • the PTAT diode combination can include a third diode D3, the third diode D3 is the same as the second diode D2, or the PTAT diode combination can include multiple third diodes D3, as long as the area of the second diode D2 is equal to the area of the PTAT diode combination, which does not affect the implementation of the embodiment of the present application.
  • the closing time of the third PTAT circuit switch S PTAT3 and the fourth PTAT circuit switch S PTAT4 that is, by controlling the discharge time of the second diode D2 and the PTAT diode combination
  • the current density flowing through the second diode D2 and the PTAT diode combination is controlled, thereby generating a PTAT voltage ⁇ V D that increases with increasing temperature.
  • the embodiments of the present application can be applied to various existing switched capacitor ADC architectures, thereby removing the additional reference
  • the signal generating circuit and the reference signal driving circuit greatly simplify the system architecture.
  • the CTAT circuit based on capacitor biased diode includes a first CTAT circuit switch S CTAT1 , a CTAT diode branch and a CTAT capacitor branch.
  • One end of the first CTAT circuit switch S CTAT1 is respectively connected to one end of the CTAT diode branch and one end of the CTAT capacitor branch.
  • One end of the first CTAT circuit switch S CTAT1 is also connected to a third CTAT circuit switch S CTAT3 .
  • the other end of the CTAT diode branch is grounded.
  • the other end of the CTAT capacitor branch is connected to the input end of the first stage integrator.
  • the input end of the first stage integrator includes a positive end V GP and a negative end V GN .
  • the other end of the first CTAT circuit switch S CTAT1 is connected to a power supply.
  • the CTAT diode branch includes a first diode D1 and a second CTAT circuit switch S CTAT2 connected to the first diode D1.
  • the CTAT capacitor branch includes a second reference capacitor C REF2 .
  • another group of capacitors is required to form a fully differential structure, which is equivalent to sampling 0V (ground).
  • the CTAT circuit based on the capacitor bias diode also includes a branch consisting of a second reference capacitor C REF2 and a fourth CTAT circuit switch S CTAT4 .
  • One end of the second reference capacitor C REF2 is connected to the input end of the first-stage integrator, and the other end of the second reference capacitor C REF2 is connected to one end of the fourth CTAT circuit switch S CTAT4 .
  • the other end of the fourth CTAT circuit switch S CTAT4 is grounded.
  • the other end of the second reference capacitor C REF2 and one end of the fourth CTAT circuit switch S CTAT4 are also connected to a fifth CTAT circuit switch S CTAT5 .
  • the fifth CTAT circuit switch S CTAT5 is connected to the third CTAT circuit switch S CTAT3 and is connected to an AC ground, which is generally a common mode level.
  • the CTAT circuit based on the capacitor biased diode selects to input +V REF or -V REF , that is, selects to connect the positive terminal V GP or the negative terminal V GN of the input terminal of the first-stage integrator.
  • the PTAT circuit based on capacitor biased diode includes a first capacitor biased diode circuit and a second capacitor biased diode circuit
  • the first capacitor biased diode circuit includes a first PTAT circuit switch S PTAT1 , a first PTAT diode branch and a first PTAT capacitor branch
  • one end of the first PTAT circuit switch S PTAT1 is respectively connected to one end of the first PTAT diode branch and one end of the first PTAT capacitor branch
  • one end of the first PTAT circuit switch S PTAT1 is also connected to a fifth PTAT circuit switch S PTAT5 , the other end of the first PTAT diode branch is grounded, and the other end of the first PTAT capacitor branch is connected to the input end of the first-stage integrator; the other end of the first PTAT circuit switch S PTAT1 is connected to a power supply.
  • the second capacitor bias diode circuit includes a second PTAT circuit switch S PTAT2 , a second PTAT diode branch and a second PTAT capacitor branch, one end of the second PTAT circuit switch S PTAT2 is respectively connected to one end of the second PTAT diode branch and one end of the second PTAT capacitor branch, one end of the second PTAT circuit switch S PTAT2 is also connected to a sixth PTAT circuit switch S PTAT6 , the other end of the second PTAT diode branch is grounded, and the other end of the second PTAT capacitor branch is connected to the input end of the first stage integrator; the other end of the second PTAT circuit switch S PTAT2 is connected to the power supply.
  • the fifth PTAT circuit switch S PTAT5 and the sixth PTAT circuit switch S PTAT6 are connected and commonly connected to an AC ground, which is generally a common mode level.
  • the first PTAT diode branch includes a second diode D2 and a third PTAT circuit switch S PTAT3 connected to the second diode D2.
  • the second PTAT diode branch includes a fourth PTAT circuit switch S PTAT4 and a PTAT diode combination connected to the fourth PTAT circuit switch S PTAT4 , wherein the PTAT diode combination includes a plurality of third diodes D3 connected in parallel.
  • the first PTAT capacitor branch and the second PTAT capacitor branch each include a first reference capacitor C REF1 .
  • the first-stage integrator includes an integrating capacitor C INT
  • the control timing of the delta-sigma modulator includes: the input signal V IN is sampled in the sampling period ⁇ 1, and the signal is transferred and integrated in the integration period ⁇ 2; for the reference signal branch, the sampling period ⁇ 1 is divided into two parts: rst and ⁇ 3, wherein in the rst state, the first reference capacitor CREF1 and the second reference capacitor CREF2 are pre-charged to the power supply voltage VDD; in the ⁇ 3 state, the second reference capacitor CREF2 is discharged through the first diode D1, and the first reference capacitor CREF1 is discharged through the second diode D2 and the PTAT diode combination, and the reference signal is sampled on the first reference capacitor CREF1 and the second reference capacitor CREF2 at the end of ⁇ 3 and ⁇ 1; in the integration phase ⁇ 2, the charges on the first reference capacitor CREF1 and the second reference capacitor CREF2 are transferred to the integrating capacitor C
  • the delta-sigma modulator outputs a 1-bit BS code stream
  • +/-V REF is selected and generated according to the output 1-bit BS code stream to achieve balance with the input signal V IN , and the average value of the BS code stream is V IN /V REF .
  • the analog-to-digital converter can also be a charge-sharing successive approximation analog-to-digital converter (SARADC, Successive Approximation Register ADC), the successive approximation analog-to-digital converter includes an input capacitor CIN, the capacitor digital-to-analog converter and a comparator.
  • the capacitor analog-to-digital converter uses the above-mentioned CBD principle to sample a temperature-independent reference signal on the N-bit first reference capacitor C REF1 and the second reference capacitor C REF2 during the sampling phase, and generates a feedback control signal proportional to the reference signal according to the comparator result during the comparison phase.
  • CBD Charge-sharing successive approximation analog-to-digital converter
  • the capacitor analog-to-digital converter uses the above-mentioned CBD principle to sample a temperature-independent reference signal on the N-bit first reference capacitor C REF1 and the second reference capacitor C REF2 during the sampling phase, and generates a feedback control signal proportional to the reference signal according to the comparat
  • the capacitance digital-to-analog converter comprises a CTAT circuit based on a capacitance bias diode and a PTAT circuit based on a capacitance bias diode.
  • the CTAT circuit based on a capacitance bias diode generates a CTAT voltage V D which decreases as the temperature increases
  • the PTAT circuit based on a capacitance bias diode generates a PTAT voltage ⁇ V D which increases as the temperature increases.
  • the capacitor-biased diode-based CTAT circuit includes a first CTAT circuit switch S CTAT1 , a CTAT diode branch and a CTAT capacitor branch, one end of the first CTAT circuit switch S CTAT1 is respectively connected to one end of the CTAT diode branch and one end of the CTAT capacitor branch, one end of the first CTAT circuit switch S CTAT1 is also connected to a sixth CTAT circuit switch S CTAT6 , the other end of the CTAT diode branch and the other end of the CTAT capacitor branch are both grounded; the other end of the first CTAT circuit switch S CTAT1 is connected to a power supply.
  • the CTAT diode branch includes a first diode D1 and a second CTAT circuit switch S CTAT2 connected to the first diode D1.
  • the CTAT capacitor branch includes N second capacitor branches connected in parallel
  • the second capacitor branch includes a second reference capacitor C REF2 and a second reference switch S REF2 connected to the second reference capacitor C REF2
  • the fourth reference switch S REF4 is connected to the MSB or the LSB.
  • the PTAT circuit based on capacitor biased diode includes a first capacitor biased diode circuit and a second capacitor biased diode circuit
  • the first capacitor biased diode circuit includes a first PTAT circuit switch S PTAT1 , a first PTAT diode branch and a first PTAT capacitor branch
  • one end of the first PTAT circuit switch S PTAT1 is respectively connected to one end of the first PTAT diode branch and one end of the first PTAT capacitor branch
  • one end of the first PTAT circuit switch S PTAT1 is also connected to a seventh PTAT circuit switch S PTAT7 , the other end of the first PTAT diode branch and the other end of the first PTAT capacitor branch are both grounded; the other end of the first PTAT circuit switch S PTAT1 is connected to a power supply.
  • the second capacitor biasing diode circuit includes a second PTAT circuit switch S PTAT2 , a second PTAT diode branch and a second PTAT capacitor branch, one end of the second PTAT circuit switch S PTAT2 is respectively connected to one end of the second PTAT diode branch and one end of the second PTAT capacitor branch, one end of the second PTAT circuit switch S PTAT2 is connected to the seventh PTAT circuit switch S PTAT7 , the other end of the second PTAT diode branch and the other end of the second PTAT capacitor branch are both grounded; the other end of the second PTAT circuit switch S PTAT2 is connected to the power supply.
  • the first PTAT diode branch includes a second diode D2 and a third PTAT circuit switch S PTAT3 connected to the second diode D2.
  • the second PTAT diode branch includes a fourth PTAT circuit switch S PTAT4 and a PTAT diode combination connected to the fourth PTAT circuit switch S PTAT4 , wherein the PTAT diode combination includes a plurality of third diodes D3 connected in parallel.
  • the first PTAT capacitor branch and the second PTAT capacitor branch each include N first capacitor branches connected in parallel, wherein the first capacitor branch includes a first reference capacitor C REF1 and a first reference switch S REF1 connected to the first reference capacitor C REF1 , and further includes a third reference switch S REF3 connected to the first reference capacitor C REF1 , wherein the third reference switch S REF3 is connected to the MSB or the LSB.
  • the second PTAT capacitor branch further includes an eighth PTAT circuit switch S PTAT8 , one end of which is connected to the N first capacitor branches connected in parallel, and the other end of which is grounded; one end of the eighth PTAT circuit switch S PTAT8 is also connected to the sixth CTAT circuit switch S CTAT6 .
  • the sixth CTAT circuit switch S CTAT6 , the seventh PTAT circuit switch S PTAT7 and the eighth PTAT circuit switch S PTAT8 are used to implement the addition of the CTAT voltage V D and the PTAT voltage ⁇ V D .
  • the control timing of the charge sharing successive approximation analog-to-digital converter includes:
  • the input signal is sampled and held on the input capacitor CIN, and the reference voltage of the reference signal is held on the first reference capacitor C REF1 and the second reference capacitor C REF2 ; the differential input signals INP and INN are sampled and held on the input capacitor CIN when the sampling phase Fs is high.
  • the first reference capacitor C REF1 is connected to the circuit through the first reference switch S REF1 and the third reference switch S REF3 in the sampling phase Fs
  • the second reference capacitor C REF2 is connected to the circuit through the second reference switch S REF2 and the fourth reference switch S REF4 in the sampling phase Fs to generate a reference signal.
  • the sampling phase Fs can be divided into two parts: the ⁇ 1 phase and the ⁇ 2 phase.
  • the ⁇ 1 phase realizes the generation of the PTAT voltage signal ⁇ V D that is positively correlated with the temperature and the CTAT voltage signal V D that is negatively correlated with the temperature; the ⁇ 2 phase realizes the proportional addition of the PTAT voltage signal ⁇ V D and the CTAT voltage signal V D to obtain a reference signal ⁇ V D +V D that is independent of the temperature.
  • the ⁇ 1 phase is further split into two sub-phases: rst and ⁇ d/ ⁇ d1,2.
  • the first reference capacitor C REF1 and the second reference capacitor C REF2 are pre-charged to the power supply voltage VDD; in the ⁇ d state, the second reference capacitor C REF2 is discharged through the first diode D1, and in the ⁇ d1 and ⁇ d2 states, the first reference capacitor C REF1 is discharged through the combination of the second diode D2 and the third diode D3, and at the end of ⁇ 1, ⁇ d and ⁇ d1,2, the PTAT voltage signal ⁇ V D and the CTAT voltage signal V D are sampled on the first reference capacitor C REF1 and the second reference capacitor C REF2 respectively; in the phase ⁇ 2, the eighth PTAT circuit switch S PTAT8 is opened, the sixth CTAT circuit switch S PTAT6 and the seventh PTAT circuit switch S PTAT7 are closed, so that the PTAT voltage signal ⁇ V D and the CTAT voltage signal V D are added, and a reference signal independent of temperature is generated on the first reference capacitor C REF1 and the second reference capacitor
  • the comparison quantization phase ⁇ SAR is entered.
  • the first reference capacitor C REF1 , the second reference capacitor C REF2 and the input capacitor CIN share charges to obtain the comparator input voltage.
  • the result obtained by the comparator comparison is used to control the working state of the next capacitance digital-to-analog converter; multiple successive approximation comparisons are performed to obtain the final converted output signal.
  • the analog-to-digital converter can also be a pipelined analog-to-digital converter (pipelined ADC).
  • the pipelined analog-to-digital converter includes conversion modules connected in series step by step. Each conversion module includes the sampling and holding circuit and the capacitor digital-to-analog converter.
  • the sampling and holding circuit samples and holds the analog input signal V IN to obtain a first signal; the capacitor digital-to-analog converter generates a reference signal, and generates a second signal proportional to the reference signal according to the feedback digital output signal; the first signal and the second signal are subtracted to obtain an error signal.
  • the pipelined ADC has R stages, and each stage realizes N bit conversion.
  • the input of the previous stage is first sampled (S/H), and at the same time, quantization is realized through the sub-N-bit ADC.
  • the quantized digital signal is converted into an analog signal through the N-bit sub-CDAC, and is subtracted from the input signal, and sent to the next stage after amplification.
  • the sub-CDAC can be implemented by using the CDAC architecture based on the CBD principle of FIG5.
  • the N-bit sub-CDAC includes a CTAT circuit based on a capacitor bias diode and a PTAT circuit based on a capacitor bias diode.
  • the CTAT circuit based on a capacitor bias diode and the PTAT circuit based on a capacitor bias diode jointly generate the reference signal, and the reference signal is independent of temperature.
  • the CTAT circuit based on a capacitor bias diode generates a CTAT voltage V D that decreases as the temperature increases
  • the PTAT circuit based on a capacitor bias diode generates a PTAT voltage ⁇ V D that increases as the temperature increases.
  • the CTAT circuit based on capacitor biased diode includes a first CTAT circuit switch S CTAT1 , a CTAT diode branch and a CTAT capacitor branch, one end of the first CTAT circuit switch S CTAT1 is respectively connected to one end of the CTAT diode branch and one end of the CTAT capacitor branch, and the other end of the CTAT diode branch and the other end of the CTAT capacitor branch are both grounded; the other end of the first CTAT circuit switch S CTAT1 is connected to a power supply.
  • the CTAT diode branch includes a first diode D1 and a second CTAT circuit switch S CTAT2 connected to the first diode D1.
  • the CTAT capacitor branch includes N parallel second capacitor branches, and the second capacitor branch includes a second reference capacitor C REF2 and a second reference switch S REF2 connected to the second reference capacitor C REF2 .
  • the PTAT circuit based on capacitor bias diode includes a first capacitor bias diode circuit and a second capacitor bias diode circuit, wherein the first capacitor bias diode circuit includes a first PTAT circuit switch S PTAT1 , a first PTAT diode branch and a first PTAT capacitor branch, one end of the first PTAT circuit switch S PTAT1 is respectively connected to one end of the first PTAT diode branch and one end of the first PTAT capacitor branch, the other end of the first PTAT diode branch and the other end of the first PTAT capacitor branch are both grounded; the other end of the first PTAT circuit switch S PTAT1 is connected to a power supply.
  • the first capacitor bias diode circuit includes a first PTAT circuit switch S PTAT1 , a first PTAT diode branch and a first PTAT capacitor branch, one end of the first PTAT circuit switch S PTAT1 is respectively connected to one end of the first PTAT diode branch and
  • the second capacitor bias diode circuit includes a second PTAT circuit switch S PTAT2 , a second PTAT diode branch and a second PTAT capacitor branch, one end of the second PTAT circuit switch S PTAT2 is respectively connected to one end of the second PTAT diode branch and one end of the second PTAT capacitor branch, the other end of the second PTAT diode branch and the other end of the second PTAT capacitor branch are both grounded; the other end of the second PTAT circuit switch S PTAT2 is connected to a power supply.
  • the first PTAT diode branch includes a second diode D2 and a third PTAT circuit switch S PTAT3 connected to the second diode D2.
  • the second PTAT diode branch includes a fourth PTAT circuit switch S PTAT4 and a PTAT diode combination connected to the fourth PTAT circuit switch S PTAT4 , wherein the PTAT diode combination includes a plurality of third diodes D3 connected in parallel.
  • the first PTAT capacitor branch and the second PTAT capacitor branch each include N first capacitor branches connected in parallel, wherein the first capacitor branch includes a first reference capacitor C REF1 and a first reference switch S REF1 connected to the first reference capacitor C REF1 .
  • the embodiment of the present application provides an analog-to-digital converter calibration method with integrated reference voltage generation, which is applied to the above-mentioned analog-to-digital converter with integrated reference voltage generation, and is specifically implemented as follows:
  • Step 1 inputting an analog input signal into the analog-to-digital converter generated by the integrated reference voltage to obtain a digital output signal;
  • Step 2 subtracting the digital output signal from the ideal value to obtain a difference value
  • Step 3 adjusting the reference capacitance or the discharge time of the capacitance digital-to-analog converter according to the difference, so as to calibrate the digital output signal.
  • the ideal value in step 2 is the ratio of the analog input signal value to the desired designed reference signal value.
  • adjusting the reference capacitance of the capacitance digital-to-analog converter according to the difference is adjusting the first reference capacitance C REF1 or the second reference capacitance C REF2 reference capacitance, which specifically includes:
  • the first reference capacitor C REF1 or the second reference capacitor C REF2 is increased until the difference is zero;
  • the first reference capacitor C REF1 or the second reference capacitor C REF2 is reduced until the difference is zero.
  • adjusting the discharge time of the capacitor digital-to-analog converter according to the difference is adjusting the discharge time of closing the third PTAT circuit switch S PTAT3 and the fourth PTAT circuit switch S PTAT4 , which specifically includes:
  • the discharge time t can be made adjustable, such as t in the waveform diagram of Figure 4.
  • the specific implementation can be to obtain the delay t through external high-frequency clock counting. It can also be obtained through on-chip RC delay. To make it adjustable, you only need to adjust the count number or RC value to control the time t.
  • the above scheme can calibrate all system errors such as ADC and reference signal through a one-time calibration, thus eliminating the need for additional reference signal or driver calibration.
  • the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium can store a computer program, and when the computer program is executed by the data processing unit, the invention content of the analog-to-digital converter calibration method with integrated reference voltage generation provided by the present invention and some or all of the steps in each embodiment can be run.
  • the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.
  • the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on such an understanding, the technical solutions in the embodiments of the present invention are essentially or partly contributed to the prior art can be embodied in the form of a computer program, i.e., a software product, which can be stored in a storage medium and includes several instructions for enabling a device including a data processing unit (which can be a personal computer, a server, a single-chip microcomputer, a MUU or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.
  • a data processing unit which can be a personal computer, a server, a single-chip microcomputer, a MUU or a network device, etc.
  • the present invention provides an analog-to-digital converter and a calibration method for integrated reference voltage generation.

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Abstract

一种集成参考电压产生的模数转换器及校准方法，集成参考电压产生的模数转换器包括采样保持电路、电容数模转换器和量化器，采样保持电路用于对模拟输入信号进行采样保持，获得第一信号；电容数模转换器用于产生参考信号，根据反馈的数字输出信号产生和参考信号等比例的第二信号；第一信号和第二信号做差获得误差信号；量化器用于对误差信号进行数字化，获得数字输出信号。模数转换器内部自带高精度参考基准源，将参考信号直接在模数转换器的电容数模转换器内部产生，无需额外的参考信号产生电路和参考信号驱动器，解决传统架构的功耗、面积、误差大等缺点，只需一步校准即可实现输出校准，降低系统校正成本，实现高精度。

Description

一种集成参考电压产生的模数转换器及校准方法 技术领域
本发明属于模数转换技术领域，尤其涉及一种集成参考电压产生的模数转换器及校准方法。
背景技术
高精度传感器应用领域需要高精度的模数转换器(ADC，Analog to Digital Converter)实现输入信号采集，同时还需要不随温度、供电等环境变化的高精度基准源作为ADC的参考信号。此外，为了驱动ADC，还需要额外的参考信号驱动器。在传统设计中，参考信号产生模块、驱动器以及模数转换器往往分开设计，不可避免存在功耗大、面积大、误差大等缺点。为了实现高精度，各部件需要单独校准，增加了校正成本。
发明内容
发明目的：本发明所要解决的技术问题是针对现有技术的不足，提供一种集成参考电压产生的模数转换器及校准方法。
为了解决上述技术问题，第一方面公开了一种集成参考电压产生的模数转换器，包括采样保持电路、电容数模转换器和量化器，
所述采样保持电路，用于对模拟输入信号进行采样保持，获得第一信号；
所述电容数模转换器，用于产生参考信号，根据反馈的数字输出信号，产生和参考信号等比例的第二信号；第一信号和第二信号做差获得误差信号；
所述量化器，用于对误差信号进行数字化，获得数字输出信号。
可选的，在一些模数转换器中，量化器前可添加环路滤波器，环路滤波器用于噪声整形，提高分辨率。
进一步地，所述电容数模转换器包括基于电容偏置二极管的CTAT电路和基于电容偏置二极管的PTAT电路，所述基于电容偏置二极管的CTAT电路和基于电容偏置二极管的PTAT电路共同产生所述参考信号，且所述参考信号和温度无关。
进一步地，所述基于电容偏置二极管的CTAT电路产生随温度变高而变低的CTAT电压VD，所述基于电容偏置二极管的PTAT电路产生随温度变高而变高的PTAT电压ΔVD，将CTAT电压VD和PTAT电压ΔVD组合相加，产生所述参考信号的参考电压VREF，VREF＝αΔVD+VD，α为比例因子，比例因子α的取值使得所述参考电压VREF和温度无关。
进一步地，所述基于电容偏置二极管的CTAT电路包括第一CTAT电路开关SCTAT1、CTAT二极管支路和CTAT电容支路，所述第一CTAT电路开关SCTAT1的一端分别与CTAT二极管支路的一端和CTAT电容支路的一端连接，CTAT二极管支路的另一端和CTAT电容支路的另一端均接地；第一CTAT电路开关SCTAT1的另一端与电源连接。
进一步地，所述基于电容偏置二极管的PTAT电路包括第一电容偏置二极管电路和第二电容偏置二极管电路，所述第一电容偏置二极管电路包括第一PTAT电路开关SPTAT1、第一PTAT二极管支路和第一PTAT电容支路，所述第一PTAT电路开关SPTAT1的一端分别与第一PTAT二极管支路的一端和第一PTAT电容支路的一端连接，第一PTAT二极管支路的另一端和第一PTAT电容支路的另一端均接地；第一PTAT电路开关SPTAT1的另一端与电源连接；所述第二电容偏置二极管电路包括第二PTAT电路开关SPTAT2、第二PTAT二极管支路和第二PTAT电容支路，所述第二PTAT电路开关SPTAT2的一端分别与第二PTAT二极管支路的一端和第二PTAT电容支路的一端连接，第二PTAT二极管支路的另一端和第二PTAT电容支路的另一端均接地；第二PTAT电路开关SPTAT2的另一端与电源连接。
进一步地，所述CTAT二极管支路包括第一二极管D1和与第一二极管D1连接的第二CTAT电路开关SCTAT2。
进一步地，当所述数字输出信号为1位数字输出，所述CTAT电容支路包括第二参考电容CREF2。
进一步地，当所述数字输出信号为N位数字输出，N>1，所述CTAT电容支路包括N个并联的第二电容支路，所述第二电容支路包括第二参考电容CREF2和与第二参考电容CREF2连接的第二参考开关SREF2。
进一步地，所述第一PTAT二极管支路包括第二二极管D2和与第二二极管D2连接的第三PTAT电路开关SPTAT3。
进一步地，所述第二PTAT二极管支路包括第四PTAT电路开关SPTAT4和与第四PTAT电路开关SPTAT4连接的PTAT二极管组合，所述PTAT二极管组合包括多个并联的第三二极管D3。
进一步地，当所述数字输出信号为1位数字输出，所述第一PTAT电容支路和第二PTAT电容支路均包括第一参考电容CREF1。
进一步地，当所述数字输出信号为N位数字输出，N>1，所述第一PTAT电容支路和第二PTAT电容支路均包括N个并联的第一电容支路，所述第一电容支路包括第一参考电容CREF1和与第一参考电容CREF1连接的第一参考开关SREF1。
进一步地，第二参考电容CREF2先通过第一CTAT电路开关SCTAT1预充电到电源电压VDD，然后断开第一CTAT电路开关SCTAT1，闭合第二CTAT电路开关SCTAT2，第二参考电容CREF2通过第一二极管D1放电；若固定放电时长，第二参考电容CREF2上的残余电压随温度变高而变低，所述残余电压即为CTAT电压VD。
进一步地，第一电容偏置二极管电路的第一参考电容CREF1先通过第一PTAT电路开关SPTAT1预充电到电源电压VDD，然后断开第一PTAT电路开关SPTAT1，闭合第三PTAT电路开关SPTAT3，第一电容偏置二极管电路的第一参考电容CREF1通过第二二极管D2放电，获得第一残余电压VD1。
进一步地，第二电容偏置二极管电路的第一参考电容CREF1先通过第二PTAT电路开关SPTAT2预充电到电源电压VDD，然后断开第二PTAT电路开关SPTAT2，闭合第四PTAT电路开关SPTAT4，第二电容偏置二极管电路的第一参考电容CREF1通过PTAT二极管组合放电，获得第二残余电压VD2。
进一步地，第一残余电压VD1和第二残余电压VD2的电压差VD1-VD2随温度变高而变高，所述电压差为PTAT电压ΔVD。
进一步地，第一CTAT电路开关SCTAT1、第一PTAT电路开关SPTAT1和第二PTAT电路开关SPTAT2的控制时序相同。
进一步地，第二CTAT电路开关SCTAT2、第三PTAT电路开关SPTAT3和第四PTAT电路开关SPTAT4的控制时序相同，第二二极管D2的面积与PTAT二极管组合的面积比设置为1：p，p>1。
进一步地，第二CTAT电路开关SCTAT2和第三PTAT电路开关SPTAT3的控制时序相同，第二二极管D2的面积与PTAT二极管组合的面积相等，第三PTAT电路开关SPTAT3和第四PTAT电路开关SPTAT4闭合的起始时间相同，闭合时长之比为1：p，p>1。
进一步地，所述模数转换器为delta-sigma模数转换器，所述delta-sigma模数转换器包括delta-sigma调制器，所述delta-sigma调制器包括所述电容数模转换器和第一级积分器，电容数模转换器产生CTAT电压VD和PTAT电压ΔVD，CTAT电压VD和PTAT电压ΔVD通过第一级积分器实现相加组合，获得参考信号VREF＝αΔVD+VD，其中α＝CREF1/CREF2。
进一步地，所述第一级积分器包括积分电容CINT，delta-sigma调制器的控制时序包括：输入信号VIN在采样周期Φ1实现信号采样，在积分周期Φ2实现信号转移和积分；对于参考信号支路，采样周期Φ1拆分为两部分：rst和Φ3，其中rst状态下，第一参考电容CREF1和第二参考电容CREF2预充电到电源电压；在Φ3状态下，第二参考电容CREF2通过第一二极管D1放电，第一参考电容CREF1通过第二二极管D2和PTAT二极管组合放电，在Φ3和Φ1结束时将参考信号采样在第一参考电容CREF1和第二参考电容CREF2；在积分相位Φ2，第一参考电容CREF1和第二参考电容CREF2上的电荷被转移到积分电容CINT上。
进一步地，若delta-sigma调制器输出1比特BS码流，根据输出的1比特BS码流选择产生+/-VREF，用于和输入信号VIN实现平衡，BS码流平均值为VIN/VREF。
进一步地，所述模数转换器为电荷共享型逐次逼近型模数转换器，所述逐次逼近型模数转换器包括输入电容CIN、所述电容数模转换器和比较器，所述电容模数转换器在采样阶段将和温度无关的参考信号采样在N-bit第一参考电容CREF1和第二参考电容CREF2上，并在比较阶段根据比较器结果产生和参考信号等比例的反馈控制信号。
进一步地，所述电容数模转换器中，基于电容偏置二极管的CTAT电路的第一CTAT电路开关SCTAT1的一端还连接有第六CTAT电路开关SCTAT6，当所述数字输出信号为N位数字输出，N>1，CTAT电容支路包括N个并联的第二电容支路，所述第二电容支路包括第二参考电容CREF2和与第二参考电容CREF2连接的第二参考开关SREF2，还包括与第二参考电容CREF2连接的第四参考开关SREF4，第四参考开关SREF4与MSB或者LSB连接；
基于电容偏置二极管的PTAT电路中，第一PTAT电路开关SPTAT1的一端还连接有第七PTAT电路开关SPTAT7， 第二PTAT电路开关SPTAT2的一端与第七PTAT电路开关SPTAT7连接，所述第一PTAT电容支路和第二PTAT电容支路均包括N个并联的第一电容支路，所述第一电容支路包括第一参考电容CREF1和与第一参考电容CREF1连接的第一参考开关SREF1，还包括与第一参考电容CREF1连接的第三参考开关SREF3，第三参考开关SREF3与MSB或者LSB连接；所述第二PTAT电容支路还包括第八PTAT电路开关SPTAT8，所述第八PTAT电路开关SPTAT8的一端与N个并联的第一电容支路连接，第八PTAT电路开关SPTAT8的另一端接地；第八PTAT电路开关SPTAT8的一端还与第六CTAT电路开关SCTAT6连接。
进一步地，所述电荷共享型逐次逼近型模数转换器的控制时序包括：输入信号采样保持在输入电容CIN上，参考信号的参考电压保持在第一参考电容CREF1和第二参考电容CREF2上；差分输入信号INP和INN在采样相位Fs为高时实现信号采样保持在输入电容CIN上，对于参考信号支路，第一参考电容CREF1在采样相位Fs通过第一参考开关SREF1和第三参考开关SREF3接入电路，第二参考电容CREF2在采样相位Fs通过第二参考开关SREF2和第四参考开关SREF4接入电路，产生参考信号。其中采样相位Fs可拆分为两部分：Φ1相位和Φ2相位，Φ1相位实现与温度正相关的PTAT电压信号ΔVD及与温度负相关的CTAT电压信号VD的产生；Φ2相位实现PTAT电压信号ΔVD和CTAT电压信号VD按比例相加，得到和温度无关的参考信号αΔVD+VD。其中为产生PTAT电压信号ΔVD和CTAT电压信号VD，Φ1相位进一步拆分为两个子相位：rst和Φd/Φd1,2。在rst状态下，第一参考电容CREF1和第二参考电容CREF2预充电到电源电压VDD；在Φd状态下，第二参考电容CREF2通过第一二极管D1放电，在Φd1和Φd2状态下第一参考电容CREF1通过第二二极管D2和第三二极管D3组合放电，在Φ1、Φd和Φd1,2结束时将PTAT电压信号ΔVD和CTAT电压信号VD分别采样在第一参考电容CREF1和第二参考电容CREF2；在相位Φ2，第八PTAT电路开关SPTAT8断开，第六CTAT电路开关SPTAT6和第七PTAT电路开关SPTAT7闭合，实现PTAT电压信号ΔVD和CTAT电压信号VD相加，在第一参考电容CREF1和第二参考电容CREF2产生和温度无关的参考信号。
在采样相位Fs结束后，进入比较量化相位ΦSAR，通过逐次逼近的算法逻辑，第一参考电容CREF1、第二参考电容CREF2和输入电容CIN进行电荷分享，获得比较器输入电压，比较器比较获得的结果用于控制下一次电容数模转换器的工作状态；多次逐次逼近比较获得最终转换的输出信号。
进一步地，所述模数转换器为流水线模数转换器，所述流水线结构模数转换器包括逐级串联的转换模块，每级转换模块包括所述采样保持电路和所述电容数模转换器，采样保持电路对模拟输入信号进行采样保持，获得第一信号；电容数模转换器产生参考信号，根据反馈的数字输出信号，产生和参考信号等比例的第二信号；第一信号和第二信号做差获得误差信号。
第二方面公开了一种集成参考电压产生的模数转换器校准方法，应用于上述集成参考电压产生的模数转换器，其特征在于，包括：
步骤1，将模拟输入信号输入至所述的集成参考电压产生的模数转换器，获得数字输出信号；
步骤2，对所述数字输出信号和理想值做差，获得差值；
步骤3，根据差值调节所述电容数模转换器的参考电容或放电时长，从而校准数字输出信号。
进一步地，步骤2中理想值为模拟输入信号值和所希望设计的参考信号值的比值。
进一步地，步骤3包括：
当差值为正时，增大第一参考电容CREF1或第二参考电容CREF2，直至差值为零；
当差值为负时，减小第一参考电容CREF1或第二参考电容CREF2，直至差值为零。
进一步地，步骤3包括：
当差值为正时，减小第一参考电容CREF1或第二参考电容CREF2的放电时长，直至差值为零；
当差值为负时，增大第一参考电容CREF1或第二参考电容CREF2的放电时长，直至差值为零。
有益效果：
本申请所提出的模数转换器内部自带高精度参考基准源，即将参考信号直接采样在模数转换器的电容数模转换器，无需额外的参考信号产生电路和参考信号驱动器，从而从根源上解决传统架构的功耗、面积、误差大等缺点。该模数转换器可用于各类开关电容ADC，如delta-sigmaADC、SARADC和PipelinedADC。
针对所提出的模数转换器，还提出一种集成参考电压产生的模数转换器校准方法，只需一步校准，即给定输 入电压，测量所述模数转换器的输出，根据输出校准模数转换器的电容数模转换器即可实现输出校准，无需传统架构中单独校准基准参考电路，降低系统校正成本，实现高精度。
附图说明
下面结合附图和具体实施方式对本发明做更进一步的具体说明，本发明的上述和/或其他方面的优点将会变得更加清楚。
图1为传统ADC架构示意图。
图2为本申请实施例提供的模数转换器架构示意图。
图3为CBD电路结构和工作原理示意图。
图4为CBD产生PTAT和CTAT电压的电路结构示意图。
图5为本申请实施例提供的模数转换器中基于CBD原理的CDAC架构示意图。
图6为本申请实施例提供的集成参考电压产生电路的delta-sigma调制器电路示意图。
图7为本申请实施例提供的集成参考电压产生电路的电荷共享SARADC电路示意图。
图8为本申请实施例提供的包含CBD CDAC的PipelinedADC电路示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整的描述，所描述的实施例仅为本发明的可能的技术实现，并非全部实现可能。本领域技术人员完全可以结合本发明的实施例，在没有进行创造性劳动的情况下得到其他实施例，而这些实施例也在本发明的保护范围之内。
图1为传统的开关电容模数转换器架构及其周边模块，主要包含模数转换器ADC、参考信号产生电路以及参考信号驱动器。输入信号VIN经过采样保持电路S&H后和反馈参考信号做差得到误差信号，然后经过环路滤波器以及量化器得到数字输出。数字输出同时用于反馈控制数模转换器(DAC，Digital toAnalog Converter)，结合外部输入的参考信号VREF一起产生反馈参考信号。
本发明的发明人发现，在该传统架构中，ADC和参考信号产生电路以及参考信号驱动器需要分开设计。即使每个模块优化很好，组合起来往往无法达到系统整体信号最优。特别是为了驱动ADC，参考信号驱动器需要较大的功耗和面积，同时也会引入额外的误差，如直流失调、噪声等等。在系统应用中，为了达到高精度，每个模块需要单独校准，且校准方式不同，进一步增加了系统成本。例如校准参考信号，需要额外的引脚，通过高精度万用表测量参考信号输出并校准。为了校准ADC，则需要给定另外的信号源输入VIN，校准ADC的误差。基于此，发明人所提供的本申请一实施例中，所述集成参考电压产生的模数转换器的电容数模转换器(CDAC，capacitive digital to analog converter)直接自带参考信号产生功能，从而无需额外的参考信号产生电路以及参考信号驱动电路。与传统架构相比，由于无需额外的参考信号产生电路和参考信号驱动器，所述集成参考电压产生的模数转换器的面积和功耗大大降低，并且减少可能的误差来源。此外，为了进一步提升精度，本申请实施例提供的模数转换器架构校准只需要一次校准，即给定输入信号VIN，直接测量ADC输出，即可实现信号全通路一体校准。
如图2所示，本申请一实施例中，所述集成参考电压产生的模数转换器包括采样保持电路S&H、电容数模转换器CDAC和量化器，所述采样保持电路S&H，用于对模拟输入信号VIN进行采样保持，获得第一信号；所述电容数模转换器CDAC，用于产生参考信号，根据反馈的数字输出信号，产生和参考信号等比例的第二信号，例如第二信号为参考信号和反馈的数字输出信号的乘积；第一信号和第二信号做差获得误差信号；所述量化器，用于对误差信号进行数字化，获得数字输出信号。该数字输出信号支持N位数字输出，其中N≥1。可选的，在一些模数转换器中，例如delta-sigma模数转换器中，量化器前可添加环路滤波器，环路滤波器用于噪声整形，提高分辨率。
如图5所示，在本申请实施例中，所述电容数模转换器包括基于电容偏置二极管的CTAT(complementary to absolute temperature，与绝对温度互补)电路和基于电容偏置二极管的PTAT(proportional to absolute temperature，与绝对温度成比例)电路，所述基于电容偏置二极管的CTAT电路和基于电容偏置二极管的PTAT电路共同产生所述参考信号，且所述参考信号和温度无关。
所述基于电容偏置二极管的CTAT电路产生随温度变高而变低的CTAT电压VD，所述基于电容偏置二极管的PTAT电路产生随温度变高而变高的PTAT电压ΔVD，将CTAT电压VD和PTAT电压ΔVD组合相加，产生所述参考 信号的参考电压VREF，VREF＝αΔVD+VD，α为比例因子，比例因子α的取值使得所述参考电压VREF和温度无关。
在本申请实施例中，所述基于电容偏置二极管的CTAT电路包括第一CTAT电路开关SCTAT1、CTAT二极管支路和CTAT电容支路，所述第一CTAT电路开关SCTAT1的一端分别与CTAT二极管支路的一端和CTAT电容支路的一端连接，CTAT二极管支路的另一端和CTAT电容支路的另一端均接地；第一CTAT电路开关SCTAT1的另一端与电源连接。其中，为了CTAT电容支路能够预充电至电源，第一CTAT电路开关SCTAT1可以使用普通PMOS开关实现。
在本申请一实施例中，所述CTAT二极管支路包括第一二极管D1和与第一二极管D1连接的第二CTAT电路开关SCTAT2。其中，第一二极管D1可以使用P+/Nwell二极管，或者Pwell/N+二极管，为了减小开关导通电阻、电荷馈通等对CTAT电压的影响，第二CTAT电路开关SCTAT2可以使用带栅压自举开关或带dummy管的开关。
在本申请其他实施例中，CTAT二极管支路中的第一二极管D1可以替换为由二极管接法的三极管(将三极管的基极和集电极短接)或DTMOST(动态阈值MOS管)等其他器件实现。所述的三极管可以是PNP或者NPN，基极和集电极短接形成等效的二极管能够实现更好的二极管性能。
在本申请的各个实施例中，当所述数字输出信号为1位数字输出，所述CTAT电容支路包括一个第二参考电容CREF2。所述第二参考电容CREF2可以使用MIM(Metal-Insulator-Metal，金属绝缘体金属)电容或者MOM(Metal-Oxide-Metal，金属氧化物金属)电容。
当所述数字输出信号为N位数字输出，N>1，所述CTAT电容支路包括N个并联的第二电容支路，所述第二电容支路包括一个第二参考电容CREF2和与第二参考电容CREF2连接的第二参考开关SREF2，即第二参考电容CREF2可以根据需要拆成N-bit用于数字控制，形成N-bit的电容数模转换器。所述第二参考电容CREF2可以使用MIM电容或者MOM电容，所述第二参考开关SREF2可以使用普通NMOS开关。
在本申请实施例中，所述基于电容偏置二极管的PTAT电路包括第一电容偏置二极管电路和第二电容偏置二极管电路，两个电路产生的电压差即为PTAT电压ΔVD。
所述第一电容偏置二极管电路包括第一PTAT电路开关SPTAT1、第一PTAT二极管支路和第一PTAT电容支路，所述第一PTAT电路开关SPTAT1的一端分别与第一PTAT二极管支路的一端和第一PTAT电容支路的一端连接，第一PTAT二极管支路的另一端和第一PTAT电容支路的另一端均接地；第一PTAT电路开关SPTAT1的另一端与电源连接。为了第一PTAT电容支路能够预充电至电源，所述第一PTAT电路开关SPTAT1可以使用普通PMOS开关实现。
所述第二电容偏置二极管电路包括第二PTAT电路开关SPTAT2、第二PTAT二极管支路和第二PTAT电容支路，所述第二PTAT电路开关SPTAT2的一端分别与第二PTAT二极管支路的一端和第二PTAT电容支路的一端连接，第二PTAT二极管支路的另一端和第二PTAT电容支路的另一端均接地；第二PTAT电路开关SPTAT2的另一端与电源连接。为了第二PTAT电容支路能够预充电至电源，所述第二PTAT电路开关SPTAT2可以使用普通PMOS开关实现。
在本申请一实施例中，所述第一PTAT二极管支路包括第二二极管D2和与第二二极管D2连接的第三PTAT电路开关SPTAT3。其中，第二二极管D2可以使用P+/Nwell二极管，或者Pwell/N+二极管，为了减小开关导通电阻、电荷馈通等对PTAT电压的影响，第三PTAT电路开关SPTAT3可以使用带栅压自举开关或带dummy管的开关。
所述第二PTAT二极管支路包括第四PTAT电路开关SPTAT4和与第四PTAT电路开关SPTAT4连接的PTAT二极管组合，所述PTAT二极管组合包括多个并联的第三二极管D3。为了减小开关导通电阻、电荷馈通等对PTAT电压的影响，第四PTAT电路开关SPTAT4可以使用带栅压自举开关或带dummy管的开关，第三二极管D3可以使用P+/Nwell二极管，或者Pwell/N+二极管。
在本申请的其他实施例中，第一PTAT二极管支路中的第二二极管D2、PTAT二极管组合中的第三二极管D3均可以替换为由二极管接法的三极管(将三极管的基极和集电极短接)或DTMOST等其他器件实现。所述的三极管可以是PNP或者NPN，基极和集电极短接形成等效的二极管能够实现更好的二极管性能。
在本申请的各个实施例中，当所述数字输出信号为1位数字输出，所述第一PTAT电容支路和第二PTAT电容支路均包括一个第一参考电容CREF1。所述第一参考电容CREF1可以使用MIM电容或者MOM电容，需要和第二参考电容CREF2类型相同。
所述数字输出信号为N位数字输出，N>1，所述第一PTAT电容支路和第二PTAT电容支路均包括N个并联的第一电容支路，所述第一电容支路包括一个第一参考电容CREF1和与第一参考电容CREF1连接的第一参考开关SREF1， 即第一参考电容CREF1可以根据需要拆成N-bit用于数字控制，形成N-bit的电容数模转换器。所述第一参考电容CREF1可以使用MIM电容或者MOM电容，需要和第二参考电容CREF2类型相同。所述第一参考开关SREF1可以使用普通NMOS开关。
如图3所示，本申请实施例中，第二参考电容CREF2先通过第一CTAT电路开关SCTAT1预充电到电源电压VDD，然后断开第一CTAT电路开关SCTAT1，闭合第二CTAT电路开关SCTAT2，第二参考电容CREF2通过第一二极管D1放电；电容上的残余电压随时间而变小，经过一段时间(纳秒级)，电容上的残余电压和其初始电压无关，而只由二极管特性决定。若固定放电时长，第二参考电容CREF2上的残余电压随温度变高而变低，所述残余电压即为CTAT电压VD，VD的表达式如下所示：
VD＝VT(VT*CREF2/t/Is)
其中VT为热电压，可以表示为VT＝kT/q，T表示当前温度，k表示玻尔兹曼常数，q表示电荷常量，t表示闭合第二CTAT电路开关SCTAT2的时长，Is表示二极管或三极管的饱和电流。如图3所示，二极管电压(Diode Voltage)也即为CTAT电压VD，CTAT电压VD随着时间而变小，同时随着温度变高，CTAT电压VD变低。
如图4所示，第一电容偏置二极管电路的第一参考电容CREF1先通过第一PTAT电路开关SPTAT1预充电到电源电压VDD，然后断开第一PTAT电路开关SPTAT1，闭合第三PTAT电路开关SPTAT3，第一电容偏置二极管电路的第一参考电容CREF1通过第二二极管D2放电，获得第一残余电压VD1。
第二电容偏置二极管电路的第一参考电容CREF1先通过第二PTAT电路开关SPTAT2预充电到电源电压VDD，然后断开第二PTAT电路开关SPTAT2，闭合第四PTAT电路开关SPTAT4，第二电容偏置二极管电路的第一参考电容CREF1通过PTAT二极管组合放电，获得第二残余电压VD2。
第一残余电压VD1和第二残余电压VD2的电压差VD1-VD2随温度变高而变高，所述电压差为PTAT电压ΔVD，ΔVD的表达式如下所示：
ΔVD＝VD1-VD2＝kT/q(p)
其中，p表示第二二极管D2的面积与PTAT二极管组合的面积比，或者第三PTAT电路开关SPTAT3和第四PTAT电路开关SPTAT4在闭合起始时间相同的情况下，闭合时长之比。
如图4右侧以温度T为横坐标，电压V为纵坐标所示的温度和电压变化关系图所示，若将PTAT电压ΔVD和CTAT电压VD以一定比例组合相加，则可以抵消它们的温度特性，实现和温度无关的带隙参考电压输出VREF＝αΔVD+VD。例如，通过设置第一参考电容CREF1和第二参考电容CREF2的相对比例大小，来调节PTAT电路和CTAT电路的比例，实现两者在电荷域温度系数平衡抵消，实现等效的带隙参考基准。
在本申请实施例中，第一CTAT电路开关SCTAT1、第一PTAT电路开关SPTAT1和第二PTAT电路开关SPTAT2的控制时序相同。
在本发明一实施例中，第二CTAT电路开关SCTAT2、第三PTAT电路开关SPTAT3和第四PTAT电路开关SPTAT4的控制时序相同，第二二极管D2的面积与PTAT二极管组合的面积比设置为1：p，p>1。其中，PTAT二极管组合中的第三二极管D3可以和第二二极管D2相同，PTAT二极管组合包含p个第三二极管D3，或者第三二极管D3可以和第二二极管D2不相同，只要确保第二二极管D2的面积与PTAT二极管组合的面积比设置为1：p即可，均不影响本申请实施例的实现。此处通过将第二二极管D2的面积与PTAT二极管组合的面积比设置为1：p形成电流密度比例关系，从而产生随温度变高而变高的PTAT电压ΔVD。
在本发明另一实施例中，第二CTAT电路开关SCTAT2和第三PTAT电路开关SPTAT3的控制时序相同，第二二极管D2的面积与PTAT二极管组合的面积相等，第三PTAT电路开关SPTAT3和第四PTAT电路开关SPTAT4闭合的起始时间相同，闭合时长之比为1：p，p>1。其中，PTAT二极管组合可以包含一个第三二极管D3，第三二极管D3和第二二极管D2相同，或者PTAT二极管组合可以包含多个第三二极管D3，只要确保第二二极管D2的面积与PTAT二极管组合的面积相等即可，均不影响本申请实施例的实现。此处通过控制第三PTAT电路开关SPTAT3和第四PTAT电路开关SPTAT4闭合时长，即通过第二二极管D2和PTAT二极管组合的放电时长控制流过第二二极管D2和PTAT二极管组合的电流密度，从而产生随温度变高而变高的PTAT电压ΔVD。
基于上述架构，本申请实施例可以应用于现有的各类开关电容的ADC架构，从而去除现有架构中的额外参考 信号产生电路和参考信号驱动电路，大大简化系统架构。
如图6所示，所述模数转换器可以为delta-sigma模数转换器，所述delta-sigma模数转换器包括delta-sigma调制器，所述delta-sigma调制器包括所述电容数模转换器和第一级积分器，所述电容数模转换器包括基于电容偏置二极管的CTAT电路和基于电容偏置二极管的PTAT电路，所述基于电容偏置二极管的CTAT电路产生随温度变高而变低的CTAT电压VD，所述基于电容偏置二极管的PTAT电路产生随温度变高而变高的PTAT电压ΔVD，CTAT电压VD和PTAT电压ΔVD通过第一级积分器实现相加组合，获得参考信号VREF＝αΔVD+VD，其中α为比例因子，比例因子α的取值使得所述参考电压VREF和温度无关。图6中的环路滤波器表示后面还可以级联更多级数的积分器。
所述基于电容偏置二极管的CTAT电路包括第一CTAT电路开关SCTAT1、CTAT二极管支路和CTAT电容支路，所述第一CTAT电路开关SCTAT1的一端分别与CTAT二极管支路的一端和CTAT电容支路的一端连接，第一CTAT电路开关SCTAT1的一端还连接有第三CTAT电路开关SCTAT3，CTAT二极管支路的另一端接地，CTAT电容支路的另一端连接第一级积分器的输入端，第一级积分器的输入端包括正端VGP和负端VGN；第一CTAT电路开关SCTAT1的另一端与电源连接。所述CTAT二极管支路包括第一二极管D1和与第一二极管D1连接的第二CTAT电路开关SCTAT2。输出1比特BS码流时，所述CTAT电容支路包括一个第二参考电容CREF2。在差分模数转换器中，需要另一组电容形成全差分结构，作用相当于采样0V(地)，在具体实现过程中，所述基于电容偏置二极管的CTAT电路还包括一个由第二参考电容CREF2和第四CTAT电路开关SCTAT4组成的支路，该第二参考电容CREF2的一端连接第一级积分器的输入端，该第二参考电容CREF2的另一端连接第四CTAT电路开关SCTAT4的一端，第四CTAT电路开关SCTAT4的另一端接地。该第二参考电容CREF2的另一端和第四CTAT电路开关SCTAT4的一端还连接有第五CTAT电路开关SCTAT5，第五CTAT电路开关SCTAT5与第三CTAT电路开关SCTAT3连接并共同连接交流地，所述交流地一般是共模电平。根据BS码流的是0还是1，基于电容偏置二极管的CTAT电路选择输入+VREF还是-VREF，即选择连接第一级积分器的输入端正端VGP还是负端VGN。
所述基于电容偏置二极管的PTAT电路包括第一电容偏置二极管电路和第二电容偏置二极管电路，所述第一电容偏置二极管电路包括第一PTAT电路开关SPTAT1、第一PTAT二极管支路和第一PTAT电容支路，所述第一PTAT电路开关SPTAT1的一端分别与第一PTAT二极管支路的一端和第一PTAT电容支路的一端连接，第一PTAT电路开关SPTAT1的一端还连接有第五PTAT电路开关SPTAT5，第一PTAT二极管支路的另一端接地，第一PTAT电容支路的另一端连接第一级积分器的输入端；第一PTAT电路开关SPTAT1的另一端与电源连接。所述第二电容偏置二极管电路包括第二PTAT电路开关SPTAT2、第二PTAT二极管支路和第二PTAT电容支路，所述第二PTAT电路开关SPTAT2的一端分别与第二PTAT二极管支路的一端和第二PTAT电容支路的一端连接，第二PTAT电路开关SPTAT2的一端还连接有第六PTAT电路开关SPTAT6，第二PTAT二极管支路的另一端接地，第二PTAT电容支路的另一端连接第一级积分器的输入端；第二PTAT电路开关SPTAT2的另一端与电源连接。第五PTAT电路开关SPTAT5和第六PTAT电路开关SPTAT6连接并共同连接交流地，所述交流地一般是共模电平。
所述第一PTAT二极管支路包括第二二极管D2和与第二二极管D2连接的第三PTAT电路开关SPTAT3。所述第二PTAT二极管支路包括第四PTAT电路开关SPTAT4和与第四PTAT电路开关SPTAT4连接的PTAT二极管组合，所述PTAT二极管组合包括多个并联的第三二极管D3。当所述数字输出信号为1位数字输出，所述第一PTAT电容支路和第二PTAT电容支路均包括一个第一参考电容CREF1。
本实施例中α通过第一参考电容CREF1和第二参考电容CREF2的相对比例大小进行调节，α＝CREF1/CREF2。
所述第一级积分器包括积分电容CINT，delta-sigma调制器的控制时序包括：输入信号VIN在采样周期Φ1实现信号采样，在积分周期Φ2实现信号转移和积分；对于参考信号支路，采样周期Φ1拆分为两部分：rst和Φ3，其中rst状态下，第一参考电容CREF1和第二参考电容CREF2预充电到电源电压VDD；在Φ3状态下，第二参考电容CREF2通过第一二极管D1放电，第一参考电容CREF1通过第二二极管D2和PTAT二极管组合放电，在Φ3和Φ1结束时将参考信号采样在第一参考电容CREF1和第二参考电容CREF2；在积分相位Φ2，第一参考电容CREF1和第二参考电容CREF2上的电荷被转移到积分电容CINT上。
若delta-sigma调制器输出1比特BS码流，根据输出的1比特BS码流选择产生+/-VREF，用于和输入信号VIN实现平衡，BS码流平均值为VIN/VREF。
如图7所示，所述模数转换器还可以为电荷共享型逐次逼近型模数转换器(SARADC，SuccessiveApproximation RegisterADC)，所述逐次逼近型模数转换器包括输入电容CIN、所述电容数模转换器和比较器，所述电容模数转换器利用上述CBD原理在采样阶段将和温度无关的参考信号采样在N-bit第一参考电容CREF1和第二参考电容CREF2上，并在比较阶段根据比较器结果产生和参考信号等比例的反馈控制信号，其简化等效图如图7下方虚线框所示，具体实现如图7上方电路图所示。所述电容数模转换器包括基于电容偏置二极管的CTAT电路和基于电容偏置二极管的PTAT电路，所述基于电容偏置二极管的CTAT电路产生随温度变高而变低的CTAT电压VD，所述基于电容偏置二极管的PTAT电路产生随温度变高而变高的PTAT电压ΔVD，CTAT电压VD和PTAT电压ΔVD通过第一级积分器实现相加组合，获得参考信号VREF＝αΔVD+VD，其中α为比例因子，比例因子α的取值使得所述参考电压VREF和温度无关。
所述基于电容偏置二极管的CTAT电路包括第一CTAT电路开关SCTAT1、CTAT二极管支路和CTAT电容支路，所述第一CTAT电路开关SCTAT1的一端分别与CTAT二极管支路的一端和CTAT电容支路的一端连接，第一CTAT电路开关SCTAT1的一端还连接有第六CTAT电路开关SCTAT6，CTAT二极管支路的另一端和CTAT电容支路的另一端均接地；第一CTAT电路开关SCTAT1的另一端与电源连接。所述CTAT二极管支路包括第一二极管D1和与第一二极管D1连接的第二CTAT电路开关SCTAT2。当所述数字输出信号为N位数字输出，N>1，所述CTAT电容支路包括N个并联的第二电容支路，所述第二电容支路包括第二参考电容CREF2和与第二参考电容CREF2连接的第二参考开关SREF2，还包括与第二参考电容CREF2连接的第四参考开关SREF4，第四参考开关SREF4与MSB或者LSB连接。
所述基于电容偏置二极管的PTAT电路包括第一电容偏置二极管电路和第二电容偏置二极管电路，所述第一电容偏置二极管电路包括第一PTAT电路开关SPTAT1、第一PTAT二极管支路和第一PTAT电容支路，所述第一PTAT电路开关SPTAT1的一端分别与第一PTAT二极管支路的一端和第一PTAT电容支路的一端连接，第一PTAT电路开关SPTAT1的一端还连接有第七PTAT电路开关SPTAT7，第一PTAT二极管支路的另一端和第一PTAT电容支路的另一端均接地；第一PTAT电路开关SPTAT1的另一端与电源连接。所述第二电容偏置二极管电路包括第二PTAT电路开关SPTAT2、第二PTAT二极管支路和第二PTAT电容支路，所述第二PTAT电路开关SPTAT2的一端分别与第二PTAT二极管支路的一端和第二PTAT电容支路的一端连接，第二PTAT电路开关SPTAT2的一端与第七PTAT电路开关SPTAT7连接，第二PTAT二极管支路的另一端和第二PTAT电容支路的另一端均接地；第二PTAT电路开关SPTAT2的另一端与电源连接。
所述第一PTAT二极管支路包括第二二极管D2和与第二二极管D2连接的第三PTAT电路开关SPTAT3。所述第二PTAT二极管支路包括第四PTAT电路开关SPTAT4和与第四PTAT电路开关SPTAT4连接的PTAT二极管组合，所述PTAT二极管组合包括多个并联的第三二极管D3。当所述数字输出信号为N位数字输出，N>1，所述第一PTAT电容支路和第二PTAT电容支路均包括N个并联的第一电容支路，所述第一电容支路包括第一参考电容CREF1和与第一参考电容CREF1连接的第一参考开关SREF1，还包括与第一参考电容CREF1连接的第三参考开关SREF3，第三参考开关SREF3与MSB或者LSB连接。所述第二PTAT电容支路还包括第八PTAT电路开关SPTAT8，所述第八PTAT电路开关SPTAT8的一端与N个并联的第一电容支路连接，第八PTAT电路开关SPTAT8的另一端接地；第八PTAT电路开关SPTAT8的一端还与第六CTAT电路开关SCTAT6连接。第六CTAT电路开关SCTAT6、第七PTAT电路开关SPTAT7和第八PTAT电路开关SPTAT8用于实现CTAT电压VD和PTAT电压ΔVD的相加。
本实施例中α通过第一参考电容CREF1和第二参考电容CREF2的相对比例大小进行调节，α＝CREF1/CREF2。
所述电荷共享型逐次逼近型模数转换器的控制时序包括：
输入信号采样保持在输入电容CIN上，参考信号的参考电压保持在第一参考电容CREF1和第二参考电容CREF2上；差分输入信号INP和INN在采样相位Fs为高时实现信号采样保持在输入电容CIN上，对于参考信号支路，第一参考电容CREF1在采样相位Fs通过第一参考开关SREF1和第三参考开关SREF3接入电路，第二参考电容CREF2在采样相位Fs通过第二参考开关SREF2和第四参考开关SREF4接入电路，产生参考信号。其中采样相位Fs可拆分为两部分：Φ1相位和Φ2相位，Φ1相位实现与温度正相关的PTAT电压信号ΔVD及与温度负相关的CTAT电压信号VD的产生；Φ2相位实现PTAT电压信号ΔVD和CTAT电压信号VD按比例相加，得到和温度无关的参考信号αΔVD+VD。其中为产生PTAT电压信号ΔVD和CTAT电压信号VD，Φ1相位进一步拆分为两个子相位：rst和Φd/Φd1,2。在rst 状态下，第一参考电容CREF1和第二参考电容CREF2预充电到电源电压VDD；在Φd状态下，第二参考电容CREF2通过第一二极管D1放电，在Φd1和Φd2状态下第一参考电容CREF1通过第二二极管D2和第三二极管D3组合放电，在Φ1、Φd和Φd1,2结束时将PTAT电压信号ΔVD和CTAT电压信号VD分别采样在第一参考电容CREF1和第二参考电容CREF2；在相位Φ2，第八PTAT电路开关SPTAT8断开，第六CTAT电路开关SPTAT6和第七PTAT电路开关SPTAT7闭合，实现PTAT电压信号ΔVD和CTAT电压信号VD相加，在第一参考电容CREF1和第二参考电容CREF2产生和温度无关的参考信号。
在采样相位Fs结束后，进入比较量化相位ΦSAR，通过逐次逼近的算法逻辑，第一参考电容CREF1、第二参考电容CREF2和输入电容CIN进行电荷分享，获得比较器输入电压，比较器比较获得的结果用于控制下一次电容数模转换器的工作状态；多次逐次逼近比较获得最终转换的输出信号。
如图8所示，所述模数转换器还可以为流水线模数转换器(pipelinedADC)，所述流水线结构模数转换器包括逐级串联的转换模块，每级转换模块包括所述采样保持电路和所述电容数模转换器，采样保持电路对模拟输入信号VIN进行采样保持，获得第一信号；电容数模转换器产生参考信号，根据反馈的数字输出信号，产生和参考信号等比例的第二信号；第一信号和第二信号做差获得误差信号。如图8所示，流水线ADC有R级，每级实现N bit转换。对于每一级实现，首先对于前一级输入采样(S/H)，同时，通过子N-bitADC实现量化，量化后的数字信号通过N-bit子CDAC转换为模拟信号，并和输入信号做差，经过放大后送入下一级。其中该子CDAC可以采用图5的基于CBD原理的CDAC架构实现，在具体实现过程中，N-bit子CDAC包括基于电容偏置二极管的CTAT电路和基于电容偏置二极管的PTAT电路，所述基于电容偏置二极管的CTAT电路和基于电容偏置二极管的PTAT电路共同产生所述参考信号，且所述参考信号和温度无关。所述基于电容偏置二极管的CTAT电路产生随温度变高而变低的CTAT电压VD，所述基于电容偏置二极管的PTAT电路产生随温度变高而变高的PTAT电压ΔVD，将CTAT电压VD和PTAT电压ΔVD组合相加，产生所述参考信号的参考电压VREF，VREF＝αΔVD+VD，α为比例因子，比例因子α的取值使得所述参考电压VREF和温度无关。
所述基于电容偏置二极管的CTAT电路包括第一CTAT电路开关SCTAT1、CTAT二极管支路和CTAT电容支路，所述第一CTAT电路开关SCTAT1的一端分别与CTAT二极管支路的一端和CTAT电容支路的一端连接，CTAT二极管支路的另一端和CTAT电容支路的另一端均接地；第一CTAT电路开关SCTAT1的另一端与电源连接。所述CTAT二极管支路包括第一二极管D1和与第一二极管D1连接的第二CTAT电路开关SCTAT2。当所述数字输出信号为N位数字输出，N>1，所述CTAT电容支路包括N个并联的第二电容支路，所述第二电容支路包括第二参考电容CREF2和与第二参考电容CREF2连接的第二参考开关SREF2。
所述基于电容偏置二极管的PTAT电路包括第一电容偏置二极管电路和第二电容偏置二极管电路，所述第一电容偏置二极管电路包括第一PTAT电路开关SPTAT1、第一PTAT二极管支路和第一PTAT电容支路，所述第一PTAT电路开关SPTAT1的一端分别与第一PTAT二极管支路的一端和第一PTAT电容支路的一端连接，第一PTAT二极管支路的另一端和第一PTAT电容支路的另一端均接地；第一PTAT电路开关SPTAT1的另一端与电源连接。所述第二电容偏置二极管电路包括第二PTAT电路开关SPTAT2、第二PTAT二极管支路和第二PTAT电容支路，所述第二PTAT电路开关SPTAT2的一端分别与第二PTAT二极管支路的一端和第二PTAT电容支路的一端连接，第二PTAT二极管支路的另一端和第二PTAT电容支路的另一端均接地；第二PTAT电路开关SPTAT2的另一端与电源连接。
所述第一PTAT二极管支路包括第二二极管D2和与第二二极管D2连接的第三PTAT电路开关SPTAT3。所述第二PTAT二极管支路包括第四PTAT电路开关SPTAT4和与第四PTAT电路开关SPTAT4连接的PTAT二极管组合，所述PTAT二极管组合包括多个并联的第三二极管D3。当所述数字输出信号为N位数字输出，N>1，所述第一PTAT电容支路和第二PTAT电容支路均包括N个并联的第一电容支路，所述第一电容支路包括第一参考电容CREF1和与第一参考电容CREF1连接的第一参考开关SREF1。
本实施例中α通过第一参考电容CREF1和第二参考电容CREF2的相对比例大小进行调节，α＝CREF1/CREF2。
此外，由于无需额外的参考信号产生电路和参考信号驱动器，系统校准可以一步完成，本申请实施例提供一种集成参考电压产生的模数转换器校准方法，应用于上述的集成参考电压产生的模数转换器，具体实现如下：
步骤1，将模拟输入信号输入至所述的集成参考电压产生的模数转换器，获得数字输出信号；
步骤2，对所述数字输出信号和理想值做差，获得差值；
步骤3，根据差值调节所述电容数模转换器的参考电容或放电时长，从而校准数字输出信号。
进一步地，步骤2中理想值为模拟输入信号值和所希望设计的参考信号值的比值。
进一步地，步骤3中根据差值调节所述电容数模转换器的参考电容为调节第一参考电容CREF1或第二参考电容CREF2参考电容，具体包括：
当差值为正时，增大第一参考电容CREF1或第二参考电容CREF2，直至差值为零；
当差值为负时，减小第一参考电容CREF1或第二参考电容CREF2，直至差值为零。
进一步地，步骤3中根据差值调节所述电容数模转换器的放电时长为调节第三PTAT电路开关SPTAT3和第四PTAT电路开关SPTAT4闭合的放电时长，具体包括：
当差值为正时，减小第一参考电容CREF1或第二参考电容CREF2的放电时长，直至差值为零；
当差值为负时，增大第一参考电容CREF1或第二参考电容CREF2的放电时长，直至差值为零。
放电时长t可以做成可调节的，如图4的波形示意图中的t。具体实现可以通过外部高频时钟计数得到延时t。也可以通过片上RC延时得到t。做成可调只需要把计数个数或者RC值可调即可控制时长t。
上述方案可以通过一次校准，校准了ADC、参考信号等所有系统误差，从而无需额外的参考信号或驱动器校准。
具体实现中，本申请提供计算机存储介质以及对应的数据处理单元，其中，该计算机存储介质能够存储计算机程序，所述计算机程序通过数据处理单元执行时可运行本发明提供的一种集成参考电压产生的模数转换器校准方法的发明内容以及各实施例中的部分或全部步骤。所述的存储介质可为磁碟、光盘、只读存储记忆体(read-only memory，ROM)或随机存储记忆体(random access memory，RAM)等。
本领域的技术人员可以清楚地了解到本发明实施例中的技术方案可借助计算机程序以及其对应的通用硬件平台的方式来实现。基于这样的理解，本发明实施例中的技术方案本质上或者说对现有技术做出贡献的部分可以以计算机程序即软件产品的形式体现出来，该计算机程序软件产品可以存储在存储介质中，包括若干指令用以使得一台包含数据处理单元的设备(可以是个人计算机，服务器，单片机，MUU或者网络设备等)执行本发明各个实施例或者实施例的某些部分所述的方法。
本发明提供了一种集成参考电压产生的模数转换器及校准方法，具体实现该技术方案的方法和途径很多，以上所述仅是本发明的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。本实施例中未明确的各组成部分均可用现有技术加以实现。

Claims (30)

  1. 一种集成参考电压产生的模数转换器，其特征在于，包括采样保持电路、电容数模转换器和量化器，
    所述采样保持电路，用于对模拟输入信号进行采样保持，获得第一信号；
    所述电容数模转换器，用于产生参考信号，根据反馈的数字输出信号，产生和参考信号等比例的第二信号；第一信号和第二信号做差获得误差信号；
    所述量化器，用于对误差信号进行数字化，获得数字输出信号。
  2. 根据权利要求1所述的一种集成参考电压产生的模数转换器，其特征在于，所述电容数模转换器包括基于电容偏置二极管的CTAT电路和基于电容偏置二极管的PTAT电路，所述基于电容偏置二极管的CTAT电路和基于电容偏置二极管的PTAT电路共同产生所述参考信号，且所述参考信号和温度无关。
  3. 根据权利要求2所述的一种集成参考电压产生的模数转换器，其特征在于，所述基于电容偏置二极管的CTAT电路产生随温度变高而变低的CTAT电压VD，所述基于电容偏置二极管的PTAT电路产生随温度变高而变高的PTAT电压ΔVD，将CTAT电压VD和PTAT电压ΔVD组合相加，产生所述参考信号的参考电压VREF，VREF＝αΔVD+VD，α为比例因子，比例因子α的取值使得所述参考电压VREF和温度无关。
  4. 根据权利要求3所述的一种集成参考电压产生的模数转换器，其特征在于，所述基于电容偏置二极管的CTAT电路包括第一CTAT电路开关SCTAT1、CTAT二极管支路和CTAT电容支路，所述第一CTAT电路开关SCTAT1的一端分别与CTAT二极管支路的一端和CTAT电容支路的一端连接，CTAT二极管支路的另一端和CTAT电容支路的另一端均接地；第一CTAT电路开关SCTAT1的另一端与电源连接。
  5. 根据权利要求4所述的一种集成参考电压产生的模数转换器，其特征在于，所述基于电容偏置二极管的PTAT电路包括第一电容偏置二极管电路和第二电容偏置二极管电路，所述第一电容偏置二极管电路包括第一PTAT电路开关SPTAT1、第一PTAT二极管支路和第一PTAT电容支路，所述第一PTAT电路开关SPTAT1的一端分别与第一PTAT二极管支路的一端和第一PTAT电容支路的一端连接，第一PTAT二极管支路的另一端和第一PTAT电容支路的另一端均接地；第一PTAT电路开关SPTAT1的另一端与电源连接；
    所述第二电容偏置二极管电路包括第二PTAT电路开关SPTAT2、第二PTAT二极管支路和第二PTAT电容支路，所述第二PTAT电路开关SPTAT2的一端分别与第二PTAT二极管支路的一端和第二PTAT电容支路的一端连接，第二PTAT二极管支路的另一端和第二PTAT电容支路的另一端均接地；第二PTAT电路开关SPTAT2的另一端与电源连接。
  6. 根据权利要求4所述的一种集成参考电压产生的模数转换器，其特征在于，所述CTAT二极管支路包括第一二极管D1和与第一二极管D1连接的第二CTAT电路开关SCTAT2。
  7. 根据权利要求6所述的一种集成参考电压产生的模数转换器，其特征在于，当所述数字输出信号为1位数字输出，所述CTAT电容支路包括第二参考电容CREF2。
  8. 根据权利要求6所述的一种集成参考电压产生的模数转换器，其特征在于，当所述数字输出信号为N位数字输出，N>1，所述CTAT电容支路包括N个并联的第二电容支路，所述第二电容支路包括第二参考电容CREF2和与第二参考电容CREF2连接的第二参考开关SREF2。
  9. 根据权利要求7或8所述的一种集成参考电压产生的模数转换器，其特征在于，第一PTAT二极管支路包括第二二极管D2和与第二二极管D2连接的第三PTAT电路开关SPTAT3。
  10. 根据权利要求9所述的一种集成参考电压产生的模数转换器，其特征在于，第二PTAT二极管支路包括第四PTAT电路开关SPTAT4和与第四PTAT电路开关SPTAT4连接的PTAT二极管组合，所述PTAT二极管组合包括多个并联的第三二极管D3。
  11. 根据权利要求10所述的一种集成参考电压产生的模数转换器，其特征在于，当所述数字输出信号为1位数字输出，所述第一PTAT电容支路和第二PTAT电容支路均包括第一参考电容CREF1。
  12. 根据权利要求10所述的一种集成参考电压产生的模数转换器，其特征在于，当所述数字输出信号为N位数字输出，N>1，所述第一PTAT电容支路和第二PTAT电容支路均包括N个并联的第一电容支路，所述第一电容支路包括第一参考电容CREF1和与第一参考电容CREF1连接的第一参考开关SREF1。
  13. 根据权利要求11或12所述的一种集成参考电压产生的模数转换器，其特征在于，第二参考电容CREF2先通过第一CTAT电路开关SCTAT1预充电到电源电压VDD，然后断开第一CTAT电路开关SCTAT1，闭合第二CTAT电路 开关SCTAT2，第二参考电容CREF2通过第一二极管D1放电；若固定放电时长，第二参考电容CREF2上的残余电压随温度变高而变低，所述残余电压即为CTAT电压VD。
  14. 根据权利要求13所述的一种集成参考电压产生的模数转换器，其特征在于，第一电容偏置二极管电路的第一参考电容CREF1先通过第一PTAT电路开关SPTAT1预充电到电源电压VDD，然后断开第一PTAT电路开关SPTAT1，闭合第三PTAT电路开关SPTAT3，第一电容偏置二极管电路的第一参考电容CREF1通过第二二极管D2放电，获得第一残余电压VD1。
  15. 根据权利要求14所述的一种集成参考电压产生的模数转换器，其特征在于，第二电容偏置二极管电路的第一参考电容CREF1先通过第二PTAT电路开关SPTAT2预充电到电源电压VDD，然后断开第二PTAT电路开关SPTAT2，闭合第四PTAT电路开关SPTAT4，第二电容偏置二极管电路的第一参考电容CREF1通过PTAT二极管组合放电，获得第二残余电压VD2。
  16. 根据权利要求15所述的一种集成参考电压产生的模数转换器，其特征在于，第一残余电压VD1和第二残余电压VD2的电压差VD1-VD2随温度变高而变高，所述电压差为PTAT电压ΔVD。
  17. 根据权利要求16所述的一种集成参考电压产生的模数转换器，其特征在于，第一CTAT电路开关SCTAT1、第一PTAT电路开关SPTAT1和第二PTAT电路开关SPTAT2的控制时序相同。
  18. 根据权利要求17所述的一种集成参考电压产生的模数转换器，其特征在于，第二CTAT电路开关SCTAT2、第三PTAT电路开关SPTAT3和第四PTAT电路开关SPTAT4的控制时序相同，第二二极管D2的面积与PTAT二极管组合的面积比设置为1：p，p>1。
  19. 根据权利要求17所述的一种集成参考电压产生的模数转换器，其特征在于，第二CTAT电路开关SCTAT2和第三PTAT电路开关SPTAT3的控制时序相同，第二二极管D2的面积与PTAT二极管组合的面积相等，第三PTAT电路开关SPTAT3和第四PTAT电路开关SPTAT4闭合的起始时间相同，闭合时长之比为1：p，p>1。
  20. 根据权利要求11或12所述的一种集成参考电压产生的模数转换器，其特征在于，所述模数转换器为delta-sigma模数转换器，所述delta-sigma模数转换器包括delta-sigma调制器，所述delta-sigma调制器包括所述电容数模转换器和第一级积分器，电容数模转换器产生CTAT电压VD和PTAT电压ΔVD，CTAT电压VD和PTAT电压ΔVD通过第一级积分器实现相加组合，获得参考信号VREF＝αΔVD+VD，其中α＝CREF1/CREF2。
  21. 根据权利要求20所述的一种集成参考电压产生的模数转换器，其特征在于，所述第一级积分器包括积分电容CINT，delta-sigma调制器的控制时序包括：输入信号VIN在采样周期Φ1实现信号采样，在积分周期Φ2实现信号转移和积分；对于参考信号支路，采样周期Φ1拆分为两部分：rst和Φ3，其中rst状态下，第一参考电容CREF1和第二参考电容CREF2预充电到电源电压；在Φ3状态下，第二参考电容CREF2通过第一二极管D1放电，第一参考电容CREF1通过第二二极管D2和PTAT二极管组合放电，在Φ3和Φ1结束时将参考信号采样在第一参考电容CREF1和第二参考电容CREF2；在积分相位Φ2，第一参考电容CREF1和第二参考电容CREF2上的电荷被转移到积分电容CINT上。
  22. 根据权利要求21所述的一种集成参考电压产生的模数转换器，其特征在于，若delta-sigma调制器输出1比特BS码流，根据输出的1比特BS码流选择产生+/-VREF，用于和输入信号VIN实现平衡，BS码流平均值为VIN/VREF。
  23. 根据权利要求12所述的一种集成参考电压产生的模数转换器，其特征在于，所述模数转换器为电荷共享型逐次逼近型模数转换器，所述逐次逼近型模数转换器包括输入电容CIN、所述电容数模转换器和比较器，所述电容模数转换器在采样阶段将和温度无关的参考信号采样在N-bit第一参考电容CREF1和第二参考电容CREF2上，并在比较阶段根据比较器结果产生和参考信号等比例的反馈控制信号。
  24. 根据权利要求23所述的一种集成参考电压产生的模数转换器，其特征在于，所述电容数模转换器中，基于电容偏置二极管的CTAT电路的第一CTAT电路开关SCTAT1的一端还连接有第六CTAT电路开关SCTAT6，当所述数字输出信号为N位数字输出，N>1，CTAT电容支路包括N个并联的第二电容支路，所述第二电容支路包括第二参考电容CREF2和与第二参考电容CREF2连接的第二参考开关SREF2，还包括与第二参考电容CREF2连接的第四参考开关SREF4，第四参考开关SREF4与MSB或者LSB连接；
    基于电容偏置二极管的PTAT电路中，第一PTAT电路开关SPTAT1的一端还连接有第七PTAT电路开关SPTAT7，第二PTAT电路开关SPTAT2的一端与第七PTAT电路开关SPTAT7连接，所述第一PTAT电容支路和第二PTAT电容支 路均包括N个并联的第一电容支路，所述第一电容支路包括第一参考电容CREF1和与第一参考电容CREF1连接的第一参考开关SREF1，还包括与第一参考电容CREF1连接的第三参考开关SREF3，第三参考开关SREF3与MSB或者LSB连接；所述第二PTAT电容支路还包括第八PTAT电路开关SPTAT8，所述第八PTAT电路开关SPTAT8的一端与N个并联的第一电容支路连接，第八PTAT电路开关SPTAT8的另一端接地；第八PTAT电路开关SPTAT8的一端还与第六CTAT电路开关SCTAT6连接。
  25. 根据权利要求24所述的一种集成参考电压产生的模数转换器，其特征在于，所述电荷共享型逐次逼近型模数转换器的控制时序包括：输入信号采样保持在输入电容CIN上，参考信号的参考电压保持在第一参考电容CREF1和第二参考电容CREF2上；差分输入信号INP和INN在采样相位Fs为高时实现信号采样保持在输入电容CIN上，对于参考信号支路，第一参考电容CREF1在采样相位Fs通过第一参考开关SREF1和第三参考开关SREF3接入电路，第二参考电容CREF2在采样相位Fs通过第二参考开关SREF2和第四参考开关SREF4接入电路，产生参考信号；其中采样相位Fs可拆分为两部分：Φ1相位和Φ2相位，Φ1相位实现与温度正相关的PTAT电压信号ΔVD及与温度负相关的CTAT电压信号VD的产生；Φ2相位实现PTAT电压信号ΔVD和CTAT电压信号VD按比例相加，得到和温度无关的参考信号αΔVD+VD；其中为产生PTAT电压信号ΔVD和CTAT电压信号VD，Φ1相位进一步拆分为两个子相位：rst和Φd/Φd1,2；在rst状态下，第一参考电容CREF1和第二参考电容CREF2预充电到电源电压VDD；在Φd状态下，第二参考电容CREF2通过第一二极管D1放电，在Φd1和Φd2状态下第一参考电容CREF1通过第二二极管D2和第三二极管D3组合放电，在Φ1、Φd和Φd1,2结束时将PTAT电压信号ΔVD和CTAT电压信号VD分别采样在第一参考电容CREF1和第二参考电容CREF2；在相位Φ2，第八PTAT电路开关SPTAT8断开，第六CTAT电路开关SPTAT6和第七PTAT电路开关SPTAT7闭合，实现PTAT电压信号ΔVD和CTAT电压信号VD相加，在第一参考电容CREF1和第二参考电容CREF2产生和温度无关的参考信号；
    在采样相位Fs结束后，进入比较量化相位ΦSAR，通过逐次逼近的算法逻辑，第一参考电容CREF1、第二参考电容CREF2和输入电容CIN进行电荷分享，获得比较器输入电压，比较器比较获得的结果用于控制下一次电容数模转换器的工作状态；多次逐次逼近比较获得最终转换的输出信号。
  26. 根据权利要求11或12所述的一种集成参考电压产生的模数转换器，其特征在于，所述模数转换器为流水线模数转换器，所述流水线结构模数转换器包括逐级串联的转换模块，每级转换模块包括所述采样保持电路和所述电容数模转换器，采样保持电路对模拟输入信号进行采样保持，获得第一信号；电容数模转换器产生参考信号，根据反馈的数字输出信号，产生和参考信号等比例的第二信号；第一信号和第二信号做差获得误差信号。
  27. 一种集成参考电压产生的模数转换器校准方法，应用于权利要求13-26任一项所述的集成参考电压产生的模数转换器，其特征在于，包括：
    步骤1，将模拟输入信号输入至所述的集成参考电压产生的模数转换器，获得数字输出信号；
    步骤2，对所述数字输出信号和理想值做差，获得差值；
    步骤3，根据差值调节所述电容数模转换器的参考电容或放电时长，从而校准数字输出信号。
  28. 根据权利要求27所述的一种集成参考电压产生的模数转换器校准方法，其特征在于，步骤2中理想值为模拟输入信号值和所希望设计的参考信号值的比值。
  29. 根据权利要求28所述的一种集成参考电压产生的模数转换器校准方法，其特征在于，步骤3包括：
    当差值为正时，增大第一参考电容CREF1或第二参考电容CREF2，直至差值为零；
    当差值为负时，减小第一参考电容CREF1或第二参考电容CREF2，直至差值为零。
  30. 根据权利要求28所述的一种集成参考电压产生的模数转换器校准方法，其特征在于，步骤3包括：
    当差值为正时，减小第一参考电容CREF1或第二参考电容CREF2的放电时长，直至差值为零；
    当差值为负时，增大第一参考电容CREF1或第二参考电容CREF2的放电时长，直至差值为零。
PCT/CN2023/108062 2023-06-01 2023-07-19 一种集成参考电压产生的模数转换器及校准方法 WO2024082732A1 (zh)

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