WO2024082703A1 - 显示装置 - Google Patents

显示装置 Download PDF

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Publication number
WO2024082703A1
WO2024082703A1 PCT/CN2023/103980 CN2023103980W WO2024082703A1 WO 2024082703 A1 WO2024082703 A1 WO 2024082703A1 CN 2023103980 W CN2023103980 W CN 2023103980W WO 2024082703 A1 WO2024082703 A1 WO 2024082703A1
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WO
WIPO (PCT)
Prior art keywords
signal
node
display
transistor
sub
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Application number
PCT/CN2023/103980
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English (en)
French (fr)
Inventor
陶宝生
刘超
吴昊
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Publication of WO2024082703A1 publication Critical patent/WO2024082703A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present application relates to the field of display technology, and in particular to a display device.
  • the embodiment of the present application provides a display device that can take into account both display performance requirements and battery life performance requirements.
  • the embodiment of the present application provides a display device, including a display panel, a gate driver and an emission driver.
  • the display panel includes a plurality of sub-pixels;
  • the gate driver includes a first gate driving unit and a second gate driving unit, the first gate driving unit is configured to output a first scanning signal to the sub-pixel, and the second gate driving unit is configured to output a second scanning signal to the sub-pixel;
  • the emission driver is configured to output a light emitting control signal to the sub-pixel.
  • the display panel has a plurality of display cycles, at least one of the display cycles includes a write frame and a plurality of hold frames, each of the write frame and the plurality of hold frames has a first duration.
  • the light emitting control signal has a plurality of cycles, and the ratio of the number of cycles of the light emitting control signal to the first duration is greater than a critical flicker frequency.
  • the light-emitting control signal has a valid pulse and an invalid pulse in each of the cycles
  • the first scanning signal has a valid pulse within the action time of each invalid pulse of the light-emitting control signal in the write frame and the plurality of hold frames
  • the second scanning signal has a valid pulse within the action time of the invalid pulse in the first cycle of the light-emitting control signal in the write frame.
  • the present application provides a display device, which includes a display panel, a gate driver and an emission driver, wherein the gate driver includes a first gate driving unit and a second gate driving unit that output a first scan signal and a second scan signal to a sub-pixel of the display panel, and the emission driver outputs a light-emitting control signal to the sub-pixel.
  • the display panel includes a plurality of display cycles, and at least one display cycle has a write frame and a plurality of hold frames.
  • the sub-pixel can realize multiple switching between display state and non-display state in the write frame and the plurality of hold frames respectively under the control of the light-emitting control signal, thereby reducing the audience's perception of the flicker problem of the display panel within the total duration corresponding to the write frame and the plurality of hold frames, so that the display panel has better display performance.
  • the sub-pixels are controlled by the light-emitting control signal, the first scanning signal and the second scanning signal to realize multiple switching of display states and non-display states according to the same display content in the write frame and multiple hold frames respectively, so that the information displayed by multiple sub-pixels is the same within the total time corresponding to the write frame and multiple hold frames, so as to achieve the purpose of taking into account both display performance and battery life performance.
  • FIG1 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • FIG2 is a diagram showing the perception of flicker by the human eye provided by an embodiment of the present application.
  • FIG3 is a schematic diagram of the structure of a sub-pixel provided in an embodiment of the present application.
  • FIG4 is a timing diagram corresponding to a high frequency driving mode provided by an embodiment of the present application.
  • FIG5 is a schematic diagram showing a principle of increasing the duration corresponding to each frame provided by an embodiment of the present application.
  • FIG6 is a timing diagram of writing frames in an ultra-low frequency driving mode provided by an embodiment of the present application.
  • FIG7 is a schematic diagram of the measured results of the light emitting waveform with a brightness of 50 nit provided in an embodiment of the present application;
  • FIG8 is a timing diagram of a display cycle in an ultra-low frequency driving mode provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of power consumption test results provided in an embodiment of the present application.
  • Fig. 1 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • the present application provides a display device, including a display panel and a drive control module.
  • the display panel includes a self-luminous display panel.
  • the self-luminous display panel includes an organic light emitting diode display panel, a sub-millimeter light emitting diode display panel, a micro light emitting diode display panel, a quantum dot display panel, etc.
  • the display panel includes a plurality of sub-pixels SP, a plurality of scan lines, a plurality of data lines, and a plurality of light-emitting control lines.
  • the plurality of sub-pixels SP form a plurality of pixel units Pi arranged in an array, and the plurality of scan lines, the plurality of data lines, and the plurality of light-emitting control lines are electrically connected to the plurality of sub-pixels SP, so that the plurality of sub-pixels SP realize a display function according to corresponding scan signals, data signals Data, and light-emitting control signals EM.
  • each pixel unit Pi includes three sub-pixels SP.
  • the three sub-pixels SP included in each pixel unit Pi emit different luminous colors, wherein the luminous colors of the sub-pixels SP include red, green, blue, yellow, white, etc.
  • the driving control module includes a gate driver, an emission driver and a data driver.
  • the gate driver is configured to output a scan signal to the display panel.
  • the gate driver is electrically connected to a plurality of scan lines to transmit the scan signal to a plurality of sub-pixels SP through the plurality of scan lines.
  • the gate driver includes a first gate driving unit and a second gate driving unit.
  • the first gate driving unit is configured to output a first scanning signal Pscan1 to the display panel.
  • the second gate driving unit is configured to output a second scanning signal Pscan2 to the display panel.
  • the emission driver is configured to output the emission control signal EM to the display panel.
  • the emission driver is electrically connected to a plurality of emission control lines to output the emission control signal EM to a plurality of sub-pixels SP through the plurality of emission control lines.
  • the data driver is configured to output the data signal Data to the display panel.
  • the data driver is electrically connected to a plurality of data lines to output the data signal Data to a plurality of sub-pixels SP through the plurality of data lines.
  • the driving controller includes a receiver, a register, a timing controller, a memory controller, a random access memory and a dynamic frame rate module.
  • the driving controller controls the gate driver, the data driver and the emission driver to realize the control of the display state of multiple pixel units Pi as follows:
  • Phase 1 The receiver outputs instruction c to the register according to the register instruction a sent by the host, and the register is configured according to instruction c.
  • the second stage the host sends image data signal b to the receiver at a certain time interval (such as one minute), the receiver outputs image data signal d to the memory controller according to the image data signal b sent by the host, and the memory controller outputs image data signal f to the random access memory according to the image data signal d.
  • a certain time interval such as one minute
  • the third stage the register outputs the instruction e of the corresponding timing control setting to the timing controller, the random access memory outputs the image data signal h to the timing controller according to the image data signal f, and the dynamic frame rate module outputs the high-frequency switching instruction i to the timing controller after detecting that the random access memory has an updated data signal g.
  • the fourth stage the timing controller sends the corresponding high-frequency switching instruction j to the gate driver, the emission driver and the data driver respectively, so as to control the display panel to realize display of the plurality of sub-pixels SP in the high-frequency driving mode through the gate driver, the emission driver and the data driver.
  • Phase 5 The host stops outputting the image data signal to the receiver, the dynamic frame rate module detects that there is no updated data signal g in the random access memory, and outputs the low-frequency switching instruction i to the timing controller.
  • Phase 6 The timing controller sends the corresponding low-frequency switching instruction j to the gate driver, the emission driver and the data driver respectively, so as to control the display panel to realize display of the plurality of sub-pixels SP in the ultra-low-frequency driving mode through the gate driver, the emission driver and the data driver.
  • the display panel may have multiple display cycles. In order to realize the variable frequency technology, the duration corresponding to each display cycle of the display panel may be different.
  • the display cycle may only include one write frame WF.
  • the display panel may include one write frame WF and at least one hold frame HF.
  • the data signal Data is written to the sub-pixel SP within the effective pulse action time of the second scan signal Pscan2 in the write frame WF, and the data signal Data written to the sub-pixel SP in the write frame WF is maintained in the hold frame HF, so that when the display panel adopts the frequency lower than the high-frequency driving mode to realize the display, the information displayed by the display panel within the total duration tsu corresponding to a display cycle is the same.
  • the display panel can be made to use an ultra-low frequency to display.
  • the ultra-low frequency refers to a frequency less than 1Hz.
  • the display panel uses an ultra-low frequency to display, it will cause a more serious flicker problem.
  • each of the write frame WF and the multiple hold frames HF have a first duration tfr
  • the light control signal EM has multiple periods T
  • the ratio of the number of periods Ncft of the light control signal EM to the first duration tfr is greater than the critical flicker frequency CFF, that is, Ncft/tfr>CFF, so that the sub-pixel SP can realize multiple switching between the display state and the non-display state in the write frame WF and the multiple hold frames HF under the control of the light control signal EM, thereby reducing the audience's perception of the flicker problem of the display panel within the total duration tsu corresponding to the write frame WF and the multiple hold frames HF, so that the display panel has better display performance.
  • the first scanning signal Pscan1 has a valid pulse during the action time of each invalid pulse of the light-emitting control signal EM in the write frame WF and multiple holding frames HF
  • the second scanning signal Pscan2 has a valid pulse during the action time of the invalid pulse in the first cycle of the light-emitting control signal EM in the write frame WF, so that within the total duration tsu corresponding to a display cycle, the sub-pixel SP can be controlled by the light-emitting control signal EM, the first scanning signal Pscan1 and the second scanning signal Pscan2 to switch between the display state and the non-display state multiple times according to the same display content in the write frame WF and multiple holding frames HF, so that the information displayed by multiple sub-pixels SP is the same within the total duration tsu corresponding to the write frame WF and multiple holding frames HF, so as to achieve the purpose of taking into account both display performance and
  • the critical flicker frequency CFF is the minimum flicker frequency that can be perceived as stable light by human eyes.
  • the critical flicker frequency CFF is greater than or equal to 45 Hz.
  • the critical flicker frequency CFF is closely related to many factors such as display brightness, ambient brightness, and viewing distance and is not a constant. According to FIG2 , when the frequency is greater than or equal to 60 Hz, the human eye cannot perceive the flicker problem.
  • the ratio of the number of cycles Ncft of the light-emitting control signal EM in each of the write frame WF and the plurality of hold frames HF to the first duration tfr can be made greater than or equal to 60 Hz; that is, Ncft/tfr ⁇ 60 Hz, so as to ensure that when the display device is actually used, the human eye cannot perceive the flicker problem on the display screen.
  • a display cycle includes a total of frames.
  • the number m needs to be less than or equal to the upper limit SKL of frame skipping that can be provided in the driving control module; that is: m ⁇ SKL.
  • the ratio of the total duration tsu corresponding to a display cycle to the first duration tfr is less than or equal to the upper limit SKL of frame skipping that can be provided in the driving control module; that is, sut/tfr ⁇ SKL.
  • the upper limit SKL of frame skipping that can be provided in the driving control module is determined by the number of bits of the register for controlling the number of frame skipping included in the driving control module.
  • the register for controlling the number of frame skipping is xbit
  • the upper limit SKL of frame skipping is equal to 2 ⁇ x
  • the register for controlling the number of frame skipping is 8bit
  • the register for controlling the number of frame skipping is 10bit
  • the registers shown in Figure 1 represent all the registers included in the display device, and are not only used to represent the register for controlling the number of frame skipping.
  • the target frequency f1 of the second scan signal Pscan2 within the total duration tsu corresponding to a display cycle can be less than 1Hz, i.e., f1 ⁇ 1Hz, so that the sub-pixel SP updates the display information according to each display cycle, thereby enabling the display panel to achieve ultra-low frequency display.
  • the target frequency f1 is the frequency used when the display panel adopts an ultra-low frequency driving mode to realize display. That is, the target frequency f1 can be equal to 0.99Hz, 0.98Hz, ..., 0.9Hz, 0.89Hz, ..., 0.75Hz, ..., 0.5Hz, ..., 0.11Hz, 0.1Hz, 0.099Hz, 0.098Hz, ..., 0.09Hz, 0.089Hz, ..., 0.08Hz, 0.079Hz, ..., 0.07Hz, 0.069Hz, ..., 0.064Hz, ..., 0.06Hz, ..., 0.05Hz, ..., 0.04Hz, ..., 0.032Hz, ..., 0.03Hz, ..., 0.02Hz, ..., 0.016Hz, 0.015Hz, ..., 0.01Hz, 0.009Hz, 0.008Hz ..., 0.006Hz, 0.005Hz, 0.004Hz ... and so on.
  • the product of the basic frequency f3 of the second scanning signal Pscan2 and the number of cycles Ncft of the light control signal EM is equal to the intermediate frequency f2 of the light control signal EM, so that within the first time length tfr corresponding to each of the write frame WF and multiple hold frames HF, the number of cycles Ncft included in the light control signal EM meets the requirements, thereby making the display picture of the display panel meet the display performance requirements.
  • FIG3 is a schematic diagram of the structure of the sub-pixel SP provided in an embodiment of the present application. It can be understood that the structure of the sub-pixel SP is not limited to the form shown in FIG3.
  • Each sub-pixel SP includes a driving transistor Tdr, a first reset transistor Ti1, a second reset transistor Ti2, a data transistor Tda, a light emitting control transistor, and a light emitting device D.
  • the driving transistor Tdr is configured to generate a driving current according to the data signal Data to drive the light emitting device D to emit light.
  • the driving transistor Tdr includes an input electrode connected to the first node N1, an output electrode connected to the second node N2, and a control electrode connected to the third node N3.
  • the control electrode is the gate, the input electrode is one of the source and the drain, and the output electrode is the other of the source and the drain.
  • the first reset transistor Ti1 is configured to reset the anode potential of the light emitting device D according to the first scan signal Pscan1.
  • the first reset transistor Ti1 includes a control electrode configured to receive the first scan signal Pscan1, an input electrode configured to receive the first reset signal VI1, and an output electrode connected to the fourth node N4.
  • the second reset transistor Ti2 is configured to reset the input electrode potential and the output electrode potential of the driving transistor Tdr according to the first scanning signal Pscan1.
  • the second reset transistor Ti2 includes a control electrode configured to receive the first scanning signal Pscan1, an input electrode configured to receive the second reset signal VI2, and an output electrode connected to the first node N1.
  • the first reset transistor Ti1 and the second reset transistor Ti2 are under the influence of the level state corresponding to the effective pulse of the first scanning signal Pscan1. It is turned on and is turned off under the action of the level state corresponding to the invalid pulse of the first scanning signal Pscan1.
  • the data transistor Tda is configured to transmit the data signal Data to the driving transistor Tdr through the first node N1 according to the second scan signal Pscan2.
  • the data transistor Tda includes a control electrode configured to receive the second scan signal Pscan2, an input electrode configured to receive the data signal Data, and an output electrode connected to the first node N1.
  • the data transistor Tda is turned on under the action of the level state corresponding to the valid pulse of the second scan signal Pscan2, and is turned off under the action of the level state corresponding to the invalid pulse of the second scan signal Pscan2.
  • the light emitting control transistor is configured to control the on and off of the flow path of the driving current according to the light emitting control signal EM.
  • the light emitting control transistor includes a first switch transistor Ts1 and a second switch transistor Ts2;
  • the first switch transistor Ts1 includes a control electrode configured to receive the light emitting control signal EM, an input electrode configured to be connected to the first power supply terminal VDD, and an output electrode connected to the first node N1;
  • the second switch transistor Ts2 includes a control electrode configured to receive the light emitting control signal EM, an input electrode configured to be connected to the second node N2, and an output electrode connected to the fourth node N4.
  • the first switch transistor Ts1 and the second switch transistor Ts2 are turned on under the action of the level state corresponding to the effective pulse of the light emitting control signal EM, and are turned off under the action of the level state corresponding to the invalid pulse of the light emitting control signal EM.
  • the light emitting device D includes an anode connected to the fourth node N4 and a cathode configured to be connected to the second power supply terminal VSS.
  • the light emitting device D includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, or the like.
  • the gate driver further includes a third gate driving unit, and the third gate driving unit is configured to output the third scanning signal Nscan1 and the fourth scanning signal Nscan2 to the sub-pixel SP.
  • the third scanning signal Nscan1 and the fourth scanning signal Nscan2 both have a valid pulse within the action time of the invalid pulse in the first cycle of the light emitting control signal EM in the write frame WF, so as to initialize the potential of the third node N3 in the write frame WF, and transmit the data signal Data to the gate of the driving transistor Tdr in the write frame WF, so as to keep the sub-pixel SP displayed in the hold frame HF according to the data signal Data written into the sub-pixel SP in the write frame WF.
  • the sub-pixel SP further includes a compensation transistor Tc, a third reset transistor Ti3 and a storage capacitor Cst.
  • the compensation transistor Tc includes a control electrode configured to receive the third scan signal Nscan1, The input electrode is connected to the third node N3 and the output electrode is connected to the second node N2.
  • the third reset transistor Ti3 includes a control electrode receiving the fourth scan signal Nscan2, an input electrode configured to receive the third reset signal VI3, and an output electrode connected to the third node N3.
  • the storage capacitor Cst includes a first electrode configured to be connected to the first power terminal VDD and a second electrode connected to the third node N3.
  • the active layer of the compensation transistor Tc and the active layer of the third reset transistor Ti3 both include oxide semiconductors
  • the active layer of the driving transistor Tdr, the active layer of the first reset transistor Ti1, the active layer of the second reset transistor Ti2, the active layer of the data transistor Tda, and the active layer of the light-emitting control transistor all include silicon semiconductors.
  • the silicon semiconductor includes materials such as single crystal silicon, polycrystalline silicon, and amorphous silicon
  • the oxide semiconductor includes at least one of materials such as zinc oxide, zinc tin oxide, zinc indium oxide, indium oxide, titanium oxide, indium gallium zinc oxide, and indium zinc tin oxide.
  • the driving transistor Tdr, the first reset transistor Ti1, the second reset transistor Ti2, the data transistor Tda, and the light-emitting control transistor are made using a low-temperature polysilicon process.
  • the potential of the first node N1, the potential of the second node N2, the potential of the third node N3 and the potential of the fourth node N4 are kept equal when the sub-pixel SP realizes multiple non-display states or display states in the corresponding writing frame WF and each holding frame HF.
  • the potentials of the first node N1 remain equal, the potentials of the second node N2 remain equal, the potentials of the third node N3 remain equal, and the potentials of the fourth node N4 remain equal to improve the flicker problem.
  • the voltage value of the second reset signal VI2 can be controlled to achieve that during the action time of multiple invalid pulses of the light emitting control signal EM, the potential of the first node N1 and the potential of the second node N2 remain equal.
  • the driving transistor Tdr is a P-type transistor, and during the action time of each valid pulse of the first scanning signal Pscan1, the difference between the potential of the third node N3 and the second reset signal VI2 is less than the threshold voltage of the driving transistor Tdr, so that when the second reset transistor Ti2 is turned on, the driving transistor Tdr is also turned on, so that the second reset transistor Ti2 resets the input electrode potential (i.e., the potential of the first node N1) and the output electrode potential (i.e., the potential of the second node N2) of the driving transistor Tdr according to the first scanning signal Pscan1.
  • FIG4 is a timing diagram corresponding to the high-frequency driving mode provided by an embodiment of the present application.
  • the corresponding frequency is 60 Hz
  • the driving transistor Tdr the first reset transistor Ti1, and the second reset transistor
  • the driving transistor Tdr the driving transistor Tdr
  • the first reset transistor Ti1 the driving transistor Tdr
  • the second reset transistor Taking the transistor Ti2, the data transistor Tda, the first switch transistor Ts1 and the second switch transistor Ts2 as P-type transistors, the compensation transistor Tc and the third reset transistor Ti3 as N-type transistors as an example, the working principle of the sub-pixel SP shown in FIG3 is described.
  • a display cycle only includes a writing frame WF, and the writing frame WF includes an initialization phase P1, a data writing phase P2, a node reset phase P3 and a light emitting phase P4.
  • Initialization stage P1 the light-emitting control signal EM, the first scanning signal Pscan1, the second scanning signal Pscan2, the third scanning signal Nscan1 and the fourth scanning signal Nscan2 are all in a high-level state, the third reset transistor Ti3 is turned on in response to the fourth scanning signal Nscan2, the compensation transistor Tc is turned on in response to the third scanning signal Nscan1 so that the driving transistor Tdr is diode-connected, the driving transistor Tdr is turned on, and the third reset signal resets the potentials of the third node N3, the second node N2 and the first node N1.
  • the first reset transistor Ti1 and the second reset transistor Ti2 are both turned off in response to the first scanning signal Pscan1, the data transistor Tda is turned off in response to the second scanning signal Pscan2, and the first switch transistor Ts1 and the second switch transistor Ts2 are both turned off in response to the light-emitting control signal EM.
  • Data writing stage P2 the light emitting control signal EM, the first scanning signal Pscan1 and the third scanning signal Nscan1 all correspond to the high level state, the second scanning signal Pscan2 and the fourth scanning signal Nscan2 all correspond to the low level state, the data transistor Tda is turned on in response to the second scanning signal Pscan2, the compensation transistor Tc is turned on in response to the third scanning signal Nscan1 so that the driving transistor Tdr is diode-connected, the driving transistor Tdr is turned on, and the data signal Data is transmitted to the third node N3 via the data transistor Tda, the first node N1, the driving transistor Tdr, the second node N2 and the compensation transistor Tc, so as to realize the writing of the data signal Data and the capture of the threshold voltage of the driving transistor Tdr.
  • the first reset transistor Ti1 and the second reset transistor Ti2 are both turned off in response to the first scanning signal Pscan1, the first switch transistor Ts1 and the second switch transistor Ts2 are turned off in response to the light emitting control signal EM, and the third reset transistor Ti3 is turned off in response to the fourth scanning signal Nscan2.
  • Node reset stage P3 The light emitting control signal EM and the second scanning signal Pscan2 are both in a high level state, the first scanning signal Pscan1, the third scanning signal Nscan1 and the fourth scanning signal Nscan2 are both in a low level state, the first reset transistor Ti1 and the second reset transistor Ti2 are both turned on in response to the first scanning signal Pscan1, and the first reset signal VI1 resets the potential of the fourth node N4.
  • the second reset signal VI2 has a higher voltage value, and the voltage difference between the gate and the source of the driving transistor Tdr is the voltage difference between the third node N3 and the first node N1.
  • the driving transistor Tdr can be turned on, thereby making the third node N3 and the first node N1 smaller than the threshold voltage of the driving transistor Tdr.
  • the second reset signal VI2 resets the potential of the first node N1 and the second node N2.
  • the data transistor Tda is turned off in response to the second scan signal Pscan2
  • the compensation transistor Tc is turned off in response to the third scan signal Nscan1
  • the third reset transistor Ti3 is turned off in response to the fourth scan signal Nscan2
  • the first switch transistor Ts1 and the second switch transistor Ts2 are both turned off in response to the light emitting control signal EM.
  • Light-emitting stage P4 the light-emitting control signal EM, the third scanning signal Nscan1 and the fourth scanning signal Nscan2 all correspond to the low level state, the first scanning signal Pscan1 and the second scanning signal Pscan2 all correspond to the high level state, the first switching transistor Ts1 and the second switching transistor Ts2 are both turned on in response to the light-emitting control signal EM, the driving transistor Tdr remains turned on under the action of the storage capacitor, and the driving current generated by the driving transistor Tdr according to the data signal Data flows in the path between the first power supply terminal VDD and the second power supply terminal VSS, so that the light-emitting device D emits light.
  • the first reset transistor Ti1 and the second reset transistor Ti2 are both turned off in response to the first scanning signal Pscan1, the data transistor Tda is turned off in response to the second scanning signal Pscan2, the compensation transistor Tc is turned off in response to the third scanning signal Nscan1, and the third reset transistor Ti3 is turned off in response to the fourth scanning signal Nscan2.
  • Vth in Table 1 is the threshold voltage of the driving transistor Tdr, and Lum.vo indicates that the potential is actually affected by the change of the charging and discharging state in the circuit and has a certain fluctuation.
  • the duration of each frame (1Frame) included in a display cycle under the corresponding ultra-low frequency driving mode is increased, and then the display function of the ultra-low frequency driving mode is realized by combining the frame skipping method.
  • FIG5 is a schematic diagram of increasing the duration of each frame provided by an embodiment of the present application.
  • VBP represents the vertical back porch
  • VFP represents the vertical front porch
  • HBP represents the horizontal back porch
  • HFP represents the horizontal front porch
  • y1, y3 and y5 all represent the number of rows of the pixel unit Pi
  • y2, y4 and y6 all represent the number of columns of the pixel unit Pi; y1 ⁇ y3 ⁇ y5; y2 ⁇ y4 ⁇ y6.
  • the driving control module may be made to believe that the number of scanning lines V-proch to be controlled N V-porch is greater than the number of rows of pixel units Pi, and/or the number of scanning pixel units Pi to be controlled in each row N H-line is greater than the number of columns of pixel units Pi.
  • the number of scanning lines V-proch to be controlled N V-porch is increased, so that the number of rows to be scanned in each frame increases, thereby increasing the duration corresponding to each frame;
  • the scanning time N H-line /f osc of the pixel units Pi to be controlled in each row is increased, thereby increasing the duration corresponding to each frame;
  • the number of scanning lines V-proch to be controlled N V-porch and the scanning time N H-line /f osc of the pixel units Pi to be controlled in each row are increased, thereby increasing the duration corresponding to each frame.
  • f osc represents the crystal oscillator frequency of the driving control module
  • 1/f osc represents the time required for the driving control module to control one pixel unit Pi to realize display.
  • the timing is optimized.
  • the display panel uses a high-frequency driving mode to realize display and uses an ultra-low frequency driving mode to realize display.
  • the working principle is similar.
  • the ultra-low driving mode is used to realize display, the light-emitting stage P4 includes multiple light-emitting sub-stages and multiple non-light-emitting sub-stages.
  • the light-emitting control signal EM has a valid pulse
  • the first scan signal Pscan1, the second scan signal Pscan2, the third scan signal Nscan1, and the fourth scan signal Nscan2 all have invalid pulses, so that the first switch transistor Ts1 and the second switch transistor Ts2 are both turned on in response to the light-emitting control signal EM, and the driving transistor Tdr generates a driving current according to the data signal Data in the path between the first power supply terminal VDD and the second power supply terminal VSS to control the light-emitting device D to emit light.
  • the light-emitting control signal EM, the third scan signal Nscan1, and the fourth scan signal Nscan2 all have invalid pulses
  • the first The scanning signal Pscan1 has a valid pulse within the duration of the invalid pulse of the light emitting control signal EM
  • the maintenance duration of the valid pulse of the first scanning signal Pscan1 is less than or equal to the maintenance duration of the invalid pulse of the light emitting control signal EM, so that the first reset transistor Ti1 and the second reset transistor Ti2 are both turned on in response to the first scanning signal Pscan1, thereby resetting the potential of the fourth node N4 by using the first reset signal VI1, and the second reset signal VI2 has a higher voltage value to turn on the driving transistor Tdr, thereby resetting the potential of the first node N1 and the second node N2 by using the second reset signal VI2.
  • FIG. 6 is a timing diagram of writing frame WF in the corresponding ultra-low frequency driving mode provided by an embodiment of the present application; taking the first duration tfr corresponding to the writing frame WF, the second scanning signal Pscan2 has a basic frequency f3 of 16Hz, the driving transistor Tdr, the first reset transistor Ti1, the second reset transistor Ti2, the data transistor Tda, the first switch transistor Ts1 and the second switch transistor Ts2 are all P-type transistors, and the compensation transistor Tc and the third reset transistor Ti3 are all N-type transistors as an example, the working principle of the light-emitting stage P4 in the corresponding ultra-low frequency driving mode of the sub-pixel SP shown in Figure 3 is described.
  • the light-emitting stage P4 includes the first light-emitting sub-stage P41, the first non-light-emitting sub-stage P42, the second light-emitting sub-stage P43, the second non-light-emitting sub-stage P44, the third light-emitting sub-stage P45, the third non-light-emitting sub-stage P46, and the fourth light-emitting sub-stage P47.
  • the light-emitting control signal EM the third scan signal Nscan1 and the fourth scan signal Nscan2 all correspond to a low level state
  • the first scan signal Pscan1 and the second scan signal Pscan2 all correspond to a high level state
  • the first switching transistor Ts1 and the second switching transistor Ts2 are both turned on in response to the light-emitting control signal EM
  • the driving transistor Tdr remains turned on under the action of the storage capacitor Cst.
  • the driving current generated by the driving transistor Tdr according to the data signal Data flows in the path between the first power supply terminal VDD and the second power supply terminal VSS to make the light-emitting device D emit light.
  • the light-emitting control signal EM and the second scanning signal Pscan2 both correspond to a high level state
  • the third scanning signal Nscan1 and the fourth scanning signal Nscan2 both correspond to a low level state
  • the first scanning signal Pscan1 has a low level state for a certain period of time during the time when the light-emitting control signal EM corresponds to the high level state.
  • the first reset transistor Ti1 and the second reset transistor Ti2 are both turned on in response to the first scanning signal Pscan1, and the first reset transistor Ti1 is turned on in response to the first reset transistor Ti2.
  • the reset signal VI1 resets the potential of the fourth node N4.
  • the second reset signal VI2 has a relatively high voltage value to turn on the driving transistor Tdr.
  • the second reset signal VI2 resets the potentials of the first node N1 and the second node N2.
  • the potential of the first node N1 remains equal, the potential of the second node N2 remains equal, the potential of the third node N3 remains equal, and the potential of the fourth node N4 remains equal.
  • the potential of the first node N1 remains equal, the potential of the second node N2 remains equal, the potential of the third node N3 remains equal, and the potential of the fourth node N4 remains equal, so that the display brightness of the sub-pixel SP in each light-emitting sub-stage can be kept consistent.
  • the luminous stage include multiple luminous sub-stages and multiple non-luminous sub-stages, the display brightness of the sub-pixel SP in each luminous sub-stage can be kept consistent, and the flicker problem can also be improved.
  • the second scan signal Pscan2 has a base frequency f3 of 16 Hz, and the number of cycles Ncft of the light-emitting control signal EM is 4, and thus the intermediate frequency f2 of the light-emitting control signal EM is 64 Hz.
  • the number of cycles Ncft of the light-emitting control signal EM can be determined based on the sum of the number of light-emitting sub-stages and the number of non-light-emitting sub-stages included in the write frame WF.
  • the stage corresponding to the initialization stage P1, the data writing stage P2, and the node reset stage P3 of the write frame WF also belongs to a non-light-emitting sub-stage, and the non-light-emitting sub-stage composed of the initialization stage P1, the data writing stage P2, and the node reset stage P3, and the light-emitting sub-stage and the non-light-emitting sub-stage included in the light-emitting stage.
  • the sum of the segments is equal to twice the number of cycles Ncft of the light emitting control signal EM; that is, each cycle T of the light emitting control signal EM actually corresponds to a non-light emitting sub-stage and a light emitting sub-stage.
  • the number of cycles Ncft of the light-emitting control signal EM is an integer, so that when frame skipping is performed subsequently to achieve an ultra-low frequency display mode, the number of light-emitting sub-stages and non-light-emitting sub-stages included in each frame can be kept equal.
  • the light-emitting stage also corresponds to a plurality of light-emitting sub-stages and a plurality of non-light-emitting sub-stages.
  • the number of light-emitting sub-stages included in each holding frame HF is equal to the number of light-emitting sub-stages included in the writing frame WF
  • the number of non-light-emitting sub-stages included in each holding frame HF is equal to the number of non-light-emitting sub-stages included in the writing frame WF, so that the writing frame WF and each holding frame HF have a first duration tfr.
  • Figure 8 is a timing diagram corresponding to a display cycle under the ultra-low frequency driving mode provided by an embodiment of the present application; within the total duration tsu corresponding to a display cycle, the target frequency f1 of the second scanning signal Pscan2 is 0.016Hz; within the first duration tfr corresponding to the write frame WF, the base frequency f3 of the second scanning signal Pscan2 is 16Hz, combined with the sub-pixel shown in Figure 3, the number of frame skips corresponding to a display cycle when the ultra-low frequency driving mode is adopted is explained.
  • each holding frame HF the sub-pixel SP switches between the non-display state and the display state under the control of the light emission control signal EM.
  • the number of frame skipping SKF is equal to the number of multiple hold frames HF included in one display cycle, i.e., the number of frame skipping SKF is equal to 999.
  • the frame skipping number SKF is an integer, so that each display cycle includes an integer number of write frames WF and hold frames HF.
  • the frame skipping number SKF is less than the frame skipping upper limit SKL, so that the display device can achieve the target frequency to be achieved.
  • the display panel By including a writing frame WF and a plurality of holding frames HF in one display cycle, the display panel displays the same display content within the total time length tsu corresponding to one display cycle, and since the sub-pixel SP switches between the display state and the non-display state for multiple times within the first time length tfr corresponding to the writing frame WF and each holding frame HF, the human eye cannot perceive that the display panel switches between the display state and the non-display state within the total time length tsu corresponding to one display cycle. There is a flickering issue.
  • the number of cycles Ncft of the light-emitting control signal EM is greater than or equal to the ratio of the minimum intermediate frequency to the maximum basic frequency; that is, Ncft ⁇ fmin/fmax.
  • the maximum basic frequency fmax can be determined according to the frame skipping upper limit SKL and the target frequency f1.
  • the ratios of multiple basic frequencies f3 and the target frequency f1 are respectively used to make differences with the frame skipping upper limit SKL to obtain multiple first differences, and the basic frequency f3 corresponding to the minimum difference among the multiple first differences is the maximum basic frequency fmax.
  • the ratios of the multiple basic frequencies f3 and the target frequency f1 are all less than the frame skipping upper limit SKL.
  • the minimum intermediate frequency fmin can be determined according to the product of the critical flicker frequency CFF and the number of cycles Ncft. For example, a plurality of intermediate frequencies f2 are respectively used to make differences with the critical flicker frequency CFF to obtain a plurality of second differences, and the intermediate frequency f2 corresponding to the minimum difference among the plurality of second differences is the minimum intermediate frequency fmin. Among them, the plurality of intermediate frequencies f2 are all greater than the critical flicker frequency CFF.
  • Table 4 is a flicker test result table corresponding to a basic frequency f3 of 16 Hz, an intermediate frequency f2 of 64 Hz, and a target frequency f1 of 0.016 Hz.
  • FIG9 is a schematic diagram of the power consumption test results provided by an embodiment of the present application.
  • 25% OPR means that 25% of the display area of the screen is luminous
  • 10% OPR means that 25% of the display area of the screen is luminous.
  • the ultra-low frequency drive mode used in the present application for display reduces power consumption by 14.1% when corresponding to 25% OPR, and reduces power consumption by 18.4% when corresponding to 10% OPR. Therefore, the purpose of reducing power consumption can be achieved, and the display device can have better endurance.
  • the display device includes a mobile display device (such as a laptop computer, a mobile phone, etc.), a fixed terminal (such as a desktop computer, a television, etc.), a measuring device (such as a sports bracelet, a thermometer, etc.), etc.
  • a mobile display device such as a laptop computer, a mobile phone, etc.
  • a fixed terminal such as a desktop computer, a television, etc.
  • a measuring device such as a sports bracelet, a thermometer, etc.

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Abstract

本申请提供一种显示装置，包括显示面板、栅极驱动器及发射驱动器。在写入帧和每一保持帧对应的第一时长内，发光控制信号具有的周期数与第一时长之比大于临界闪烁频率，第一扫描信号的有效脉冲与发光控制信号的无效脉冲对应，第二扫描信号的有效脉冲位于发光控制信号对应写入帧的第一个周期的无效脉冲作用时间内。

Description

显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示装置。
背景技术
随着智能手机、智能手表等显示装置的不断更新迭代，用户对显示装置的显示性能要求和续航性能要求越来越高。但在实际使用时，使显示装置具有较高的显示性能，往往会增大功耗，继而降低了续航能力，而为提高续航能力，就需牺牲显示性能，因而显示装置无法兼顾显示性能要求和续航性能要求。
技术问题
本申请实施例提供一种显示装置，可以兼顾显示性能要求和续航性能要求。
技术解决方案
本申请实施例提供一种显示装置，包括显示面板、栅极驱动器以及发射驱动器。所述显示面板包括多个子像素；所述栅极驱动器包括第一栅极驱动单元和第二栅极驱动单元，所述第一栅极驱动单元被配置为将第一扫描信号输出至所述子像素，所述第二栅极驱动单元被配置为将第二扫描信号输出至所述子像素；所述发射驱动器被配置为将发光控制信号输出至所述子像素。
其中，所述显示面板具有多个显示周期，至少一所述显示周期包括一写入帧和多个保持帧，所述写入帧和多个所述保持帧中的每一个均具有第一时长。在所述写入帧和多个所述保持帧中的每一个内，所述发光控制信号具有多个周期，所述发光控制信号的周期数与所述第一时长之比大于临界闪烁频率。
所述发光控制信号在每一所述周期内均具有一有效脉冲和一无效脉冲，所述第一扫描信号在所述写入帧和多个所述保持帧中的所述发光控制信号的每一所述无效脉冲的作用时间内具有一有效脉冲，所述第二扫描信号在所述写入帧中的所述发光控制信号的第一个所述周期内的所述无效脉冲的作用时间内具有一有效脉冲。
有益效果
本申请提供一种显示装置，显示装置包括显示面板、栅极驱动器及发射驱动器，栅极驱动器包括将第一扫描信号和第二扫描信号输出至显示面板的子像素的第一栅极驱动单元和第二栅极驱动单元，发射驱动器将发光控制信号输出至子像素。显示面板包括多个显示周期，至少一显示周期具有一写入帧和多个保持帧。在写入帧和每一保持帧内对应的第一时长内，通过使发光控制信号具有的周期数与第一时长之比大于临界闪烁频率，以使子像素在发光控制信号的控制下分别于写入帧和多个保持帧内实现多次显示状态和不显示状态的切换，从而在写入帧和多个保持帧对应的总时长内降低受众对显示面板闪烁问题的感受，使显示面板具有较好的显示性能。通过使第一扫描信号具有的有效脉冲与发光控制信号具有的无效脉冲一一对应，且使第二扫描信号的有效脉冲仅位于写入帧的发光控制信号的第一个周期内的无效脉冲的作用时间内，以在一显示周期对应的总时长内，使子像素在发光控制信号、第一扫描信号和第二扫描信的控制下分别于写入帧和多个保持帧内按照相同的显示内容实现多次显示状态和不显示状态的切换，从而在写入帧和多个保持帧对应的总时长内使多个子像素显示的信息相同，以实现兼顾显示性能和续航性能的目的。
附图说明
图1是本申请实施例提供的显示装置的结构示意图；
图2是本申请实施例提供的人眼对闪烁的感知图；
图3是本申请实施例提供的子像素的结构示意图；
图4是本申请实施例提供的对应高频驱动模式下的时序图；
图5是本申请实施例提供的提高每帧对应的时长的原理图；
图6是本申请实施例提供的对应超低频驱动模式下写入帧的时序图；
图7是本申请实施例提供的亮度为50nit的发光波形实测结果示意图；
图8是本申请实施例提供的对应超低频驱动模式下一显示周期的时序图；
图9是本申请实施例提供的功耗测试结果示意图。
本发明的实施方式
应当理解，此处所描述的实施例仅用以解释本申请，并不用于限定本申请。
具体地，如图1是本申请实施例提供的显示装置的结构示意图。本申请提供一种显示装置，包括显示面板及驱动控制模块。
可选地，显示面板包括自发光显示面板。可选地，自发光显示面板包括有机发光二极管显示面板、次毫米发光二极管显示面板、微型发光二极管显示面板、量子点显示面板等。
显示面板包括多个子像素SP、多条扫描线、多条数据线及多条发光控制线。多个子像素SP形成阵列排布的多个像素单元Pi，多条扫描线、多条数据线及多条发光控制线与多个子像素SP电性连接，以使多个子像素SP根据对应的扫描信号、数据信号Data及发光控制信号EM实现显示功能。
可选地，每一像素单元Pi包括三个子像素SP。可选地，每一像素单元Pi包括的三个子像素SP的发光颜色不同。其中，子像素SP的发光颜色包括红色、绿色、蓝色、黄色、白色等。
可选地，驱动控制模块包括栅极驱动器、发射驱动器及数据驱动器。
栅极驱动器被配置为将扫描信号输出至显示面板。可选地，栅极驱动器与多条扫描线电性连接，以通过多条扫描线将扫描信号传输至多个子像素SP。
可选地，栅极驱动器包括第一栅极驱动单元和第二栅极驱动单元。第一栅极驱动单元被配置为将第一扫描信号Pscan1输出至显示面板。第二栅极驱动单元被配置为将第二扫描信号Pscan2输出至显示面板。
发射驱动器被配置为将发光控制信号EM输出至显示面板。可选地，发射驱动器与多条发光控制线电性连接，以通过多条发光控制线将发光控制信号EM输出至多个子像素SP。
数据驱动器被配置为将数据信号Data输出至显示面板。可选地，数据驱动器与多条数据线电性连接，以通过多条数据线将数据信号Data输出至多个子像素SP。
可选地，驱动控制器包括接收器、寄存器、时序控制器、内存控制器、随机存取存储器及动态帧频模块。驱动控制器控制栅极驱动器、数据驱动器及发射驱动器实现多个像素单元Pi的显示状态的控制的原理如下：
第一阶段：接收器根据主机端送入的寄存器指令a向寄存器输出指令c，寄存器根据指令c进行配置。
第二阶段：主机端按一定时间间隔(如时间间隔为一分钟)向接收器送入图像数据信号b，接收器根据主机端送入的图像数据信号b向内存控制器输出图像数据信号d，内存控制器根据图像数据信号d向随机存取存储器输出图像数据信号f。
第三阶段：寄存器将相应时序控制设置的指令e输出至时序控制器，随机存取存储器根据图像数据信号f将图像数据信号h输出至时序控制器，动态帧频模块检测到随机存取存储器具有更新的数据信号g后将高频切换指令i输出至时序控制器。
第四阶段：时序控制器将对应的高频切换指令j分别送入栅极驱动器、发射驱动器及数据驱动器，以通过栅极驱动器、发射驱动器及数据驱动器控制显示面板以高频驱动模式使多个子像素SP实现显示。
第五阶段：主机端停止向接收器输出图像数据信号，动态帧频模块检测到随机存取存储器无更新的数据信号g，将低频切换指令i输出至时序控制器。
第六阶段：时序控制器将对应的低频切换指令j分别送入栅极驱动器、发射驱动器及数据驱动器，以通过栅极驱动器、发射驱动器及数据驱动器控制显示面板以超低频驱动模式使多个子像素SP实现显示。
为实现显示功能，显示面板可具有多个显示周期。为实现变频技术，显示面板的每一显示周期对应的时长可不同。在显示面板采用高频驱动模式实现显示时，显示周期内可仅包括一写入帧WF，在显示面板采用低于高频驱动模式的频率实现显示时，显示面板可包括一写入帧WF和至少一保持帧HF。数据信号Data于写入帧WF中的第二扫描信号Pscan2有效脉冲作用时间内被写入至子像素SP，并于保持帧HF内保持在写入帧WF写入到子像素SP的数据信号Data，以使显示面板在采用低于高频驱动模式的频率实现显示时，使显示面板于一显示周期对应的总时长tsu内显示的信息相同。
显示面板采用越低的频率实现显示，越有利于提升显示装置的续航性能。特别的，为提高显示装置的续航性能，可使显示面板采用超低频率实现显示。其中，超低频率是指频率小于1Hz的频率。但显示面板采用超低频率实现显示时，会引起较严重的闪烁问题。
为使显示面板可以应用超低频率实现显示的同时，改善闪烁问题，以实现 兼顾显示性能和续航性能的目的，本申请使写入帧WF和多个保持帧HF中的每一个均具有第一时长tfr，在写入帧WF和多个保持帧HF中的每一个内，发光控制信号EM具有多个周期T，发光控制信号EM的周期数Ncft与第一时长tfr之比大于临界闪烁频率CFF，即Ncft/tfr>CFF，以使子像素SP在发光控制信号EM的控制下分别于写入帧WF和多个保持帧HF内实现多次显示状态和不显示状态的切换，从而在写入帧WF和多个保持帧HF对应的总时长tsu内降低受众对显示面板闪烁问题的感受，使显示面板具有较好的显示性能。
通过使发光控制信号EM在每一周期内均具有一有效脉冲和一无效脉冲，第一扫描信号Pscan1在写入帧WF和多个保持帧HF中的发光控制信号EM的每一无效脉冲的作用时间内具有一有效脉冲，第二扫描信号Pscan2在写入帧WF中的发光控制信号EM的第一个周期内的无效脉冲的作用时间内具有一有效脉冲，以在一显示周期对应的总时长tsu内，使子像素SP在发光控制信号EM、第一扫描信号Pscan1和第二扫描信号Pscan2的控制下分别于写入帧WF和多个保持帧HF内按照相同的显示内容实现多次显示状态和不显示状态的切换，从而在写入帧WF和多个保持帧HF对应的总时长tsu内使多个子像素SP显示的信息相同，以实现兼顾显示性能和续航性能的目的。
其中，临界闪烁频率CFF为人眼所能感知成稳定光的最小闪烁光的频率。可选地，临界闪烁频率CFF大于或等于45Hz。
如图2是本申请实施例提供的人眼对闪烁的感知图，由于临界闪烁频率CFF与显示亮度、环境亮度、观看距离等诸多因素密切相关而不为常数，而根据图2可知，在频率大于或等于60Hz时，人眼便无法察觉到闪烁问题。因此，可以使发光控制信号EM在写入帧WF和多个保持帧HF中的每一个内的周期数Ncft与第一时长tfr之比大于或等于60Hz；即：Ncft/tfr≥60Hz，以确保显示装置在实际应用时，人眼感知不到显示画面存在闪烁问题。
可以理解的，一显示周期对应的总时长tsu即为一显示周期包括的写入帧WF和多个保持帧HF对应的多个第一时长tfr之和。即sut＝m*tfr；其中，m为帧总数，帧总数m为一显示周期内包括的写入帧WF和多个保持帧HF的数量之和。
可选地，为使显示面板能采用超低频率实现显示，一显示周期包括的帧总 数m需小于或等于驱动控制模块中所能提供的跳帧上限SKL；即：m≤SKL。相应的，一显示周期对应的总时长tsu与第一时长tfr之比小于或等于驱动控制模块中所能提供的跳帧上限SKL；即sut/tfr≤SKL。可选地，驱动控制模块中所能提供的跳帧上限SKL由驱动控制模块中所包括的控制跳帧数量的寄存器的位数确定。具体的，控制跳帧数量的寄存器的是xbit，则跳帧上限等于2^x；如控制跳帧数量的寄存器的是8bit，则跳帧上限SKL等于2^8＝256；控制跳帧数量的寄存器的是10bit，则跳帧上限SKL等于2^10＝1024。其中，图1中所示的寄存器表示显示装置中所包括的所有的寄存器，而不仅用于表示控制跳帧数量的寄存器。
可选地，由于数据信号Data于写入帧WF中的第二扫描信号Pscan2有效脉冲作用时间内被写入至子像素SP，且在一显示周期对应的总时长tsu内，显示面板显示的信息相同，因而可使第二扫描信号Pscan2在一显示周期对应的总时长tsu(即写入帧WF和多个保持帧HF对应的多个第一时长之和)内具有的目标频率f1小于1Hz，即f1<1Hz，以使子像素SP根据每个显示周期进行显示信息的更新，从而使显示面板实现超低频的显示。相应的，一显示周期对应的总时长tsu与第二扫描信号Pscan2在一显示周期所具有的目标频率f1成倒数；即tsu＝1/f1。
可选地，目标频率f1即为显示面板采用超低频驱动模式实现显示时所用的频率。即目标频率f1可等于0.99Hz、0.98Hz、……、0.9Hz、0.89Hz、……、0.75Hz、……、0.5Hz、……、0.11Hz、0.1Hz、0.099Hz、0.098Hz、……、0.09Hz、0.089Hz、……、0.08Hz、0.079Hz、……、0.07Hz、0.069Hz、……、0.064Hz、……、0.06Hz、……、0.05Hz、……、0.04Hz、……、0.032Hz、……、0.03Hz、……、0.02Hz、……、0.016Hz、0.015Hz、……、0.01Hz、0.009Hz、0.008Hz……、0.006Hz、0.005Hz、0.004Hz……等等。
可选地，在写入帧WF内，第二扫描信号Pscan2具有的基础频率f3与发光控制信号EM所具有的周期数Ncft的乘积等于发光控制信号EM所具有的中间频率f2，以在写入帧WF和多个保持帧HF中的每一个对应的第一时长tfr内，使发光控制信号EM所包括的周期数Ncft满足需求，从而使显示面板的显示画面满足显示性能要求。
由于数据信号Data于写入帧WF中的第二扫描信号Pscan2有效脉冲作用时间内被写入至子像素SP，且在一显示周期对应的总时长tsu内，显示面板显示的信息相同，因而可使写入帧WF和每一保持帧HF对应的第一时长tfr均与第二扫描信号Pscan2在写入帧WF所具有的基础频率f3成倒数；即tfr＝1/f3，以使子像素SP在一显示周期内显示相同的信息，从而使显示面板实现超低频的显示。
可选地，可依据基础频率f3与目标频率f1得到帧总数m，即基础频率f3与目标频率f1之比等于帧总数m(也即是基础频率f3与目标频率f1之比等于写入帧WF和多个保持帧HF的数量之和)；即f3/f1＝m。
下面将结合子像素SP的具体形式对显示面板采用高频驱动模式和低频驱动模式实现显示时所对应的作用原理进行说明。可选地，如图3是本申请实施例提供的子像素SP的结构示意图。可以理解的，子像素SP的结构不限于图3所示的形式。
每一子像素SP包括驱动晶体管Tdr、第一复位晶体管Ti1、第二复位晶体管Ti2、数据晶体管Tda、发光控制晶体管及发光器件D。
驱动晶体管Tdr被配置为根据数据信号Data生成驱动电流以驱动发光器件D发光。可选地，驱动晶体管Tdr包括连接至第一节点N1的输入电极，连接至第二节点N2的输出电极以及连接至第三节点N3的控制电极。其中，控制电极即为栅极，输入电极为源极和漏极中的一个，输出电极为源极和漏极中的另一个。
第一复位晶体管Ti1被配置为根据第一扫描信号Pscan1复位发光器件D的阳极电位。可选地，第一复位晶体管Ti1包括被配置为接收第一扫描信号Pscan1的控制电极，被配置为接收第一复位信号VI1的输入电极以及连接至第四节点N4的输出电极。
第二复位晶体管Ti2被配置为根据第一扫描信号Pscan1复位驱动晶体管Tdr的输入电极电位和输出电极电位。可选地，第二复位晶体管Ti2包括被配置为接收第一扫描信号Pscan1的控制电极，被配置为接收第二复位信号VI2的输入电极以及连接至第一节点N1的输出电极。第一复位晶体管Ti1和第二复位晶体管Ti2在第一扫描信号Pscan1的有效脉冲对应的电平状态的作用下 导通，在第一扫描信号Pscan1的无效脉冲对应的电平状态的作用下截止。
数据晶体管Tda被配置为根据第二扫描信号Pscan2通过第一节点N1向驱动晶体管Tdr传输数据信号Data。可选地，数据晶体管Tda包括被配置为接收第二扫描信号Pscan2的控制电极，被配置为接收数据信号Data的输入电极以及连接至第一节点N1的输出电极。数据晶体管Tda在第二扫描信号Pscan2的有效脉冲对应的电平状态的作用下导通，在第二扫描信号Pscan2的无效脉冲对应的电平状态的作用下截止。
发光控制晶体管被配置为根据发光控制信号EM控制驱动电流的流通路径的通断。可选地，发光控制晶体管包括第一开关晶体管Ts1和第二开关晶体管Ts2；第一开关晶体管Ts1包括被配置为接收发光控制信号EM的控制电极，被配置为连接至第一电源端VDD的输入电极以及连接至第一节点N1的输出电极；第二开关晶体管Ts2包括被配置为接收发光控制信号EM的控制电极，被配置连接至第二节点N2的输入电极以及连接至第四节点N4的输出电极。第一开关晶体管Ts1和第二开关晶体管Ts2在发光控制信号EM的有效脉冲对应的电平状态的作用下导通，在发光控制信号EM的无效脉冲对应的电平状态的作用下截止。
发光器件D包括连接至第四节点N4的阳极以及被配置为连接至第二电源端VSS的阴极。可选地，发光器件D包括有机发光二极管、次毫米发光二极管、微型发光二极管等。
可选地，请继续参阅图1～图3，栅极驱动器还包括第三栅极驱动单元，第三栅极驱动单元被配置为将第三扫描信号Nscan1及第四扫描信号Nscan2输出至子像素SP。
可选地，第三扫描信号Nscan1和第四扫描信号Nscan2在写入帧WF中的发光控制信号EM的第一个周期内的无效脉冲的作用时间内均具有一有效脉冲，以在写入帧WF内实现对第三节点N3的电位的初始化，并在写入帧WF内将数据信号Data传输至驱动晶体管Tdr的栅极，从而在保持帧HF内使子像素SP依据写入帧WF内写入到子像素SP中的数据信号Data保持显示。
子像素SP还包括补偿晶体管Tc、第三复位晶体管Ti3及存储电容Cst。
补偿晶体管Tc包括被配置为接收第三扫描信号Nscan1的控制电极，被配 置为连接至第三节点N3的输入电极以及连接至第二节点N2的输出电极。
第三复位晶体管Ti3包括接收第四扫描信号Nscan2的控制电极，被配置为接收第三复位信号VI3的输入电极以及连接至第三节点N3的输出电极。
存储电容Cst包括被配置为连接至第一电源端VDD的第一电极和连接至第三节点N3的第二电极。
可选地，补偿晶体管Tc的有源层和第三复位晶体管Ti3的有源层均包括氧化物半导体，驱动晶体管Tdr的有源层、第一复位晶体管Ti1的有源层、第二复位晶体管Ti2的有源层、数据晶体管Tda的有源层及发光控制晶体管的有源层均包括硅半导体。可选地，硅半导体包括单晶硅、多晶硅、非晶硅等材料，氧化物半导体包括氧化锌、氧化锌锡、氧化锌铟、氧化铟、氧化钛、氧化铟镓锌、氧化铟锌锡等材料中的至少一种。可选地，驱动晶体管Tdr、第一复位晶体管Ti1、第二复位晶体管Ti2、数据晶体管Tda及发光控制晶体管采用低温多晶硅工艺制得。
为改善闪烁问题，使子像素SP对应写入帧WF和每一保持帧HF内实现多次不显示状态或显示状态时的第一节点N1的电位保持相等、第二节点N2的电位保持相等、第三节点N3的电位保持相等及第四节点N4的电位保持相等。
可选地，在发光控制信号EM的多个无效脉冲的作用时间内，第一节点N1的电位保持相等，第二节点N2的电位保持相等，第三节点N3的电位保持相等，第四节点N4的电位保持相等，以改善闪烁问题。
可选地，可通过控制第二复位信号VI2的电压伏值，以实现在发光控制信号EM的多个无效脉冲的作用时间内，第一节点N1的电位保持相等，第二节点N2的电位保持相等。可选地，驱动晶体管Tdr为P型晶体管，在第一扫描信号Pscan1的每一有效脉冲的作用时间内，第三节点N3的电位与第二复位信号VI2之差小于驱动晶体管Tdr的阈值电压，以使第二复位晶体管Ti2导通时，使驱动晶体管Tdr也导通，从而使第二复位晶体管Ti2根据第一扫描信号Pscan1复位驱动晶体管Tdr的输入电极电位(即第一节点N1的电位)和输出电极电位(即第二节点N2的电位)。
图4是本申请实施例提供的对应高频驱动模式下的时序图。以高频驱动模式下对应的频率为60Hz，驱动晶体管Tdr、第一复位晶体管Ti1、第二复位晶体 管Ti2、数据晶体管Tda、第一开关晶体管Ts1和第二开关晶体管Ts2均为P型晶体管，补偿晶体管Tc及第三复位晶体管Ti3均为N型晶体管为例，对图3所示的子像素SP的工作原理进行说明。一显示周期仅包括写入帧WF，写入帧WF包括初始化阶段P1、数据写入阶段P2、节点复位阶段P3及发光阶段P4。
初始化阶段P1：发光控制信号EM、第一扫描信号Pscan1、第二扫描信号Pscan2、第三扫描信号Nscan1及第四扫描信号Nscan2均对应高电平状态，第三复位晶体管Ti3响应第四扫描信号Nscan2导通，补偿晶体管Tc响应第三扫描信号Nscan1导通使得驱动晶体管Tdr呈二极管式连接，驱动晶体管Tdr导通，第三复位信号对第三节点N3、第二节点N2及第一节点N1的电位进行复位。第一复位晶体管Ti1和第二复位晶体管Ti2均响应第一扫描信号Pscan1截止，数据晶体管Tda响应第二扫描信号Pscan2截止，第一开关晶体管Ts1和第二开关晶体管Ts2均响应发光控制信号EM截止。
数据写入阶段P2：发光控制信号EM、第一扫描信号Pscan1及第三扫描信号Nscan1均对应高电平状态，第二扫描信号Pscan2及第四扫描信号Nscan2均对应低电平状态，数据晶体管Tda响应第二扫描信号Pscan2导通，补偿晶体管Tc响应第三扫描信号Nscan1导通使得驱动晶体管Tdr呈二极管式连接，驱动晶体管Tdr导通，数据信号Data经数据晶体管Tda、第一节点N1、驱动晶体管Tdr、第二节点N2及补偿晶体管Tc被传输至第三节点N3，以实现数据信号Data的写入及驱动晶体管Tdr的阈值电压的抓取。第一复位晶体管Ti1和第二复位晶体管Ti2均响应第一扫描信号Pscan1截止，第一开关晶体管Ts1和第二开关晶体管Ts2响应发光控制信号EM截止，第三复位晶体管Ti3响应第四扫描信号Nscan2截止。
节点复位阶段P3：发光控制信号EM及第二扫描信号Pscan2均对应高电平状态，第一扫描信号Pscan1、第三扫描信号Nscan1及第四扫描信号Nscan2均对应低电平状态，第一复位晶体管Ti1和第二复位晶体管Ti2均响应第一扫描信号Pscan1导通，第一复位信号VI1对第四节点N4的电位进行复位。而第二复位信号VI2具有较高的电压伏值，驱动晶体管Tdr的栅极和源极之间的电压差即为第三节点N3与第一节点N1之间的电压差，因而使第三节点N3与第一节点N1之间的电压差小于驱动晶体管Tdr的阈值电压即可使驱动晶体管Tdr导通，从而使第 二复位信号VI2对第一节点N1及第二节点N2的电位进行复位。数据晶体管Tda响应第二扫描信号Pscan2截止，补偿晶体管Tc响应第三扫描信号Nscan1截止，第三复位晶体管Ti3响应第四扫描信号Nscan2截止，第一开关晶体管Ts1和第二开关晶体管Ts2均响应发光控制信号EM截止。
发光阶段P4：发光控制信号EM、第三扫描信号Nscan1及第四扫描信号Nscan2均对应低电平状态，第一扫描信号Pscan1及第二扫描信号Pscan2均对应高电平状态，第一开关晶体管Ts1和第二开关晶体管Ts2均响应发光控制信号EM导通，驱动晶体管Tdr在存储电容的作用下维持导通，驱动晶体管Tdr根据数据信号Data生成的驱动电流在第一电源端VDD和第二电源端VSS之间路径中流通，以使发光器件D发光。第一复位晶体管Ti1和第二复位晶体管Ti2均响应第一扫描信号Pscan1截止，数据晶体管Tda响应第二扫描信号Pscan2截止，补偿晶体管Tc响应第三扫描信号Nscan1截止，第三复位晶体管Ti3响应第四扫描信号Nscan2截止。
其中，子像素SP中的第一节点N1、第二节点N2、第三节点N3及第四节点N4在对应高频驱动模式中的各工作阶段的电位变化如表1所示。表1中的Vth为驱动晶体管Tdr的阈值电压，Lum.vo表示电位实际受电路中充放电状态的变化，具有一定的浮动。
为在实现超低频驱动模式的显示功能的同时，改善超低频驱动模式引起的闪烁问题，对对应超低频驱动模式下一显示周期包括的每一帧(1Frame)的时长进行提升，之后再配合跳帧的方式实现超低驱动模式的显示功能。
如图5是本申请实施例提供的提高每帧对应的时长的原理图。其中，图5中的VBP表示垂直后廊、VFP表示垂直前廊、HBP表示水平后廊、HFP表示水平前廊，y1、y3和y5均表示像素单元Pi的行数，y2、y4和y6均表示像素单元Pi的列数；y1≠y3≠y5；y2≠y4≠y6。
由于显示面板在制备完成后，分辨率已被固定，因而若想提升每帧对应的时长，则可使驱动控制模块认为所需控制的扫描行数V-proch的数量NV-porch大于像素单元Pi的行数，和/或每行所需控制的像素单元Pi的扫描个数NH-line大于像素单元Pi的列数。即可在每行所需控制的像素单元Pi的扫描个数NH-line不变的情况下，增加所需控制的扫描行数V-proch的数量NV-porch，使得每帧所需扫描的行数增多，从而实现每一帧对应的时长的增加；也可在所需控制的扫描行数V-proch的数量NV-porch不变的情况下，增加每行所需控制的像素单元Pi的扫描时间NH-line/fosc，从而实现每一帧对应的时长的增加；也可增加所需控制的扫描行数V-proch的数量NV-porch，和每行所需控制的像素单元Pi的扫描时间NH-line/fosc，从而实现每一帧对应的时长的增加。其中，fosc表示驱动控制模块的晶振频率，1/fosc表示驱动控制模块控制一个像素单元Pi实现显示所需的时间。
每帧对应的时长Tframe＝NV-porch*NH-line/fosc，而受驱动控制模块的功能限制，NH-line和NV-porch的取值均具有上限，如控制跳帧数量的寄存器的是10bit，NH-line最大可取1024，NV-porch最大可取VAA+1028，VAA为NV-porch最小可取值。
在经过对每帧对应的时长进行提升后，一显示周期包括的写入帧WF和每一保持帧HF所对应的第一时长tfr与驱动控制器控制一个像素单元Pi实现显示所需要的时长的比值(即t1*fosc＝NV-porch*NH-line)大于显示装置的像素单元Pi的数量。
由于每帧以低于临界闪烁频率CFF的频率进行显示时会出现闪烁问题，因而对时序进行优化。具体的，在写入帧WF的初始化阶段P1、数据写入阶段P2、节点复位阶段P3的阶段，显示面板采用高频驱动模式实现显示和采用超低频驱动模式实现显示的工作原理相似。而在采用超低驱动模式实现显示时，使发光阶段P4包括多个发光子阶段和多个不发光子阶段。在每一发光子阶段中，发光控制信号EM具有有效脉冲，第一扫描信号Pscan1、第二扫描信号Pscan2、第三扫描信号Nscan1及第四扫描信号Nscan2均对应具有无效脉冲，以使第一开关晶体管Ts1和第二开关晶体管Ts2均响应发光控制信号EM导通，驱动晶体管Tdr根据数据信号Data生成的驱动电流在第一电源端VDD和第二电源端VSS之间路径中流通控制发光器件D发光。而在每一不发光子阶段中，发光控制信号EM、第三扫描信号Nscan1及第四扫描信号Nscan2均对应具有无效脉冲，第一 扫描信号Pscan1在发光控制信号EM具有无效脉冲的时长内具有有效脉冲，且第一扫描信号Pscan1有效脉冲的维持时长小于或等于发光控制信号EM维持无效脉冲的时长，以使第一复位晶体管Ti1和第二复位晶体管Ti2均响应第一扫描信号Pscan1导通，从而利用第一复位信号VI1对第四节点N4的电位进行复位，利用第二复位信号VI2具有较高的电压伏值使驱动晶体管Tdr导通，从而利用第二复位信号VI2对第一节点N1及第二节点N2的电位进行复位。通过在发光阶段内使子像素SP在显示状态和不显示状态之间进行切换，从而提高了显示频率，继而改善闪烁问题。
具体的，先对对应超低频驱动模式下写入帧WF的时序图进行说明。图6是本申请实施例提供的对应超低频驱动模式下写入帧WF的时序图；以写入帧WF对应的第一时长tfr内，第二扫描信号Pscan2具有的基础频率f3为16Hz，驱动晶体管Tdr、第一复位晶体管Ti1、第二复位晶体管Ti2、数据晶体管Tda、第一开关晶体管Ts1和第二开关晶体管Ts2均为P型晶体管，补偿晶体管Tc及第三复位晶体管Ti3均为N型晶体管为例，对图3所示的子像素SP的对应超低频驱动模式下的发光阶段P4的工作原理进行说明。发光阶段P4中包括第一发光子阶段P41、第一不发光子阶段P42、第二发光子阶段P43、第二不发光子阶段P44、第三发光子阶段P45、第三不发光子阶段P46、第四发光子阶段P47。
在第一发光子阶段P41、第二发光子阶段P43、第三发光子阶段P45及第四发光子阶段P47：发光控制信号EM、第三扫描信号Nscan1及第四扫描信号Nscan2均对应低电平状态，第一扫描信号Pscan1及第二扫描信号Pscan2均对应高电平状态，第一开关晶体管Ts1和第二开关晶体管Ts2均响应发光控制信号EM导通，驱动晶体管Tdr在存储电容Cst的作用下维持导通，驱动晶体管Tdr根据数据信号Data生成的驱动电流在第一电源端VDD和第二电源端VSS之间路径中流通，以使发光器件D发光。
在第一不发光子阶段P42、第二不发光子阶段P44、第三不发光子阶段P46：发光控制信号EM及第二扫描信号Pscan2均对应高电平状态，第三扫描信号Nscan1及第四扫描信号Nscan2均对应低电平状态，第一扫描信号Pscan1在发光控制信号EM对应具有高电平状态的时长内具有一定时长的低电平状态。第一复位晶体管Ti1和第二复位晶体管Ti2均响应第一扫描信号Pscan1导通，第一复 位信号VI1对第四节点N4的电位进行复位。第二复位信号VI2具有较高的电压伏值使驱动晶体管Tdr导通，第二复位信号VI2对第一节点N1及第二节点N2的电位进行复位。
其中，子像素SP中的第一节点N1、第二节点N2、第三节点N3及第四节点N4在对应高频驱动模式中的各工作阶段的电位变化如表2所示。
由表2可知，在多个不发光子阶段中，第一节点N1的电位保持相等，第二节点N2的电位保持相等，第三节点N3的电位保持相等，第四节点N4的电位保持相等。在多个发光子阶段中，第一节点N1的电位保持相等，第二节点N2的电位保持相等，第三节点N3的电位保持相等，第四节点N4的电位保持相等，因而可使子像素SP在每次发光子阶段的显示亮度保持一致。
图7是本申请实施例提供的亮度为50nit的发光波形实测结果示意图，通过使发光阶段包括多个发光子阶段和多个不发光子阶段，可使子像素SP在每次发光子阶段的显示亮度保持一致，还可改善闪烁问题。
在图6所示的实施例中，写入帧WF对应的第一时长tfr内，第二扫描信号Pscan2具有的基础频率f3为16Hz，而发光控制信号EM的周期数Ncft为4，因而，发光控制信号EM具有的中间频率f2为64Hz。其中，发光控制信号EM的周期数Ncft可根据写入帧WF内包括的发光子阶段的数量和不发光子阶段的数量之和确定。即写入帧WF对应初始化阶段P1、数据写入阶段P2、节点复位阶段P3的阶段亦属于一个不发光子阶段，而初始化阶段P1、数据写入阶段P2、节点复位阶段P3的阶段组成的不发光子阶段、发光阶段包括的发光子阶段和不发光子阶 段之和等于发光控制信号EM的周期数Ncft的2倍；也即是发光控制信号EM的每一周期T实际对应一个不发光子阶段和一个发光子阶段。
可选地，发光控制信号EM的周期数Ncft为整数，以在后续进行跳帧以实现超低频显示模式时，可以使每帧包括的发光子阶段和不发光子阶段的数量保持相等。
为实现超低频驱动模式的显示功能，在保持帧HF内，发光阶段也对应具有多个发光子阶段和多个不发光子阶段。可选地，每一保持帧HF内包括的发光子阶段的数量等于写入帧WF内包括的发光子阶段的数量，每一保持帧HF内包括的不发光子阶段的数量等于写入帧WF内包括的不发光子阶段的数量，以使写入帧WF和每一保持帧HF均对应具有第一时长tfr。
在已可提升每帧时长的基础上，对采用超低频驱动模式时一显示周期对应的跳帧次数进行说明。图8是本申请实施例提供的对应超低频驱动模式下一显示周期的时序图；以一显示周期对应的总时长tsu内，第二扫描信号Pscan2具有的目标频率f1为0.016Hz；写入帧WF对应的第一时长tfr内，第二扫描信号Pscan2具有的基础频率f3为16Hz，结合图3所示的子像素，对采用超低频驱动模式时一显示周期对应的跳帧次数进行说明。
在每一保持帧HF内，子像素SP在发光控制信号EM的控制下，在不显示状态和显示状态之间切换。帧总数m＝16/0.016＝1000(即一显示周期包括的写入帧WF和多个保持帧HF的数量之和等于16/0.016＝1000)，即一显示周期包括一个写入帧WF(即对应图8中的1st 16Hz)和999个保持帧HF(即对应图8中的2nd～999th 16Hz和1000th 16Hz)。而跳帧次数SKF等于一显示周期包括的多个保持帧HF的数量，即跳帧次数SKF等于999。
可选地，跳帧次数SKF为整数，以使每一显示周期均包括的写入帧WF和保持帧HF的数量为整数个。可选地，跳帧次数SKF小于跳帧上限SKL，以使所述显示装置可以实现所要达成的目标频率。
通过在一显示周期包括一个写入帧WF和多个保持帧HF，以在一显示周期对应的总时长tsu内使显示面板显示相同的显示内容，且由于写入帧WF和每一保持帧HF对应的第一时长tfr内，子像素SP均做了多次显示状态和不显示状态的切换，因而，可使人眼感知不到显示面板在一显示周期对应的总时长tsu内 存在闪烁问题。
可以理解的，除实现目标频率f1为0.016Hz的显示外，还可依据目标频率f1、中间频率f2、基础频率f3、发光控制信号EM的周期数Ncft、帧总数m、第一时长tfr、总时长tsu之间的关系得到更多的对应超低频率的显示。表3中仅示出对应跳帧上限SKL等于2^10＝1024时的部分示例，不用于限制本申请。
由表3可知，用于实现目标频率f1的基础频率f3可以具有多个，用于实现目标频率f1的中间频率f2也可以具有多个。多个基础频率f3中具有一个最大基础频率fmax，多个中间频率f2中具有一个最小中间频率fmin。其中，在一显示周期包括的写入帧WF和每一保持帧HF对应的第一时长tfr内，发光控制信号EM所具有的周期数Ncft大于或等于最小中间频率与最大基础频率之比；即Ncft≥fmin/fmax。
可根据跳帧上限SKL与目标频率f1确定最大基础频率fmax。如分别利用多个基础频率f3和目标频率f1的比值与跳帧上限SKL作差，得到多个第一差值，多个第一差值中的最小差值所对应的基础频率f3即为最大基础频率fmax。其中，多个基础频率f3和目标频率f1的比值均小于跳帧上限SKL。
可根据临界闪烁频率CFF和周期数Ncft的乘积确定最小中间频率fmin。如分别利用多个中间频率f2与临界闪烁频率CFF作差，得到多个第二差值，多个第二差值中的最小差值对应的中间频率f2即为最小中间频率fmin。其中，多个中间频率f2均大于临界闪烁频率CFF。
即若跳帧上限SKL等于2^10＝1024，目标频率f1为0.016Hz，则最小中间频率fmin为64Hz，最大基础频率fmax为16Hz，那么，在一显示周期包括的写入帧WF和每一保持帧HF对应的第一时长tfr内，发光控制信号EM所具有的周期数Ncft大于或等于4。
可以理解的，在超低频驱动显示模式下，依据所要实现的目标频率f1的不同，对应写入帧WF的时序和一显示周期的时序与图6和图8也会不同，而本领域技术人员依据本申请可得到与所要实现的目标频率f1相对应的写入帧WF时序和一显示周期时序，在本申请中为节省篇幅不再对其他实施例进行赘述。
表4是对应基础频率f3为16Hz、中间频率f2为64Hz、目标频率f1为0.016Hz得到的闪烁测试结果表。
由表4可知，在显示面板采用目标频率f1为0.016Hz的超低频驱动模式实现显示时，显示面板存在的闪烁程度仍小于规格值，因而，显示面板在实现超低频显示时，可使人眼感知不到闪烁问题，从而使显示面板具有较好的显示性能。
如图9是本申请实施例提供的功耗测试结果示意图。其中，25％OPR是指屏幕有25％的显示区域发光，10％OPR是指屏幕有25％的显示区域发光。由图9可知，相对于现有的采用低频驱动模式实现显示，本申请的采用超低频驱动模式实现显示，对应25％OPR时，功耗降低14.1％，对应10％OPR时，功耗降低18.4％。因此，可实现降低功耗的目的，可以使显示装置具有较好的续航能力。
可以理解地，显示装置包括可移动显示装置(如笔记本电脑、手机等)、固定终端(如台式电脑、电视等)、测量装置(如运动手环、测温仪等)等。
对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (12)

  1. 一种显示装置，其中，包括：
    显示面板，包括多个子像素；
    栅极驱动器，包括第一栅极驱动单元和第二栅极驱动单元，所述第一栅极驱动单元被配置为将第一扫描信号输出至所述子像素，所述第二栅极驱动单元被配置为将第二扫描信号输出至所述子像素；以及，
    发射驱动器，配置为将发光控制信号输出至所述子像素；
    其中，所述显示面板具有多个显示周期，至少一所述显示周期包括一写入帧和多个保持帧，所述写入帧和多个所述保持帧中的每一个均具有第一时长；在所述写入帧和多个所述保持帧中的每一个内，所述发光控制信号具有多个周期，所述发光控制信号的周期数与所述第一时长之比大于临界闪烁频率；
    所述发光控制信号在每一所述周期内均具有一有效脉冲和一无效脉冲，所述第一扫描信号在所述写入帧和多个所述保持帧中的所述发光控制信号的每一所述无效脉冲的作用时间内具有一有效脉冲，所述第二扫描信号在所述写入帧中的所述发光控制信号的第一个所述周期内的所述无效脉冲的作用时间内具有一有效脉冲。
  2. 根据权利要求1所述的显示装置，其中，在所述写入帧和多个所述保持帧对应的总时长内，所述第二扫描信号具有的目标频率小于1Hz。
  3. 根据权利要求2所述的显示装置，其中，在所述写入帧内，所述第二扫描信号具有的基础频率与所述发光控制信号所具有的所述周期数的乘积等于所述发光控制信号所具有的中间频率。
  4. 根据权利要求3所述的显示装置，其中，所述基础频率与所述目标频率之比等于所述写入帧和多个所述保持帧的数量之和。
  5. 根据权利要求3所述的显示装置，其中，所述基础频率为16Hz，所述中间频率为64Hz，所述目标频率为0.016Hz。
  6. 根据权利要求1所述的显示装置，其中，一所述显示周期包括的帧总数小于或等于跳帧上限；其中，所述帧总数为一所述显示周期内包括的所述写入帧和多个所述保持帧的数量之和，所述跳帧上限为2^x，x为控制跳帧数量的寄存器所对应的比特数x。
  7. 根据权利要求1所述的显示装置，其中，每一所述子像素包括：
    发光器件；
    驱动晶体管，被配置为根据数据信号生成驱动电流以驱动所述发光器件发光；
    第一复位晶体管，被配置为根据所述第一扫描信号复位所述发光器件的阳极电位，
    第二复位晶体管，被配置为根据所述第一扫描信号复位所述驱动晶体管的输入电极电位和输出电极电位；
    数据晶体管，被配置为根据所述第二扫描信号通过第一节点向所述驱动晶体管传输所述数据信号；
    发光控制晶体管，被配置为根据所述发光控制信号控制所述驱动电流的流通路径的通断。
  8. 根据权利要求7所述的显示装置，其中，
    所述驱动晶体管包括连接至所述第一节点的所述输入电极，连接至第二节点的所述输出电极以及连接至第三节点的控制电极；
    所述数据晶体管包括被配置为接收所述第二扫描信号的控制电极，被配置为接收所述数据信号的输入电极以及连接至所述第一节点的输出电极；
    所述发光控制晶体管包括第一开关晶体管和第二开关晶体管；所述第一开关晶体管包括被配置为接收所述发光控制信号的控制电极，被配置为连接至第一电源端的输入电极以及连接至所述第一节点的输出电极；所述第二开关晶体管包括被配置为接收所述发光控制信号的控制电极，被配置连接至所述第二节点的输入电极以及连接至第四节点的输出电极；
    所述第一复位晶体管包括被配置为接收所述第一扫描信号的控制电极，被配置为接收第一复位信号的输入电极以及连接至所述第四节点的输出电极；
    所述第二复位晶体管包括被配置为接收所述第一扫描信号的控制电极，被配置为接收第二复位信号的输入电极以及连接至所述第一节点的输出电极；以及
    所述发光器件包括连接至所述第四节点的阳极以及被配置为连接至第二电源端的阴极；
    其中，在所述发光控制信号的多个所述无效脉冲的作用时间内，所述第一节点的电位保持相等，所述第二节点的电位保持相等，所述第三节点的电位保持相等，所述第四节点的电位保持相等。
  9. 根据权利要求8所述的显示装置，其中，所述驱动晶体管为P型晶体管，在所述第一扫描信号的每一所述有效脉冲的作用时间内，所述第三节点的电位与所述第二复位信号之差小于所述驱动晶体管的阈值电压。
  10. 根据权利要求8所述的显示装置，其中，
    所述栅极驱动器还包括第三栅极驱动单元，所述第三栅极驱动单元被配置为将第三扫描信号及第四扫描信号输出至所述子像素；
    所述子像素还包括补偿晶体管、第三复位晶体管及存储电容；
    所述补偿晶体管包括被配置为接收所述第三扫描信号的控制电极，被配置为连接至所述第三节点的输入电极以及连接至所述第二节点的输出电极；
    所述第三复位晶体管包括被配置为接收所述第四扫描信号的控制电极，被配置为接收第三复位信号的输入电极以及连接至所述第三节点的输出电极；
    所述存储电容包括被配置为连接至所述第一电源端的第一电极和连接至所述第三节点的第二电极；
    其中，所述第三扫描信号和所述第四扫描信号在所述写入帧中的所述发光控制信号的所述第一个周期内的所述无效脉冲的作用时间内均具有一有效脉冲。
  11. 根据权利要求1所述的显示装置，其中，多个所述子像素形成阵列排布的多个像素单元，每一所述像素单元包括三个所述子像素；所述显示装置还包括驱动控制器，所述驱动控制器被配置为生成控制信号，以控制所述栅极驱动器及所述发射驱动器实现多个所述像素单元的显示状态的控制；
    其中，所述第一时长与所述驱动控制器控制一个所述像素单元实现显示所需要的时长的比值大于所述显示装置的所述像素单元的数量。
  12. 根据权利要求11所述的显示装置，其中，所述比值等于NH-line与NV-porch的乘积；
    其中，NH-line大于所述像素单元的列数，NV-porch大于所述像素单元的行数。
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