WO2024082616A1 - 确定节点时延的方法、存储介质和电子设备 - Google Patents

确定节点时延的方法、存储介质和电子设备 Download PDF

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Publication number
WO2024082616A1
WO2024082616A1 PCT/CN2023/093321 CN2023093321W WO2024082616A1 WO 2024082616 A1 WO2024082616 A1 WO 2024082616A1 CN 2023093321 W CN2023093321 W CN 2023093321W WO 2024082616 A1 WO2024082616 A1 WO 2024082616A1
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node
delay
moment
offset
determining
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PCT/CN2023/093321
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English (en)
French (fr)
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朱向阳
喻敬海
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中兴通讯股份有限公司
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Publication of WO2024082616A1 publication Critical patent/WO2024082616A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays

Definitions

  • the present application relates to the field of communication technology, and in particular to a method for determining node delay, a storage medium, and an electronic device.
  • Cycle Specified Queuing and Forwarding (CSQF) and Large-scale Deterministic Internet Protocol Network (LDN) do not require time synchronization across the entire network, but only require frequency synchronization, and can provide deterministic transmission services for critical businesses.
  • CQF Cycle Specified Queuing and Forwarding
  • LDN Large-scale Deterministic Internet Protocol Network
  • Node delay mainly includes node processing delay (processDelay), regulation delay (regulatorDelay) and queue delay (queueDelay).
  • ProcessDelay can be measured.
  • RegulatorDelay and queueDelay are the time the message is in the egress queue. During the regulatorDelay time, the message is not allowed to be scheduled and sent. During the queueDelay time, the queue to which the message belongs gets the scheduling opportunity.
  • the control plane is responsible for planning the end-to-end service path to meet the service Quality of Service (QoS) requirements and constructing the service path calculation topology.
  • QoS Quality of Service
  • the control plane is responsible for planning the end-to-end service path to meet the service Quality of Service (QoS) requirements and constructing the service path calculation topology.
  • QoS Quality of Service
  • the forwarding nodes use periodic scheduling for forwarding, the node delay cannot be directly substituted into the service path calculation, and there is no relevant solution to disclose how to determine the node delay.
  • the purpose of the embodiments of the present application is to provide a method for determining node delay, a storage medium and Electronic device capable of accurately determining the time deviation value within a cycle.
  • an embodiment of the present application provides a method for determining a node delay, including: determining a time deviation offset within a cycle, wherein the time deviation within the cycle is the time difference between a second moment and a start moment of a target cycle window, the second moment being the moment when a downstream node receives a first message sent by an upstream node; determining a node delay nodeDelay based on the offset and the length T of a cycle template.
  • an embodiment of the present application provides an electronic device, comprising: a memory, a processor, and computer executable instructions stored in the memory and executable on the processor, wherein the computer executable instructions, when executed by the processor, implement the method for determining node latency described in the first aspect.
  • an embodiment of the present application provides a computer-readable storage medium, which is used to store computer-executable instructions.
  • the computer-executable instructions are executed by a processor, the method for determining node latency described in the first aspect is implemented.
  • FIG. 1 a shows a schematic flow chart of a method for determining node delay provided in an embodiment of the present application.
  • FIG1b is a schematic diagram of a method for determining node delay according to an embodiment of the present application.
  • Figures 1c-1d are schematic diagrams of determining node delay according to an embodiment of the present application.
  • FIG. 2 shows a schematic diagram of a process of a method for determining node delay provided in an embodiment of the present application. picture.
  • FIG. 3 a is a schematic diagram of determining node delay according to an embodiment of the present application.
  • 3b-3d are schematic diagrams of message formats.
  • FIG4 shows a schematic diagram of the structure of an apparatus for determining node delay provided in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the hardware structure of the electronic device.
  • FIG. 1a shows a flow chart of a method for determining node delay provided in an embodiment of the present application.
  • the method can be executed by a network node. As shown in the figure, the method can include the following steps.
  • S102 Determine a time deviation offset within a cycle.
  • the intra-cycle time deviation is the time difference between the second moment and the start moment of the target cycle window, and the second moment is the moment when the downstream node receives the first message sent by the upstream node. Since there is no time synchronization between nodes, there is a certain deviation between the time slots of the same cycle template of the upstream and downstream nodes, which is called the phase difference ⁇ .
  • the deviation value is a random value.
  • the offset value is related to the link delay and the phase difference ⁇ . If the cycle template window size is T, the offset value range is [0, T), and the offset value needs to be determined.
  • Fig. 1b is a schematic diagram of a method for measuring a time deviation value according to an embodiment of the present application.
  • the upstream node sends a first message at time t0 and receives a first message sent by the upstream node, wherein the first message instructs the downstream node to measure the time deviation value.
  • the second time t2 falls into the corresponding target cycle window WA of the downstream node A.
  • the second time t2 falls into the corresponding target cycle window WB of the downstream node B.
  • the second time t2 falls into the corresponding target cycle window WC of the downstream node C.
  • the time difference between the second moment and the start moment of the target cycle window is determined as the time deviation value within the cycle, such as offsetA, offsetB, and offsetC shown in the figure.
  • S104 Determine the node delay nodeDelay according to the offset and the length T of the periodic template.
  • the method for determining node delay provided in the embodiment of the present application can determine the node delay nodeDelay.
  • the node delay nodeDelay is determined according to the offset and the length T of the cycle template, so that the node delay can be accurately determined.
  • the time deviation value may be determined according to the first moment, the second moment and the length of the periodic template, wherein the first moment is the start moment of the downstream node or the start moment of the target periodic window.
  • offset is the time deviation value
  • t1 is the first moment
  • T is the length of the periodic template
  • MOD is used to return the remainder after (t2-t1) is divided by T.
  • the remainder after dividing (t2-t1) by T is the offset value.
  • one cycle of the downstream node C includes 2 cycle templates T.
  • the quotient of (t2-t1) divided by T in the downstream node C is 1, that is, (t2-t1) shown in the figure contains 1 T, and offsetC is the remainder.
  • the downstream node One cycle of B includes 6 cycle templates T.
  • the quotient of (t2-t1) divided by T in the downstream node B is 3, that is, (t2-t1) shown in the figure contains 3 Ts, and offsetB is the remainder.
  • the embodiment of the present application can accurately determine the time deviation value within a cycle, thereby accurately determining the node delay.
  • the regulation delay regulatorDelay may be determined according to the following formula (1):
  • the processDelay is a processing delay.
  • the processDelay is relatively fixed and can be a predetermined value. It has a theoretical upper limit and a lower limit, and can also be obtained by measurement. The symbol indicates rounding up.
  • the node delay nodeDelay is determined.
  • Fig. 1c is a schematic diagram of measuring and determining node delay according to an embodiment of the present application.
  • the receiving window of the message is y, and assuming that the upper limit of processDelay is 0.5T, then according to formula (1), the regulatorDelay value is calculated to be T.
  • the time slot scheduling window opens, and queueDelay is the time the scheduling window opens, that is, T.
  • nodeDelayA regulatorDelay+queueDelay+(T-offset) (2)
  • the node delay nodeDelay can be determined according to the regulatorDelay and the queue delay queueDelay, wherein the processDelay is the processing delay.
  • the queueDelay may be T, thereby obtaining formula (4), and the node delay nodeDelay may be determined according to the regulatorDelay and the length T of the cycle.
  • the corresponding offset value can be measured for each periodic template, so the corresponding nodeDelay can also be calculated. For example, if the upstream and downstream nodes support three periodic templates A, B, and C at the same time, the offset values may be different, respectively recorded as offsetA, offsetB, and offsetC. Further, according to formula (4), the corresponding periodic scheduling delays nodeDelayA, nodeDelayB, and nodeDelayC can be calculated, as shown in Figure 1d.
  • the embodiment of the present application can perform certain absorption processing on processDelay through regulatorDelay, eliminate the jitter caused by the processing delay, and finally accurately determine the node delay.
  • FIG2 shows a flow chart of a method for determining node delay provided in an embodiment of the present application.
  • the method can be executed by a network node. As shown in the figure, the method can include the following steps.
  • a time deviation value measurement function of a network node when activated, a first message constructed and sent by an upstream node is received, wherein the activation of the time deviation value measurement function of the network node includes causing the upstream node to send the first message according to a predetermined rule, and the predetermined rule includes: at least one of a sending time, a sending frequency, or a sending number of times.
  • the sending time may be a start time or an end time of a period window.
  • the time when the upstream node sends the first message can be at the start or end time of all period template windows, so the first message needs to be sent at the start or end time of the window of the maximum period template.
  • the C template is the maximum window template, so a first message can be sent at the start time of the C template window, and different offset values are measured for the A, B, and C templates in the downstream node, respectively, and recorded as offsetA, offsetB, and offsetC, respectively, and these three values may be equal or unequal.
  • the first message may adopt a variety of protocol types, which are not limited in this solution.
  • the upstream node receives The first message sent.
  • the downstream node may be instructed to measure the time deviation value through a first field in the first message.
  • the first field may be an existing field in the first message or a newly added field.
  • This step can trigger the measurement of the offset value when the target function is activated or enabled.
  • S204 Determine a second time point at which the downstream node receives the first message.
  • the first message is sent at the target time of the first cycle window of the upstream node.
  • the target time of the first cycle window may include the start time or the end time of the first cycle window.
  • This step is the same as the corresponding step in the embodiment of FIG. 1 and will not be described in detail.
  • S210 Send a first notification message.
  • the above steps can be performed inside the controller, and the offset and processDelay values corresponding to each template need to be measured and reported.
  • the above calculation process can also be optionally performed inside the downstream node.
  • the delay value can be saved in the local node.
  • the content at least includes the address and interface that can identify the local network device, the address and interface that can identify the opposite network device, the periodic template window size, the node processing delay, the window offset offset and the determined node delay value.
  • the network device can notify the controller of the value through the first notification message, so that the controller can obtain the information and perform accurate path planning, traffic scheduling, etc. based on the information and other required information. If the node supports multi-cycle templates, multiple cycle templates and corresponding determined delay nodeDelay value information can be optionally notified in one message.
  • the present invention does not limit the way of information notification, for example, it can be reported to the controller through multiple extension interfaces.
  • the correspondence between the period template and the nodeDelay may be recorded.
  • the first notification message includes a corresponding relationship between the periodic template and the nodeDelay.
  • the network device can send a second notification message to other nodes or controllers in the entire network to notify the offset value, so that components such as the path calculation unit or controller can obtain the information and perform accurate path planning, traffic scheduling, etc. based on the information and other required information.
  • the second notification message includes the identification information of the downstream node, the correspondence between the time deviation value and the target period window.
  • the identification information of the downstream node may include an address, an interface, etc. that can identify the downstream node device.
  • the second notification message may also include identification information that can identify the network device at the receiving end of the second notification message, such as an address, an interface, etc.
  • the second notification message may also include information such as a period template window size.
  • the network device supports multi-cycle scheduling, it is optional to send notification messages separately or notify multiple cycle templates and corresponding offset value information in one message.
  • This embodiment does not limit the way of information notification.
  • IGP Interior Gateway Protocols
  • OSPF Open Shortest Path First
  • ISIS Intermediate System-to-Intermediate System
  • Border Gateway Protocol BGP
  • NETCONF Network Configuration Protocol
  • BGPCEP Border Gateway Path Computation Element Protocol
  • BGP Link-state Border Gateway Protocol Link-state
  • BGP-LS Border Gateway Protocol Link-state
  • the time deviation value may also be recorded; and/or the corresponding relationship between the identification information of the downstream node, the time deviation value and the target period window may be recorded.
  • N1 and N2 Assume there are two network devices N1 and N2, the frequency between the two devices is synchronized but the time is not synchronized.
  • N1 is the upstream device node and N2 is the downstream device node.
  • Both N1 and N2 devices support three cycle templates, namely A, B, and C.
  • the node delay determination process can be performed in the controller.
  • the processDelay value and offsetA, offsetB and offSet are reported to the controller.
  • the node delay can also be performed in the downstream node N2.
  • the node delay determination value is:
  • the following table is an example of the data corresponding to the nodeDelay value of each periodic template recorded locally on the N2 node:
  • This embodiment provides an example of encapsulation of a nodeDelay value reporting message when the downstream node performs node delay determination. Assuming that there are three templates A, B, and C, this embodiment carries information of the nodeDelay values corresponding to the three templates in one notification message. Taking the Path Computation Element Protocol (PCEP) as an example, the Object-class field and the OT field are reserved to provide a convenient extension method for the PCEP protocol to indicate new message types.
  • PCEP Path Computation Element Protocol
  • the object-class field and the OT field value can be flexibly allocated to indicate that the message content is a period template and a corresponding node delay determination value.
  • the encapsulation format is shown in FIG. 3b , where the meaning of each field is described as follows:
  • the upstream node ID, nodeId1 field occupies 4 bytes; the upstream node egress port ID, inferfaceId1 field occupies 4 bytes;
  • nodeId2 field occupies 4 bytes; downstream node inbound port ID, interfaceId2 occupies 4 bytes;
  • cycle template lengths cycleLengthA, cycleLengthB and cycleLengthC occupy 1 byte respectively; the corresponding node delay determination values nodeDelayA, nodeDelayB and nodeDelayC occupy 3 bytes respectively.
  • extension method and value of the PCEP protocol message in this embodiment are only examples.
  • the node delay determination value information can also be reported based on other protocol extensions.
  • the content of the embodiment is not intended to limit the present invention.
  • N1 is the upstream device node
  • N2 is the downstream device node.
  • the local window start time of the N2 node device is determined to be 150000ns in nanoseconds
  • both N1 and N2 devices support three periodic templates, namely A, B, and C, and the periodic template time slot lengths are 10000ns, 20000ns, and 40000ns, respectively.
  • the steps to measure the offset value are as follows:
  • the offset value measurement function is enabled, and the N1 device is activated to send the first message, with a sending frequency of 40us and a sending frequency of 3 times.
  • the N1 node constructs the first message, and the first message indicates to do offset value measurement.
  • the N1 node sends the first message at the beginning (or end) of the C template window, with an interval of 40us, and sends a total of 3 first messages.
  • the N2 node records the receiving time of the three first messages, and determines them in nanoseconds as 865000us, 905010ns and 945005ns respectively.
  • the corresponding offset values are calculated for the three periodic templates A, B and C respectively.
  • the calculation method of the subsequent two first messages is the same as that of the first first message.
  • the following table is an example of the data corresponding to the offset value of each periodic template recorded locally on the N2 node:
  • This embodiment gives an example of the encapsulation format of the first message.
  • multiple first message carrying methods can be defined. If the network is Ethernet, based on the Operation Administration and Maintenance (OAM) message encapsulation format of Y.1731, a new value 0x88 can be assigned in the OpCode field to indicate that the OAM message is used to measure the offset value, and the data field of the OAM message is empty and does not carry other values, as shown in Figure 3c; in a Multi-Protocol Label Switching (MPLS) network, the OAM first message extension based on the G-Ach header can be defined, for example, a new ChannelType value 0xt88 is defined to indicate that the carried message is used to measure the offset value, as shown in Figure 3d.
  • MPLS Multi-Protocol Label Switching
  • the destination User Datagram Protocol/Transmission Control Protocol (UDP/TCP) port number of the OAM message is usually used to indicate the type of OAM message.
  • UDP/TCP port 8888 can be assigned to indicate the first message with an offset value.
  • the encapsulation message example of the second notification message includes: Assuming there are three templates, the information of the offset values corresponding to the three templates is carried in one notification message.
  • the ISIS protocol can be extended to add a link attribute sub-TLV called offset-measurement-sub-TLV, which is used to carry the offset measurement value information between the upstream and downstream devices connected by the link.
  • the encapsulation schematic format is shown in Figure 5:
  • the type field uses a specific value to indicate that this sub-TLV is an offset measurement value type.
  • the length field indicates the total length of the data portion of the sub-TLV in bytes. The value of the length field is 12.
  • the cycle-A-length, cycle-B-length, and cycle-C-length fields each occupy 8 bits and are used to indicate the cycle size in microseconds. For example, 10 indicates that the cycle is 10us. 20 indicates that the period is 20us, and 40 indicates that the period is 40us.
  • the offsetA, offsetB, and offsetC fields respectively indicate the offset values measured for the three templates, in nanoseconds (ns), and each occupies 3 bytes.
  • FIG4 shows a schematic diagram of the structure of an apparatus for determining a node delay according to an embodiment of the present application.
  • the apparatus 400 includes: a first determining module 410 and a second determining module 420 .
  • the first determination module 410 is used to determine the intra-cycle time deviation offset, wherein the intra-cycle time deviation is the time difference between the second moment and the start moment of the target cycle window, and the second moment is the moment when the downstream node receives the first message sent by the upstream node; the second determination module 420 is used to determine the node delay nodeDelay based on the offset and the length T of the cycle template.
  • the first determination module 410 is used to determine the time deviation value based on a first moment, the second moment and the length of a period template, wherein the first moment is the start moment of the downstream node or the start moment of the target period window.
  • offset is the time deviation value
  • t1 is the first moment
  • T is the length of the periodic template
  • MOD is used to return the remainder after (t2-t1) and T are divided.
  • the second determination module 420 is used to determine the nodeDelay according to the following formula:
  • the processDelay is the processing delay.
  • the second determination module 420 is configured to determine the regulation delay regulatorDelay according to the following formula.
  • the processDelay is the processing delay.
  • the node delay nodeDelay is determined.
  • the second determination module 420 is used to determine the modulation according to the following formula: Section delay regulatorDelay.
  • the processing delay processDelay is determined according to the upper limit value or the lower limit value.
  • the second determining module 420 is used to record the corresponding relationship between the period template and the nodeDelay after determining the node delay nodeDelay.
  • the second determination module 420 is used to send a first notification message after determining the node delay nodeDelay, where the first notification message includes a correspondence between the periodic template and the nodeDelay.
  • the device 400 provided in the embodiment of the present application can execute the various methods described in the foregoing method embodiments, and realize the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be repeated here.
  • FIG5 shows a schematic diagram of the hardware structure of an electronic device that implements the embodiment of the present application.
  • the electronic device includes a processor, and optionally, an internal bus, a network interface, and a memory.
  • the memory may include a memory, such as a high-speed random access memory (RAM), and may also include a non-volatile memory (non-volatile memory), such as at least one disk storage, etc.
  • RAM high-speed random access memory
  • non-volatile memory such as at least one disk storage, etc.
  • the electronic device may also include hardware required for other services.
  • the processor, the network interface and the memory may be interconnected via an internal bus, which may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus may be divided into an address bus, a data bus, a control bus, etc.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the memory is used to store the program.
  • the program may include a program code, and the program code includes a computer operation instruction.
  • the memory may include a memory and a non-volatile memory, and provides instructions and data to the processor.
  • the processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, forming a device for locating the target user at the logical level.
  • the processor executes the program stored in the memory and is specifically used to execute the method for determining the node delay described in the embodiment of Figure 1a or Figure 2.
  • the method disclosed in the embodiment shown in FIG. 1a or FIG. 2 of the present application can be applied to a processor or implemented by a processor.
  • the processor may be an integrated circuit chip with signal processing capabilities.
  • each step of the above method can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software.
  • the above processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed.
  • the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.
  • the steps of the method disclosed in the embodiments of the present application can be directly embodied as a hardware decoding processor for execution, or a combination of hardware and software modules in the decoding processor for execution.
  • the software module can be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc.
  • the storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.
  • the electronic device can also execute the methods described in the foregoing method embodiments, and realize the functions and beneficial effects of the methods described in the foregoing method embodiments, which will not be described in detail here.
  • the electronic device of the present application does not exclude other implementations, such as logic devices or a combination of software and hardware, etc., that is, the execution of the following processing flow
  • the row body is not limited to each logical unit, but may also be hardware or a logical device.
  • An embodiment of the present application also proposes a computer-readable storage medium, which stores one or more programs.
  • the one or more programs are executed by an electronic device including multiple applications, the electronic device executes the method for determining node delay described in the embodiment of Figure 1a or Figure 2.
  • the computer-readable storage medium includes read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.
  • an embodiment of the present application also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions.
  • the program instructions When the program instructions are executed by a computer, the method for determining node delay described in the embodiment of Figure 1a or Figure 2 is implemented.
  • a typical implementation device is a computer.
  • the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
  • Computer-readable media include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, Parallel Random Access Machine (PRAM), Static Random-Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of random access memory (Random Access Memory, DRAM), and other types of random access memory (Random Access Memory).
  • Computer readable media includes any non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include transitory media such as modulated data signals and carrier waves.

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Abstract

本申请实施例提供了确定节点时延的方法、存储介质和电子设备，所述方法包括：确定周期内时间偏差offset，其中，所述周期内时间偏差为第二时刻与目标周期窗口开始时刻之间的时间差，所述第二时刻为下游节点接收上游节点发送的第一报文的时刻；根据所述offset和周期模板的长度T，确定节点时延nodeDelay。

Description

确定节点时延的方法、存储介质和电子设备
交叉引用
本申请要求在2022年10月20日提交中国专利局、申请号为202211289349.2、发明名称为“确定节点时延的方法、存储介质和电子设备”的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及确定节点时延的方法、存储介质和电子设备。
背景技术
相关技术中，指定周期排队转发(Cycle Specified Queuing and Forwarding，CSQF)和大规模确定性网络网际互联协议技术(Large-scale Deterministic Internet Protocol Network，LDN)，不要求全网时间同步，仅要求频率同步，能够为关键业务提供确定性传输服务。
节点时延主要包括节点处理时延(processDelay)、调节时延(regulatorDelay)和排队时延(queueDelay)。processDelay可以测量得到。regulatorDelay和queueDelay为报文在出口队列中的时间，regulatorDelay时间内报文不允许被调度发送，在queueDelay时间内报文所属队列获得调度机会。
控制面负责规划业务端到端路径以满足业务服务质量(Quality of Service，QoS)要求，构造业务路径计算拓扑，然而由于转发节点采用周期调度转发，不能直接将节点时延代入进行业务路径计算，没有相关方案披露如何确定节点时延。
发明内容
本申请实施例的目的是提供一种确定节点时延的方法、存储介质和 电子设备，能够精确地确定周期内的时间偏差值。
为解决上述技术问题，本申请实施例是通过以下各方面实现的。
第一方面，本申请实施例提供了一种确定节点时延的方法，包括：确定周期内时间偏差offset，其中，所述周期内时间偏差为第二时刻与目标周期窗口开始时刻之间的时间差，所述第二时刻为下游节点接收上游节点发送的第一报文的时刻；根据所述offset和周期模板的长度T，确定节点时延nodeDelay。
第二方面，本申请实施例提供了一种电子设备，包括：存储器、处理器和存储在所述存储器上并可在所述处理器上运行的计算机可执行指令，所述计算机可执行指令被所述处理器执行时实现第一方面所述的确定节点时延的方法。
第三方面，本申请实施例提供了一种计算机可读存储介质，所述计算机可读存储介质用于存储计算机可执行指令，所述计算机可执行指令被处理器执行时实现第一方面所述的确定节点时延的方法。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1a示出本申请实施例提供的确定节点时延的方法的一种流程示意图。
图1b是本申请实施例确定节点时延的方法的示意图。
图1c-1d是本申请实施例确定节点时延的示意图。
图2示出本申请实施例提供的确定节点时延的方法的一种流程示意 图。
图3a是本申请实施例确定节点时延的示意图。
图3b-图3d是报文格式的示意图。
图4示出本申请实施例提供的确定节点时延的装置的结构示意图。
图5为电子设备的硬件结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请中的技术方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
图1a示出本申请实施例提供的确定节点时延的方法的一种流程示意图，该方法可以由网络节点执行，如图所示，该方法可以包括以下步骤。
S102：确定周期内时间偏差offset。
其中，所述周期内时间偏差为第二时刻与目标周期窗口开始时刻之间的时间差，所述第二时刻为下游节点接收上游节点发送的第一报文的时刻。由于节点间没有时间同步，在上下游节点相同周期模板的时隙间存在一定的偏差，称为相位差Δ，该偏差值是随机值。offset值与链路时延和相位差Δ有关，如果周期模板窗口大小为T，offset的取值范围为[0,T)，需要确定offset的值。
图1b是本申请实施例测量时间偏差值的方法的示意图。如图所示，在一实施方式中，上游节点在t0时刻发出第一报文，接收上游节点发送的第一报文，所述第一报文指示所述下游节点测量所述时间偏差值。
确定下游节点接收第一报文的第二时刻t2。确定所述第二时刻对应的所述下游节点的目标周期窗口。
对于下游节点A，第二时刻t2落入对应的所述下游节点A的目标周期窗口WA。对于下游节点B，第二时刻t2落入对应的所述下游节点B的目标周期窗口WB。对于下游节点C，第二时刻t2落入对应的所述下游节点C的目标周期窗口WC。
将所述第二时刻与所述目标周期窗口开始时刻之间的时间差，确定为周期内的时间偏差值，如图所示的offsetA、offsetB、offsetC。
S104：根据所述offset和周期模板的长度T，确定节点时延nodeDelay。
由此，本申请实施例提供的确定节点时延的方法，能够确定节点时延nodeDelay。
在本申请实施例中，通过确定周期内时间偏差offset，其中，所述周期内时间偏差为第二时刻与目标周期窗口开始时刻之间的时间差，所述第二时刻为下游节点接收上游节点发送的第一报文的时刻；根据所述offset和周期模板的长度T，确定节点时延nodeDelay，能够精确地确定节点时延。
在一种可能的实现方式中，在步骤S102中可以根据第一时刻、所述第二时刻和周期模板的长度，确定所述时间偏差值，其中，所述第一时刻为所述下游节点的启动时刻或所述目标周期窗口的开始时刻。
在一种可能的实现方式中，根据以下公式，确定所述时间偏差值，offset＝MOD((t2-t1)，T)。
其中，offset为所述时间偏差值，t1为所述第一时刻，T为所述周期模板的长度，MOD用于返回(t2-t1)与T相除后的余数。
如图所示，(t2-t1)与T相除后的余数为offset值，例如，下游节点C一个周期包括2个周期模板T，下游节点C中(t2-t1)与T相除的商为1，即图中所示的(t2-t1)中包含1个T，offsetC为余数。再例如，下游节点 B一个周期包括6个周期模板T，下游节点B中(t2-t1)与T相除的商为3，即图中所示的(t2-t1)中包含3个T，offsetB为余数。
由此，本申请实施例能够精确地确定周期内的时间偏差值，从而精确地确定节点时延。
在一种可能的实现方式中，在步骤S104中可以根据以下公式(1)，确定调节时延regulatorDelay；
其中，所述processDelay为处理时延。processDelay相对固定，可以为预定值，其存在理论上的上界值和下界值，也可由测量得到。符号表示向上取整。
根据所述regulatorDelay和周期的长度T，确定节点时延nodeDelay。
图1c是本申请实施例测量确定节点时延的示意图。如图所示，报文的接收窗口为y，假设processDelay上界值为0.5T，则根据公式(1)，regulatorDelay值计算得到为T。
在通告regulatorDelay调整后，时隙调度窗口开启，queueDelay为调度窗口开启的时间，即T。
测量报文P2落入窗口的时间偏移量为offset，需要将offset值扣除，即节点时延的确定公式应为公式(2)：
nodeDelayA＝regulatorDelay+queueDelay+(T-offset)     (2)
基于公式(1)和(2)，得到公式(3)
由此，可以根据所述regulatorDelay和排队时延queueDelay，确定节点时延nodeDelay，其中，所述processDelay为处理时延。
在一实施方式中，所述queueDelay可以为所述T，由此得到公式(4)，可以根据所述regulatorDelay和周期的长度T，确定节点时延nodeDelay。
如果上下游节点同时支持多个周期模板，则对每个周期模板，都可测量得到对应的offset值，因此也可计算得到对应的nodeDelay。例如如果上下游节点同时支持三个周期模板A、B、C，则offset值可能不同，分别记为offsetA、offsetB和offsetC，进一步根据公式(4)可计算得到对应的周期调度确定时延nodeDelayA、nodeDelayB和nodeDelayC，如附图1d所示。
由此，本申请实施例能够通过regulatorDelay对processDelay进行一定的吸收处理，消除处理时延带来的抖动，最终精确地确定节点时延。
图2示出本申请实施例提供的确定节点时延的方法的一种流程示意图，该方法可以由网络节点执行，如图所示，该方法可以包括以下步骤。
S202：在激活或使能目标功能的情况下，接收第一报文。
在一实施方式中，在激活网络节点的时间偏差值测量功能的情况下，接收上游节点构造并发送的第一报文，其中，所述激活网络节点的时间偏差值测量功能包括使所述上游节点按照预定规则发送第一报文，所述预定规则包括：发送时刻、发送频率或发送次数中的至少一种。发送时刻可以为周期窗口的开始时刻或结束时刻。
在一实施方式中，为了通过单个第一报文测量多个周期模板的offset值，上游节点第一报文发送时刻对所有的周期模板窗口可以处于开始或结束时刻，因此该第一报文需要在最大周期模板的窗口开始或结束时刻发送。如图1b所示，其中C模板为最大窗口模板，因此可在C模板窗口开始时刻发送一个第一报文，在下游节点中对A、B、C模板分别测量得到不同的offset值，分别记为offsetA、offsetB和offsetC，这三个值可能相等也可能不等。
第一报文可采用多种协议类型，本方案对此不做限定。在一实施方式中，在使能网络节点的时间偏差值测量功能的情况下，接收上游节点 发送的第一报文。
其中，可以通过所述第一报文中的第一字段指示所述下游节点测量所述时间偏差值。第一字段可以为第一报文中现有的字段，也可以是新增加的字段。
通过本步骤可以在激活或使能目标功能的情况下触发offset值的测量。
S204：确定下游节点接收第一报文的第二时刻。
所述第一报文是在所述上游节点的第一周期窗口的目标时刻发送的。第一周期窗口的目标时刻可以包括第一周期窗口的开始时刻或结束时刻。
S206：确定所述第二时刻对应的所述下游节点的目标周期窗口。
S208：确定时间偏差值和节点时延。
本步骤与图1实施例对应步骤相同，不再赘述。
S210：发送第一通告消息。
上述步骤可以控制器内部进行，此时需要将各模板对应的offset和processDelay值测量并上报。上述计算过程还可选的在下游节点内部进行，当下游节点计算得到确定节点时延后，可将该时延值保存在本地节点中，内容至少包含能够标识本端网络设备的地址、接口，能够标识对端网络设备的地址、接口，周期模板窗口大小，节点处理时延，窗口偏移量offset和确定的节点时延值等。
在本步骤中网络设备可以通过第一通告消息将该值向控制器进行通告，以便控制器可以获取该信息，并根据该信息以及其他所需信息进行精准的路径规划、流量调度等。若节点支持多周期模板，则可选的在一个报文中通告多个周期模板和对应确定时延nodeDelay值信息。本发明对信息通告的方式不做限制，例如可通过多种扩展接口上报到控制器。
在一实施方式中，可以记录所述周期模板和所述nodeDelay之间的对 应关系。所述第一通告消息包括所述周期模板和所述nodeDelay之间的对应关系。
此外，在测量出offset值后，网络设备可以将offset值向全网其他节点或者控制器发送第二通告消息进行通告，以便路径计算单元或控制器等组件可以获取该信息，并根据该信息以及其他所需信息进行精准的路径规划、流量调度等。
所述第二通告消息包括所述下游节点的标识信息、所述时间偏差值和所述目标周期窗口之间的对应关系。下游节点的标识信息可以包括能够标识下游节点设备的地址、接口等。第二通告消息还可以包括能够标识第二通告消息接收端网络设备的标识信息，例如地址、接口等。第二通告消息还可以包括周期模板窗口大小等信息。
若网络设备支持多周期调度，则可选的分别发送通告报文或在一个报文中通告多个周期模板和对应offset值信息。本实施例对信息通告的方式不做限制，例如可以通过扩展内部网关协议(Interior Gateway Protocols，IGP)(最短路径优先(Open Shortest Path First，OSPF)、中间系统到中间系统(Intermediate System-to-Intermediate System，ISIS))、边界网关协议(Border Gateway Protocol，BGP)的属性通告到网络其它节点，也可通过扩展南向接口，如网络配置协议(Network Configuration Protocol，NETCONF)、边界网关路径计算单元通信协议(Border Gateway Path Computation Element Protocol，BGPCEP)、边界网关协议链路状态(BGP Link-state，BGP-LS)等，上报到控制器。
在一实施方式中，还可以记录所述时间偏差值；和/或记录所述下游节点的标识信息、所述时间偏差值和所述目标周期窗口之间的对应关系。
以下以示例对本申请实施例进行举例说明。
示例1
假设有两台网络设备N1和N2，两设备间频率同步但时间不同步， 在业务方向N1->N2上，N1是上游设备节点，N2是下游设备节点。N1和N2设备都支持3个周期模板，分别为A、B、C，周期模板时隙长度分别为cycleLengthA＝10us，cycleLengthB＝20us和cycleLengthC＝40us。
下游节点窗口初始化时刻为t1＝10000us，假设上游节点在周期模板C的窗口结束时刻发送的测量报文落在下游节点的时刻为t2＝50015us，则在步骤S102中对应三个模板的周期内偏移量可根据以下计算：
offsetA＝MOD((t2-t1)，cycleLengthA)＝MOD(50015-10000,10)＝5us；
offsetB＝MOD((t2-t1)，cycleLengthB)＝MOD(50015-10000,20)＝15us；
offsetC＝MOD((t2-t1)，cycleLengthC)＝MOD(50015-10000,40)＝15us，如图3a所示。
假设节点处理时延processDelay的下界值为15us，上界值为35us。
节点时延确定过程可在控制器中进行，在S210中将processDelay值和offsetA、offsetB和offSet上报到控制器，节点时延也可在下游节点N2中进行。在S104中对周期模板A，根据以下公式，节点时延确定值为：
类似的，对周期模板B和C，则有：

下表是在N2节点本地记录的各周期模板对应nodeDelay值的数据示例：
表1

示例2
本实施例给出当由下游节点执行节点时延确定时，nodeDelay值上报报文的封装示例，假设存在三个模板A、B和C，本实施例在一个通告报文中同时携带三个模板对应nodeDelay值的信息。以路径计算单元通信协议(Path Computation Element Protocol，PCEP)为例，保留Object-class字段和OT字段为PCEP协议提供方便的扩展方式，用于指示新的消息类型。
在本实施例中，可灵活分配object-class字段和OT字段值表示消息内容为周期模板和对应节点时延确定值，封装格式如图3b所示，其中各字段含义说明如下：
上游节点id，nodeId1字段占用4字节；上游节点出端口id，inferfaceId1字段占4字节；
下游节点id，nodeId2字段占4字节；下游节点入端口id，interfaceId2占4字节；
周期模板长度cycleLengthA、cycleLengthB和cycleLengthC分别占1字节；对应的节点时延确定值nodeDelayA、nodeDelayB和nodeDelayC分别占3字节。
需要指出，本实施例中对PCEP协议报文的扩展方式和取值仅作为示例，此外还可以基于其它协议扩展上报节点时延确定值信息，实施例的内容不作为对本发明的限定。
示例3
假设有两台网络设备N1和N2，两设备间频率同步但时间不同步，在业务方向N1->N2上，N1是上游设备节点，N2是下游设备节点。假设N2节点设备的本地窗口起始时间确定成纳秒为单位为150000ns，N1和N2设备都支持3个周期模板，分别为A、B、C，周期模板时隙长度分别为10000ns，20000ns和40000ns，则测量offset值的步骤如下：
在S202中，使能offset值测量功能，激活N1设备发送第一报文，发送频率为40us，发送次数为3次。N1节点构造第一报文，第一报文指示做offset值测量。N1节点在C模板窗口的开始(或结束)时刻发出第一报文，以40us为间隔，共发出3个第一报文。
在S204中，N2节点记录下3个第一报文的接收时刻，确定成纳秒为单位分别为865000us、905010ns和945005ns。N2接收到每个第一报文时，在S206-S208中，对A、B、C三个周期模板，分别计算对应的offset值，例如第一个第一报文对A模板，offsetA＝MOD(855000-150000,10000)＝5000ns，对B模板有offsetB＝MOD(865000-150000,20000)＝7500ns，对C模板有offsetC＝MOD(865000-150000,40000)＝8750ns；后续两个第一报文计算方式与第一个第一报文相同。N2节点对三次测量结果计算平均值，可得到offsetA＝5005ns,offsetB＝7505ns,offsetC＝8755ns,将计算结果记录在本地。
下表是在N2节点本地记录的各周期模板对应offset值的数据示例：
表2

本实施例给出所述第一报文的封装格式示例。对不同的网络封装和协议，可定义多种第一报文携带方式。如果网络是以太网(Ethernet)，可基于Y.1731的操作维护管理(Operation Administration and Maintenance，OAM)报文封装格式，在OpCode字段中分配一个新的值0x88表示该OAM报文用于测量offset值，OAM报文的数据字段为空，不携带其它值，如图3c所示；在多协议标签交换(Multi-Protocol Label Switching，MPLS)网络中，可基于G-Ach头的OAM第一报文扩展，例如定义新的ChannelType值0xt88表示携带的报文用于测量offset值，如附图3d所示。
在IP网络中，OAM报文目的用户数据报协议/传输控制协议(User Datagram Protocol/Transmission Control Protocol，UDP/TCP)端口号通常用于指示OAM报文的类型，类似的，可分配一个UDP/TCP端口8888指示offset值第一报文。
以其它网络封装和OAM协议做载体的offset值第一报文扩展方式类似，在此不一一举例。
在S210中，发送第二通告消息。
第二通告消息的封装报文示例包括：假设存在三个模板，在一个通告报文中同时携带三个模板对应offset值的信息。例如可以扩展ISIS协议，新增一种链路属性sub-TLV叫做offset-measurement-sub-TLV，用来携带链路连接的上下游设备间offset的测量值信息，封装示意格式如附图五所示：
其中，type字段用一个特定的数值表示此sub-TLV为offset测量值类型，length字段表示该sub-TLV的数据部分的总长度，以字节为单位，length字段的值为12；cycle-A-length、cycle-B-length和cycle-C-length字段各占8bit，用来表示周期大小，单位为微秒，例如10表示周期是10us， 20表示周期是20us，40表示周期是40us。offsetA、offsetB和offsetC字段分别表示针对三个模板测量得到的offset值，单位为纳秒(ns)，分别占3字节。
需要指出，上述各实施例所列举的offset值测量过程和报文的封装格式等均仅作举例说明，不作为对本发明的限定。
图4示出本申请实施例提供的确定节点时延的方法的装置的结构示意图，该装置400包括：第一确定模块410、第二确定模块420。
第一确定模块410用于确定周期内时间偏差offset，其中，所述周期内时间偏差为第二时刻与目标周期窗口开始时刻之间的时间差，所述第二时刻为下游节点接收上游节点发送的第一报文的时刻；第二确定模块420用于根据所述offset和周期模板的长度T，确定节点时延nodeDelay。
在一种实现方式中，第一确定模块410用于根据第一时刻、所述第二时刻和周期模板的长度，确定所述时间偏差值，其中，所述第一时刻为所述下游节点的启动时刻或所述目标周期窗口的开始时刻。
在一种实现方式中，第一确定模块410用于根据以下公式，确定所述时间偏差值；offset＝MOD((t2-t1)，T)。
其中，offset为所述时间偏差值，t1为所述第一时刻，T为所述周期模板的长度，MOD用于返回(t2-t1)和T相除后的余数。
在一种实现方式中，第二确定模块420用于根据以下公式，确定所述nodeDelay；其中，所述processDelay为处理时延。
在一种实现方式中，第二确定模块420用于根据以下公式，确定调节时延regulatorDelay。
所述processDelay为处理时延。
根据所述regulatorDelay和周期的长度T，确定节点时延nodeDelay。
在一种实现方式中，第二确定模块420用于根据以下公式，确定调 节时延regulatorDelay。
根据所述regulatorDelay和排队时延queueDelay，确定节点时延nodeDelay，其中，所述queueDelay为所述T。
在一种实现方式中，根据上界值或下界值，确定处理时延processDelay。
在一种实现方式中，第二确定模块420用于在确定节点时延nodeDelay之后，记录所述周期模板和所述nodeDelay之间的对应关系。
在一种实现方式中，第二确定模块420用于在确定节点时延nodeDelay之后，发送第一通告消息，所述第一通告消息包括所述周期模板和所述nodeDelay之间的对应关系。
本申请实施例提供的该装置400，可执行前文方法实施例中所述的各方法，并实现前文方法实施例中所述的各方法的功能和有益效果，在此不再赘述。
图5示出执行本申请实施例提供的电子设备的硬件结构示意图，参考该图，在硬件层面，电子设备包括处理器，可选地，包括内部总线、网络接口、存储器。其中，存储器可能包含内存，例如高速随机存取存储器(Random-Access Memory，RAM)，也可能还包括非易失性存储器(non-volatile memory)，例如至少1个磁盘存储器等。当然，该电子设备还可能包括其他业务所需要的硬件。
处理器、网络接口和存储器可以通过内部总线相互连接，该内部总线可以是工业标准体系结构(Industry Standard Architecture，ISA)总线、外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，该图中仅用一个双向箭头表示，但并不表示仅有一根总线或一种类型的总线。
存储器，用于存放程序。具体地，程序可以包括程序代码，所述程序代码包括计算机操作指令。存储器可以包括内存和非易失性存储器，并向处理器提供指令和数据。
处理器从非易失性存储器中读取对应的计算机程序到内存中然后运行，在逻辑层面上形成定位目标用户的装置。处理器，执行存储器所存放的程序，并具体用于执行图1a或图2实施例所述的确定节点时延的方法。
上述如本申请图1a或图2所示实施例揭示的方法可以应用于处理器中，或者由处理器实现。处理器可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器可以是通用处理器，包括中央处理器(Central Processing Unit，CPU)、网络处理器(Network Processor，NP)等；还可以是数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field－Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
该电子设备还可执行前文方法实施例中所述的各方法，并实现前文方法实施例中所述的各方法的功能和有益效果，在此不再赘述。
当然，除了软件实现方式之外，本申请的电子设备并不排除其他实现方式，比如逻辑器件抑或软硬件结合的方式等等，也就是说以下处理流程的执 行主体并不限定于各个逻辑单元，也可以是硬件或逻辑器件。
本申请实施例还提出了一种计算机可读存储介质，所述计算机可读介质存储一个或多个程序，所述一个或多个程序当被包括多个应用程序的电子设备执行时，使得所述电子设备执行图1a或图2实施例所述的确定节点时延的方法。
其中，所述的计算机可读存储介质包括只读存储器(Read-Only Memory，简称ROM)、随机存取存储器(Random Access Memory，简称RAM)、磁碟或者光盘等。
进一步地，本申请实施例还提供了一种计算机程序产品，所述计算机程序产品包括存储在非暂态计算机可读存储介质上的计算机程序，所述计算机程序包括程序指令，当所述程序指令被计算机执行时，实现图1a或图2实施例所述的确定节点时延的方法。
总之，以上所述仅为本申请的较佳实施例，并非用于限定本申请的保护范围。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。
上述实施例阐明的系统、装置、模块或单元，具体可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算机。具体的，计算机例如可以为个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任何设备的组合。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(Parallel Random Access Machine，PRAM)、静态随机存取存储器(Static Random-Access Memory，SRAM)、动态随机存取存储器(Dynamic Random Access Memory，DRAM)、其他类型的随机存取存储器(Random Access  Machine，RAM)、只读存储器(Read-Only Memory，ROM)、电可擦除可编程只读存储器(Electrically Erasable Programmable read only memory，EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(Compact Disc Read-Only Memory，CD-ROM)、数字多功能光盘(Digital Video Disc，DVD)或其他光学存储、磁盒式磁带，磁带磁磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。

Claims (10)

  1. 一种确定节点时延的方法，包括：
    确定周期内时间偏差offset，其中，所述周期内时间偏差为第二时刻与目标周期窗口开始时刻之间的时间差，所述第二时刻为下游节点接收上游节点发送的第一报文的时刻；
    根据所述offset和周期模板的长度T，确定节点时延nodeDelay。
  2. 根据权利要求1所述的方法，其中，所述确定周期内时间偏差offset，包括：
    根据第一时刻、所述第二时刻和周期模板的长度，确定所述时间偏差值，其中，所述第一时刻为所述下游节点的启动时刻或所述目标周期窗口的开始时刻。
  3. 根据权利要求2所述的方法，其中，根据第一时刻、所述第二时刻和周期模板的长度，确定所述时间偏差值，包括：
    根据以下公式，确定所述时间偏差值；
    offset＝MOD((t2-t1)，T)；
    其中，offset为所述时间偏差值，t1为所述第一时刻，T为所述周期模板的长度，MOD用于返回(t2-t1)和T相除后的余数。
  4. 根据权利要求1所述的方法，其中，根据所述offset和周期模板的长度T，确定节点时延nodeDelay，包括：
    根据以下公式，确定所述nodeDelay；
    其中，所述processDelay为处理时延。
  5. 根据权利要求1所述的方法，其中，根据所述offset和周期模板的长度T，确定节点时延nodeDelay，包括：
    根据以下公式，确定调节时延regulatorDelay；
    所述processDelay为处理时延；
    根据所述regulatorDelay和周期的长度T，确定节点时延nodeDelay。
  6. 根据权利要求1所述的方法，其中，根据所述offset和周期模板的长度T，确定节点时延nodeDelay，包括：
    根据以下公式，确定调节时延regulatorDelay；
    根据所述regulatorDelay和排队时延queueDelay，确定节点时延nodeDelay，其中，所述processDelay为处理时延、所述queueDelay为所述T。
  7. 根据权利要求1所述的方法，其中，在确定节点时延nodeDelay之后，所述方法还包括：
    记录所述周期模板和所述nodeDelay之间的对应关系。
  8. 根据权利要求1所述的方法，其中，在确定节点时延nodeDelay之后，所述方法还包括：
    发送第一通告消息，所述第一通告消息包括所述周期模板和所述nodeDelay之间的对应关系。
  9. 一种电子设备，包括：
    处理器；以及
    被安排成存储计算机可执行指令的存储器，所述可执行指令在被执行时使用所述处理器执行：权利要求1-8中任一项所述的确定节点时延的方法。
  10. 一种计算机可读介质，所述计算机可读介质存储一个或多个程序，所述一个或多个程序当被包括多个应用程序的电子设备执行时，使得所述电子设备执行：权利要求1-8中任一项所述的确定节点时延的方法。
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