WO2024078043A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2024078043A1
WO2024078043A1 PCT/CN2023/104277 CN2023104277W WO2024078043A1 WO 2024078043 A1 WO2024078043 A1 WO 2024078043A1 CN 2023104277 W CN2023104277 W CN 2023104277W WO 2024078043 A1 WO2024078043 A1 WO 2024078043A1
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WIPO (PCT)
Prior art keywords
ohmic contact
layer
substrate
contact layer
source
Prior art date
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Ceased
Application number
PCT/CN2023/104277
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English (en)
French (fr)
Inventor
李治福
刘广辉
艾飞
宋德伟
李壮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US18/851,809 priority Critical patent/US20250212512A1/en
Publication of WO2024078043A1 publication Critical patent/WO2024078043A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technology, and in particular to a display panel.
  • Integrating pixel drive circuits, gate drive circuits, multiplexed power circuits, source drive circuits, timing controllers and other circuits on a glass substrate can greatly improve the integration of display panels, reduce dependence on integrated circuit chips, and thus reduce costs.
  • SOG system on glass
  • the architecture of the thin film transistor of the existing display panel cannot further reduce the channel length, volume and floor space of the thin film transistor. Therefore, the architecture of the thin film transistor of the existing display panel needs to be improved urgently.
  • An embodiment of the present invention provides a display panel to solve the technical problem that the thin film transistors of the existing display panel occupy a large area.
  • An embodiment of the present invention provides a display panel, including:
  • a multi-layer ohmic contact layer is stacked on the substrate
  • a multi-layer insulating layer wherein at least one insulating layer is disposed between two adjacent ohmic contact layers;
  • a semiconductor layer at least disposed on the first sidewall on the same side of the multiple ohmic contact layers, wherein the semiconductor layer comprises a plurality of spaced active portions, and the active portions contact and connect the first sidewalls of two of the ohmic contact layers;
  • a gate disposed on a side of the semiconductor layer facing away from the substrate;
  • the source-drain electrode layer is arranged on a side of the gate away from the substrate, and the source-drain electrode layer is electrically connected to the corresponding ohmic contact layer.
  • the semiconductor layer includes a plurality of oxidized insulating portions, each of which is located between two adjacent active portions.
  • the active portion and the oxidized insulating portion are in a continuous pattern.
  • an orthographic projection of the oxidized insulating portion on the first side wall of the ohmic contact layer is located between two adjacent ohmic contact layers.
  • the material of the oxidized insulating portion includes silicon oxide, and the material of the active portion includes polysilicon.
  • the semiconductor layer includes a hollow portion, and the hollow portion is located between two adjacent active portions.
  • the display panel includes a first ohmic contact layer, a first insulating layer, a second ohmic contact layer, a second insulating layer, a third ohmic contact layer, a third insulating layer, and a fourth ohmic contact layer sequentially stacked on the substrate.
  • the semiconductor layer includes a first active portion and a second active portion, the first active portion is in contact with the first ohmic contact layer and the second ohmic contact layer, and the second active portion is in contact with the third ohmic contact layer and the fourth ohmic contact layer.
  • the source-drain layer includes a first source, a first drain, a second source and a second drain, which are arranged on the side of the gate facing away from the substrate, one of the first source and the first drain is electrically connected to the first ohmic contact layer, the other of the first source and the first drain is electrically connected to the second ohmic contact layer, one of the second source and the second drain is electrically connected to the third ohmic contact layer, and the other of the second source and the second drain is electrically connected to the fourth ohmic contact layer.
  • the orthographic projections of the first source and the first drain on the substrate are located on one side of the orthographic projection of the gate on the substrate, and the second source and the second drain are located on the other side opposite to the orthographic projection of the gate on the substrate.
  • the first ohmic contact layer includes a first protrusion, the orthographic projection of the first protrusion on the substrate does not overlap with the orthographic projections of the second ohmic contact layer, the third ohmic contact layer and the fourth ohmic contact layer on the substrate, and the first protrusion is electrically connected to one of the first source and the first drain;
  • the second ohmic contact layer includes a second protrusion, the orthographic projection of the second protrusion on the substrate does not overlap with the orthographic projections of the third ohmic contact layer and the fourth ohmic contact layer on the substrate, and the second protrusion is electrically connected to the other of the first source and the first drain;
  • the third ohmic contact layer includes a third protrusion, the orthographic projection of the third protrusion on the substrate does not overlap with the orthographic projection of the fourth ohmic contact layer on the substrate, and the third protrusion is electrically connected to one of the second source and the second drain.
  • the second insulating layer includes a via hole
  • the third ohmic contact layer is electrically connected to the second ohmic contact layer through the via hole.
  • the source-drain layer includes a first source and a first drain arranged on the side of the gate facing away from the substrate, one of the first source and the first drain is electrically connected to the first ohmic contact layer, and the other of the first source and the first drain is electrically connected to the fourth ohmic contact layer.
  • the orthographic projection of the first source electrode on the substrate is located on one side of the orthographic projection of the gate electrode on the substrate, and the orthographic projection of the first drain electrode on the substrate is located on the other side of the orthographic projection of the gate electrode on the substrate.
  • the first ohmic contact layer includes a first protrusion
  • the orthographic projection of the first protrusion on the substrate does not overlap with the orthographic projections of the second ohmic contact layer, the third ohmic contact layer, and the fourth ohmic contact layer on the substrate, and the first protrusion is electrically connected to one of the first source and the first drain.
  • a distance between the first active portion and the second active portion is greater than zero and less than H1 , where H1 is the sum of a width of a first sidewall of the second ohmic contact layer, a width of a second sidewall of the second insulating layer, and a width of a first sidewall of the third ohmic contact layer.
  • the semiconductor layer further includes a horizontal portion, the horizontal portion is in contact with and connected to one of the active portions, and the horizontal portion is disposed on the surface of the substrate.
  • the horizontal portion and the active portion are arranged obliquely, and the angle between the horizontal portion and the active portion is 90° to 135°.
  • the material of the horizontal portion includes amorphous silicon material.
  • the substrate includes a base plate, a buffer layer arranged on a side of the base plate close to the ohmic contact layer, and a shading layer located between the base plate and the buffer layer, and the orthographic projection of the shading layer on the base plate covers the orthographic projection of each active portion of the semiconductor layer on the base plate.
  • the display panel provided by the embodiment of the present invention includes a substrate, a plurality of ohmic contact layers, a plurality of insulating layers, a semiconductor layer, a gate electrode and a source-drain electrode layer, wherein at least one insulating layer is provided between two adjacent ohmic contact layers, the semiconductor layer is at least provided on the first side wall on the same side of the plurality of ohmic contact layers, the semiconductor layer includes a plurality of spaced active portions, the active portions contact and connect the first side walls of the two ohmic contact layers, the gate electrode is provided on the side of the semiconductor layer away from the substrate, the source-drain electrode layer is provided on the side of the gate electrode away from the substrate, and is electrically connected to the corresponding ohmic contact layer.
  • the plurality of ohmic contact layers By stacking the plurality of ohmic contact layers and arranging the semiconductor layer on the side wall of the ohmic contact layer, not only the length of the thin film transistor is reduced and the on-state current is increased, but also the stacking of multiple thin film transistors in the thickness direction of the display panel can be realized, the volume of the thin film transistor is reduced, and the footprint of the thin film transistor is reduced, which is conducive to improving the integration of the device.
  • FIG1 is a schematic diagram of a planar structure of a thin film transistor provided by an embodiment of the present invention.
  • Fig. 2 is a schematic cross-sectional view along the B-B direction in Fig. 1;
  • Fig. 3 is a schematic cross-sectional view along the A-A direction in Fig. 1;
  • FIG4 is a schematic diagram of a stacked structure of a thin film transistor provided by another embodiment of the present invention.
  • FIG5 is a schematic diagram of a planar structure of a thin film transistor provided by another embodiment of the present invention.
  • Fig. 6 is a schematic cross-sectional view along the B-B direction in Fig. 5;
  • Fig. 7 is a schematic cross-sectional view along the A-A direction in Fig. 5;
  • 8a to 8i are schematic structural diagrams of a process for preparing a display panel according to an embodiment of the present invention.
  • a first feature "on” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them.
  • a first feature "on”, “above” or “above” a second feature includes that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.
  • Figure 1 is a schematic plan view of a thin film transistor of a display panel provided by an embodiment of the present invention
  • Figure 2 is a schematic cross-sectional view along the B-B direction in Figure 1
  • Figure 3 is a schematic cross-sectional view along the A-A direction in Figure 1.
  • the display panel 100 provided by an embodiment of the present invention includes a substrate 10 and a thin film transistor 20, and the thin film transistor 20 is disposed on the substrate 10.
  • the thin film transistor 20 can be applied to many circuits such as a pixel driving circuit, a gate driving circuit, a source driving circuit, a timing controller, and a multiplexing circuit in the display panel.
  • the display panel 100 includes a substrate 10, a plurality of ohmic contact layers (such as 21, 22, 23, 24), a plurality of insulating layers (such as 31, 32, 33), a semiconductor layer 25, a gate 26 and a source-drain electrode layer 27, wherein the plurality of ohmic contact layers are stacked on the substrate 10, at least one insulating layer is provided between adjacent ohmic contact layers, the semiconductor layer 25 is provided at least on a first side wall 201 of the plurality of ohmic contact layers, the gate 26 is provided on a side of the semiconductor layer 25 away from the substrate 10, and the source-drain electrode layer 27 is provided on a side of the gate 26 away from the substrate 10.
  • a gate insulating layer 34 is provided between the gate 26 and the semiconductor layer 25, an interlayer dielectric layer 35 is provided between the source-drain electrode layer 27 and the gate 26, and the semiconductor layer 25 includes a plurality of spaced active portions (such as 251, 252), and the active portions contact and connect the first sidewalls 201 of the two layers of the ohmic contact layer (such as 251 contacting and connecting 21, 22, and 252 contacting and connecting 23, 24).
  • the thin film transistor 20 can be composed of, but not limited to, the above-mentioned multiple layers of ohmic contact layers, semiconductor layer 25, gate 26, and source-drain electrode layer 27.
  • the active layer of the thin film transistor in the prior art is prepared on the same plane, and multiple thin film transistors are arranged flat, resulting in a large circuit footprint.
  • the channel length is generally above 2 microns, and the size of the transistor cannot be further reduced.
  • the channel of the thin film transistor 20 (the part of the active part that contacts and connects the two ohmic contact layers) is formed on the first side wall 201 of the ohmic contact layer. The channel length is determined by the distance between the ohmic contact layers on both sides.
  • the embodiment of the present invention can achieve the stacking of multiple thin film transistors 20 in the thickness direction of the display panel, which can greatly reduce the footprint of the thin film transistor 20 and thus improve the integration of the device.
  • the thin film transistor 20 is a polycrystalline silicon thin film transistor, that is, the active portion of the semiconductor layer 25 is a polycrystalline silicon material, and the semiconductor layer 25 further includes a plurality of oxidized insulating portions 253, each of which is located between two adjacent active portions (such as 251 and 252), and the adjacent active portions are separated by the oxidized insulating portions 253 to achieve electrical isolation.
  • an amorphous silicon film is formed on the first side wall 201 , and a portion of the amorphous silicon film that needs to be insulated is oxidized to form silicon oxide (eg, a silicon oxide film layer), thereby forming the oxidized insulating portion 253 .
  • silicon oxide eg, a silicon oxide film layer
  • the oxidized insulating portion 253 and the active portion together form a continuous pattern, which can be realized by only one film deposition process, without adding a new film process, and the process is simple, and the film adhesion of the semiconductor layer 25 on the inclined surface can also be enhanced.
  • the continuous pattern mentioned above refers to a pattern formed continuously without seams or openings.
  • a hollow portion 254 can also be formed by etching the semiconductor layer 25 while etching the semiconductor layer 25.
  • the hollow portion 254 is located between two adjacent active portions, and no new process is added. It is understandable that the hollow portion 254 penetrates the semiconductor layer 25 in the thickness direction of the semiconductor layer 25, thereby achieving insulation between adjacent active portions.
  • the scheme of forming the hollow portion 254 may have the risk of incomplete etching, and the adhesion of the film layer will be reduced. Therefore, in the specific embodiment of the present invention, the scheme of oxidizing the insulating portion is preferred, and its semiconductor film layer has stronger stability.
  • the semiconductor layer 25 at least covers the first side wall 201 of the multi-layer ohmic contact layer and the second side wall 301 of the multi-layer insulating layer on the same side as the first side wall 201.
  • the semiconductor layer 25 further includes a horizontal portion 255, the horizontal portion 255 is in contact with an active portion, and the horizontal portion 255 is disposed on the surface of the substrate 10.
  • the active portion is the one closest to the substrate 10 among the multiple active portions, that is, the active portion is the first active portion 251. Since the active part is inclined at a certain angle relative to the substrate 10, the horizontal part 255 is inclined to the active part.
  • the material of the horizontal part 255 is amorphous silicon material.
  • a seed crystal can be formed at the corner between the horizontal part 255 and the first active part 251.
  • the seed crystal can be generated along the oblique wall direction where the first side wall 201 and the second side wall 301 are located.
  • the channel length of the thin film transistor 20 is controlled between 0.01 and 1 micron. In this way, there can be only one grain in a channel, that is, the channel is composed of a single grain, and there is no grain boundary. Compared with the existing thin film transistor with multiple grain boundaries, while reducing the size of the thin film transistor, the mobility of the thin film transistor is greatly improved.
  • the semiconductor layer 25 by extending the semiconductor layer 25 to form the horizontal part 255, the adhesion between the semiconductor layer and the film layer can be increased, and the stability of the thin film transistor device can be improved.
  • the angle ⁇ between the horizontal portion 255 and the active portion is preferably 90° ⁇ 135°, and the angle ⁇ is also the angle between the first side wall 201 and the second side wall 301 and the substrate 10.
  • the thickness between two adjacent ohmic contact layers in an embodiment of the present invention is 0.0071 ⁇ 1 micron, so that the length of the channel can be controlled to be less than 1 micron.
  • the semiconductor layer 25 can also cover the surface of the multi-layer ohmic contact layer facing away from the substrate 10, that is, the semiconductor layer 25 can continue to extend upward to another horizontal portion parallel to the substrate 10. In this way, the preparation of a small-sized semiconductor layer 25 can be achieved with the accuracy of the existing exposure machine without changing the process.
  • the embodiment of the present invention is described by taking the stacking of two thin film transistors as an example, but the invention is not limited thereto, and three, four or more thin film transistors may also be stacked.
  • the display panel includes a first ohmic contact layer 21, a first insulating layer 31, a second ohmic contact layer 22, a second insulating layer 32, a third ohmic contact layer 23, a third insulating layer 33, and a fourth ohmic contact layer 24 stacked sequentially on the substrate 10.
  • the semiconductor layer 25 includes a first active portion 251 and a second active portion 252, the first active portion 251 is in contact with the first ohmic contact layer 21 and the second ohmic contact layer 22, and the portion of the first active portion 251 located between the first ohmic contact layer 21 and the second ohmic contact layer 22 forms a channel of a thin film transistor, that is, the length of the channel can be determined by the length and inclination angle of the second side wall 301 of the first insulating layer 31 between the first ohmic contact layer 21 and the second ohmic contact layer 22, and the length of the channel can be controlled to be less than 1 micron.
  • the source-drain layer 27 includes a first source 271 and a first drain 272 disposed on a side of the gate 26 away from the substrate 10 , one of the first source 271 and the first drain 272 is electrically connected to the first ohmic contact layer 21 , and the other of the first source 271 and the first drain 272 is electrically connected to the second ohmic contact layer 22 .
  • the second active portion 252 is in contact with the third ohmic contact layer 23 and the fourth ohmic contact layer 24, and a portion of the second active portion 252 located between the third ohmic contact layer 23 and the fourth ohmic contact layer 24 forms a channel of another thin film transistor.
  • the length of the channel is determined by the length and the inclination angle of the second side wall 301 of the third insulating layer 33 between the third ohmic contact layer 23 and the fourth ohmic contact layer 24, and the length of the channel can be controlled to be less than 1 micron.
  • the source-drain layer 27 also includes a second source 273 and a second drain 274 disposed on a side of the gate 26 away from the substrate 10 , one of the second source 273 and the second drain 274 being electrically connected to the third ohmic contact layer 23 , and the other of the second source 273 and the second drain 274 being electrically connected to the fourth ohmic contact layer 24 .
  • the orthographic projection of the gate electrode 26 on the substrate 10 covers the orthographic projection of the semiconductor layer 25 on the substrate 10 , so as to facilitate control of the formation positions and lengths of the channels of the plurality of thin film transistors.
  • a thin film transistor is composed of but not limited to a first active portion 251, a first ohmic contact layer 21, a second ohmic contact layer 22, a first source 271, a first drain 272 and a gate 26, and another thin film transistor is composed of but not limited to a second active portion 252, a third ohmic contact layer 23, a fourth ohmic contact layer 24, a second source 273, a second drain 274 and a gate 26.
  • a short channel thin film transistor device be prepared on the basis of an existing process to increase the on-state current, but also a plurality of thin film transistors can be stacked in the thickness direction, thereby reducing the transistor footprint, improving the device integration, and facilitating the integration of IC circuits on a substrate.
  • the first source electrode 271 and the first drain electrode 272 are disposed on one side of the gate electrode 26, and the second source electrode 273 and the second drain electrode 274 are disposed on the other side opposite to the gate electrode 26.
  • the orthographic projections of the first source electrode 271 and the first drain electrode 272 on the substrate 10 are located on one side of the orthographic projection of the gate electrode 26 on the substrate 10, and the second source electrode 273 and the second drain electrode 274 are located on the other side opposite to the orthographic projection of the gate electrode 26 on the substrate 10.
  • the source and drain electrodes of the two thin film transistors can be connected to their respective corresponding ohmic contact layers via holes.
  • the first ohmic contact layer 21 includes a first protrusion 211, the orthographic projection of the first protrusion 211 on the substrate 10 does not overlap with the orthographic projections of the second ohmic contact layer 22, the third ohmic contact layer 23, and the fourth ohmic contact layer 24 on the substrate 10, and the first protrusion 211 is electrically connected to one of the first source 271 and the first drain 272.
  • the first source 271/the first drain 272 can be prevented from passing through the upper ohmic contact layer and contacting the upper ohmic contact layer.
  • the second ohmic contact layer 22 includes a second protruding portion 221, the orthographic projection of the second protruding portion 221 on the substrate 10 does not overlap with the orthographic projections of the third ohmic contact layer 23 and the fourth ohmic contact layer 24 on the substrate 10, and the second protruding portion 221 is electrically connected to the other of the first source 271 and the first drain 272.
  • the second protruding portion 221 and the first protruding portion 211 are located on the same side of the gate 26.
  • the third ohmic contact layer 23 includes a third protruding portion 231, the orthographic projection of the third protruding portion 231 on the substrate 10 does not overlap with the orthographic projection of the fourth ohmic contact layer 24 on the substrate 10, and the third protruding portion 231 is electrically connected to one of the second source 273 and the second drain 274.
  • the third protruding portion 231 is disposed on a different side from the second protruding portion 221 and the first protruding portion 211, and the third protruding portion 231 is located on the other side opposite to the gate 26.
  • first source 271, the first drain 272, the second source 273 and the second drain 274 may also be located on the same side of the gate 26, but considering the wiring space, it is preferred to arrange the first source 271, the first drain 272 and the second source 273, the second drain 274 on opposite sides of the gate 26.
  • the above embodiment is a superposition of two thin film transistors.
  • Other embodiments of superposition of more thin film transistors are similar to the above embodiment and can refer to the above description.
  • the ohmic contact layers of two thin film transistors may be electrically connected through via holes.
  • Figure 5 is a schematic top view of a thin film transistor of another embodiment of the present invention
  • Figure 6 is a schematic cross-sectional view of Figure 5 along the B-B direction
  • Figure 7 is a schematic cross-sectional view of Figure 6 along the A-A direction.
  • two thin film transistors are still used as an example for explanation.
  • the structures of other thin film transistors can refer to the description of this embodiment.
  • the third ohmic contact layer 23 can be electrically connected to the second ohmic contact layer 22.
  • the second insulating layer 32 includes a via hole, and the third ohmic contact layer 23 is electrically connected to the second ohmic contact layer 22 through the via hole.
  • the two thin film transistors connected in series only need one source and drain, that is, the source-drain layer 27 includes a first source 271 and a first drain 272 arranged on the side of the gate 26 away from the substrate 10, wherein one of the first source 271 and the first drain 272 is electrically connected to the first ohmic contact layer 21, and the other of the first source 271 and the first drain 272 is electrically connected to the fourth ohmic contact layer 24.
  • the first source 271 and the first drain 272 are respectively arranged on two opposite sides of the gate 26 to facilitate wiring design. That is, the orthographic projection of the first source 271 on the substrate 10 is located on one side of the orthographic projection of the gate 26 on the substrate 10, and the orthographic projection of the first drain 272 on the substrate 10 is located on the other side of the orthographic projection of the gate 26 on the substrate 10.
  • the first ohmic contact layer 21 includes a first protruding portion 211, the orthographic projection of the first protruding portion 211 on the substrate 10 does not overlap with the orthographic projections of the second ohmic contact layer 22, the third ohmic contact layer 23, and the fourth ohmic contact layer 24 on the substrate 10, and the first protruding portion 211 is electrically connected to one of the first source 271 and the first drain 272.
  • the first source 271/first drain 272 formed subsequently can avoid the upper ohmic contact layer and directly pass through the via hole of the insulating layer to be electrically connected to the first ohmic contact layer 21.
  • the spacing between two adjacent active parts is greater than zero and less than H 1 , H 1 being the sum of the width of the first sidewalls 201 of the two adjacent ohmic contact layers to which the two active parts are respectively connected and the width of the second sidewall 301 of the insulating layer between the two adjacent ohmic contact layers.
  • H 1 being the sum of the width of the first sidewall 201 of the second ohmic contact layer 22 and the width of the second sidewall 301 of the second insulating layer 32 and the width of the first sidewall 201 of the third ohmic contact layer 23.
  • H 1 corresponds to the width of the hollow part 254 or the maximum width of the oxidized insulating part 253, so that the electrical insulation between the adjacent active parts can be ensured, and the active parts can be in contact and connected with the ohmic contact layer below them.
  • the substrate 10 includes a base plate 11 and a buffer layer 12 disposed between the thin film transistor 20 and the base plate 11.
  • a light shielding layer 13 may be disposed between the buffer layer 12 and the base plate 11, and the orthographic projection of the light shielding layer 13 on the base plate 11 covers the orthographic projection of each active portion of the semiconductor layer 25 on the base plate 11.
  • the step flow chart of the preparation method of the display panel mentioned in the above embodiment is shown in Figures 8a to 8i, and the preparation method includes: S10, alternately depositing materials of multiple layers of ohmic contact layers and multiple layers of insulating layers on the substrate 10 in sequence, as shown in Figures 8a and 8b; S20, etching different positions of the multiple layers of ohmic contact layers and the multiple layers of insulating layers at different depths to form ohmic contact layers of different lengths and multiple layers of insulating layers of different lengths, as shown in Figures 8c to 8e; S30, depositing amorphous silicon material on the outermost ohmic contact layer, and oxidizing the set area 2501 so that the amorphous silicon in the set area 2501 is oxidized into oxide silicide, as shown in Figures 8f and 8g; S40, preparing the gate 26 and the source and drain layer 27 in sequence, as shown in Figures 8h and 8i.
  • a light shielding layer 13 is formed on the substrate 11 , and the material of the light shielding layer 13 includes but is not limited to a metal material. Then, a buffer layer 12 is deposited on the light shielding layer 13 .
  • the material of the buffer layer 12 includes, but is not limited to, any one of silicon nitride, silicon oxide, or silicon oxynitride, or a combination of multiple materials.
  • the material of the first ohmic contact layer 21, the material of the first insulating layer 31, the material of the second ohmic contact layer 22, the material of the second insulating layer 32, the material of the third ohmic contact layer 23, the material of the third insulating layer 33 and the material of the fourth ohmic contact layer 24 are sequentially stacked on the buffer layer 12; then etching of different depths is performed to form the first protrusion 211, the second protrusion 221 and the third protrusion 231.
  • the etching process of different depths can be performed through the same grayscale mask or in multiple photomasks, which is not limited here.
  • the ohmic contact layers mentioned above are all N-type heavily doped amorphous silicon materials, and the ohmic contact layers may also be doped with impurity elements such as phosphorus or arsenic.
  • the materials of the insulating layers mentioned above may be commonly used inorganic insulating materials such as silicon nitride, silicon oxide or silicon oxynitride.
  • an amorphous silicon material is deposited on the fourth ohmic contact layer 24, and the amorphous silicon is crystallized, and then the amorphous silicon material is etched to form a pattern of the semiconductor layer 25; then a hard mask layer (hard mask) 200 is formed on the semiconductor layer 25, and a fracture is formed in a set area 2501 to expose the amorphous silicon material in the set area 2501, and the hard mask layer 200 can be a SiN layer; then the above-mentioned device is placed in an oxygen environment, so that the exposed amorphous silicon material is oxidized into oxysilicide to become an insulator, that is, an oxidized insulating portion 253 is formed; finally, the hard mask layer is removed.
  • the amorphous silicon material can be crystallized by an excimer laser annealing process, so that the amorphous silicon can be transformed into a polycrystalline silicon structure, and then the polycrystalline silicon structure is etched to form a pattern of the semiconductor layer 25. Since the energy of the excimer laser annealing process is limited and is completely absorbed by the amorphous silicon, when the amorphous silicon layer is crystallized, the ohmic contact layer can still maintain the amorphous silicon structure.
  • the crystallization of amorphous silicon can also be performed after the oxidation treatment, which is not limited here.
  • a gate insulating layer 34 is first formed on the semiconductor layer 25, and then a pattern of the gate 26 is formed; then, the material of the interlayer dielectric layer 35 is deposited on the gate 26, and then the interlayer dielectric layer 35 and the gate insulating layer 34 are etched by the same etching process to form vias of different depths at different positions; then, a pattern of the source-drain electrode layer 27 is formed on the interlayer dielectric layer 35, and each source and drain of the source-drain electrode layer 27 is electrically connected to the corresponding ohmic contact layer of the lower layer through vias of different positions and depths.
  • an embodiment of the present invention provides a display panel, including a substrate 10, multiple ohmic contact layers, multiple insulating layers, a semiconductor layer 25, a gate electrode 26 and a source-drain electrode layer 27, wherein at least one insulating layer is provided between two adjacent ohmic contact layers, the semiconductor layer 25 is at least provided on the first side wall on the same side of the multiple ohmic contact layers, the semiconductor layer 25 includes multiple spaced active portions, the active portions contact and connect the first side walls 201 of the two ohmic contact layers, the gate electrode 26 is provided on the side of the semiconductor layer 25 away from the substrate 10, and the source-drain electrode layer 27 is provided on the side of the gate electrode 26 away from the substrate 10, and is electrically connected to the corresponding ohmic contact layer.
  • the semiconductor layer 25 By stacking multiple ohmic contact layers and arranging the semiconductor layer 25 on the side wall of the ohmic contact layer, not only the length of the thin film transistor is reduced and the on-state current is increased, but also the stacking of multiple thin film transistors in the thickness direction of the display panel can be realized, the volume of the thin film transistor is reduced, and the footprint of the thin film transistor is reduced, which is conducive to improving the integration of the device.
  • a display panel provided by an embodiment of the present invention is introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

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Abstract

一种显示面板，包括衬底、多层欧姆接触层、多层绝缘层，一半导体层、栅极及源漏极层，相邻的两欧姆接触层之间设有至少一绝缘层，半导体层至少设于多层欧姆接触层的第一侧壁上，半导体层包括与第一侧壁接触连接的多个有源部，栅极设于半导体层背离衬底的一侧，源漏极层设于栅极背离衬底的一侧，且与对应的欧姆接触层电连接。

Description

显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
将像素驱动电路、栅极驱动电路、复用电力路、源极驱动电路、时序控制器等电路集成在玻璃基板上（system on glass，SOG），可以极大提高显示面板的集成度，降低对于集成电路芯片的依赖性，从而降低成本。实现SOG需要提高现有显示面板中的薄膜晶体管的集成度、最大工作频率和电流密度，这些都要求薄膜晶体管具有更短的沟道长度、更高的迁移率和更小的体积。
然而，现有显示面板的薄膜晶体管的架构无法进一步减小薄膜晶体管的沟道长度、体积和占地面积。故，现有的显示面板的薄膜晶体管的架构亟需改进。
 发明概述
本发明实施例提供一种显示面板，以解决现有的显示面板的薄膜晶体管的占地面积较大的技术问题。
本发明实施例提供一种显示面板，包括：
一衬底；
多层欧姆接触层，层叠设置于所述衬底上；
多层绝缘层，相邻的两所述欧姆接触层之间设有至少一层所述绝缘层；
一半导体层，至少设置于所述多层欧姆接触层的同一侧的第一侧壁上，其中，所述半导体层包括多个间隔的有源部，所述有源部接触连接两所述欧姆接触层的所述第一侧壁；
栅极，设置于所述半导体层背离所述衬底的一侧；以及
源漏极层，设置于所述栅极背离所述衬底的一侧，所述源漏极层与对应的所述欧姆接触层电连接。
在本发明的一些实施例中，所述半导体层包括多个氧化绝缘部，每一所述氧化绝缘部位于相邻的两所述有源部之间。
在本发明的一些实施例中，所述有源部与所述氧化绝缘部呈连续性图案。
在本发明的一些实施例中，所述氧化绝缘部在所述欧姆接触层的所述第一侧壁上的正投影位于相邻的两所述欧姆接触层之间。
在本发明的一些实施例中，所述氧化绝缘部的材料包括硅氧化物，所述有源部的材料包括多晶硅。
在本发明的一些实施例中，所述半导体层包括镂空部，所述镂空部位于相邻的两所述有源部之间。
在本发明的一些实施例中，所述显示面板包括依次层叠于所述衬底上的第一欧姆接触层、第一绝缘层、第二欧姆接触层、第二绝缘层、第三欧姆接触层、第三绝缘层，以及第四欧姆接触层。
在本发明的一些实施例中，所述半导体层包括第一有源部和第二有源部，所述第一有源部与所述第一欧姆接触层和所述第二欧姆接触层接触连接，所述第二有源部与所述第三欧姆接触层和所述第四欧姆接触层接触连接。
在本发明的一些实施例中，所述源漏极层包括设于所述栅极背离所述衬底一侧的第一源极、第一漏极、第二源极和第二漏极，所述第一源极和第一漏极中的一个与所述第一欧姆接触层电连接，所述第一源极和第一漏极中的另一个与所述第二欧姆接触层电连接，所述第二源极和第二漏极中的一个与所述第三欧姆接触层电连接，所述第二源极和第二漏极中的另一个与所述第四欧姆接触层电连接。
在本发明的一些实施例中，所述第一源极和所述第一漏极在所述衬底上的正投影位于所述栅极在所述衬底上的正投影的一侧，所述第二源极和所述第二漏极位于所述栅极在所述衬底上的正投影的相对的另一侧。
在本发明的一些实施例中，所述第一欧姆接触层包括第一凸出部，所述第一凸出部在所述衬底上的正投影与所述第二欧姆接触层、第三欧姆接触层以及所述第四欧姆接触层在所述衬底上的正投影不重叠，所述第一凸出部与所述第一源极和所述第一漏极之一电连接；所述第二欧姆接触层包括第二凸出部，所述第二凸出部在所述衬底上的正投影与所述第三欧姆接触层以及所述第四欧姆接触层在所述衬底上的正投影不重叠，所述第二凸出部与所述第一源极和所述第一漏极之另一电连接；所述第三欧姆接触层包括第三凸出部，所述第三凸出部在所述衬底上的正投影与所述第四欧姆接触层在所述衬底上的正投影不重叠，所述第三凸出部与所述第二源极和所述第二漏极之一电连接。
在本发明的一些实施例中，所述第二绝缘层包括过孔，所述第三欧姆接触层通过所述过孔与所述第二欧姆接触层电连接。
在本发明的一些实施例中，所述源漏极层包括设于所述栅极背离所述衬底一侧的第一源极和第一漏极，所述第一源极和所述第一漏极中的一个与所述第一欧姆接触层电连接，所述第一源极和所述第一漏极中的另一个与所述第四欧姆接触层电连接。
在本发明的一些实施例中，所述第一源极在所述衬底上的正投影位于所述栅极在所述衬底上的正投影的一侧，所述第一漏极在所述衬底上的正投影位于所述栅极在所述衬底上的正投影的另一侧。
在本发明的一些实施例中，所述第一欧姆接触层包括第一凸出部，所述第一凸出部在所述衬底上的正投影与所述第二欧姆接触层、所述第三欧姆接触层以及所述第四欧姆接触层在所述衬底上的正投影不重叠，所述第一凸出部与所述第一源极和第一漏极中的一个电连接。
在本发明的一些实施例中，所述第一有源部和所述第二有源部之间的间距大于零且小于H 1，H 1为所述第二欧姆接触层的第一侧壁的宽度与所述第二绝缘层的第二侧壁的宽度及所述第三欧姆接触层的第一侧壁的宽度之和。
在本发明的一些实施例中，所述半导体层还包括水平部，所述水平部与一所述有源部接触连接，所述水平部设置于所述衬底表面。
在本发明的一些实施例中，所述水平部与所述有源部倾斜设置，所述水平部与所述有源部之间的夹角为90°~135°。
在本发明的一些实施例中，所述水平部的材料包括非晶硅材料。
在本发明的一些实施例中，所述衬底包括基板、设置于所述基板靠近所述欧姆接触层一侧的缓冲层，以及位于所述基板与所述缓冲层之间的遮光层，所述遮光层在所述基板上的正投影覆盖所述半导体层的各个有源部在所述基板上的正投影。
有益效果
本发明实施例提供的显示面板，包括衬底、多层欧姆接触层、多层绝缘层，一半导体层、栅极及源漏极层，其中，相邻的两欧姆接触层之间设有至少一层绝缘层，半导体层至少设置于多层欧姆接触层的同一侧的第一侧壁上，半导体层包括多个间隔的有源部，有源部接触连接两欧姆接触层的第一侧壁，栅极设置于半导体层背离衬底的一侧，源漏极层设置于栅极背离衬底的一侧，且与对应的所述欧姆接触层电连接。通过叠加多层欧姆接触层并将半导体层设置于欧姆接触层的侧壁上，如此不仅减小薄膜晶体管的长度，增大开态电流，还可实现多个薄膜晶体管在显示面板厚度方向上的叠加，降低薄膜晶体管的体积，减小薄膜晶体管的占地面积，有利于提高器件的集成度。
 附图说明
图1为本发明实施例提供的薄膜晶体管的平面结构示意图；
图2为图1中沿B-B方向的剖面示意图；
图3为图1中沿A-A方向的剖面示意图；
图4为发明另一实施例提供的薄膜晶体管的叠层示意图；
图5为本发明另一实施例提供的薄膜晶体管的平面结构示意图；
图6为图5中沿B-B方向的剖面示意图；
图7为图5中沿A-A方向的剖面示意图；
图8a~8i为本发明实施例提供的显示面板的制备过程的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。
请参阅图1至图3，图1为本发明实施例提供的显示面板的薄膜晶体管的平面示意图，图2为图1中沿B-B方向的剖面示意图，图3为图1中沿A-A方向的剖面示意图。本发明实施例提供的显示面板100，包括衬底10和薄膜晶体管20，薄膜晶体管20设置于衬底10上。所述薄膜晶体管20可应用于显示面板中的像素驱动电路、栅极驱动电路、源极驱动电路、时序控制器、复用电路等诸多电路中。
具体地，所述显示面板100包括一衬底10、多层欧姆接触层（如21、22、23、24）、多层绝缘层（如31、32、33）、一半导体层25、栅极26以及源漏极层27，所述多层欧姆接触层层叠设置于所述衬底10上，相邻的所述欧姆接触层之间设有至少一层所述绝缘层，所述半导体层25至少设置于所述多层欧姆接触层的第一侧壁201上，所述栅极26设置于所述半导体层25背离所述衬底10的一侧，所述源漏极层27设置于栅极26背离所述衬底10的一侧。其中，所述栅极26与所述半导体层25之间设有栅极绝缘层34，所述源漏极层27与所述栅极26之间设有层间介质层35，所述半导体层25包括多个间隔的有源部（如251、252），所述有源部接触连接两层所述欧姆接触层的第一侧壁201（如251接触连接21、22，252接触连接23、24）。所述薄膜晶体管20可以由但不限于由上述多层欧姆接触层、半导体层25、栅极26、源漏极层27构成。
现有技术中的薄膜晶体管的有源层制备在同一平面，多个薄膜晶体管平铺设置，导致形成的电路占地面积较大，且受曝光、刻蚀工艺限制，沟道长度一般在2微米以上，晶体管尺寸无法进一步缩小。本发明实施例通过将薄膜晶体管20的沟道（有源部的接触连接两欧姆接触层之间的部分）形成在欧姆接触层的第一侧壁201上，沟道长度由两侧的欧姆接触层的距离决定，因此在现有工艺基础上很容易将本发明实施例的沟道长度控制在1微米以下，形成短沟道薄膜晶体管器件，达到缩小薄膜晶体管尺寸的目的，从而增大开态电流。此外，本发明实施例通过在显示面板的厚度方向上叠加多层欧姆接触层，能够实现多个薄膜晶体管20在显示面板厚度方向上的堆叠，在很大程度上可减小薄膜晶体管20的占地面积，进而提高器件的集成度。
进一步地，为实现相邻的薄膜晶体管20的电隔离，需将半导体层25的相邻的有源部之间进行绝缘处理。在一些实施例中，所述薄膜晶体管20为多晶硅薄膜晶体管，即半导体层25的有源部为多晶硅材料，所述半导体层25还包括多个氧化绝缘部253，每一所述氧化绝缘部253位于相邻的两所述有源部（如251、252）之间，通过氧化绝缘部253间隔相邻的有源部以实现电隔离。
具体地，通过在第一侧壁201上形成非晶硅薄膜，将非晶硅薄膜的需绝缘处理的部分进行氧化处理，形成硅氧化物（如氧化硅膜层），从而形成氧化绝缘部253。
所述氧化绝缘部253和所述有源部一起呈连续性图案，仅需一道膜层沉积工艺便可实现，不会增加新的膜层工艺，制程简单，且也可增强半导体层25在斜面上的膜层附着力。上述提及的连续性图案指的是没有拼缝、没有开口等连续性形成的图案。
在其他实施例中，如图4所示，也可通过在对半导体层25进行刻蚀的同时，刻蚀工艺形成镂空部254，所述镂空部254位于相邻的两有源部之间，不会增加新的制程。可以理解的是，所述镂空部254在所述半导体层25的厚度方向上贯穿所述半导体层25，从而实现相邻有源部之间的绝缘。相比于图2所示的实施例，形成镂空部254的方案可能会存在刻蚀不完全的风险，膜层粘附力会降低，因此本发明的具体实施例中优选氧化绝缘部的方案，其半导体膜层稳定性更强。
所述半导体层25至少覆盖所述多层欧姆接触层的第一侧壁201以及所述多层绝缘层的与所述第一侧壁201同侧的第二侧壁301。在本发明的实施例中，所述半导体层25还包括水平部255，所述水平部255与一有源部接触连接，所述水平部255设置于所述衬底10表面。该有源部为多个有源部中最靠近衬底10的一个，即该有源部为第一有源部251。由于有源部相对于衬底10会倾斜一定的角度，因此水平部255与有源部之间会倾斜设置，所述水平部255的材料为非晶硅材料，一方面来讲，水平部255与第一有源部251之间的拐角处可以形成籽晶，所述籽晶可沿第一侧壁201和第二侧壁301所在的斜壁方向生成，通过控制绝缘层和欧姆接触层的厚度，使得薄膜晶体管20的沟道长度控制在0.01~1微米之间，如此可使得一个沟道内仅存在一个晶粒，即沟道由单颗晶粒构成，不存在晶界，相比于存在多晶界的现有薄膜晶体管，在减小薄膜晶体管尺寸的同时，大幅提升薄膜晶体管的迁移率。另一方面通过延长半导体层25以形成水平部255，可增大半导体层与膜层之间的附着力，提高薄膜晶体管器件的稳定性。
在一些实施例中，所述水平部255与所述有源部之间的夹角θ优选为90°~135°，该夹角θ也为第一侧壁201以及第二侧壁301与衬底10之间的夹角，本发明实施例的相邻的两欧姆接触层之间的厚度为0.0071~1微米，如此可控制沟道的长度在1微米以下。
此外，所述半导体层25还可覆盖所述多层欧姆接触层背离所述衬底10一侧的表面，即半导体层25还可继续向上延伸出平行于衬底10的另一水平部，如此，可在现有工艺的曝光机的精度上便能实现小尺寸的半导体层25的制备，无需更改工艺。
本发明实施例以叠加两个薄膜晶体管为例进行说明，但不以此为限，还可叠加三个、四个或更多个的薄膜晶体管。
具体地，如图1~3所示，所述显示面板包括依次层叠于所述衬底10上的第一欧姆接触层21、第一绝缘层31、第二欧姆接触层22、第二绝缘层32、第三欧姆接触层23、第三绝缘层33，以及第四欧姆接触层24。
所述半导体层25包括第一有源部251和第二有源部252，所述第一有源部251与所述第一欧姆接触层21和所述第二欧姆接触层22接触连接，所述第一有源部251的位于所述第一欧姆接触层21和所述第二欧姆接触层22之间的部分形成一薄膜晶体管的沟道，即沟道的长度可由第一欧姆接触层21和第二欧姆接触层22之间的第一绝缘层31的第二侧壁301的长度和倾斜角度决定，可将沟道的长度控制在1微米以下。
所述源漏极层27包括设于所述栅极26背离所述衬底10一侧的第一源极271和第一漏极272，所述第一源极271和第一漏极272中的一个与所述第一欧姆接触层21电连接，所述第一源极271和第一漏极272中的另一个与所述第二欧姆接触层22电连接。
所述第二有源部252与所述第三欧姆接触层23和所述第四欧姆接触层24接触连接，所述第二有源部252的位于所述第三欧姆接触层23和所述第四欧姆接触层24之间的部分形成另一薄膜晶体管的沟道。同样地，沟道的长度由第三欧姆接触层23和第四欧姆接触层24之间的第三绝缘层33的第二侧壁301的长度和倾斜角度决定，可将沟道的长度控制在1微米以下。
所述源漏极层27还包括设于所述栅极26背离所述衬底10一侧的第二源极273和第二漏极274，所述第二源极273和第二漏极274中的一个与所述第三欧姆接触层23电连接，所述第二源极273和第二漏极274中的另一个与所述第四欧姆接触层24电连接。
在本发明的实施例中，如图1所示，所述栅极26在所述衬底10上的正投影覆盖所述半导体层25在所述衬底10上的正投影，如此便于控制多个薄膜晶体管的沟道的形成位置及长短。
在上述实施例中，一薄膜晶体管由但不限于由第一有源部251、第一欧姆接触层21、第二欧姆接触层22、第一源极271、第一漏极272以及栅极26构成，另一薄膜晶体管由但不限于由第二有源部252、第三欧姆接触层23、第四欧姆接触层24、第二源极273、第二漏极274以及栅极26构成，如此不仅可在现有的工艺基础上制备短沟道薄膜晶体管器件，增大开态电流，也可实现多个薄膜晶体管在厚度方向上的叠加，减小晶体管占地面积，提高器件集成度，有利于实现基板上的IC电路集成。
如图1和图3所示，所述第一源极271和所述第一漏极272设置于所述栅极26的一侧，所述第二源极273和所述第二漏极274设置于所述栅极26相对的另一侧。换言之，所述第一源极271和所述第一漏极272在所述衬底10上的正投影位于所述栅极26在所述衬底10上的正投影的一侧，所述第二源极273和所述第二漏极274位于所述栅极26在所述衬底10上的正投影的相对的另一侧。如此可便于两个薄膜晶体管的源漏极与各自对应的欧姆接触层实现过孔连接。
具体地，如图3所示，所述第一欧姆接触层21包括第一凸出部211，所述第一凸出部211在所述衬底10上的正投影与所述第二欧姆接触层22、第三欧姆接触层23以及所述第四欧姆接触层24在所述衬底10上的正投影不重叠，所述第一凸出部211与所述第一源极271和所述第一漏极272之一电连接。通过将第一欧姆接触层21凸出于上层的欧姆接触层，可避免第一源极271/第一漏极272穿过上层欧姆接触层，避免与上层欧姆接触层接触。
同理，所述第二欧姆接触层22包括第二凸出部221，所述第二凸出部221在所述衬底10上的正投影与所述第三欧姆接触层23以及所述第四欧姆接触层24在所述衬底10上的正投影不重叠，所述第二凸出部221与所述第一源极271和所述第一漏极272之另一电连接。所述第二凸出部221与所述第一凸出部211位于所述栅极26的同一侧。
所述第三欧姆接触层23包括第三凸出部231，所述第三凸出部231在所述衬底10上的正投影与所述第四欧姆接触层24在所述衬底10上的正投影不重叠，所述第三凸出部231与所述第二源极273和所述第二漏极274之一电连接。所述第三凸出部231与所述第二凸出部221、所述第一凸出部211异侧设置，所述第三凸出部231位于所述栅极26的相对的另一侧。
在其他实施例中，所述第一源极271、所述第一漏极272、所述第二源极273以及所述第二漏极274也可位于所述栅极26的同一侧，但考虑到布线空间，优选于将所述第一源极271、所述第一漏极272与所述第二源极273、所述第二漏极274设置于所述栅极26的相对两侧。
上述实施例为两个薄膜晶体管的叠加，其他更多个薄膜晶体管的叠加的实施例与上述实施例相似，可参考上述描述。
进一步地，为实现薄膜晶体管的串联，可将两个薄膜晶体管的欧姆接触层通过过孔电连接。
具体地，请参考图5至图7，图5为本发明另一实施例的薄膜晶体管的俯视示意图，图6为图5沿B-B方向的剖面示意图，图7为图6沿A-A方向的剖面示意图。在图5~图7所示的实施例中，还是以两个薄膜晶体管为例进行说明，其他更多个薄膜晶体管的结构可参考本实施例的描述。为实现两个薄膜晶体管的串联，可将第三欧姆接触层23与第二欧姆接触层22电连接起来。所述第二绝缘层32包括过孔，所述第三欧姆接触层23穿过所述过孔与所述第二欧姆接触层22电连接。在此实施例中，串联的两个薄膜晶体管只需一个源极和漏极即可，即所述源漏极层27包括设于所述栅极26背离所述衬底10一侧的第一源极271和第一漏极272，其中，所述第一源极271和所述第一漏极272中的一个与所述第一欧姆接触层21电连接，所述第一源极271和所述第一漏极272中的另一个与所述第四欧姆接触层24电连接。
所述第一源极271和所述第一漏极272分别设于所述栅极26的两相对侧，以便于布线设计。即所述第一源极271在所述衬底10上的正投影位于所述栅极26在所述衬底10上的正投影的一侧，所述第一漏极272在所述衬底10上的正投影位于所述栅极26在所述衬底10上的正投影的另一侧。
进一步地，所述第一欧姆接触层21包括第一凸出部211，所述第一凸出部211在所述衬底10上的正投影与所述第二欧姆接触层22、所述第三欧姆接触层23以及所述第四欧姆接触层24在所述衬底10上的正投影不重叠，所述第一凸出部211与所述第一源极271和第一漏极272中的一个电连接。通过延长第一欧姆接触层21形成凸出于上层欧姆接触层（22、23、24）的第一凸出部211，可使得后续形成的第一源极271/第一漏极272避开上层欧姆接触层，直接穿过绝缘层的过孔与第一欧姆接触层21电连接。
在本发明的上述实施例中，相邻的两个有源部之间的间距大于零且小于H 1，H 1为两有源部分别连接的两个相邻的欧姆接触层的第一侧壁201的宽度，与该两相邻欧姆接触层之间的绝缘层的第二侧壁301的宽度之和。举例来说，如图4所示，所述第一有源部251和所述第二有源部252之间的间距大于零且小于H 1，H 1为所述第二欧姆接触层22的第一侧壁201的宽度与所述第二绝缘层32的第二侧壁301的宽度及所述第三欧姆接触层23的第一侧壁201的宽度之和。即H 1对应镂空部254的宽度或氧化绝缘部253的最大宽度，如此既可保证相邻有源部之间的电绝缘，还能保证有源部能够与其下方的欧姆接触层接触连接。
在一些实施例中，所述衬底10包括基板11和设于薄膜晶体管20和基板11之间的缓冲层12。如图2和图6所示，为了避免环境光照射对半导体层25的电性产生影响，可在所述缓冲层12和所述基板11之间设置遮光层13，所述遮光层13在所述基板11上的正投影覆盖所述半导体层25的各个有源部在所述基板11上的正投影。
上述实施例提及的显示面板的制备方法的步骤流程图如图8a~图8i所示，所述制备方法包括：S10，在衬底10上依次交替沉积多层欧姆接触层和多层绝缘层的材料，如图8a和8b所示；S20，对多层欧姆接触层和多层绝缘层的不同位置进行不同深度的刻蚀，以形成不同长度的欧姆接触层和不同长度的多层绝缘层，如图8c~8e所示；S30，在最外层欧姆接触层上沉积非晶硅材料，并对设定区域2501进行氧化处理以使得所述设定区域2501的非晶硅被氧化为氧硅化物，如图8f和图8g所示；S40，依序制备栅极26和源漏极层27，如图8h和图8i所示。
具体地，S10中，在基板11上形成遮光层13，所述遮光层13的材料包括但不限于金属材料。之后在所述遮光层13上沉积缓冲层12。
所述缓冲层12的材料包括但不限于氮化硅、氧化硅或者氮氧化硅中的任意一种或者多种的组合材料。
在S20中，如图8c~8e所示，以两个薄膜晶体管为例，依次在所述缓冲层12上依次层叠第一欧姆接触层21的材料、第一绝缘层31的材料、第二欧姆接触层22的材料、第二绝缘层32的材料、第三欧姆接触层23的材料、第三绝缘层33的材料以及第四欧姆接触层24的材料；之后进行不同深度的刻蚀，以形成第一凸出部211、第二凸出部221、第三凸出部231。该不同深度的刻蚀工艺可经过同一灰度掩模板进行，也可分多次光罩进行，这里不做限制。
上述提及的欧姆接触层均为N型重掺杂非晶硅材料，欧姆接触层中还可以掺杂有磷或砷等杂质元素。上述提及的绝缘层的材料可以为氮化硅、氧化硅或者氮氧化硅等常用的无机绝缘材料。
在S30中，请参阅图8f和8h，在所述第四欧姆接触层24上沉积非晶硅材料，并对非晶硅进行结晶处理，再对非晶硅材料进行刻蚀以形成半导体层25的图案；之后在半导体层25上形成硬掩模层（hard mask）200，并在设定区域2501形成断口，以露出设定区域2501内的非晶硅材料，所述硬掩模板层200可为SiN层；再将上述器件置于氧气环境中，使得暴露的非晶硅材料被氧化为氧硅化物，成为绝缘体，即形成氧化绝缘部253；最后，去除硬掩模层。
可以通过准分子激光退火工艺对非晶硅材料进行结晶处理，使非晶硅可以转变为多晶硅结构，再对多晶硅结构进行蚀刻，形成半导体层25的图案。由于准分子激光退火工艺的能量有限，且全部被非晶硅所吸收，在对非晶硅层进行结晶处理时，欧姆接触层仍然可以保持非晶硅结构。非晶硅的结晶处理也可在氧化处理之后进行，这里不做限制。
在S40中，先在半导体层25上形成栅极绝缘层34，再形成栅极26的图案；之后在所述栅极26上沉积层间介质层35的材料，再通过同一道刻蚀工艺对层间介质层35和栅极绝缘层34进行刻蚀，在不同位置形成不同深度的过孔；然后在所述层间介质层35上形成源漏极层27的图案，源漏极层27的各个源极、漏极通过不同位置不同深度的过孔与下层对应的欧姆接触层电连接。
综上，本发明实施例提供一种显示面板，包括衬底10、多层欧姆接触层、多层绝缘层，一半导体层25、栅极26及源漏极层27，其中，相邻的两欧姆接触层之间设有至少一层绝缘层，半导体层25至少设置于多层欧姆接触层的同一侧的第一侧壁上，半导体层25包括多个间隔的有源部，有源部接触连接两欧姆接触层的第一侧壁201，栅极26设置于半导体层25背离衬底10的一侧，源漏极层27设置于栅极26背离衬底10的一侧，且与对应的所述欧姆接触层电连接。通过叠加多层欧姆接触层并将半导体层25设置于欧姆接触层的侧壁上，如此不仅减小薄膜晶体管的长度，增大开态电流，还可实现多个薄膜晶体管在显示面板厚度方向上的叠加，降低薄膜晶体管的体积，减小薄膜晶体管的占地面积，有利于提高器件的集成度。
上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本发明实施例所提供的一种显示面板进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其中，包括：
    一衬底；
    多层欧姆接触层，层叠设置于所述衬底上；
    多层绝缘层，相邻的两所述欧姆接触层之间设有至少一层所述绝缘层；
    一半导体层，至少设置于所述多层欧姆接触层的同一侧的第一侧壁上，其中，所述半导体层包括多个间隔的有源部，所述有源部接触连接两所述欧姆接触层的所述第一侧壁；
    栅极，设置于所述半导体层背离所述衬底的一侧；以及
    源漏极层，设置于所述栅极背离所述衬底的一侧，所述源漏极层与对应的所述欧姆接触层电连接。
  2. 根据权利要求1所述的显示面板，其中，所述半导体层包括多个氧化绝缘部，每一所述氧化绝缘部位于相邻的两所述有源部之间。
  3. 根据权利要求2所述的显示面板，其中，所述有源部与所述氧化绝缘部呈连续性图案。
  4. 根据权利要求3所述的显示面板，其中，所述氧化绝缘部在所述欧姆接触层的所述第一侧壁上的正投影位于相邻的两所述欧姆接触层之间。
  5. 根据权利要求2所述的显示面板，其中，所述氧化绝缘部的材料包括硅氧化物，所述有源部的材料包括多晶硅。
  6. 根据权利要求1所述的显示面板，其中，所述半导体层包括镂空部，所述镂空部位于相邻的两所述有源部之间。
  7. 根据权利要求1所述的显示面板，其中，所述显示面板包括依次层叠于所述衬底上的第一欧姆接触层、第一绝缘层、第二欧姆接触层、第二绝缘层、第三欧姆接触层、第三绝缘层，以及第四欧姆接触层。
  8. 根据权利要求7所述的显示面板，其中，所述半导体层包括第一有源部和第二有源部，所述第一有源部与所述第一欧姆接触层和所述第二欧姆接触层接触连接，所述第二有源部与所述第三欧姆接触层和所述第四欧姆接触层接触连接。
  9. 根据权利要求8所述的显示面板，其中，所述源漏极层包括设于所述栅极背离所述衬底一侧的第一源极、第一漏极、第二源极和第二漏极，所述第一源极和第一漏极中的一个与所述第一欧姆接触层电连接，所述第一源极和第一漏极中的另一个与所述第二欧姆接触层电连接，所述第二源极和第二漏极中的一个与所述第三欧姆接触层电连接，所述第二源极和第二漏极中的另一个与所述第四欧姆接触层电连接。
  10. 根据权利要求9所述的显示面板，其中，所述第一源极和所述第一漏极在所述衬底上的正投影位于所述栅极在所述衬底上的正投影的一侧，所述第二源极和所述第二漏极位于所述栅极在所述衬底上的正投影的相对的另一侧。
  11. 根据权利要求9所述的显示面板，其中，
    所述第一欧姆接触层包括第一凸出部，所述第一凸出部在所述衬底上的正投影与所述第二欧姆接触层、第三欧姆接触层以及所述第四欧姆接触层在所述衬底上的正投影不重叠，所述第一凸出部与所述第一源极和所述第一漏极之一电连接；
    所述第二欧姆接触层包括第二凸出部，所述第二凸出部在所述衬底上的正投影与所述第三欧姆接触层以及所述第四欧姆接触层在所述衬底上的正投影不重叠，所述第二凸出部与所述第一源极和所述第一漏极之另一电连接；
    所述第三欧姆接触层包括第三凸出部，所述第三凸出部在所述衬底上的正投影与所述第四欧姆接触层在所述衬底上的正投影不重叠，所述第三凸出部与所述第二源极和所述第二漏极之一电连接。
  12. 根据权利要求8所述的显示面板，其中，所述第二绝缘层包括过孔，所述第三欧姆接触层通过所述过孔与所述第二欧姆接触层电连接。
  13. 根据权利要求12所述的显示面板，其中，所述源漏极层包括设于所述栅极背离所述衬底一侧的第一源极和第一漏极，所述第一源极和所述第一漏极中的一个与所述第一欧姆接触层电连接，所述第一源极和所述第一漏极中的另一个与所述第四欧姆接触层电连接。
  14. 根据权利要求13所述的显示面板，其中，所述第一源极在所述衬底上的正投影位于所述栅极在所述衬底上的正投影的一侧，所述第一漏极在所述衬底上的正投影位于所述栅极在所述衬底上的正投影的另一侧。
  15. 根据权利要求13所述的显示面板，其中，所述第一欧姆接触层包括第一凸出部，所述第一凸出部在所述衬底上的正投影与所述第二欧姆接触层、所述第三欧姆接触层以及所述第四欧姆接触层在所述衬底上的正投影不重叠，所述第一凸出部与所述第一源极和第一漏极中的一个电连接。
  16. 根据权利要求8所述的显示面板，其中，所述第一有源部和所述第二有源部之间的间距大于零且小于H 1 ，H 1 为所述第二欧姆接触层的第一侧壁的宽度与所述第二绝缘层的第二侧壁的宽度及所述第三欧姆接触层的第一侧壁的宽度之和。
  17. 根据权利要求1所述的显示面板，其中，所述半导体层还包括水平部，所述水平部与一所述有源部接触连接，所述水平部设置于所述衬底表面。
  18. 根据权利要求17所述的显示面板，其中，所述水平部与所述有源部倾斜设置，所述水平部与所述有源部之间的夹角为90°~135°。
  19. 根据权利要求17所述的显示面板，其中，所述水平部的材料包括非晶硅材料。
  20. 根据权利要求1所述的显示面板，其中，所述衬底包括基板、设置于所述基板靠近所述欧姆接触层一侧的缓冲层，以及位于所述基板与所述缓冲层之间的遮光层，所述遮光层在所述基板上的正投影覆盖所述半导体层的各个有源部在所述基板上的正投影。
PCT/CN2023/104277 2022-10-12 2023-06-29 显示面板 Ceased WO2024078043A1 (zh)

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