WO2024078005A1 - 基于ssd主控变频的时间管理方法、装置、设备及介质 - Google Patents

基于ssd主控变频的时间管理方法、装置、设备及介质 Download PDF

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Publication number
WO2024078005A1
WO2024078005A1 PCT/CN2023/101670 CN2023101670W WO2024078005A1 WO 2024078005 A1 WO2024078005 A1 WO 2024078005A1 CN 2023101670 W CN2023101670 W CN 2023101670W WO 2024078005 A1 WO2024078005 A1 WO 2024078005A1
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Prior art keywords
firmware
frequency conversion
value
facing
frequency
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PCT/CN2023/101670
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English (en)
French (fr)
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李瀚卿
钟戟
尹作刚
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苏州元脑智能科技有限公司
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Publication of WO2024078005A1 publication Critical patent/WO2024078005A1/zh

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629Configuration or reconfiguration of storage systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of storage, and in particular to a time management method, device, equipment and medium based on SSD master control frequency conversion.
  • SSD Solid State Drives
  • firmware software programs running inside the SSD
  • the execution of many firmware functions needs to follow a strict time sequence. Ensuring that the controller timing is correct and that there is no timing confusion is an issue that must be considered when designing the firmware.
  • time counting methods there is a set of time counting methods inside the controller. This method depends on the controller's own frequency, namely the clock tick (Ticks). The clock tick gradually increases with time. Developers can calculate the passage of time based on the time tick value and the known controller frequency.
  • Some controllers also provide timer functions to meet the needs of periodically executing a task, but the timer cannot be used arbitrarily and there are resource limitations.
  • the first method is simple and easy to use, but inconvenient to use in many cases.
  • the frequency of the controller is variable, it is impossible to calculate the time by counting the clock beats and the controller frequency, because the main control frequency is unknown; on the other hand, logs should be stored during the operation of the SSD to monitor the operation of the device and locate bugs when problems occur in the storage device. If the time when each log occurs is calculated by clock beats, it will be extremely unfriendly and inefficient.
  • the above second method is easy to use, but it is more suitable for periodic tasks, cannot directly record time, and has resource limitations.
  • the present application proposes a time management method, device, equipment and readable medium based on SSD master frequency conversion.
  • the time management method based on SSD master frequency conversion proposed in the present application is applied to the time management method of multi-core frequency conversion of SSD, which mainly includes: time calculation in the case of single-core frequency conversion, that is, the time management method of a CPU with variable main frequency; the time synchronization problem between the cores of the controller in the case of multi-core, so that multiple cores are synchronized with the external time; at the same time, through the function of timestamp, the current time value of the SSD facing the firmware after the frequency conversion is converted into the current time facing the user after the frequency conversion, that is, the internal time of the SSD is converted into the year, month, day, hour, minute and second, so that the functions related to time series such as logs are simpler and easier to use, and more user-friendly.
  • one aspect of an embodiment of the present application provides a time management method based on SSD master frequency conversion, the method comprising the following steps: obtaining a new frequency value of the SSD master frequency conversion and a starting clock beat value facing the firmware during the frequency conversion, and calculating the starting time value facing the firmware during the frequency conversion; calculating the current time difference facing the firmware after the frequency conversion according to the current clock beat value facing the firmware after the frequency conversion, the starting clock beat value facing the firmware during the frequency conversion, and the new frequency value; obtaining the current time value facing the firmware after the frequency conversion based on the sum of the starting time value facing the firmware during the frequency conversion and the current time difference facing the firmware after the frequency conversion.
  • the method also includes: setting and recording the start time value and the start clock beat value facing the firmware when the frequency is not changed, and obtaining the frequency value when the frequency is not changed; calculating the time difference facing the firmware when the frequency is changed according to the start clock beat value facing the firmware when the frequency is changed, the start clock beat value facing the firmware when the frequency is not changed, and the frequency value when the frequency is not changed; obtaining the start time value facing the firmware when the frequency is changed based on the sum of the start time value facing the firmware when the frequency is not changed and the time difference facing the firmware when the frequency is changed.
  • the setting records the starting time value and the starting clock beat value facing the firmware when the frequency is not changed, and obtains the frequency value when the frequency is not changed, including: initializing the starting time value facing the firmware when the frequency is not changed to 0 and recording the corresponding clock beat value as the starting clock beat value facing the firmware when the frequency is not changed.
  • the time difference for the firmware during frequency conversion is calculated according to the starting clock beat value for the firmware during frequency conversion, the starting clock beat value for the firmware during non-frequency conversion, and the frequency value during non-frequency conversion, including: The difference between the beat value and the firmware-oriented starting clock beat when the frequency is not changed is obtained by obtaining the current clock difference when the frequency is changed; the ratio of the current clock difference when the frequency is changed to the frequency value when the frequency is not changed is calculated to obtain the firmware-oriented time difference when the frequency is changed.
  • the current time difference facing the firmware after the frequency conversion is calculated based on the current clock beat value facing the firmware after the frequency conversion, the starting clock beat value facing the firmware during the frequency conversion, and the new frequency value, including: obtaining the current clock difference after the frequency conversion based on the difference between the current clock beat value facing the firmware after the frequency conversion and the starting clock beat value facing the firmware during the frequency conversion; calculating the ratio of the current clock difference after the frequency conversion to the new frequency value to obtain the current time difference facing the firmware after the frequency conversion.
  • the method also includes: in response to a new frequency change, updating the firmware-oriented starting clock beat value and the firmware-oriented starting time value with the clock beat value and the firmware-oriented time value at the new frequency change, and calculating the firmware-oriented current time value of the new frequency change based on the frequency value of the new frequency change.
  • the method also includes: in response to the SSD running as a multi-core, selecting one of the multi-cores as a baseline core for time synchronization of the multi-cores; respectively calculating the deviation values of the remaining cores and the baseline core, and calculating the current time value of the remaining cores facing the firmware after the frequency conversion based on the deviation values, so that the current time value of the remaining cores facing the firmware after the frequency conversion is consistent with the current time value of the baseline core facing the firmware after the frequency conversion.
  • selecting one of the multiple cores as a reference core for time synchronization of the multiple cores includes: selecting the core with the best performance among the multiple cores as the reference core for time synchronization of the multiple cores.
  • respectively calculating the deviation values of the remaining cores and the benchmark core, and calculating the current time value of the remaining core facing the firmware after the frequency conversion based on the deviation value, so that the current time value of the remaining core facing the firmware after the frequency conversion is consistent with the current time value of the benchmark core facing the firmware after the frequency conversion includes: obtaining the deviation value of the remaining core and the benchmark core based on the difference between the starting clock beat value of the firmware facing the remaining core when the frequency is not converted and the starting clock beat value of the firmware facing the benchmark core when the frequency is not converted; according to the current clock beat value of the firmware facing the remaining core after the frequency conversion, the starting clock beat value of the firmware facing the remaining core when the frequency is converted, the deviation value and The frequency value of the remaining cores after frequency conversion is calculated to obtain the current time difference of the remaining cores facing the firmware after frequency conversion; the current time value of the remaining cores facing the firmware after frequency conversion is obtained based on the sum of the starting time value of the benchmark core facing the firmware during frequency conversion and
  • the deviation value between the remaining cores and the benchmark core is obtained based on the difference between the firmware-oriented starting clock beat value of the remaining cores when the frequency is not changed and the firmware-oriented starting clock beat value of the benchmark core when the frequency is not changed, including: initializing the firmware-oriented starting time value of the benchmark core when the frequency is not changed to 0 and recording the corresponding clock beat value as the firmware-oriented starting clock beat value of the benchmark core when the frequency is not changed.
  • the current time difference of the remaining cores facing the firmware after the frequency conversion is calculated based on the current clock beat value of the remaining cores facing the firmware after the frequency conversion, the starting clock beat value of the remaining cores facing the firmware when the frequency conversion occurs, the deviation value and the frequency value of the remaining cores after the frequency conversion, including: adding the deviation value based on the difference between the current clock beat value of the remaining cores facing the firmware after the frequency conversion and the starting clock beat value of the remaining cores facing the firmware when the frequency conversion occurs, to obtain the current clock difference value of the remaining cores after the frequency conversion; calculating the ratio of the current clock difference value of the remaining cores after the frequency conversion to the frequency value of the remaining cores after the frequency conversion, to obtain the current time difference of the remaining cores facing the firmware after the frequency conversion.
  • the method also includes: obtaining a current time value facing the firmware after frequency conversion corresponding to the timestamp based on the timestamp received by the SSD, and obtaining a current time value facing the user after frequency conversion based on the timestamp and the current time value facing the firmware after frequency conversion corresponding to the timestamp.
  • obtaining the current time value facing the user after the frequency conversion based on the timestamp and the current time value facing the firmware after the frequency conversion corresponding to the timestamp includes:
  • a current time value facing the user after frequency conversion is obtained based on the time difference and the timestamp.
  • the frequency conversion is obtained based on the time difference and the timestamp.
  • the current time value to the user includes:
  • the current time value facing the user after frequency conversion is obtained based on the sum of the time difference and the timestamp.
  • the SSD receives the timestamp.
  • executing the SSD receiving the timestamp includes:
  • a command for synchronizing timestamps sent by a host to the SSD is received to receive the timestamps and record the timestamps.
  • the timestamp is a millisecond timestamp.
  • Another aspect of the embodiments of the present application further provides a time management device based on SSD master control frequency conversion, including the following modules: a first module, configured to obtain a new frequency value of the SSD master control frequency conversion and a starting clock beat value facing the firmware during the frequency conversion, and calculate the starting time value facing the firmware during the frequency conversion; a second module, configured to calculate the current time difference facing the firmware after the frequency conversion based on the current clock beat value facing the firmware after the frequency conversion, the starting clock beat value facing the firmware during the frequency conversion, and the new frequency value; a third module, configured to obtain the current time value facing the firmware after the frequency conversion based on the sum of the starting time value facing the firmware during the frequency conversion and the current time difference facing the firmware after the frequency conversion.
  • a first module configured to obtain a new frequency value of the SSD master control frequency conversion and a starting clock beat value facing the firmware during the frequency conversion, and calculate the starting time value facing the firmware during the frequency conversion
  • a second module configured to calculate the current time difference facing the firmware after the frequency conversion based
  • the device also includes: a fourth module, configured to update the firmware-oriented starting clock beat value and the firmware-oriented starting time value with the clock beat value and the firmware-oriented time value at the time of the new frequency change in response to a new frequency change, and calculate the firmware-oriented current time value of the new frequency change based on the frequency value of the new frequency change.
  • a fourth module configured to update the firmware-oriented starting clock beat value and the firmware-oriented starting time value with the clock beat value and the firmware-oriented time value at the time of the new frequency change in response to a new frequency change, and calculate the firmware-oriented current time value of the new frequency change based on the frequency value of the new frequency change.
  • the device also includes: a fifth module, configured to select one of the multi-cores as a baseline core for time synchronization of the multi-cores in response to the SSD running as a multi-core; a sixth module, configured to respectively calculate the deviation values of the remaining cores and the baseline core, and calculate the current time value of the remaining cores facing the firmware after the frequency conversion based on the deviation value, so that the current time value of the remaining cores facing the firmware after the frequency conversion is consistent with the current time value of the baseline core facing the firmware after the frequency conversion.
  • the device further includes: a seventh module configured to The timestamp received by the SSD obtains the current time value facing the firmware after the frequency conversion corresponding to the timestamp, and obtains the current time value facing the user after the frequency conversion based on the timestamp and the current time value facing the firmware after the frequency conversion corresponding to the timestamp.
  • a computer device comprising at least one processor; and a memory, wherein the memory stores computer instructions executable on the processor, and the instructions implement the steps of any of the above methods when executed by the processor.
  • a non-volatile computer-readable storage medium which stores a computer program that implements any of the above method steps when executed by a processor.
  • the present application has at least the following beneficial effects:
  • the present application proposes a time management method, device, equipment and medium based on SSD master frequency conversion, wherein the time management method based on SSD master frequency conversion proposed in the present application is applied to the time management method when the SSD main frequency is variable, and the time system is encapsulated layer by layer by using the single-core frequency conversion, multi-core synchronization and timestamp synchronization methods, and finally a time management method that is simple and easy for users to use is obtained.
  • the method can eliminate the problem of inaccurate time counting caused by frequency conversion, and facilitate direct firmware calls; the multi-core time synchronization method in this method facilitates the unified scheduling of firmware; the timestamp function is added in this method to keep the time inside the SSD device consistent with the time displayed to the user, which is convenient for R&D and problem location, and is more user-friendly.
  • FIG1 is a schematic diagram showing an embodiment of a time management method based on SSD master control frequency conversion provided by the present application
  • FIG. 2 shows an embodiment of a time management method based on SSD master control frequency conversion provided by the present application
  • FIG. 3 shows an implementation of a time management device based on SSD master frequency conversion provided by the present application. Schematic diagram of the embodiment
  • FIG4 is a schematic diagram showing another embodiment of a time management device based on SSD master control frequency conversion provided by the present application.
  • FIG5 is a schematic diagram showing another embodiment of a time management device based on SSD master control frequency conversion provided by the present application.
  • FIG6 is a schematic diagram showing another embodiment of a time management device based on SSD master control frequency conversion provided by the present application.
  • FIG7 is a schematic diagram showing an embodiment of a computer device provided by the present application.
  • FIG8 is a schematic diagram showing an embodiment of a non-volatile computer-readable storage medium provided by the present application.
  • the time management methods for SSD devices include: there is a set of time counting methods inside the controller, which depends on the frequency of the controller itself, namely the clock tick (Ticks).
  • the clock tick increases gradually over time, and the developer can calculate the passage of time based on the time tick value and the known controller frequency; some controllers also provide timer functions to meet the needs of periodically executing a task, but the timer cannot be used arbitrarily and there are resource limitations.
  • Both of the above methods have some problems.
  • the first method is simple and easy to use, it is not convenient to use in many cases. If the frequency of the controller is variable, then it is impossible to use the clock tick count and the controller.
  • the frequency is used to calculate the time, because the master frequency is unknown; in addition, logs should be stored during the operation of the SSD to monitor the operation of the device and locate bugs when problems occur in the storage device. If the time of each log is calculated by clock beats, it will be extremely unfriendly and inefficient. Although the second method mentioned above is easy to use, it is more suitable for periodic tasks, cannot directly record time, and has resource limitations.
  • FIG1 shows a schematic diagram of an embodiment of a time management method based on SSD master control frequency conversion provided by the present application.
  • a time management method based on SSD master control frequency conversion in an embodiment of the present application includes the following steps:
  • FIG2 shows a schematic diagram of another embodiment of a time management method based on SSD master frequency conversion provided by the present application. As shown in FIG2, it includes:
  • the time difference can be directly calculated by dividing the difference between the two ticks by the controller frequency, and the latter is recorded as Ticks is Ticks 2 , and the previous Ticks is Ticks 1 , then the time difference of the fixed frequency controller is:
  • a Real_time that records the time after frequency conversion is defined and calculated on top of Ticks.
  • users can directly use Real_time and skip the calculation using Ticks to avoid the impact of frequency conversion.
  • the calculation method of Real_time includes:
  • Ps represents Real_time in picoseconds, that is, 1000,000,000,000 per second
  • Ti current is the starting clock beat for the firmware when the frequency is not converted.
  • Step 2 When the controller changes frequency, update Ti0 and Rt0, the controller frequency becomes P2, the new Ti0 is the ticks at the frequency change moment, and the new Rt0 can be calculated using Formula 2.
  • the frequency change is P2 (i.e. the new frequency value)
  • the current time value Real_time facing the firmware after the frequency change can be obtained:
  • each core has its own clock beat, each core has its own separate time system. Based on the above time management method in the case of single-core frequency conversion, it is necessary to unify the time of each core to facilitate unified management of upper-level applications. When the controller is powered on, the internal cores start working. Due to differences in functional allocation, each core runs completely different code. In order to maintain time synchronization among the cores, it is necessary to first select one of the cores as the reference core for time synchronization. Generally, the core with the best performance is selected as the reference core; secondly, each core is initialized at some point during power-on.
  • the firmware can run accurately according to the correct timing.
  • the time at this time is the time for the firmware, not the time directly facing the user. Users are more familiar with the AD time such as 2022.06.01.15:30:00, and do not pay attention to the internal time of the firmware. For example, when obtaining a firmware log, the user only knows how many seconds after power-on the execution time of a certain command is, but the user wants to know more about the day and time when the command was executed. Therefore, with the help of timestamps, the time in the firmware can be converted to AD time. Based on this, a timestamp method is provided to convert the firmware-oriented time into user-oriented time:
  • the host sends a command to synchronize the timestamp TimeStamp (i.e. the timestamp received by the SSD) to the SSD device, that is, the host sends the current AD time in the form of a millisecond timestamp to the SSD device.
  • Real_time start is the starting time value for the firmware during frequency conversion.
  • the problem of inaccurate time counting caused by frequency conversion can be eliminated, which facilitates direct firmware calls;
  • the multi-core time synchronization method in this method facilitates unified scheduling of firmware;
  • the timestamp function is added in this method to keep the time inside the SSD device consistent with the time displayed to the user, which facilitates R&D and problem location, and is more user-friendly.
  • FIG3 shows a schematic diagram of an embodiment of a time management device based on SSD master frequency conversion provided by the present application.
  • a time management device based on SSD master frequency conversion provided by the present application includes: a first module 011, configured to obtain a new frequency value of the SSD master frequency conversion and a starting clock beat value for the firmware during the frequency conversion, and calculate the starting time value for the firmware during the frequency conversion; a second module 012, configured to calculate the current time difference for the firmware after the frequency conversion based on the current clock beat value for the firmware after the frequency conversion, the starting clock beat value for the firmware during the frequency conversion, and the new frequency value; a third module 013, configured to obtain the current time value for the firmware after the frequency conversion based on the sum of the starting time value for the firmware during the frequency conversion and the current time difference for the firmware after the frequency conversion.
  • FIG4 shows a schematic diagram of another embodiment of a time management device based on SSD master frequency conversion provided by the present application.
  • a time management device based on SSD master frequency conversion provided by the present application also includes: a fourth module 014, configured to respond to a new frequency conversion, update the firmware-oriented starting clock beat value and the firmware-oriented starting time value with the clock beat value and the firmware-oriented time value at the time of the new frequency conversion, and calculate the firmware-oriented current time value of the new frequency conversion based on the frequency value of the new frequency conversion.
  • FIG5 shows a schematic diagram of another embodiment of a time management device based on SSD master frequency conversion provided by the present application.
  • a time management device based on SSD master frequency conversion provided by the present application also includes: a fifth module 015, configured to select one of the multiple cores as a reference core for time synchronization of the multiple cores in response to the SSD running as a multi-core; a sixth module 016, configured to respectively calculate the deviation values of the remaining cores and the reference core, and calculate the current time value of the remaining cores facing the firmware after the frequency conversion based on the deviation value, so that the current time value of the remaining cores facing the firmware after the frequency conversion is consistent with the current time value of the reference core facing the firmware after the frequency conversion.
  • FIG6 is a schematic diagram of another embodiment of a time management device based on SSD master frequency conversion provided by the present application.
  • a time management device based on SSD master frequency conversion provided by the present application The time management device also includes: a seventh module, configured to obtain the current time value facing the firmware after frequency conversion corresponding to the timestamp received by the SSD, and to obtain the current time value facing the user after frequency conversion based on the timestamp and the current time value facing the firmware after frequency conversion corresponding to the timestamp.
  • FIG7 shows a schematic diagram of an embodiment of a computer device provided by the present application.
  • an embodiment of a computer device provided by the present application includes the following modules: at least one processor 021; and a memory 022, the memory 022 stores computer instructions 023 that can be run on the processor 021, and the computer instructions 023 implement the steps of the above method when executed by the processor 021.
  • FIG8 is a schematic diagram of an embodiment of a non-volatile computer-readable storage medium provided by the present application. As shown in FIG8, the non-volatile computer-readable storage medium 031 stores a computer program 032 that performs the above method when executed by a processor.
  • the method disclosed in the embodiment of the present application can also be implemented as a computer program executed by a processor, and the computer program can be stored in a computer-readable storage medium.
  • the computer program is executed by the processor, the above functions defined in the method disclosed in the embodiment of the present application are performed.
  • the above method steps and system units may also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above steps or unit functions.
  • the function can be implemented in hardware, software, firmware or any combination thereof. If implemented in software, the function can be stored on a computer-readable medium or transmitted by a computer-readable medium as one or more instructions or codes.
  • Computer-readable media include computer storage media and communication media, and the communication media include any media that helps to transmit a computer program from one location to another.
  • the storage medium can be any available medium that can be accessed by a general or special computer.
  • the computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store the required program code in the form of an instruction or data structure and can be accessed by a general or special computer or a general or special processor.
  • any connection can be appropriately referred to as a computer-readable medium.
  • disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, Blu-ray disc, wherein disks usually reproduce data magnetically, while optical discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

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Abstract

一种基于SSD主控变频的时间管理方法、装置、设备及介质,包括:获取SSD主控变频的新频率值和变频时面向固件的起始时钟节拍值,并且计算得到变频时面向固件的起始时间值(S1);根据变频后面向固件的当前时钟节拍值、变频时面向固件的起始时钟节拍值以及新频率值计算得到变频后面向固件的当前时间差(S2);基于变频时面向固件的起始时间值与变频后面向固件的当前时间差之和得到变频后面向固件的当前时间值(S3)。可以消除变频导致时间计数不准的问题,方便固件的统一调度,增加时间戳功能使SSD设备内部的时间与面向用户的显示的时间保持一致,同时对用户使用更加友好。

Description

基于SSD主控变频的时间管理方法、装置、设备及介质
相关申请的交叉引用
本申请要求于2022年10月10日提交中国专利局,申请号为202211231964.8,申请名称为“基于SSD主控变频的时间管理方法、装置、设备及介质”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储领域,尤其涉及一种基于SSD主控变频的时间管理方法、装置、设备及介质。
背景技术
SSD(Solid State Drives固态存储器)作为一种较为复杂的嵌入式电子设备,其固件(SSD内部运行的软件程序)功能的正常运行十分关键。固件的许多功能执行需要遵循严格的时间顺序,保证控制器的时序正确、不发生时序混乱是固件设计时必须考虑的问题。现有技术中,在控制器内部均存在一套时间计数方法,该方法依赖控制器自身的频率,即时钟节拍(Ticks),时钟节拍随着时间逐步递增,开发者可根据时间节拍数值以及已知的控制器频率来计算时间流逝;还有一些控制器会提供定时器功能,以满足周期性执行某个任务的需求,但定时器不能任意使用,存在资源限制。
现有技术中的以上两种方法,第一种方法简单易用,但在许多情况下使用不方便。比如在控制器的频率是可变的情况下,无法通过时钟节拍计数和控制器频率来计算时间,因为主控频率是未知的;另一方面,SSD运行过程中应该存有日志,以便监控设备运行、存储设备出现问题时定位bug,每一条日志发生的时间如果通过时钟节拍来计算,会极不友好且效率低下。上述第二种方法使用方便,但是更适合周期性任务使用,不能直接记录时间,且存在资源限制。
发明内容
有鉴于此,本申请提出了一种基于SSD主控变频的时间管理方法、装置、设备及可读介质。其中,本申请提出的一种基于SSD主控变频的时间管理方法应用于SSD的多核变频的时间管理的方法,主要包括:在单核变频的情况下的时间计算,即一个主频可变的CPU的时间管理的方式;在多核情况下控制器的各个核之间的时间同步的问题,使多个核与外部时间保持同步;同时,还通过时间戳的功能,将SSD的变频后面向固件的当前时间值转化为变频后面向用户的当前时间,即将SSD的内部时间转化为年、月、日、时、分、秒的方式,使日志等与时序相关的功能更简单易用,对用户也更加友好。
基于以上目的,本申请的实施例的一个方面提供了一种基于SSD主控变频的时间管理方法,所述方法包括以下步骤:获取SSD主控变频的新频率值和变频时面向固件的起始时钟节拍值,并且计算得到变频时面向固件的起始时间值;根据变频后面向固件的当前时钟节拍值、所述变频时面向固件的起始时钟节拍值以及所述新频率值计算得到变频后面向固件的当前时间差;基于所述变频时面向固件的起始时间值与所述变频后面向固件的当前时间差之和得到变频后面向固件的当前时间值。
在本申请一些实施例中,所述方法还包括:设置记录未变频时面向固件的起始时间值、起始时钟节拍值,并且获取未变频时的频率值;根据所述变频时面向固件的起始时钟节拍值、所述未变频时面向固件的起始时钟节拍值以及所述未变频时的频率值计算得到变频时面向固件的时间差;基于所述未变频时面向固件的起始时间值与所述变频时面向固件的时间差之和得到所述变频时面向固件的起始时间值。
在本申请一些实施例中,所述设置记录未变频时面向固件的起始时间值、起始时钟节拍值,并且获取未变频时的频率值包括:初始化未变频时的面向固件的起始时间值为0并记录与其对应的时钟节拍值作为未变频时面向固件的起始时钟节拍值。
在本申请一些实施例中,所述根据所述变频时面向固件的起始时钟节拍值、所述未变频时面向固件的起始时钟节拍值以及所述未变频时的频率值计算得到变频时面向固件的时间差包括:根据所述变频时面向固件的起始时钟 节拍值与所述未变频时面向固件的起始时钟节拍的差值得到变频时的当前时钟差值;计算所述变频时的当前时钟差值与所述未变频时的频率值的比值得到变频时面向固件的时间差。
在本申请一些实施例中,所述根据变频后面向固件的当前时钟节拍值、所述变频时面向固件的起始时钟节拍值以及所述新频率值计算得到变频后面向固件的当前时间差包括:根据变频后面向固件的当前时钟节拍值与所述变频时面向固件的起始时钟节拍值差值得到变频后的当前时钟差值;计算所述变频后的当前时钟差值与所述新频率值的比值得到变频后面向固件的当前时间差。
在本申请一些实施例中,所述方法还包括:响应于发生新的变频时,以新的变频时的时钟节拍值和面向固件的时间值更新所述面向固件的起始时钟节拍值和所述面向固件的起始时间值,并且基于所述新的变频的频率值计算得到所述新的变频的面向固件的当前时间值。
在本申请一些实施例中,所述方法还包括:响应于所述SSD为多核运行,选择所述多核中的一个核作为所述多核的时间同步的基准核;分别计算剩余核与所述基准核的偏差值,并基于所述偏差值计算所述剩余核的变频后面向固件的当前时间值,以使所述剩余核的变频后面向固件的当前时间值与所述基准核的变频后面向固件的当前时间值保持一致。
在本申请一些实施例中,所述响应于所述SSD为多核运行,选择所述多核中的一个核作为所述多核的时间同步的基准核包括:选择多核中性能最优的核作为所述多核的时间同步的基准核。
在本申请一些实施例中,所述分别计算剩余核与所述基准核的偏差值,并基于所述偏差值计算所述剩余核的变频后面向固件的当前时间值,以使所述剩余核的变频后面向固件的当前时间值与所述基准核的变频后面向固件的当前时间值保持一致包括:基于所述剩余核的未变频时面向固件的起始时钟节拍值和所述基准核的未变频时面向固件的起始时钟节拍值之差得到所述剩余核与所述基准核的偏差值;根据所述剩余核的变频后面向固件的当前时钟节拍值、所述剩余核的变频时面向固件的起始时钟节拍值、所述偏差值以及 所述剩余核的变频后的频率值计算得到所述剩余核的变频后面向固件的当前时间差;基于所述基准核的变频时面向固件的起始时间值和所述剩余核的变频后面向固件的当前时间差之和得到所述剩余核的变频后面向固件的当前时间值,以保持与所述基准核的变频后面向固件的当前时间值一致。
在本申请一些实施例中,所述基于所述剩余核的未变频时面向固件的起始时钟节拍值和所述基准核的未变频时面向固件的起始时钟节拍值之差得到所述剩余核与所述基准核的偏差值包括:初始化所述基准核的未变频时的面向固件的起始时间值为0并记录与其对应的时钟节拍值作为所述基准核未变频时面向固件的起始时钟节拍值。
在本申请一些实施例中,所述根据所述剩余核的变频后面向固件的当前时钟节拍值、所述剩余核的变频时面向固件的起始时钟节拍值、所述偏差值以及所述剩余核的变频后的频率值计算得到所述剩余核的变频后面向固件的当前时间差包括:基于所述剩余核的变频后面向固件的当前时钟节拍值与所述剩余核的变频时面向固件的起始时钟节拍值之差添加所述偏差值,得到所述剩余核的变频后的当前时钟差值;计算所述剩余核的变频后的当前时钟差值与所述剩余核的变频后的频率值的比值,得到所述剩余核的变频后面向固件的当前时间差。
在本申请一些实施例中,所述方法还包括:基于所述SSD接收到的时间戳得到所述时间戳对应的变频后面向固件的当前时间值,并基于所述时间戳和所述时间戳对应的变频后面向固件的当前时间值得到变频后面向用户的当前时间值。
在本申请一些实施例中,所述基于所述时间戳和所述时间戳对应的变频后面向固件的当前时间值得到变频后面向用户的当前时间值,包括:
确定所述变频时面向固件的起始时间值与所述变频后面向用户的当前时间值的时间差值;
基于所述时间差值与所述时间戳得到变频后面向用户的当前时间值。
在本申请一些实施例中,所述基于所述时间差值与所述时间戳得到变频 后面向用户的当前时间值,包括:
基于所述时间差值与所述时间戳之和得到变频后面向用户的当前时间值。
在本申请一些实施例中,还包括:
当所述SSD驱动加载完毕后,执行所述SSD接收时间戳。
在本申请一些实施例中,执行所述SSD接收时间戳,包括:
接收主机发送给所述SSD的同步时间戳的命令,以接收所述时间戳,并记录所述时间戳。
在本申请一些实施例中,所述时间戳为毫秒时间戳。
本申请实施例的另一个方面,还提供了一种基于SSD主控变频的时间管理装置,包括以下模块:第一模块,配置用于获取SSD主控变频的新频率值和变频时面向固件的起始时钟节拍值,并且计算得到变频时面向固件的起始时间值;第二模块,配置用于根据变频后面向固件的当前时钟节拍值、所述变频时面向固件的起始时钟节拍值以及所述新频率值计算得到变频后面向固件的当前时间差;第三模块,配置用于基于所述变频时面向固件的起始时间值与所述变频后面向固件的当前时间差之和得到变频后面向固件的当前时间值。
在本申请一些实施例中,所述装置还包括:第四模块,配置用于响应于发生新的变频时,以新的变频时的时钟节拍值和面向固件的时间值更新所述面向固件的起始时钟节拍值和所述面向固件的起始时间值,并且基于所述新的变频的频率值计算得到所述新的变频的面向固件的当前时间值。
在本申请一些实施例中,所述装置还包括:第五模块,配置用于响应于所述SSD为多核运行,选择所述多核中的一个核作为所述多核的时间同步的基准核;第六模块,配置用于分别计算剩余核与所述基准核的偏差值,并基于所述偏差值计算所述剩余核的变频后面向固件的当前时间值,以使所述剩余核的变频后面向固件的当前时间值与所述基准核的变频后面向固件的当前时间值保持一致。
在本申请一些实施例中,所述装置还包括:第七模块,配置用于基于所 述SSD接收到的时间戳得到所述时间戳对应的变频后面向固件的当前时间值,并基于所述时间戳和所述时间戳对应的变频后面向固件的当前时间值得到变频后面向用户的当前时间值。
本申请实施例的另一方面,还提供一种计算机设备,包括至少一个处理器;以及存储器,存储器存储有可在处理器上运行的计算机指令,指令由处理器执行时实现上述任一方法的步骤。
本申请实施例的又一方面,还提供了一种非易失性计算机可读存储介质,非易失性计算机可读存储介质存储有被处理器执行时实现如上任一方法步骤的计算机程序。
本申请至少具有以下有益效果:本申请提出一种基于SSD主控变频的时间管理方法、装置、设备及介质,其中,本申请提出的一种基于SSD主控变频的时间管理方法应用于SSD主频可变的情况下的时间管理的方法,采用单核变频、多核同步、时间戳同步的方法,将时间系统层层封装,最终得到一种用户简单易用的时间管理方法。该方法可以消除变频导致时间计数不准的问题,方便固件直接调用;此方法中的多核时间同步方法,方便固件的统一调度;此方法中增加时间戳功能,使SSD设备内部的时间与面向用户的显示的时间保持一致,方便研发开发和定位问题,同时对用户使用更加友好。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它的实施例。
图1示出的为本申请提供的一种基于SSD主控变频的时间管理方法的实施例的示意图;
图2示出的为本申请提供的一种基于SSD主控变频的时间管理方法的实施例;
图3示出的为本申请提供的一种基于SSD主控变频的时间管理装置的实 施例的示意图;
图4示出的为本申请提供的一种基于SSD主控变频的时间管理装置的另一实施例的示意图;
图5示出的为本申请提供的一种基于SSD主控变频的时间管理装置的另一实施例的示意图;
图6示出的是本申请提供的一种基于SSD主控变频的时间管理装置的另一实施例的示意图;
图7示出的是本申请提供的一种计算机设备的实施例的示意图;
图8示出的是本申请提供的一种非易失性计算机可读存储介质的实施例的示意图。
具体实施方式
以下描述了本申请的实施例。然而,应该理解,所公开的实施例仅仅是示例,并且其它实施例可以采取各种替代形式。
此外,需要说明的是,本申请实施例中所有使用“第一”和“第二”的表述均是为了区分两个相同名称非相同的实体或者非相同的参量,可见“第一”“第二”仅为了表述的方便,不应理解为对本申请实施例的限定,后续实施例对此不再一一说明。术语“包括”、“包含”或其任何其它变形旨在涵盖非排他性的包括,以使包含一系列要素的过程、方法、物品或装置不仅包括那些要素,也可以包括未明确列出的或这些过程、方法、物品或装置所固有的要素。
现有技术中,对SSD设备的时间管理的方法包括:在控制器内部均存在一套时间计数方法,该方法依赖控制器自身的频率,即时钟节拍(Ticks),时钟节拍随着时间逐步递增,开发者可根据时间节拍数值以及已知的控制器频率来计算时间流逝;还有的控制器会提供定时器功能,以满足周期性执行某个任务的需求,但定时器不能任意使用,存在资源限制。上述两种方法均存在一些问题,上述的第一种方式虽然简单易用,但在许多情况下使用并不方便。如果控制器的频率是可变的,那么就无法通过时钟节拍计数和控制器 频率来计算时间,因为主控频率是未知的;此外,SSD运行过程中应该存有日志,以便监控设备运行、存储设备出现问题时定位bug,每一条日志发生的时间如果通过时钟节拍来计算,会极不友好且效率低下。上述第二种方式虽然使用方便,但是更适合周期性任务使用,不能直接记录时间,且存在资源限制。
下面将结合附图说明本申请的一个或多个实施例。
基于以上目的,本申请实施例的第一个方面,提出了一种基于SSD主控变频的时间管理方法的实施例。图1示出的为本申请提供的一种基于SSD主控变频的时间管理方法的实施例的示意图。如图1所示,本申请实施例的一种基于SSD主控变频的时间管理方法包括以下步骤:
S1、获取SSD主控变频的新频率值和变频时面向固件的起始时钟节拍值,并且计算得到变频时面向固件的起始时间值;
S2、根据变频后面向固件的当前时钟节拍值、所述变频时面向固件的起始时钟节拍值以及所述新频率值计算得到变频后面向固件的当前时间差;
S3、基于所述变频时面向固件的起始时间值与所述变频后面向固件的当前时间差之和得到变频后面向固件的当前时间值。
基于以上目的,本申请实施例的第一个方面,提出了一种基于SSD主控变频的时间管理方法的实施例。图2示出的为本申请提供的一种基于SSD主控变频的时间管理方法的另一实施例的示意图。如图2所示,包括:
在单核变频的情况下的时间管理,即对于一个主频可变的CPU的时间管理,一般来说CPU的频率越高,性能越高,相应的功耗也越高,协调性能和功耗是SSD需要考虑的问题。一种简单的解决方法是当SSD在处理用户业务时,CPU保持高频,当SSD处于休眠状态时,SSD处于低频。借助控制器提供的时钟节拍Ticks计算时间是最基础的方式。例如,控制器频率为500M,即一秒钟内,控制器Ticks增加500,000,000次,当频率变为1000M时,一秒钟内Ticks增加1000,000,000。因此,对定频的控制器来说,可以直接通过前后两次Ticks之差除以控制器频率的方式计算时间差,记后一次 Ticks为Ticks2,前一次Ticks为Ticks1,则定频控制器的时间差为:
基于以上在定频时的时间差的计算方式,在Ticks之上定义并计算了一个记录变频后时间的Real_time,当需要使用时间时,用户可以直接使用Real_time,跳过需要使用Ticks进行计算从而避免变频的影响。
对于Real_time的计算方式,包括:
步骤一:控制器上电时,以高频P1启动,记录此时的Ticks(即变频时面向固件的起始时钟节拍值),记录为Ti0,并初始化Rt0=0(即初始化未变频时的面向固件的起始时间值)。若上电后未变频,则变频时面向固件的起始时间值Real_time可求得:
上式中,Ps表示Real_time以皮秒为单位,即1000,000,000,000每秒,Ticurrent为所述未变频时面向固件的起始时钟节拍。
步骤二:当控制器变频时,更新Ti0和Rt0,控制器频率变为P2,新的Ti0为变频时刻的Ticks,新的Rt0可用式二计算得出。变频为P2(即新频率值)后,变频后面向固件的当前时间值Real_time可求得:
每当控制器变频时,重复上述步骤二,这种情况下,变频造成的时间混乱的影响就消除了。每次需要获取时间时,用户可以调用式二或式三来计算Real_time。
随着SSD性能需求的提升,对SSD主控的性能要求也越来越高,因此主控芯片的核数也在增加。由于每个核有自身的时钟节拍,每个核有自己单独的时间系统,基于以上在单核变频的情况下的时间管理的方式,需要将各个核的时间统一,以方便上层应用统一管理。控制器通电开始,内部的各个核即开始工作,由于功能分配存在差异,各个核运行的是完全不同的代码。为了保持各个核的时间同步,需要首先选取其中的一个核作为时间同步的基准核,一般选取性能最好的核作为基准核;其次,各个核在上电初始化的某 个时刻,记录各自核的Ticks值Ti0[core],各个核记录的Ti0[core]不同。用各个核的Ti0[core]减去基准核的Ti0,假设基准核core number是0,得到各个核与基准核的偏差Diff_Ti[core]
除基准核外,各核在计算时间时,应该在原本计算的基础上增加Diff_Ti[core],保证时间均以基准核时间计算,则以式二为基础,各个核的Real_time变为:
通过以上方式,可以实现在多核的情况下,保持各个核的时间一致。
经以上的过变频处理和时间同步,固件可以准确无误地按照正确的时序运行了。但是此时的时间为面向固件的时间,而不是直接面向用户的时间,用户对公元时间如2022.06.01.15:30:00更熟悉,而不关注固件内部时间。比如,当获取一段固件日志时,用户只知道某条命令的执行时间是上电后多少秒,但是用户更想知道的是哪天哪个时刻执行了这条命令。因此,借助时间戳,可以将固件内时间转换为公元时间。基于此,提供一种时间戳的方式,将面向固件的时间转化为面向用户的时间:
当SSD设备驱动加载完毕后,通过主机发送给SSD设备一个同步时间戳TimeStamp(即SSD接收到的时间戳)的命令,即主机将当前公元时间以毫秒时间戳的形式发送给SSD设备。SSD设备将时间戳TineStamp记录下来,并记录此时固件内部时间Real_time(即时间戳对应的变频后面向固件的当前时间值),此后日志就可以以公元时间记录下来:
Time=Real_time-Real_timestart+TineStamp   (式六)
其中,Real_timestart为变频时面向固件的起始时间值。
基于以上操作,可以消除变频导致时间计数不准的问题,方便固件直接调用;此方法中的多核时间同步方法,方便固件的统一调度;此方法中增加时间戳功能,使SSD设备内部的时间与面向用户的显示的时间保持一致,方便研发开发和定位问题,同时对用户使用更加友好。
本申请的实施例的第二个方面,提出了一种基于SSD主控变频的时间管理装置。图3示出的是本申请提供的一种基于SSD主控变频的时间管理装置的实施例的示意图。如图3所示,本申请提供的一种基于SSD主控变频的时间管理装置包括:第一模块011,配置用于获取SSD主控变频的新频率值和变频时面向固件的起始时钟节拍值,并且计算得到变频时面向固件的起始时间值;第二模块012,配置用于根据变频后面向固件的当前时钟节拍值、所述变频时面向固件的起始时钟节拍值以及所述新频率值计算得到变频后面向固件的当前时间差;第三模块013,配置用于基于所述变频时面向固件的起始时间值与所述变频后面向固件的当前时间差之和得到变频后面向固件的当前时间值。
本申请实施例的第二个方面,提出了一种基于SSD主控变频的时间管理装置。图4示出的是本申请提供的一种基于SSD主控变频的时间管理装置的另一实施例的示意图。如图4所示,本申请提供的一种基于SSD主控变频的时间管理装置还包括:第四模块014,配置用于响应于发生新的变频时,以新的变频时的时钟节拍值和面向固件的时间值更新所述面向固件的起始时钟节拍值和所述面向固件的起始时间值,并且基于所述新的变频的频率值计算得到所述新的变频的面向固件的当前时间值。
本申请实施例的第二个方面,提出了一种基于SSD主控变频的时间管理装置。图5示出的是本申请提供的一种基于SSD主控变频的时间管理装置的另一实施例的示意图。如图5所示,本申请提供的一种基于SSD主控变频的时间管理装置还包括:第五模块015,配置用于响应于所述SSD为多核运行,选择所述多核中的一个核作为所述多核的时间同步的基准核;第六模块016,配置用于分别计算剩余核与所述基准核的偏差值,并基于所述偏差值计算所述剩余核的变频后面向固件的当前时间值,以使所述剩余核的变频后面向固件的当前时间值与所述基准核的变频后面向固件的当前时间值保持一致。
本申请实施例的第二个方面,提出了一种基于SSD主控变频的时间管理装置。图6示出的是本申请提供的一种基于SSD主控变频的时间管理装置的另一实施例的示意图。如图6所示,本申请提供的一种基于SSD主控变频的 时间管理装置还包括:第七模块,配置用于基于所述SSD接收到的时间戳得到所述时间戳对应的变频后面向固件的当前时间值,并基于所述时间戳和所述时间戳对应的变频后面向固件的当前时间值得到变频后面向用户的当前时间值。
基于以上目的,本申请实施例的第三个方面,提出了一种计算机设备,图7示出的是本申请提供的一种计算机设备的实施例的示意图。如图7所示,本申请提供的一种计算机设备的实施例,包括以下模块:至少一个处理器021;以及存储器022,存储器022存储有可在处理器021上运行的计算机指令023,计算机指令023由处理器021执行时实现如上所述方法的步骤。
本申请还提供了一种非易失性计算机可读存储介质。图8示出的是本申请提供的一种非易失性计算机可读存储介质的实施例的示意图。如图8所示,非易失性计算机可读存储介质031存储有被处理器执行时执行如上方法的计算机程序032。
最后需要说明的是,本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程,可以通过计算机程序来指令相关硬件来完成,设置系统参数的方法的程序可存储于一计算机可读取存储介质中,该程序在执行时,可包括如上述各方法的实施例的流程。其中,程序的存储介质可为磁碟、光盘、只读存储记忆体(ROM)或随机存储记忆体(RAM)等。上述计算机程序的实施例,可以达到与之对应的前述任意方法实施例相同或者相类似的效果。
此外,根据本申请实施例公开的方法还可以被实现为由处理器执行的计算机程序,该计算机程序可以存储在计算机可读存储介质中。在该计算机程序被处理器执行时,执行本申请实施例公开的方法中限定的上述功能。
此外,上述方法步骤以及系统单元也可以利用控制器以及用于存储使得控制器实现上述步骤或单元功能的计算机程序的计算机可读存储介质实现。
本领域技术人员还将明白的是,结合这里的公开所描述的各种示例性逻辑块、模块、电路和算法步骤可以被实现为电子硬件、计算机软件或两者的组合。为了清楚地说明硬件和软件的这种可互换性,已经就各种示意性组件、 方块、模块、电路和步骤的功能对其进行了一般性的描述。这种功能是被实现为软件还是被实现为硬件取决于具体应用以及施加给整个系统的设计约束。本领域技术人员可以针对每种具体应用以各种方式来实现的功能,但是这种实现决定不应被解释为导致脱离本申请实施例公开的范围。
在一个或多个示例性设计中,功能可以在硬件、软件、固件或其任意组合中实现。如果在软件中实现,则可以将功能作为一个或多个指令或代码存储在计算机可读介质上或通过计算机可读介质来传送。计算机可读介质包括计算机存储介质和通信介质,该通信介质包括有助于将计算机程序从一个位置传送到另一个位置的任何介质。存储介质可以是能够被通用或专用计算机访问的任何可用介质。作为例子而非限制性的,该计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其它光盘存储设备、磁盘存储设备或其它磁性存储设备,或者是可以用于携带或存储形式为指令或数据结构的所需程序代码并且能够被通用或专用计算机或者通用或专用处理器访问的任何其它介质。此外,任何连接都可以适当地称为计算机可读介质。例如,如果使用同轴线缆、光纤线缆、双绞线、数字用户线路(DSL)或诸如红外线、无线电和微波的无线技术来从网站、服务器或其它远程源发送软件,则上述同轴线缆、光纤线缆、双绞线、D0L或诸如红外线、无线电和微波的无线技术均包括在介质的定义。如这里所使用的,磁盘和光盘包括压缩盘(CD)、激光盘、光盘、数字多功能盘(DVD)、软盘、蓝光盘,其中磁盘通常磁性地再现数据,而光盘利用激光光学地再现数据。上述内容的组合也应当包括在计算机可读介质的范围内。
以上是本申请公开的示例性实施例,但是应当注意,在不背离权利要求限定的本申请实施例公开的范围的前提下,可以进行多种改变和修改。根据这里描述的公开实施例的方法权利要求的功能、步骤和/或动作不需以任何特定顺序执行。此外,尽管本申请实施例公开的元素可以以个体形式描述或要求,但除非明确限制为单数,也可以理解为多个。
应当理解的是,在本文中使用的,除非上下文清楚地支持例外情况,单数形式“一个”旨在也包括复数形式。还应当理解的是,在本文中使用的 “和/或”是指包括一个或者一个以上相关联地列出的项目的任意和所有可能组合。
上述本申请实施例公开实施例序号仅仅为了描述,不代表实施例的优劣。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成,也可以通过程序来指令相关的硬件完成,程序可以存储于一种计算机可读存储介质中,上述提到的存储介质可以是只读存储器,磁盘或光盘等。
所属领域的普通技术人员应当理解:以上任何实施例的讨论仅为示例性的,并非旨在暗示本申请实施例公开的范围(包括权利要求)被限于这些例子;在本申请实施例的思路下,以上实施例或者不同实施例中的技术特征之间也可以进行组合,并存在如上的本申请实施例的不同方面的许多其它变化,为了简明它们没有在细节中提供。因此,凡在本申请实施例的精神和原则之内,所做的任何省略、修改、等同替换、改进等,均应包含在本申请实施例的保护范围之内。

Claims (20)

  1. 一种基于SSD主控变频的时间管理方法,其特征在于,包括:
    获取SSD主控变频的新频率值和变频时面向固件的起始时钟节拍值,并且计算得到变频时面向固件的起始时间值;
    根据变频后面向固件的当前时钟节拍值、所述变频时面向固件的起始时钟节拍值以及所述新频率值计算得到变频后面向固件的当前时间差;
    基于所述变频时面向固件的起始时间值与所述变频后面向固件的当前时间差之和得到变频后面向固件的当前时间值。
  2. 根据权利要求1所述的方法,其特征在于,还包括:
    设置记录未变频时面向固件的起始时间值、起始时钟节拍值,并且获取未变频时的频率值;
    根据所述变频时面向固件的起始时钟节拍值、所述未变频时面向固件的起始时钟节拍值以及所述未变频时的频率值计算得到变频时面向固件的时间差;
    基于所述未变频时面向固件的起始时间值与所述变频时面向固件的时间差之和得到所述变频时面向固件的起始时间值。
  3. 根据权利要求2所述的方法,其特征在于,所述设置记录未变频时面向固件的起始时间值、起始时钟节拍值,并且获取未变频时的频率值包括:
    初始化未变频时的面向固件的起始时间值为0并记录与其对应的时钟节拍值作为未变频时面向固件的起始时钟节拍值。
  4. 根据权利要求2所述的方法,其特征在于,所述根据所述变频时面向固件的起始时钟节拍值、所述未变频时面向固件的起始时钟节拍值以及所述未变频时的频率值计算得到变频时面向固件的时间差包括:
    根据所述变频时面向固件的起始时钟节拍值与所述未变频时面向固件的起始时钟节拍的差值得到变频时的当前时钟差值;
    计算所述变频时的当前时钟差值与所述未变频时的频率值的比值得到变 频时面向固件的时间差。
  5. 根据权利要求1所述的方法,其特征在于,所述根据变频后面向固件的当前时钟节拍值、所述变频时面向固件的起始时钟节拍值以及所述新频率值计算得到变频后面向固件的当前时间差包括:
    根据变频后面向固件的当前时钟节拍值与所述变频时面向固件的起始时钟节拍值差值得到变频后的当前时钟差值;
    计算所述变频后的当前时钟差值与所述新频率值的比值得到变频后面向固件的当前时间差。
  6. 根据权利要求1所述的方法,其特征在于,还包括:
    响应于发生新的变频时,以新的变频时的时钟节拍值和面向固件的时间值更新所述面向固件的起始时钟节拍值和所述面向固件的起始时间值,并且基于所述新的变频的频率值计算得到所述新的变频的面向固件的当前时间值。
  7. 根据权利要求1所述的方法,其特征在于,还包括:
    响应于所述SSD为多核运行,选择所述多核中的一个核作为所述多核的时间同步的基准核;
    分别计算剩余核与所述基准核的偏差值,并基于所述偏差值计算所述剩余核的变频后面向固件的当前时间值,以使所述剩余核的变频后面向固件的当前时间值与所述基准核的变频后面向固件的当前时间值保持一致。
  8. 根据权利要求7所述的方法,其特征在于,所述响应于所述SSD为多核运行,选择所述多核中的一个核作为所述多核的时间同步的基准核包括:
    选择多核中性能最优的核作为所述多核的时间同步的基准核。
  9. 根据权利要求7所述的方法,其特征在于,所述分别计算剩余核与所述基准核的偏差值,并基于所述偏差值计算所述剩余核的变频后面向固件的当前时间值,以使所述剩余核的变频后面向固件的当前时间值与所述基准核的变频后面向固件的当前时间值保持一致包括:
    基于所述剩余核的未变频时面向固件的起始时钟节拍值和所述基准核的未变频时面向固件的起始时钟节拍值之差得到所述剩余核与所述基准核的偏 差值;
    根据所述剩余核的变频后面向固件的当前时钟节拍值、所述剩余核的变频时面向固件的起始时钟节拍值、所述偏差值以及所述剩余核的变频后的频率值计算得到所述剩余核的变频后面向固件的当前时间差;
    基于所述基准核的变频时面向固件的起始时间值和所述剩余核的变频后面向固件的当前时间差之和得到所述剩余核的变频后面向固件的当前时间值,以保持与所述基准核的变频后面向固件的当前时间值一致。
  10. 根据权利要求9所述的方法,其特征在于,所述基于所述剩余核的未变频时面向固件的起始时钟节拍值和所述基准核的未变频时面向固件的起始时钟节拍值之差得到所述剩余核与所述基准核的偏差值包括:
    初始化所述基准核的未变频时的面向固件的起始时间值为0并记录与其对应的时钟节拍值作为所述基准核未变频时面向固件的起始时钟节拍值。
  11. 根据权利要求9所述的方法,其特征在于,所述根据所述剩余核的变频后面向固件的当前时钟节拍值、所述剩余核的变频时面向固件的起始时钟节拍值、所述偏差值以及所述剩余核的变频后的频率值计算得到所述剩余核的变频后面向固件的当前时间差包括:
    基于所述剩余核的变频后面向固件的当前时钟节拍值与所述剩余核的变频时面向固件的起始时钟节拍值之差添加所述偏差值,得到所述剩余核的变频后的当前时钟差值;
    计算所述剩余核的变频后的当前时钟差值与所述剩余核的变频后的频率值的比值,得到所述剩余核的变频后面向固件的当前时间差。
  12. 根据权利要求1所述的方法,其特征在于,还包括:
    基于所述SSD接收到的时间戳得到所述时间戳对应的变频后面向固件的当前时间值,并基于所述时间戳和所述时间戳对应的变频后面向固件的当前时间值得到变频后面向用户的当前时间值。
  13. 根据权利要求12所述的方法,其特征在于,所述基于所述时间戳和所述时间戳对应的变频后面向固件的当前时间值得到变频后面向用户的当前时间值,包括:
    确定所述变频时面向固件的起始时间值与所述变频后面向用户的当前时间值的时间差值;
    基于所述时间差值与所述时间戳得到变频后面向用户的当前时间值。
  14. 根据权利要求12所述的方法,其特征在于,所述基于所述时间差值与所述时间戳得到变频后面向用户的当前时间值,包括:
    基于所述时间差值与所述时间戳之和得到变频后面向用户的当前时间值。
  15. 根据权利要求12所述的方法,其特征在于,还包括:
    当所述SSD驱动加载完毕后,执行所述SSD接收时间戳。
  16. 根据权利要求15所述的方法,其特征在于,执行所述SSD接收时间戳,包括:
    接收主机发送给所述SSD的同步时间戳的命令,以接收所述时间戳,并记录所述时间戳。
  17. 根据权利要求12所述的方法,其特征在于,所述时间戳为毫秒时间戳。
  18. 一种基于SSD主控变频的时间管理装置,其特征在于,包括:
    第一模块,配置用于获取SSD主控变频的新频率值和变频时面向固件的起始时钟节拍值,并且计算得到变频时面向固件的起始时间值;
    第二模块,配置用于根据变频后面向固件的当前时钟节拍值、所述变频时面向固件的起始时钟节拍值以及所述新频率值计算得到变频后面向固件的当前时间差;
    第三模块,配置用于基于所述变频时面向固件的起始时间值与所述变频后面向固件的当前时间差之和得到变频后面向固件的当前时间值。
  19. 一种计算机设备,其特征在于,包括:
    至少一个处理器;以及
    存储器,所述存储器存储有可在所述处理器上运行的计算机指令,所述指令由所述处理器执行时实现权利要求1-17任意一项所述方法的步骤。
  20. 一种非易失性计算机可读存储介质,所述非易失性计算机可读存储 介质存储有计算机程序,其特征在于,所述计算机程序被处理器执行时实现权利要求1-17任意一项所述方法的步骤。
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