WO2024077917A1

WO2024077917A1 - Anti-fuse unit and anti-fuse array

Info

Publication number: WO2024077917A1
Application number: PCT/CN2023/089185
Authority: WO
Inventors: 姜焕德
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-10-13
Filing date: 2023-04-19
Publication date: 2024-04-18
Also published as: CN115332257B; CN115332257A

Abstract

Disclosed in the embodiments of the present disclosure are an anti-fuse unit and an anti-fuse array. The anti-fuse unit comprises: an active region and at least one anti-fuse gate electrode. The active region extends in a first direction; the at least one anti-fuse gate electrode extends in a second direction; the at least one anti-fuse gate electrode is in contact with the top of the active region, covers two adjacent borders of the active region and is close to a target corner of the active region; and the target corner is the junction between two adjacent borders.

Description

Antifuse unit and antifuse array

CROSS-REFERENCE TO RELATED APPLICATIONS

This disclosure is based on the Chinese patent application with application number 202211250993.9 and application date October 13, 2022, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this disclosure as a reference.

Technical Field

The present disclosure relates to, but is not limited to, an antifuse unit and an antifuse array.

Background technique

There are usually redundant memory cells on DRAM (dynamic random access memory) chips. These redundant memory cells can replace defective memory cells when the DRAM chip has defective memory cells to achieve the purpose of repairing the DRAM. When repairing DRAM chips, one-time programmable (OTP) devices such as anti-fuse transistors are used. In related technologies, the probability of false breakdown of anti-fuse transistors is high.

Summary of the invention

In view of this, the embodiments of the present disclosure provide an anti-fuse unit and an anti-fuse array, which can reduce the uncertainty of the breakdown position, reduce the probability of false breakdown, and thus improve the reliability of the anti-fuse transistor.

The technical solution of the embodiment of the present disclosure is implemented as follows:

An embodiment of the present disclosure provides an anti-fuse unit, which includes: an active area and at least one anti-fuse gate; the active area extends along a first direction; at least one anti-fuse gate extends along a second direction; at least one anti-fuse gate contacts the top of the active area, covers two adjacent boundaries of the active area, and is close to a target corner of the active area; the target corner is the intersection of the two adjacent boundaries.

In the above scheme, the anti-fuse unit also includes: at least one selection gate; at least one selection gate extends along the second direction; at least one selection gate contacts the top of the active area and is located on the side of at least one anti-fuse gate away from the target corner.

In the above scheme, the anti-fuse gate includes: a first anti-fuse gate and a second anti-fuse gate; the first anti-fuse gate and a part of the active area on its side form a first anti-fuse transistor; the second anti-fuse gate and a part of the active area on its side form a second anti-fuse transistor; the first anti-fuse transistor and the second anti-fuse transistor are centrally symmetrically distributed on the active area; the selection gate includes: a first selection gate and a second selection gate; the first selection gate and a part of the active area on its side form a first selection transistor; the second selection gate and a part of the active area on its side form a second selection transistor; the first selection transistor and the second selection transistor are centrally symmetrically distributed on the active area.

In the above solution, the anti-fuse unit further includes: an address line contact structure; the address line contact structure contacts the top of the active area and is located between the first selection gate and the second selection gate.

In the above scheme, the active area includes: a first doped region and a second doped region; the first doped region and the second doped region are respectively located on opposite sides of the selection gate; the first doped region is located in the area between the anti-fuse gate and the selection gate; the first doped region and the second doped region have the same doping type.

In the above scheme, the active region further includes: a third doping region and a fourth doping region; the third doping region and the fourth doping region are both located below the selection gate; the third doping region contacts the selection gate and the first doping region respectively; the third doping region and the first doping region have the same doping type, and the doping concentration of the third doping region is less than the doping concentration of the first doping region; the fourth doping region contacts the selection gate and the second doping region respectively; the fourth doping region and the second doping region have the same doping type, and the fourth doping region The doping concentration of the first doping region is lower than the doping concentration of the second doping region.

In the above solution, the portion of the active region located below the anti-fuse gate has a doping type different from that of the first doping region.

In the above solution, the first direction and the second direction are both perpendicular to the vertical direction, and the first direction and the second direction are not perpendicular to each other.

An embodiment of the present disclosure also provides an anti-fuse array, which includes: a plurality of anti-fuse units described in the above scheme; the plurality of anti-fuse units form an array of M rows and N columns, wherein the anti-fuse units in each row are arranged along the second direction, and the anti-fuse units in each column are arranged along the first direction; and both M and N are even numbers greater than 0.

In the above scheme, the anti-fuse array also includes: M storage address lines; the M storage address lines all extend along the second direction; each of the storage address lines contacts the active area in each row of the anti-fuse units; each of the storage address lines passes through the central symmetrical point on the active area it contacts.

In the above solution, the anti-fuse gates and the selection gates in the plurality of anti-fuse units and the M storage body address lines are all located in the first layer in the vertical direction.

In the above scheme, the anti-fuse array also includes: N/2+1 anti-fuse control lines; N/2+1 anti-fuse control lines all extend along the first direction; two columns of anti-fuse units are arranged between two adjacent anti-fuse control lines; each anti-fuse control line is electrically connected to the anti-fuse gates in each adjacent column of anti-fuse units.

In the above scheme, the two anti-fuse units located between two adjacent anti-fuse control lines and in the same row have their first selection gates connected as a whole, their second selection gates connected as a whole, their first anti-fuse gates are not connected to each other, and their second anti-fuse gates are not connected to each other.

In the above solution, the anti-fuse array further includes: N transistor control lines; the N transistor control lines are distributed above the N columns of anti-fuse units in a one-to-one correspondence.

In the above scheme, the 2i-1th transistor control line is electrically connected to the first selection gate in the corresponding 2i-1th column of the anti-fuse unit; the 2ith transistor control line is electrically connected to the second selection gate in the corresponding 2ith column of the anti-fuse unit; i is greater than or equal to 1 and less than or equal to N/2.

In the above solution, N/2+1 of the anti-fuse control lines and N of the transistor control lines are all located in the second layer in the vertical direction.

It can be seen that the embodiments of the present disclosure provide an anti-fuse unit and an anti-fuse array, wherein the anti-fuse unit includes: an active area and at least one anti-fuse gate. The active area extends along a first direction; at least one anti-fuse gate extends along a second direction; at least one anti-fuse gate contacts the top of the active area, covers two adjacent boundaries of the active area, and is close to a target corner of the active area; the target corner is the intersection of the two adjacent boundaries. The anti-fuse gate in the embodiments of the present disclosure covers two adjacent boundaries of the active area and is close to the target corner corresponding to the two adjacent boundaries, so that the contact area between the anti-fuse gate and the active area can be reduced, thereby reducing the uncertainty of the breakdown position, reducing the probability of false breakdown, and thus improving the reliability of the anti-fuse transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a first structural diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG2 is a second structural schematic diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG3 is a third structural diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG4 is a fourth structural diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG5 is a fifth structural diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG6 is a sixth structural diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG7 is a seventh structural diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG8 is a circuit diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG9 is a first structural diagram of an antifuse array provided in an embodiment of the present disclosure;

FIG10 is a second structural diagram of an antifuse array provided in an embodiment of the present disclosure;

FIG11 is a circuit diagram of an antifuse array provided in an embodiment of the present disclosure;

FIG12 is a first schematic diagram of the effect of the antifuse array provided by an embodiment of the present disclosure;

FIG. 13 is a second schematic diagram of the effect of the antifuse array provided in the embodiment of the present disclosure.

FIG14 is a third schematic diagram of the effect of the antifuse array provided by the embodiment of the present disclosure;

FIG15 is a fourth schematic diagram of the effect of the antifuse array provided by an embodiment of the present disclosure;

FIG16 is a fifth schematic diagram of the effect of the antifuse array provided by an embodiment of the present disclosure;

FIG. 17 is a sixth schematic diagram of the effect of the antifuse array provided in an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

If similar descriptions of "first/second" appear in the application documents, the following description is added. In the following description, the terms "first/second/third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first/second/third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

FIG. 1 is a schematic diagram of an optional structure of an anti-fuse unit provided in an embodiment of the present disclosure, and FIG. 1 is a top view.

As shown in FIG1 , the anti-fuse unit 80 includes: an active area 10 and at least one anti-fuse gate 20. The active area 10 extends along a first direction p. The at least one anti-fuse gate 20 extends along a second direction q. The at least one anti-fuse gate 20 contacts the top of the active area 10, covers two adjacent boundaries (i.e., boundary a and boundary b) of the active area 10, and is close to a target corner of the active area 10. The target corner is the intersection of two adjacent boundaries.

In the embodiment of the present disclosure, the anti-fuse gate 20 and a portion of the active area 10 on its side can form an anti-fuse transistor. In actual use, a voltage can be applied to the anti-fuse gate 20 to form a breakdown in the contact surface between the anti-fuse gate 20 and the active area 10, thereby completing the programming of the anti-fuse transistor.

In the embodiment of the present disclosure, referring to FIG1 , the active area 10 extends along a first direction p, and the anti-fuse gate 20 extends along a second direction q, and the first direction p and the second direction q are different directions, and the first direction p and the second direction q are not perpendicular to each other. Furthermore, the anti-fuse gate 20 contacts the top of the active area 10, and the anti-fuse gate 20 covers two adjacent boundaries (boundary a and boundary b) of the active area 10. In this way, compared with covering two opposite boundaries of the active area 10 (for example, covering boundary b and boundary d of the active area 10), the contact area between the anti-fuse gate 20 shown in FIG1 and the active area 10 is smaller.

It should be noted that in the process of programming the anti-fuse transistor, the breakdown position is randomly generated in the contact surface between the anti-fuse gate and the active area. Therefore, the larger the contact area between the anti-fuse gate and the active area, the more difficult it is to control the breakdown position, that is, the greater the uncertainty of the breakdown position.

Therefore, the anti-fuse gate in the embodiment of the present invention covers two adjacent boundaries of the active area and is close to the target corners corresponding to the two adjacent boundaries. In this way, the contact area between the anti-fuse gate and the active area can be reduced, thereby reducing the uncertainty of the breakdown position and the probability of false breakdown, thereby improving the reliability of the anti-fuse transistor.

It should be noted that, in some embodiments, referring to FIG1 , in the anti-fuse unit 80, the number of the anti-fuse gate 20 is one, and the anti-fuse gate 20 covers the boundary a and the boundary b of the active area 10. In other embodiments, referring to FIG2 , in the anti-fuse unit 80, the number of the anti-fuse gate 20 is two, one of the anti-fuse gates 20 covers the boundary a and the boundary b of the active area 10, and the other anti-fuse gate 20 covers the boundary c and the boundary d of the active area 10; the two anti-fuse gates 20 are arranged in a central symmetric manner.

FIG. 3 is a cross-sectional view along the cross-sectional line A-A1 in FIG. 1 and FIG. 2 , wherein the substrate 00 and the shallow trench isolation region 01 in FIG. 3 are not shown in FIG. 1 and FIG. 2 .

Referring to FIG. 3 , an active region 10 is formed on a substrate 00 , wherein the material of the substrate 00 is a semiconductor material, which may include silicon (Si), germanium (Ge), gallium arsenide (GaAs) or gallium nitride (GaN) and the like. A shallow trench isolation region 01 is also formed on the substrate 00 , wherein the material of the shallow trench isolation region 01 is an insulating material. The shallow trench isolation region 01 is used to protect the active region 10 and prevent leakage current from being generated. The anti-fuse gate 20 includes an anti-fuse gate conductive layer 21 and an anti-fuse gate oxide layer 22 , wherein the anti-fuse gate conductive layer 21 is located on a side of the anti-fuse gate oxide layer 22 away from the active region 10 . The active region 10 includes a first doping region 11 , wherein the first doping region 11 is located on a side of the anti-fuse gate 20 away from the target corner. The anti-fuse gate 20 may form the gate of an anti-fuse transistor, and the first doping region 11 may form the drain or source of the anti-fuse transistor.

Continuing to refer to FIG. 3 , in the active region 10, the portion located below the anti-fuse gate 20 has a doping type different from that of the first doping region 11. Here, the portion below the anti-fuse gate 20 may be directly below the anti-fuse gate 20. For example, if the first doping region 11 is N-type doped, the portion directly below the anti-fuse gate 20 is P-type doped. In this way, the transmission direction of the carriers is not easily changed, thereby preventing the occurrence of reverse read leakage.

In some embodiments of the present disclosure, as shown in FIG. 4 or FIG. 5 (FIG. 4 and FIG. 5 are top views), the anti-fuse unit 80 further includes: at least one selection gate 30. The at least one selection gate 30 extends along the second direction q. The at least one selection gate 30 contacts the top of the active region 10 and is located on a side of the at least one anti-fuse gate 20 away from the target corner.

In the embodiment of the present disclosure, the selection gate 30 and a part of the active area 10 on its side can form a selection transistor. In actual use, the anti-fuse transistor electrically connected to the selection transistor can be controlled by controlling the on and off of the selection transistor.

It should be noted that, in some embodiments, referring to FIG4 , in the anti-fuse unit 80, the number of the anti-fuse gate 20 and the number of the selection gate 30 are both one. In other embodiments, referring to FIG5 , in the anti-fuse unit 80, the number of the anti-fuse gate 20 and the number of the selection gate 30 are both two; the two anti-fuse gates 20 and the two selection gates 30 are arranged in a central symmetric manner.

In the disclosed embodiment, referring to FIG. 4 or FIG. 5 , the active region 10 extends along a first direction p, and the anti-fuse gate 20 and the selection gate 30 both extend along a second direction q. The first direction p and the second direction q are different directions, and the first direction p and the second direction q are not perpendicular to each other. At the same time, the first direction p and the second direction q are both perpendicular to the vertical direction.

In some embodiments of the present disclosure, as shown in FIG6 (FIG6 is a top view), the anti-fuse gate in the anti-fuse unit 80 includes: a first anti-fuse gate 201 and a second anti-fuse gate 202. The first anti-fuse gate 201 and a portion of the active area 10 on its side form a first anti-fuse transistor; the second anti-fuse gate 202 and a portion of the active area 10 on its side form a second anti-fuse transistor; the first anti-fuse transistor and the second anti-fuse transistor are centrally symmetrically distributed on the active area 10.

6, the selection gate in the anti-fuse unit 80 includes: a first selection gate 301 and a second selection gate 302. The first selection gate 301 and a part of the active area 10 on its side form a first selection transistor; the second selection gate 302 and a part of the active area 10 on its side form a second selection transistor; the first selection transistor and the second selection transistor are distributed in a centrally symmetrical manner on the active area 10.

In some embodiments of the present disclosure, referring to FIG6 , the anti-fuse unit 80 further includes an address line contact structure 40. The address line contact structure 40 contacts the top of the active area 10 and is located between the first selection gate 301 and the second selection gate 302. The address line contact structure 40 can electrically connect the memory address line to the active area 10.

In the embodiment of the present disclosure, the first direction p and the second direction q shown in FIG. 6 are both perpendicular to the vertical direction, and the first direction p and the second direction q are not perpendicular to each other.

FIG7 is a cross-sectional view along the cross-sectional line B-B1 in FIG6 . The substrate 00, the shallow trench isolation region 01 and the dielectric layer 02 in FIG7 are not shown in FIG6 . Meanwhile, FIG7 only shows the cross-sectional structure of the first anti-fuse gate 201, the first selection gate 301, the address line contact structure 40 and a portion of the active region 10 in FIG6 ; the cross-sectional structure of the second anti-fuse gate 202 and the second selection gate 302 can refer to the cross-sectional structure of the first anti-fuse gate 201 and the first selection gate 301. Structure.

In conjunction with FIG. 6 and FIG. 7 , the active area 10 is formed on the substrate 00, wherein the material of the substrate 00 is a semiconductor material. A shallow trench isolation region 01 is also formed on the substrate 00, wherein the material of the shallow trench isolation region 01 is an insulating material. The shallow trench isolation region 01 is used to protect the active area 10 and avoid the generation of leakage current. The first anti-fuse gate 201 includes an anti-fuse gate conductive layer 211 and an anti-fuse gate oxide layer 221, wherein the anti-fuse gate conductive layer 211 is located on the side of the anti-fuse gate oxide layer 221 away from the active area 10. The first selection gate 301 includes a selection gate conductive layer 311 and a selection gate oxide layer 321, wherein the selection gate conductive layer 311 is located on the side of the selection gate oxide layer 321 away from the active area 10. Part of the address line contact structure 40 is embedded in the active area 10 to form an electrical contact.

In some embodiments of the present disclosure, the active region includes: a first doping region and a second doping region. The first doping region and the second doping region are respectively located on opposite sides of the selection gate. The first doping region is located in the region between the anti-fuse gate and the selection gate. The first doping region and the second doping region have the same doping type.

6 and 7, the active region 10 includes a first doping region 11, a second doping region 12, a third doping region 13 and a fourth doping region 14. The first doping region 11 and the second doping region 12 are respectively located on opposite sides of the first selection gate 301, and the first doping region 11 is located in the region between the first anti-fuse gate 201 and the first selection gate 301. The first doping region 11 and the second doping region 12 have the same doping type, for example, the first doping region 11 and the second doping region 12 are both N-type doped.

In some embodiments of the present disclosure, the active region further includes: a third doping region and a fourth doping region. The third doping region and the fourth doping region are both located below the selection gate. Here, below the selection gate may be directly below the selection gate. The third doping region contacts the selection gate and the first doping region, respectively; the third doping region and the first doping region have the same doping type, and the doping concentration of the third doping region is less than the doping concentration of the first doping region. The fourth doping region contacts the selection gate and the second doping region, respectively; the fourth doping region and the second doping region have the same doping type, and the doping concentration of the fourth doping region is less than the doping concentration of the second doping region.

In conjunction with FIG. 6 and FIG. 7 , the third doping region 13 is located directly below the first selection gate 301, and the third doping region 13 contacts the first selection gate 301 and the first doping region 11, respectively. The third doping region 13 and the first doping region 11 have the same doping type, and the doping concentration of the third doping region 13 is less than the doping concentration of the first doping region 11, for example, the first doping region 11 is heavily N-type doped, and the third doping region 13 is lightly N-type doped. Meanwhile, the fourth doping region 14 is located directly below the first selection gate 301, and the fourth doping region 14 contacts the first selection gate 301 and the second doping region 12, respectively. The fourth doping region 14 and the second doping region 12 have the same doping type, and the doping concentration of the fourth doping region 14 is less than the doping concentration of the second doping region 12, for example, the second doping region 12 is heavily N-type doped, and the fourth doping region 14 is lightly N-type doped.

In some embodiments of the present disclosure, a portion of the active region located below the anti-fuse gate has a doping type different from that of the first doping region.

Continuing with FIG. 6 and FIG. 7 , in the active region 10, the portion located below the first anti-fuse gate 201 (i.e., the portion located below the anti-fuse gate oxide layer 221) has a doping type different from that of the first doping region 11. For example, if the first doping region 11 is N-type doped, then the portion of the active region 10 located below the first anti-fuse gate 201 is P-type doped. In this way, the transmission direction of the carriers is not easy to change, thereby preventing the occurrence of reverse reading leakage. As can be seen from FIG. 7 , there is a gap between the first doping region 11 and the first anti-fuse gate 201, so that the carriers are not easy to flow from the first doping region 11 to the first anti-fuse gate 201, thereby preventing reverse reading leakage.

FIG8 is a circuit diagram of an anti-fuse unit. As shown in FIG8 , the anti-fuse unit 80 includes: a first anti-fuse transistor Mf1, a first selection transistor Mc1, a second selection transistor Mc2, and a second anti-fuse transistor Mf2. The drain of the first anti-fuse transistor Mf1 is electrically connected to the source of the first selection transistor Mc1; the drain of the first selection transistor Mc1 is electrically connected to the drain of the second selection transistor Mc2; and the source of the second selection transistor Mc2 is electrically connected to the drain of the second anti-fuse transistor Mf2.

6 and 8 , the first anti-fuse gate 201 and a portion of the active region 10 on its side form a first anti-fuse transistor Mf1 , wherein the first anti-fuse gate 201 forms the gate of the first anti-fuse transistor Mf1 . The first selection gate 301 and the part of the active area 10 on the side thereof form a second anti-fuse transistor Mf2, wherein the second anti-fuse gate 202 forms the gate of the second anti-fuse transistor Mf2. The first selection gate 301 and the part of the active area 10 on the side thereof form a first selection transistor Mc1, wherein the first selection gate 301 forms the gate of the first selection transistor Mc1. The second selection gate 302 and the part of the active area 10 on the side thereof form a second selection transistor Mc2, wherein the second selection gate 302 forms the gate of the second selection transistor Mc2. The address line contact structure 40 is located at the Lc point between the drain of the first selection transistor Mc1 and the drain of the second selection transistor Mc2.

In conjunction with FIG. 7 and FIG. 8 , the first doped region 11 can form the drain of the first anti-fuse transistor Mf1 and the source of the first selection transistor Mc1, that is, the drain of the first anti-fuse transistor Mf1 and the source of the first selection transistor Mc1 are electrically connected by sharing a doped region; accordingly, the drain of the second anti-fuse transistor Mf2 and the source of the second selection transistor Mc2 are also electrically connected by sharing a doped region. The second doped region 12 can form the drain of the first selection transistor Mc1 and the drain of the second selection transistor Mc2, that is, the drain of the first selection transistor Mc1 and the drain of the second selection transistor Mc2 are electrically connected by sharing a doped region. In some embodiments, the first doped region 11 can also form the source of the first anti-fuse transistor Mf1 and the drain of the first selection transistor Mc1.

The present disclosure also provides an antifuse array, which includes a plurality of antifuse units as described in the above embodiments. The plurality of antifuse units form an array of M rows and N columns, wherein each row of antifuse units is arranged along the second direction, and each column of antifuse units is arranged along the first direction; M and N are both even numbers greater than 0.

FIG9 illustrates the structure of the antifuse array when M and N are both 4, and FIG9 is a top view. Referring to FIG9 , the antifuse array includes a plurality of antifuse units 80, and the plurality of antifuse units 80 form an array of 4 rows and 4 columns. Each row of antifuse units 80 is arranged along the second direction q, and each column of antifuse units is arranged along the first direction p, wherein the first direction p and the second direction q are different directions, and the first direction p and the second direction q are not perpendicular to each other.

Continuing to refer to FIG9 , each anti-fuse unit 80 includes: an active region 10, a first anti-fuse gate 201, a second anti-fuse gate 202, a first selection gate 301, and a second selection gate 302. The active region 10 extends along a first direction p; the first anti-fuse gate 201, the second anti-fuse gate 202, the first selection gate 301, and the second selection gate 302 all extend along a second direction q. The first anti-fuse gate 201, the second anti-fuse gate 202, the first selection gate 301, and the second selection gate 302 all contact the top of the active region 10; the first anti-fuse gate 201, the second anti-fuse gate 202, the first selection gate 301, and the second selection gate 302 are arranged in a central symmetric manner.

Furthermore, the first anti-fuse gate 201 and the second anti-fuse gate 202 respectively cover two adjacent boundaries of the active area 10 and are close to the target corner of the active area 10, wherein the target corner is the intersection of the two adjacent boundaries. In this way, the contact area between the anti-fuse gate and the active area can be reduced, thereby reducing the uncertainty of the breakdown position and the probability of false breakdown.

In the embodiment of the present disclosure, referring to Figure 9, in each anti-fuse unit 80, the first anti-fuse gate 201 and a portion of the active area 10 on its side form a first anti-fuse transistor, wherein the first anti-fuse gate 201 forms the gate of the first anti-fuse transistor; the second anti-fuse gate 202 and a portion of the active area 10 on its side form a second anti-fuse transistor, wherein the second anti-fuse gate 202 forms the gate of the second anti-fuse transistor; the first selection gate 301 and a portion of the active area 10 on its side form a first selection transistor, wherein the first selection gate 301 forms the gate of the first selection transistor; the second selection gate 302 and a portion of the active area 10 on its side form a second selection transistor, wherein the second selection gate 302 forms the gate of the second selection transistor.

In the embodiment of the present disclosure, referring to FIG. 9 , each active region 10 includes: a first doped region and a second doped region. The first doped region and the second doped region are respectively located on opposite sides of the selection gate (i.e., the first selection gate 301 or the second selection gate 302); the first doped region is located in the region between the anti-fuse gate (i.e., the first anti-fuse gate 201 or the second anti-fuse gate 202) and the selection gate. The first doped region and the second doped region have the same doping type. The drain of the first anti-fuse transistor and the source of the first selection transistor are electrically connected by sharing a first doped region; accordingly, the drain of the second anti-fuse transistor and the source of the second selection transistor are also electrically connected by sharing a first doped region. The drain of the first selection transistor and the drain of the second selection transistor are electrically connected by sharing a second doped region.

Continuing to refer to FIG9, each active region 10 further includes: a third doping region and a fourth doping region. The four doping regions are all located below the selection gate (i.e., the first selection gate 301 or the second selection gate 302). The third doping region contacts the selection gate and the first doping region respectively; the third doping region and the first doping region have the same doping type, and the doping concentration of the third doping region is less than the doping concentration of the first doping region. The fourth doping region contacts the selection gate and the second doping region respectively; the fourth doping region and the second doping region have the same doping type, and the doping concentration of the fourth doping region is less than the doping concentration of the second doping region. In this way, the source-drain electric field of the formed device (i.e., the first selection transistor and the second selection transistor) is greatly reduced, the avalanche impact ionization is sharply reduced, the hot carrier effect is weakened, and the avalanche breakdown voltage is increased, thereby improving the short channel effect. In other words, the use of the third doping region and the fourth doping region with lower doping concentrations can effectively overcome the short channel effect and the hot carrier effect.

9, in each active region 10, the portion located below the anti-fuse gate (i.e., the first anti-fuse gate 201 or the second anti-fuse gate 202) has a doping type different from that of the first doping region. In this way, the carrier transmission direction is not easily changed, thereby preventing the occurrence of reverse read leakage.

In some embodiments of the present disclosure, the antifuse array further includes: M storage body address lines. The M storage body address lines all extend along the second direction. Each storage body address line contacts the active area in each row of antifuse cells; each storage body address line passes through a central symmetric point on the active area it contacts.

In the disclosed embodiment, referring to FIG. 9 , the antifuse array 90 includes 4 memory address lines (BA1, BA2, BA3, and BA4). The 4 memory address lines all extend along the second direction q. The memory address line BA1 contacts the active area 10 in the antifuse unit 80 of the first row and passes through the central symmetric point on the active area 10 it contacts. The memory address line BA2 contacts the active area 10 in the antifuse unit 80 of the second row and passes through the central symmetric point on the active area 10 it contacts. The memory address line BA3 contacts the active area 10 in the antifuse unit 80 of the third row and passes through the central symmetric point on the active area 10 it contacts. The memory address line BA4 contacts the active area 10 in the antifuse unit 80 of the fourth row and passes through the central symmetric point on the active area 10 it contacts. Since the drain of the first selection transistor and the drain of the second selection transistor are electrically connected at the central symmetrical point on the active area 10 , each memory address line is electrically connected to the drain of the first selection transistor and the drain of the second selection transistor formed in each row of anti-fuse units 80 .

In the disclosed embodiment, referring to FIG9 , each anti-fuse unit 80 further includes an address line contact structure (not shown in FIG9 ). The address line contact structure is located between the first selection gate 301 and the second selection gate 302 and is located at a central symmetrical point on the active area 10. Part of the address line contact structure is embedded in the active area 10 to form an electrical contact. The four memory address lines are electrically connected to the corresponding address line contact structures to form an electrical contact with the corresponding active area 10.

In some embodiments of the present disclosure, the anti-fuse gates and the selection gates in the plurality of anti-fuse units and the M memory address lines are all located in the first layer in the vertical direction.

It should be noted that FIG. 10 is a three-dimensional structural diagram of a part of the structure in FIG. 9 ; in FIG. 10 , both the first direction p and the second direction q are perpendicular to the vertical direction z.

In the embodiment of the present disclosure, referring to Figure 10, the first anti-fuse gate 201, the second anti-fuse gate 202, the first selection gate 301, the second selection gate 302, the storage address line BA1 and the storage address line BA2 have the same height in the vertical direction z, that is, they are all in the first layer in the vertical direction z.

In some embodiments of the present disclosure, the antifuse array further includes: N/2+1 (half N plus 1) antifuse control lines. The N/2+1 antifuse control lines all extend along the first direction. Two columns of antifuse units are arranged between two adjacent antifuse control lines. Each antifuse control line is electrically connected to the antifuse gates in each adjacent column of antifuse units.

In the disclosed embodiment, referring to FIG. 9 , when N is 4, the antifuse array 90 further includes 3 antifuse control lines (Af1, Af2, and Af3). The 3 antifuse control lines all extend along the first direction p. Between the antifuse control line Af1 and the antifuse control line Af2, the first column of antifuse units 80 and the second column of antifuse units 80 are arranged; between the antifuse control line Af2 and the antifuse control line Af3, the third column of antifuse units 80 and the fourth column of antifuse units 80 are arranged. The anti-fuse control line Af1 electrically connects the first anti-fuse gate 201 and the second anti-fuse gate 202 in the first column of the anti-fuse unit 80; the anti-fuse control line Af2 electrically connects the first anti-fuse gate 201 and the second anti-fuse gate 202 in the second column of the anti-fuse unit 80, and electrically connects the first anti-fuse gate 201 and the second anti-fuse gate 202 in the third column of the anti-fuse unit 80; the anti-fuse control line Af3 electrically connects the first anti-fuse gate 201 in the fourth column of the anti-fuse unit 80 and a second anti-fuse gate 202 .

It should be noted that in FIG. 9 , the electrical connection relationship between the anti-fuse control lines Af1, Af2, and Af3 and each anti-fuse gate is indicated by black filling. The anti-fuse gates electrically connected to the same anti-fuse control line can be connected as a whole. For example, the anti-fuse gates in the second column anti-fuse unit 80 and the third column anti-fuse unit 80 are both electrically connected to the anti-fuse control line Af2; thus, the anti-fuse units 80 in the same row in the second column and the third column have their first anti-fuse gates 201 connected as a whole, and their second anti-fuse gates 202 connected as a whole.

In some embodiments of the present disclosure, two anti-fuse units located between two adjacent anti-fuse control lines and in the same row have their first selection gates connected as a whole, their second selection gates connected as a whole, their first anti-fuse gates are not connected to each other, and their second anti-fuse gates are not connected to each other.

In the disclosed embodiment, referring to FIG9 , the first column of anti-fuse units 80 and the second column of anti-fuse units 80 are located between the anti-fuse control line Af1 and the anti-fuse control line Af2, that is, located between two adjacent anti-fuse control lines. Among the first column of anti-fuse units 80 and the second column of anti-fuse units 80, the two anti-fuse units 80 in the same row have their first selection gates 301 connected as a whole, their second selection gates 302 connected as a whole, their first anti-fuse gates 201 not connected to each other, and their second anti-fuse gates 202 not connected to each other. The third column of anti-fuse units 80 and the fourth column of anti-fuse units 80 are located between the anti-fuse control line Af2 and the anti-fuse control line Af3, that is, located between two adjacent anti-fuse control lines. In the third column of anti-fuse units 80 and the fourth column of anti-fuse units 80, the two anti-fuse units 80 in the same row have their first selection gates 301 connected as a whole, their second selection gates 302 connected as a whole, their first anti-fuse gates 201 not connected to each other, and their second anti-fuse gates 202 not connected to each other.

In some embodiments of the present disclosure, the anti-fuse array further includes: N transistor control lines. The N transistor control lines are distributed above the N columns of anti-fuse units in a one-to-one correspondence.

In the disclosed embodiment, referring to FIG9 , when N is 4, the anti-fuse array 90 further includes 4 transistor control lines (x1, x2, x3 and x4). The transistor control line x1 is distributed above the anti-fuse units 80 in the first column; the transistor control line x2 is distributed above the anti-fuse units 80 in the second column; the transistor control line x3 is distributed above the anti-fuse units 80 in the third column; and the transistor control line x4 is distributed above the anti-fuse units 80 in the fourth column.

In some embodiments of the present disclosure, the 2i-1th transistor control line is electrically connected to the first selection gate of the anti-fuse unit in the 2i-1th column corresponding thereto; the 2ith transistor control line is electrically connected to the second selection gate of the anti-fuse unit in the 2ith column corresponding thereto; i is greater than or equal to 1 and less than or equal to N/2 (N divided by two). In other words, the odd-numbered transistor control lines are electrically connected to the first selection gates of the anti-fuse units in the odd-numbered columns corresponding thereto; the even-numbered transistor control lines are electrically connected to the second selection gates of the anti-fuse units in the even-numbered columns corresponding thereto.

In the embodiment of the present disclosure, referring to FIG. 9 , when N is 4, i is 1 or 2. When i is 1, the transistor control line x1 (i.e., the first transistor control line) is electrically connected to the first selection gate 301 in the corresponding first column anti-fuse unit 80, and the transistor control line x2 (i.e., the second transistor control line) is electrically connected to the second selection gate 302 in the corresponding second column anti-fuse unit 80. When i is 2, the transistor control line x3 (i.e., the third transistor control line) is electrically connected to the first selection gate 301 in the corresponding third column anti-fuse unit 80, and the transistor control line x4 (i.e., the fourth transistor control line) is electrically connected to the second selection gate 302 in the corresponding fourth column anti-fuse unit 80.

Further, in each anti-fuse unit, the first selection gate 301 forms the gate of the first selection transistor, and the second selection gate 302 forms the gate of the second selection transistor. At the same time, among the anti-fuse units 80 in the first and second columns, the first selection gates 301 of the two anti-fuse units 80 in the same row are connected as a whole, and the second selection gates 302 of the two anti-fuse units 80 in the third and fourth columns are connected as a whole. Therefore, the transistor control line x1 electrically connects the gate of the first selection transistor formed by the anti-fuse units 80 in the first and second columns; the transistor control line x2 electrically connects the gate of the second selection transistor formed by the anti-fuse units 80 in the first and second columns; the transistor control line x3 electrically connects the gate of the first selection transistor formed by the anti-fuse units 80 in the third and fourth columns; and the transistor control line x4 electrically connects the gate of the second selection transistor formed by the anti-fuse units 80 in the third and fourth columns.

It should be noted that in FIG. 9 , the electrical connections between the transistor control lines x1, x2, x3 and x4 and the respective selection gates are Relationships are indicated by black fill.

In some embodiments of the present disclosure, N/2+1 anti-fuse control lines and N transistor control lines are all located in the second layer in the vertical direction.

In the disclosed embodiment, referring to FIG. 10 , three anti-fuse control lines (Af1, Af2, and Af3) and four transistor control lines (x1, x2, x3, and x4) are all in the second layer in the vertical direction z. Each anti-fuse control line or each transistor control line is electrically connected to the anti-fuse gate or the select gate in the first layer through the electrical contact structure 41. The second layer is higher than the first layer in the vertical direction z, that is, the second layer is located above the first layer.

It should be noted that Fig. 11 is a schematic diagram of a circuit of an antifuse array, and the circuit in Fig. 11 may correspond to a part of the structure in Fig. 9. The antifuse array will be described below in conjunction with Fig. 11.

As shown in FIG11 , in the anti-fuse array, a plurality of anti-fuse units 80 are arranged in an array in the form of 2 rows and 4 columns; each anti-fuse unit 80 includes: a first anti-fuse transistor Mf1, a first selection transistor Mc1, a second selection transistor Mc2, and a second anti-fuse transistor Mf2. In each anti-fuse unit 80, the drain of the first anti-fuse transistor Mf1 is electrically connected to the source of the first selection transistor Mc1; the drain of the first selection transistor Mc1 is electrically connected to the drain of the second selection transistor Mc2; and the source of the second selection transistor Mc2 is electrically connected to the drain of the second anti-fuse transistor Mf2.

Among them, the anti-fuse control line Af1 electrically connects the gate of the first anti-fuse transistor Mf1 in the first column and the gate of the second anti-fuse transistor Mf2 in the first column; the anti-fuse control line Af2 electrically connects the gate of the first anti-fuse transistor Mf1 in the second column and the gate of the second anti-fuse transistor Mf2 in the second column, and electrically connects the gate of the first anti-fuse transistor Mf1 in the third column and the gate of the second anti-fuse transistor Mf2 in the third column; the anti-fuse control line Af3 electrically connects the gate of the first anti-fuse transistor Mf1 in the fourth column and the gate of the second anti-fuse transistor Mf2 in the fourth column.

Among them, the transistor control line x1 is electrically connected to the gates of the first selection transistors Mc1 in the 1st and 2nd columns; the transistor control line x2 is electrically connected to the gates of the second selection transistors Mc2 in the 1st and 2nd columns; the transistor control line x3 is electrically connected to the gates of the first selection transistors Mc1 in the 3rd and 4th columns; the transistor control line x4 is electrically connected to the gates of the second selection transistors Mc2 in the 3rd and 4th columns.

Among them, the storage body address line BA1 electrically connects the drain of the first selection transistor Mc1 in the first row and the drain of the second selection transistor Mc2 in the first row; the storage body address line BA2 electrically connects the drain of the first selection transistor Mc1 in the second row and the drain of the second selection transistor Mc2 in the second row.

In the disclosed embodiment, referring to FIG11, if a certain anti-fuse transistor in the anti-fuse array is to be broken down, the selection transistor connected to the anti-fuse transistor needs to be turned on, and at the same time, a large voltage difference is applied between the anti-fuse control line corresponding to the anti-fuse transistor and the memory address line. The following is an example of breaking down the anti-fuse transistor Mf1 in the second row and the first column (shown by a dotted circle in FIG11).

Continuing to refer to FIG11 , if the anti-fuse transistor Mf1 in the 2nd row and the 1st column is to be broken down, a high voltage needs to be applied to the anti-fuse control line Af1, a low voltage needs to be applied to the memory address line BA2, and at the same time, a high voltage needs to be applied to the transistor control line x1 to turn on the selection transistor Mc1 in the 2nd row and the 1st column. In some embodiments, the voltages applied to the above three signal lines can be as shown in Table 1 below.

Table 1

Furthermore, when the voltage is applied to each signal line, the state of the anti-fuse transistor near the breakdown target (ie, the anti-fuse transistor Mf1 at the second row and the first column) may be different.

Case 1: The anti-fuse transistor near the breakdown target is in a non-breakdown state.

In case 1, since the storage address line BA1 is not selected (i.e., low voltage is not applied), and the transistor control line x2 is not opened (i.e., high voltage is not applied), the selection transistor Mc2 in the 1st row and 1st column is not turned on, and no path is formed between the anti-fuse control line Af1 and the storage address line BA1. Therefore, a large voltage difference cannot be formed between the gate and drain of the anti-fuse transistor Mf2 in the 1st row and 1st column, and the anti-fuse transistor Mf2 in the 1st row and 1st column will not be broken down.

At the same time, in case 1, since the storage address line BA1 is not selected (i.e., no low voltage is applied), and the transistor control line x2 is not turned on (i.e., no high voltage is applied), and the anti-fuse control line Af2 is not selected (i.e., no high voltage is applied), the selection transistor Mc2 in the 1st row and 2nd column is not turned on, no path is formed between the anti-fuse control line Af2 and the storage address line BA1, and there is no large voltage difference between the anti-fuse control line Af2 and the storage address line BA1, so that a large voltage difference cannot be formed between the gate and drain of the anti-fuse transistor Mf2 in the 1st row and 2nd column, and the anti-fuse transistor Mf2 in the 1st row and 2nd column will not be broken down.

At the same time, in case 1, since the anti-fuse control line Af2 is not selected (i.e., no high voltage is applied), there is no large voltage difference between the anti-fuse control line Af2 and the storage address line BA2. Therefore, a large voltage difference cannot be formed between the gate and drain of the anti-fuse transistor Mf1 in the second row and second column, and the anti-fuse transistor Mf1 in the second row and second column will not be broken down.

At the same time, in case 1, since the transistor control line x2 is not opened (i.e., no high voltage is applied), the selection transistor Mc2 in the second row and first column is not turned on, and no path is formed between the anti-fuse control line Af1 and the storage body address line BA2. Therefore, a large voltage difference cannot be formed between the gate and drain of the anti-fuse transistor Mf2 in the second row and first column, and the anti-fuse transistor Mf2 in the second row and first column will not be broken down.

At the same time, in case 1, since the anti-fuse control line Af2 is not selected (i.e., no high voltage is applied), and the transistor control line x2 is not opened (i.e., no high voltage is applied), the selection transistor Mc2 in the 2nd row and 2nd column is not turned on, no path is formed between the anti-fuse control line Af2 and the storage address line BA2, and there is no large voltage difference between the anti-fuse control line Af2 and the storage address line BA2. Therefore, a large voltage difference cannot be formed between the gate and drain of the anti-fuse transistor Mf2 in the 2nd row and 2nd column, and the anti-fuse transistor Mf2 in the 2nd row and 2nd column will not be broken down.

It can be understood that, in the process of breaking down any anti-fuse transistor, the anti-fuse transistor in the non-breakdown state will not be broken down by mistake, thereby improving the accuracy of the breakdown.

Case 2: The anti-fuse transistor near the breakdown target is in the breakdown state.

In case 2, since the storage address line BA1 is not selected (i.e., no low voltage is applied), and the transistor control line x2 is not turned on (i.e., no high voltage is applied), the selection transistor Mc2 in the 1st row and 1st column is not turned on, and no path is formed between the anti-fuse control line Af1 and the storage address line BA1. Therefore, the voltage on the anti-fuse control line Af1 will not be divided to the storage address line BA1 through the anti-fuse transistor Mf2 in the 1st row and 1st column, and the breakdown of the anti-fuse transistor Mf1 in the 2nd row and 1st column will not be affected.

At the same time, in case 2, since the transistor control line x2 is not turned on (i.e., no high voltage is applied), the selection transistor Mc2 in the second row and first column is not turned on, and no path is formed between the anti-fuse control line Af1 and the storage address line BA2. Therefore, the voltage on the anti-fuse control line Af1 will not be divided to the storage address line BA2 through the anti-fuse transistor Mf2 in the second row and first column, and the breakdown of the anti-fuse transistor Mf1 in the second row and first column will not be affected.

Meanwhile, in case 2, the gates of the anti-fuse transistors in the second column are not electrically connected to the anti-fuse control line Af1 , so the voltage on the anti-fuse control line Af1 will not be divided by the anti-fuse transistors in the second column.

Among them, after the anti-fuse transistor Mf2 in the 1st row and 2nd column is broken down, because the storage address line BA1 is not selected (that is, the low voltage is not applied), and the selection transistor Mc2 in the 1st row and 2nd column is not turned on, therefore, no leakage will be generated through the anti-fuse transistor Mf2 in the 1st row and 2nd column and the selection transistor Mc2, and the voltage on the anti-fuse control line Af1 will not be divided.

Among them, after the anti-fuse transistor Mf1 in the second row and the second column is broken down, because the storage body address line BA2 is selected (i.e., a low voltage is applied), the selection transistor Mc1 in the second row and the second column is turned on. At this time, there is a risk of leakage from the anti-fuse control line Af1 to the anti-fuse control line Af2. However, referring to FIG7 , since the part of the active area 10 below the gate of the anti-fuse transistor (including the anti-fuse gate conductive layer 211 and the anti-fuse gate oxide layer 221 in FIG7 ) has a different doping type from the first doping area 11, for example, the first doping area 11 is N-type doped, and the part of the active area 10 located below the gate of the anti-fuse transistor is P-type doped, that is, a PN junction is formed; therefore, the transmission direction of the carrier is not easy to change, and the current direction is difficult to point from the source or drain of the anti-fuse transistor (i.e., the first doping area 11) to the gate of the anti-fuse transistor, that is, the current is difficult to flow in the direction opposite to the PN junction, so that the anti-fuse control line Af1 will not flow in the opposite direction to the PN junction. The fuse control line Af2 is leaking.

It is understandable that, in the process of breaking down any anti-fuse transistor, the anti-fuse transistor in the broken-down state will not cause voltage division to affect the breakdown, thereby improving the accuracy of the breakdown.

In summary, the anti-fuse array provided by the embodiments of the present disclosure can improve the accuracy of breakdown, thereby enhancing the effect of fuse repair and improving the repair yield.

12 to 14 illustrate the voltage applied to the anti-fuse transistor Mf and the selection transistor Mc and the corresponding current generated when the anti-fuse transistor Mf is not broken down. The arrows in FIG12 and FIG13 indicate the direction of the current, and FIG14 shows the variation curve of the current and the voltage difference (i.e., the difference between the gate voltage Vfg of the anti-fuse transistor Mf and the source/drain voltage Vba of the selection transistor Mc).

In combination with FIG. 12 and FIG. 14 , in case a, the gate voltage Vfg of the anti-fuse transistor Mf is 0 to 3V, the source/drain voltage Vba of the selection transistor Mc is 0V, and the gate voltage Vxg of the selection transistor Mc is 0V (i.e., the selection transistor Mc is in the off state); at this time, the direction of the current is as shown by the arrow in FIG. 12 , flowing from the gate of the anti-fuse transistor Mf to the source/drain of the selection transistor Mc (i.e., positive reading). In case b, the gate voltage Vfg of the anti-fuse transistor Mf is 0 to 3V, the source/drain voltage Vba of the selection transistor Mc is 0V, and the gate voltage Vxg of the selection transistor Mc is 1V (i.e., the selection transistor Mc is in the on state); at this time, the direction of the current is as shown by the arrow in FIG. 12 , flowing from the gate of the anti-fuse transistor Mf to the source/drain of the selection transistor Mc (i.e., positive reading).

In combination with FIG. 13 and FIG. 14 , in case c, the gate voltage Vfg of the anti-fuse transistor Mf is 0V, the source/drain voltage Vba of the selection transistor Mc is 0-3V, and the gate voltage Vxg of the selection transistor Mc is 0V (i.e., the selection transistor Mc is in the off state); at this time, the direction of the current is as shown by the arrow in FIG. 13 , flowing from the source/drain of the selection transistor Mc to the gate of the anti-fuse transistor Mf (i.e., reverse reading). In case d, the gate voltage Vfg of the anti-fuse transistor Mf is 0V, the source/drain voltage Vba of the selection transistor Mc is 0-3V, and the gate voltage Vxg of the selection transistor Mc is 1V (i.e., the selection transistor Mc is in the on state); at this time, the direction of the current is as shown by the arrow in FIG. 13 , flowing from the source/drain of the selection transistor Mc to the gate of the anti-fuse transistor Mf (i.e., reverse reading).

15 to 17 illustrate the voltage applied to the anti-fuse transistor Mf and the selection transistor Mc and the corresponding current generated when the anti-fuse transistor Mf has been broken down. The arrows in FIG15 and FIG16 indicate the direction of the current, and FIG17 shows the variation curve of the current and the voltage difference (i.e., the difference between the gate voltage Vfg of the anti-fuse transistor Mf and the source/drain voltage Vba of the selection transistor Mc).

In combination with FIG. 15 and FIG. 17 , in case e, the gate voltage Vfg of the anti-fuse transistor Mf is 0 to 3V, the source/drain voltage Vba of the selection transistor Mc is 0V, and the gate voltage Vxg of the selection transistor Mc is 0V (i.e., the selection transistor Mc is in the off state); at this time, the direction of the current is as shown by the arrow in FIG. 15 , flowing from the gate of the anti-fuse transistor Mf to the source/drain of the selection transistor Mc (i.e., positive reading). In case f, the gate voltage Vfg of the anti-fuse transistor Mf is 0 to 3V, the source/drain voltage Vba of the selection transistor Mc is 0V, and the gate voltage Vxg of the selection transistor Mc is 1V (i.e., the selection transistor Mc is in the on state); at this time, the direction of the current is as shown by the arrow in FIG. 15 , flowing from the gate of the anti-fuse transistor Mf to the source/drain of the selection transistor Mc (i.e., positive reading).

In combination with FIG. 16 and FIG. 17 , in case g, the gate voltage Vfg of the anti-fuse transistor Mf is 0V, the source/drain voltage Vba of the selection transistor Mc is 0-3V, and the gate voltage Vxg of the selection transistor Mc is 0V (i.e., the selection transistor Mc is in the off state); at this time, the current direction is as shown by the arrow in FIG. 16 , flowing from the source/drain of the selection transistor Mc to the gate of the anti-fuse transistor Mf (i.e., reverse reading). In case h, the gate voltage Vfg of the anti-fuse transistor Mf is 0V, the source/drain voltage Vba of the selection transistor Mc is 0-3V, and the gate voltage Vxg of the selection transistor Mc is 1V (i.e., the selection transistor Mc is in the on state); at this time, the current direction is as shown by the arrow in FIG. 13 , flowing from the source/drain of the selection transistor Mc to the gate of the anti-fuse transistor Mf (i.e., reverse reading).

Further, in combination with FIG. 14 and FIG. 17 , in each case, the current in the anti-fuse transistor and the selection transistor increases as the voltage difference between the gate of the anti-fuse transistor and the source/drain of the selection transistor increases.

On the one hand, the current of the forward reading is greater than the current of the reverse reading, that is, the currents in cases a, b, e and f are greater than the currents in cases c, d, g and h, respectively. This shows that the embodiments of the present disclosure can effectively reduce the reverse reading current. The current, that is, the direction of the current is difficult to be directed from the source or drain of the anti-fuse transistor to the gate of the anti-fuse transistor, so that leakage will not be generated between the anti-fuse control lines.

On the other hand, the current after the anti-fuse transistor has been broken down is greater than the current when the anti-fuse transistor is not broken down, that is, the currents in cases e, f, g and h are greater than the currents in cases a, b, c and d, respectively.

On the other hand, the current when the selection transistor is in the on state is greater than the current when the selection transistor is in the off state, that is, the currents in cases b, d, f and h are greater than the currents in cases a, c, e and g, respectively.

It can be understood that the current in each case shown in FIG. 14 does not exceed 1.00E-08A (i.e., 1.00 times 10 to the -8th power ampere), and the current in each case shown in FIG. 17 does not exceed 1.00E-04A (i.e., 1.00 times 10 to the -4th power ampere). In other words, the embodiment of the present disclosure can control the current in the anti-fuse unit within a smaller range, thereby reducing power consumption.

It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Industrial Applicability

The disclosed embodiments provide an anti-fuse unit and an anti-fuse array. The anti-fuse unit includes: an active region and at least one anti-fuse gate. The active region extends along a first direction; at least one anti-fuse gate extends along a second direction; at least one anti-fuse gate contacts the top of the active region, covers two adjacent boundaries of the active region, and is close to a target corner of the active region; the target corner is the intersection of the two adjacent boundaries.

The anti-fuse gate in the embodiment of the present disclosure covers two adjacent boundaries of the active area and is close to the target corners corresponding to the two adjacent boundaries. In this way, the contact area between the anti-fuse gate and the active area can be reduced, thereby reducing the uncertainty of the breakdown position and the probability of false breakdown, thereby improving the reliability of the anti-fuse transistor.

Claims

An anti-fuse unit (80), comprising: an active region (10) and at least one anti-fuse gate (20);

The active region (10) extends along a first direction; at least one anti-fuse gate (20) extends along a second direction;

At least one of the anti-fuse gates (20) contacts the top of the active area (10), covers two adjacent boundaries of the active area (10), and is close to a target corner of the active area (10); the target corner is the intersection of the two adjacent boundaries.
The anti-fuse unit (80) according to claim 1, wherein the anti-fuse unit (80) further comprises: at least one select gate (30);

At least one of the selection gates (30) extends along the second direction;

At least one of the selection gates (30) contacts the top of the active region (10) and is located on a side of at least one of the anti-fuse gates (20) away from the target corner.
The anti-fuse unit (80) according to claim 1 or 2, wherein the anti-fuse gate (20) comprises: a first anti-fuse gate (201) and a second anti-fuse gate (202);

The first anti-fuse gate (201) and part of the active area (10) on its side form a first anti-fuse transistor; the second anti-fuse gate (202) and part of the active area (10) on its side form a second anti-fuse transistor; the first anti-fuse transistor and the second anti-fuse transistor are centrally symmetrically distributed on the active area (10);

The selection gate (30) comprises: a first selection gate (301) and a second selection gate (302);

The first selection gate (301) and part of the active area (10) on its side form a first selection transistor; the second selection gate (302) and part of the active area (10) on its side form a second selection transistor; the first selection transistor and the second selection transistor are centrally symmetrically distributed on the active area (10).
The anti-fuse unit (80) according to claim 3, wherein the anti-fuse unit (80) further comprises: an address line contact structure (40);

The address line contact structure (40) contacts the top of the active area (10) and is located between the first selection gate (301) and the second selection gate (302).
The anti-fuse unit (80) according to claim 2, wherein the active region (10) comprises: a first doping region (11) and a second doping region (12);

The first doping region (11) and the second doping region (12) are respectively located on opposite sides of the selection gate (30); the first doping region (11) is located in a region between the anti-fuse gate (20) and the selection gate (30);

The first doping region (11) and the second doping region (12) have the same doping type.
The anti-fuse unit (80) according to claim 5, wherein the active region (10) further comprises: a third doping region (13) and a fourth doping region (14);

The third doping region (13) and the fourth doping region (14) are both located below the selection gate (30);

The third doping region (13) contacts the selection gate (30) and the first doping region (11) respectively; the third doping region (13) and the first doping region (11) have the same doping type, and the doping concentration of the third doping region (13) is less than the doping concentration of the first doping region (11);

The fourth doping region (14) contacts the selection gate (30) and the second doping region (12) respectively; the fourth doping region (14) and the second doping region (12) have the same doping type, and the doping concentration of the fourth doping region (14) is less than the doping concentration of the second doping region (12).
The anti-fuse unit (80) according to claim 5 or 6, wherein:

The portion of the active region (10) located below the anti-fuse gate (20) has the same The doped regions (11) have different doping types.
The anti-fuse unit (80) according to any one of claims 1 to 7, wherein the first direction and the second direction are both perpendicular to the vertical direction, and the first direction and the second direction are not perpendicular to each other.
An antifuse array (90), comprising: a plurality of antifuse units (80) as claimed in claim 3 or 4;

The plurality of anti-fuse units (80) form an array of M rows and N columns, wherein the anti-fuse units (80) in each row are arranged along the second direction, and the anti-fuse units (80) in each column are arranged along the first direction; and both M and N are even numbers greater than 0.
The antifuse array (90) according to claim 9, wherein the antifuse array (90) further comprises: M memory address lines; the M memory address lines all extend along the second direction;

Each of the memory address lines contacts the active area (10) in each row of the anti-fuse unit (80); each of the memory address lines passes through a central symmetrical point on the active area (10) it contacts.
The antifuse array (90) according to claim 10, wherein:

The anti-fuse gates (20) and the selection gates (30) in the plurality of anti-fuse units (80) and the M storage body address lines are all located in the first layer in the vertical direction.
The antifuse array (90) according to any one of claims 9 to 11, wherein the antifuse array (90) further comprises: N/2+1 antifuse control lines; the N/2+1 antifuse control lines all extend along the first direction;

Two columns of anti-fuse units (80) are arranged between two adjacent anti-fuse control lines;

Each of the anti-fuse control lines is electrically connected to the anti-fuse gates (20) in each adjacent column of the anti-fuse units (80).
The antifuse array (90) of claim 12, wherein:

The two anti-fuse units (80) located between two adjacent anti-fuse control lines and in the same row have their first selection gates (301) connected as a whole, their second selection gates (302) connected as a whole, their first anti-fuse gates (201) not connected to each other, and their second anti-fuse gates (202) not connected to each other.
The antifuse array (90) according to any one of claims 9 to 13, wherein the antifuse array (90) further comprises: N transistor control lines;

The N transistor control lines are distributed one by one above the N columns of anti-fuse units (80).
The antifuse array (90) of claim 14, wherein:

The 2i-1th transistor control line is electrically connected to the first selection gate (301) in the anti-fuse unit (80) in the 2i-1th column corresponding thereto;

The 2i-th transistor control line is electrically connected to the second selection gate (302) in the corresponding 2i-th column of the anti-fuse unit (80); i is greater than or equal to 1 and less than or equal to N/2.
The antifuse array (90) according to claim 14 or 15, wherein N/2+1 of the antifuse control lines and the N of the transistor control lines are all located in the second layer in the vertical direction.