WO2024077914A1 - 多核处理器的核间通信系统、方法、设备及存储介质 - Google Patents

多核处理器的核间通信系统、方法、设备及存储介质 Download PDF

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Publication number
WO2024077914A1
WO2024077914A1 PCT/CN2023/088744 CN2023088744W WO2024077914A1 WO 2024077914 A1 WO2024077914 A1 WO 2024077914A1 CN 2023088744 W CN2023088744 W CN 2023088744W WO 2024077914 A1 WO2024077914 A1 WO 2024077914A1
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descriptor
inter
queue
memory
core
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PCT/CN2023/088744
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English (en)
French (fr)
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徐曼成
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深圳市中兴微电子技术有限公司
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Publication of WO2024077914A1 publication Critical patent/WO2024077914A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of processor technology, and in particular to an inter-core communication system, method, device and storage medium of a multi-core processor.
  • the inter-core communication technology of multi-core processors is generally based on the mailbox module to achieve interaction, but this mailbox module mainly provides an interrupt-based communication service to the CPU, and the CPU participates in the interaction. That is, this inter-core communication technology requires the CPU to participate in operations such as message copying, queue space maintenance, and message channel access arbitration, which increases thread occupancy and reduces CPU performance.
  • the main purpose of this application is to provide an inter-core communication system, method, device and storage medium for a multi-core processor, aiming to solve the technical problem of how to reduce CPU occupancy during inter-core communication and improve CPU performance.
  • an inter-core communication method system of a multi-core processor including an inter-core communication device connected to a plurality of systems, the plurality of systems including a first system and a second system, the inter-core communication device including:
  • a memory management module configured to receive a descriptor application instruction sent by the first system, and determine a descriptor pointer corresponding to the descriptor application instruction, wherein the first system stores the data to be transmitted in a memory corresponding to the descriptor pointer;
  • a queue management module configured to enqueue the descriptor pointer into a designated queue after receiving an enqueue application sent by the first system
  • the interrupt module is used to interrupt the queue after the number of queues corresponding to the specified queue reaches a preset threshold.
  • the descriptor in the designated queue is dequeued through the interrupt service program of the second system, wherein the second system reads the data to be transmitted in the memory corresponding to the descriptor instruction after dequeuing.
  • the present application also provides an inter-core communication method of a multi-core processor, which is applied to the inter-core communication system of the multi-core processor as described above, including:
  • the descriptor in the designated queue is dequeued through the interrupt service program of the second system, wherein the second system reads the data to be transmitted in the memory corresponding to the descriptor instruction after dequeuing.
  • the present application also provides an inter-core communication device of a multi-core processor
  • the inter-core communication device of the multi-core processor includes a memory, a processor, and an inter-core communication program of the multi-core processor stored in the memory and executable on the processor, and when the inter-core communication program of the multi-core processor is executed by the processor, the steps of the inter-core communication method of the multi-core processor as described above are implemented.
  • the present application also provides a storage medium, including a computer-readable storage medium, on which is stored a multi-core communication program for a multi-core processor, and when the inter-core communication program for a multi-core processor is executed by the processor, the steps of the inter-core communication method for a multi-core processor as described above are implemented.
  • the present application provides an inter-core communication device connected to multiple systems, and entrusts the management of message data and message space of each system during inter-core communication to a memory management module and a queue management module for processing.
  • the application of descriptor pointers is completed through the memory management module, and the queue management corresponding to the descriptor pointer is completed through the queue management module.
  • FIG1 is a schematic diagram of a terminal ⁇ device structure of a hardware operating environment involved in an embodiment of the present application
  • FIG2 is a schematic diagram of the overall framework of the inter-core communication system of the multi-core processor of the present application.
  • FIG. 3 is a diagram showing the internal structure of the inter-core communication device in the inter-core communication system of the multi-core processor of the present application. intention;
  • FIG4 is a schematic diagram of the internal structure of a memory management module in the inter-core communication system of the multi-core processor of the present application;
  • FIG5 is a schematic diagram of the internal structure of a queue management module in the inter-core communication system of the multi-core processor of the present application;
  • FIG6 is a schematic diagram of a flow chart of inter-core communication in an inter-core communication system of a multi-core processor of the present application
  • FIG. 7 is a schematic diagram of a process flow of multiple systems simultaneously accessing an inter-core communication device in an inter-core communication system of a multi-core processor of the present application;
  • FIG8 is a schematic diagram of a queue alarm interruption in an inter-core communication system of a multi-core processor of the present application
  • FIG9 is a flow chart of the inter-core communication method of the multi-core processor of the present application.
  • FIG. 1 is a schematic diagram of the terminal structure of the hardware operating environment involved in the embodiment of the present application.
  • the terminal in the embodiment of the present application is an inter-core communication device of a multi-core processor.
  • the terminal may include: a processor 1001, such as a CPU, a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002.
  • the communication bus 1002 is used to realize the connection and communication between these components.
  • the user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the user interface 1003 may also include a standard wired interface and a wireless interface.
  • the network interface 1004 may include a standard wired interface and a wireless interface (such as a WI-FI interface).
  • the memory 1005 may be a high-speed memory or a stable memory (non-volatile memory), such as a disk memory.
  • the memory 1005 may also be a storage device independent of the aforementioned processor 1001.
  • the terminal may also include a camera, an RF (Radio Frequency) circuit, a sensor, an audio circuit, a WiFi module, and the like.
  • the sensors include light sensors, motion sensors, and other sensors.
  • the light sensor may include an ambient light sensor and a proximity sensor, wherein the ambient light sensor may adjust the brightness of the display screen according to the brightness of the ambient light, and the proximity sensor may turn off the display screen and/or backlight when the terminal device is moved to the ear.
  • the terminal device may also be configured with other sensors such as a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, etc., which will not be repeated here.
  • terminal structure shown in FIG. 1 does not limit the terminal and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.
  • the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module, and an inter-core communication program of a multi-core processor.
  • the network interface 1004 is mainly used to connect to the backend server and perform data communication with the backend server;
  • the user interface 1003 is mainly used to connect to the client (user end) and perform data communication with the client;
  • the processor 1001 can be used to call the inter-core communication program of the multi-core processor stored in the memory 1005, and perform the following operations:
  • the descriptor in the designated queue is dequeued through the interrupt service program of the second system, wherein the second system reads the data to be transmitted in the memory corresponding to the descriptor instruction after dequeuing.
  • the present application provides an inter-core communication system of a multi-core processor.
  • the inter-core communication system of the multi-core processor includes an inter-core communication device 300 connected to a plurality of systems, the plurality of systems including a first system 100 and a second system 200, and the inter-core communication device 300 includes:
  • a memory management module 310 is used to receive a descriptor application instruction sent by the first system, and determine a descriptor pointer corresponding to the descriptor application instruction, wherein the first system stores the data to be transmitted in a memory corresponding to the descriptor pointer;
  • the queue management module 320 is used to enqueue the descriptor pointer into a designated queue after receiving the enqueue application sent by the first system;
  • the interrupt module 330 is used to dequeue the descriptor in the designated queue through the interrupt service program of the second system after the number of enqueue times corresponding to the designated queue reaches a preset threshold, wherein the second system reads the data to be transmitted in the memory corresponding to the descriptor instruction after dequeueing.
  • the CPU when performing inter-core communication, it can be implemented based on a mechanism of shared memory plus interrupt service, and the inter-core communication device 300 mainly includes a memory management module 310 and a queue management module 320, and both the memory management module 310 and the queue management module 320 are provided with an on-chip buffer pool, which actively accesses the off-chip DDR (Double Data Rate) through the AXI (Advanced eXtensible Interface, bus protocol) bus interface to read and write memory descriptor pointers, and the CPU configures the memory management module 310 and the queue management module 320 through the AXI bus interface.
  • DDR Double Data Rate
  • AXI Advanced eXtensible Interface, bus protocol
  • the memory management module 310 can manage the descriptor in a FIFO (First Input First Output) manner.
  • the memory management module 310 is used to obtain the descriptor pointer, and provides the CPU with an application and release interface for the descriptor pointer.
  • the queue management module 320 manages the descriptor pointer in a first-in-first-out queue manner, and provides the CPU with an entry and exit interface for the descriptor pointer. Therefore, in this embodiment, a CPU core in communication can obtain the descriptor pointer through the memory management module 310 and enter the queue into the queue management module 320, and another CPU core in communication can obtain the descriptor pointer by exiting the queue from the queue management module 320, so as to read the communication data according to the descriptor pointer.
  • a CPU core in communication can obtain the descriptor pointer through the memory management module 310 and enter the queue into the queue management module 320, and another CPU core in communication can obtain the descriptor pointer by exiting the queue from the queue management module
  • module initialization and interrupt registration Before performing inter-core communication of a multi-core processor, it is necessary to configure the inter-core communication system of the multi-core processor, which may include two parts: module initialization and interrupt registration.
  • module initialization part if two systems are set in the inter-core communication system of the multi-core processor, namely the first system 100 and the second system 200, and the first system 100 has one core, CPU0, and the second system 200 has one core, CPU1. Therefore, each module can be initialized and configured by CPU0 or CPU1.
  • CPU0 can access the control register of the memory management module 310 through the AXI_Slave interface, configure the number of different types of buffer blocks into the register, and thereby calculate the DDR memory size occupied by the buffer block, CPU0 allocates the memory segment and configures the start address and end address into the control register.
  • CPU0 accesses the control register of the queue management module 320 through the AXI_Slave interface, configures the number of queue elements of each queue into the register of this module, and then calculates the DDR memory size that the queue management module 320 needs to manage according to the product of the number of queues, the number of queue elements in each queue, and the size of the queue elements.
  • CPU0 configures the starting address and the ending address of the memory into the module control register.
  • the initialization configuration of the memory management module 310 and the queue management module 320 is completed.
  • the memory application interface and memory release interface of the memory management module 310 both have abnormal interrupt sources.
  • the descriptor application and release abnormal interrupt sources are enabled and configured (that is, the configuration function can be performed); each queue of the queue management module 320 has an entry application interrupt source, an exit application abnormal interrupt source and a queue alarm interrupt source.
  • the alarm depth of the queue alarm interrupt is also configured.
  • CPU0 will trigger an alarm interrupt after entering the queue No. 0.
  • This interrupt can be called a queue non-empty interrupt; when CPU0 configures No. 0
  • the alarm interrupt will be triggered only after CPU0 enters the queue 0 n times.
  • This interrupt can be called a queue full interrupt.
  • the interrupt status can be cleared by configuring the relevant registers.
  • CPU1 registers the alarm interrupt of the specified queue. When the number of times CPU0 enters the queue reaches the alarm depth, the alarm interrupt is triggered and enters the interrupt service program of CPU1. Among them, the triggering of each interrupt service process in this embodiment is realized by the interrupt module 330.
  • the subsequent inter-core communication operation can be performed.
  • the descriptor enqueue operation can be performed. That is, CPU0 can access the memory management module 310 according to the data size of the data to be transmitted that the first system 100 needs to transmit, so as to send a descriptor application instruction to the memory management module 310.
  • the memory management module 310 determines whether the current memory is sufficient, and when the memory is sufficient, determines the descriptor pointer corresponding to the descriptor application instruction, and feeds back the information of the successful application of the descriptor pointer to the CPU0 in the first system 100.
  • CPU0 stores the data to be transmitted in the memory pointed to by the descriptor pointer.
  • the memory management module 310 determines that the current memory is insufficient or there are other abnormalities, it will determine that the application of the descriptor pointer fails, and when it is determined that the application fails, and after the descriptor application abnormal interrupt is registered in advance, it will enter the application abnormal interrupt service program of CPU0 to perform interrupt service processing, that is, at this time, the interrupt module 330 will be triggered.
  • the first system 100 After the first system 100 applies for the descriptor pointer, it will perform a descriptor enqueue operation, which may be that CPU0 accesses the descriptor enqueue register of the queue management module 320 to enqueue the descriptor pointer into the designated queue of the queue management module 320. For example, the first system 100 sends an enqueue application to the queue management module 320. Similarly, if the enqueue exception interrupt is registered, the enqueue exception interrupt service routine of CPU0 will be entered when the enqueue fails.
  • a descriptor enqueue operation which may be that CPU0 accesses the descriptor enqueue register of the queue management module 320 to enqueue the descriptor pointer into the designated queue of the queue management module 320.
  • the first system 100 sends an enqueue application to the queue management module 320.
  • the enqueue exception interrupt if the enqueue exception interrupt
  • the interrupt module 330 When the descriptor pointer is enqueued to the specified queue, the interrupt module 330 will detect the queue depth of the specified queue, and trigger the alarm interrupt of the specified queue after the number of enqueuing times reaches a preset threshold (an arbitrary threshold set in advance by the user).
  • a preset threshold an arbitrary threshold set in advance by the user.
  • CPU1 in the second system 200 registers the alarm interrupt of this queue, and therefore will enter the interrupt service program of CPU1. Then the descriptor is dequeued.
  • CPU1 obtains the queue depth of the specified queue, that is, the number of data transmitted by CPU0, by accessing the queue management module 320, and dequeues the descriptor pointer according to the queue depth, that is, all descriptor pointers in the specified queue can be dequeued in sequence. Finally, the descriptor release stage is entered. At this time, after CPU1 obtains the descriptor pointer, it can read the data of CPU0 from the memory pointed to by the descriptor pointer.
  • CPU1 After CPU1 has finished using the memory space, it writes the descriptor pointer to the descriptor release register and returns the descriptor pointer to the memory management module 310, thereby completing the inter-core data interaction process between CPU0 and CPU1 in the multi-core heterogeneous platform, that is, completing the inter-core data interaction between the first system 100 and the second system 200.
  • the module initialization configuration is first performed, and the memory management module and the queue management module can be configured by CPU0 in the first system 100, and the interruption is registered and enabled by CPU0, and the configuration is performed by CPU1, and the memory application is performed by CPU0, and the memory management module buffers the application operation. If not, an abnormal interruption is determined. If so, CPU0 obtains a memory descriptor pointer, CPU0 writes data to the memory, and CPU0 applies for entry into the queue. Enqueue operation is performed through the queue management module. If not, an abnormal interruption is performed.
  • Dequeue operation is performed through the queue management module, if not, an abnormal interruption is performed. If so, CPU1 obtains a memory descriptor pointer, CPU1 performs memory release, and the memory management module buffers the release operation. If not, an abnormal interruption is performed, and if so, the next inter-core data communication is performed.
  • the management of message data and message space during inter-core communication between various systems is handed over to the memory management module and the queue management module for processing, and the application of descriptor pointers is completed by the memory management module, and the queue management corresponding to the descriptor pointer is completed by the queue management module, without the need for the system's own CPU to process it.
  • the memory management module 310 includes a first bus interface 311, a first register 312, a buffer 313 and an on-chip memory 314.
  • the memory management module 310 is connected to each of the systems and the off-chip memory 400 through the first bus interface 311.
  • the first register 312 is used to determine the descriptor pointer corresponding to the descriptor application instruction after receiving the descriptor pointer application instruction sent by the first system 100, and store the descriptor pointer in the on-chip memory 314;
  • the buffer 313 is used to read the descriptor pointers in the off-chip memory 400 to the on-chip memory 314 after the number of descriptor pointers in the on-chip memory 314 is less than a preset number. 314 , and after the number of descriptor pointers in the on-chip memory 314 is greater than a preset number, read the descriptor pointers in the on-chip memory 314 to the off-chip memory 400 .
  • the first bus interface 311 in the memory management module 310 may include two first bus interfaces 311 such as two AXI bus interfaces.
  • the buffer 313 may be a FIFO buffer, and an on-chip memory structure of the on-chip memory 314.
  • the two AXI bus interfaces may include an AXI Slave interface and an AXI Master interface.
  • the AXI Slave interface is used for CPU0 to read and write registers of the memory management module 310
  • the AXI Master interface is used for the memory management module 310 to actively access the off-chip memory 400.
  • the memory management module 310 manages the descriptor pointers in a secondary storage manner, that is, a part of the descriptor pointers are stored in the on-chip memory 314, and the other part is stored in the off-chip memory 400.
  • the FIFO buffer is used to control the number of descriptor pointers in the on-chip memory.
  • the FIFO controller When the number of descriptor pointers in the on-chip RAM is less than the preset number (an arbitrary number set in advance by the user), the FIFO controller will access the off-chip memory 400 through the AXI_Master interface, and read part of the descriptor pointers from it into the on-chip memory 314; on the contrary, when the number of descriptor pointers in the on-chip memory 314 exceeds the preset number, the FIFO controller will write the excess descriptor pointers to the off-chip memory 400.
  • the preset number an arbitrary number set in advance by the user
  • the first system 100 and the second system 200 can apply for the descriptor pointer through the first register 312 and store the descriptor pointer through the buffer 313 when performing inter-core communication, so that the first system can store the data to be transmitted in the memory corresponding to the descriptor pointer, thereby ensuring the effective inter-core communication.
  • the first register 312 includes:
  • the control register 3121 is used to determine the descriptor pointer corresponding to the descriptor application instruction after receiving the descriptor pointer application instruction sent by the first system 100, and store the descriptor pointer in the on-chip memory 314;
  • a descriptor application register 3122 used to provide a descriptor pointer application interface to the first system 100;
  • a descriptor release register 3123 used to provide a release interface of a descriptor pointer to the first system 100;
  • the statistics register 3124 is used to count the number of operations of the descriptor pointer.
  • control register 3121 is used for the CPU to configure the memory management module 310;
  • descriptor application register 3122 and the descriptor release register 3123 are used to provide the CPU with a memory descriptor application and release interface;
  • the statistical register 3124 is used to count the number of descriptor operations.
  • the first register 312 is divided into multiple registers according to different functions, including a control register 3121, a descriptor application register 3122, a descriptor release register 3123 and a statistical register 3124, so that the first system 100 can sequentially apply for descriptor pointers in the memory management module 310, so as to perform subsequent inter-core communication operations according to the descriptor pointers.
  • the queue management module 320 includes a second bus interface 321, a second register 322, a queue controller 323 and an on-chip memory 314, and the queue management module 320 is connected to each of the systems and the off-chip memory 400 via the second bus interface 321.
  • the second register 322 is used to determine the designated queue corresponding to the descriptor pointer through the queue controller 323 after receiving the queue entry application sent by the first system 100, and to enqueue the descriptor pointer to the designated queue;
  • the queue controller 323 is used to read the descriptor pointer in the off-chip memory 400 after the descriptor pointer in the on-chip memory 314 is less than a preset number.
  • the second bus interface 321 in the queue management module 320 may also include two types, and may be two types of AXI bus interfaces.
  • the two AXI bus interfaces may include an AXI Slave interface and an AXI Master interface.
  • the AXI Slave interface is used by CPU0 to read and write registers of the queue management module 320
  • the AXI Master interface is used by the queue management module 320 to actively access the off-chip memory 400.
  • the structure of the queue management module 320 in this embodiment is similar to the structure of the memory management module 310.
  • the descriptor pointers in the queue are stored in the on-chip memory 314, and are stored in a head-to-tail manner.
  • the queue controller 323 will maintain the number of descriptor pointers corresponding to each queue in the on-chip memory 314, and perform queue entry and dequeue operations on the descriptor pointers corresponding to each queue in the on-chip memory 314 in a first-in, first-out manner.
  • the descriptor pointer of the specified queue in the on-chip memory 314 is less than the preset number (an arbitrary number set in advance by the user)
  • the descriptor pointer in the off-chip memory 400 will be actively accessed through the AXI Master interface to read it into the on-chip memory.
  • the descriptor enqueue and dequeue registers are used to provide the CPU with the enqueue and dequeue interface of the memory descriptor, and the statistical register is used to count the number of queue dequeues and enqueues.
  • the second register 322 in the queue management module 320 is similar in structure to the first register 312 in the memory management module 310, and also includes a control register, a descriptor enqueue register, and a memory management module 310. registers, descriptor dequeue registers, and statistics registers.
  • the queue entry operation can be implemented by accessing the second register 322 in the queue management module 320. After receiving the queue entry application, the second register will first determine the designated queue corresponding to the descriptor pointer. If the designated queue cannot be determined, the queue entry exception interrupt is registered, and when the queue entry fails, the queue entry exception interrupt service program of CPU0 in the first system 100 will be entered. If the designated queue can be determined, the descriptor pointer will be enqueued to the designated queue.
  • a second bus interface 321, a second register 322, a queue controller 323 and an on-chip memory 314 are set in the queue management module 320, so that after the first system 100 applies for the descriptor pointer, it can be sequentially stored in the designated queue, so that the subsequent second system 200 can extract it from the designated queue, thereby completing the inter-core communication operation.
  • the inter-core communication device 300 further includes a bus interface module 340 , through which the memory management module 310 and the queue management module 320 are connected to each of the systems.
  • the bus interface module 340 may be an AXI Slave module and an AXI Master module, and is respectively connected to the AXI Slave interface in the memory management module 310 and the AXI Slave interface in the queue management module 320 through the AXI Slave module, and is respectively connected to the AXI Master interface in the memory management module 310 and the AXI Master interface in the queue management module 320 through the AXI Master module.
  • the AXI Slave module and the AXI Master module are connected to each system through an externally set AXI system bus, thereby realizing the connection between each module and each system in this embodiment.
  • a bus interface module 340 is further provided in the inter-core communication device, and a connection between an external system and the inter-core communication device 300 is established through the bus interface module 340, thereby ensuring the normal progress of subsequent inter-core communication.
  • the inter-core communication device 300 further includes: an arbitration module 350, wherein the arbitration module 350 is respectively connected to the memory management module 310 and the queue management module 320, and wherein the arbitration module 350 is used to perform access arbitration on the access of each of the systems according to a preset communication order when it is detected that multiple systems simultaneously access the inter-core communication device 300, and respond to the access of each of the systems in turn.
  • an arbitration module 350 is respectively connected to the memory management module 310 and the queue management module 320, and wherein the arbitration module 350 is used to perform access arbitration on the access of each of the systems according to a preset communication order when it is detected that multiple systems simultaneously access the inter-core communication device 300, and respond to the access of each of the systems in turn.
  • the arbitration module 350 responds to the access request of CPU0 first in a serial access manner according to the pre-set settings, and responds to the access request of CPU1 after the memory management module 310 successfully allocates the buffer block descriptor of the corresponding size.
  • the workflow of the arbitration module 350 is the same as that of the above-mentioned multi-core memory application.
  • the arbitration module 350 is connected to the memory management module 310 and the queue management module 320 respectively
  • the interrupt module 330 is connected to the memory management module 310 and the queue management module 320 respectively
  • the memory management module 310 and the queue management module 320 are both connected to the bus interface module 340, wherein the bus interface module 340 includes an AXI Slave module and an AXI Master module.
  • the memory application interface of buffer block 0 will be determined first, and an application interrupt will be applied through the arbitration module. If it is determined that CPU0 applies for memory first, the memory management module will respond to the memory application of CPU0, and then the memory management module will respond to the memory application of CPU1. In the queue management module, if CPU0 applies for queue 0 and CPU1 applies for queue 0 at the same time, the queue 0 application interface will be determined first, and then arbitration will be applied through the arbitration module, and then the queue management module will respond to the queue application of CPU0, and after the response is completed, the queue management module will respond to the queue application of CPU1.
  • an arbitration module is also provided in the inter-core communication device so that when multiple systems access the inter-core communication device at the same time, access arbitration can be performed through the arbitration module according to a communication sequence set in advance, thereby ensuring effective access of the system to the inter-core communication device.
  • the interrupt module 330 is further configured to perform an abnormal interrupt after an abnormality occurs in the memory management module 310 , and to perform an abnormal interrupt after an abnormality occurs in the queue management module 320 .
  • each interrupt in the interrupt module 330 may include an abnormal interrupt when applying for memory or releasing memory in the memory management module 310, an abnormal interrupt when applying for queue entry or dequeueing in the queue management module 320, and a queue non-empty alarm interrupt and a queue full load alarm interrupt.
  • the interrupt module 330 can also be used to perform an exception interrupt when an exception occurs in the memory management module 310 and the queue management module 320, thereby ensuring the effective inter-core communication and avoiding the occurrence of exceptions that affect the security of the inter-core communication system of the multi-core processor.
  • the present application provides an inter-core communication method for a multi-core processor.
  • the inter-core communication method for a multi-core processor is applied to the inter-core communication system of the multi-core processor in any of the above embodiments, including:
  • Step S10 receiving a descriptor application instruction sent by the first system, and determining a descriptor pointer corresponding to the descriptor application instruction, wherein the first system stores the data to be transmitted in a memory corresponding to the descriptor pointer;
  • Step S20 after receiving the queue application sent by the first system, the descriptor pointer is queued to a designated queue;
  • Step S30 after the number of enqueues corresponding to the designated queue reaches a preset threshold, the descriptor in the designated queue is dequeued through the interrupt service program of the second system, wherein the second system reads the data to be transmitted in the memory corresponding to the descriptor instruction after dequeuing.
  • the process of implementing each step of the inter-core communication method of the multi-core processor can refer to the various embodiments of the inter-core communication system of the multi-core processor of the present application, and will not be repeated here.
  • the present application also provides an inter-core communication device for a multi-core processor, the inter-core communication device for a multi-core processor comprising: a memory, a processor, and an inter-core communication program for the multi-core processor stored on the memory; the processor is used to execute the inter-core communication program for the multi-core processor to implement the steps of each embodiment of the inter-core communication method for the multi-core processor described above.
  • the present application also provides a storage medium, which may be a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs may also be executed by one or more processors to implement the steps of each embodiment of the above-mentioned inter-core communication method of the multi-core processor.
  • the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM/memory, disk, CD) as described above, including a number of instructions for a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.
  • a storage medium such as ROM/memory, disk, CD
  • a terminal device which can be a mobile phone, computer, server, air conditioner, or network device, etc.

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Abstract

本申请公开了一种多核处理器的核间通信系统、方法、设备及存储介质，该系统包括：与多个系统连接的核间通信装置，多个系统包括第一系统和第二系统，核间通信装置包括：内存管理模块，用于接收第一系统发送的描述符申请指令，确定描述符申请指令对应的描述符指针，其中，第一系统将待传输数据存储至描述符指针对应的内存；队列管理模块，用于在接收到第一系统发送的入队申请之后，将描述符指针入队到指定队列；中断模块，用于在指定队列对应的入队次数达到预设阈值之后，通过第二系统的中断服务程序进行指定队列中的描述符出队，其中，第二系统读取出队后的描述符指令对应的内存中的待传输数据。

Description

多核处理器的核间通信系统、方法、设备及存储介质
相关申请
本申请要求于2022年10月11号申请的、申请号为202211263547.1的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及处理器技术领域，尤其涉及一种多核处理器的核间通信系统、方法、设备及存储介质。
背景技术
目前多核处理器的核间通信技术一般是基于mailbox(邮箱)信箱模块实现交互的，但是这个信箱模块主要是向CPU提供一个基于中断的通信服务，由CPU参与进行交互的，也就是这种核间通信技术，需要CPU参与消息的拷贝、队列空间的维护、消息通道访问仲裁等操作，增加了线程占用，降低了CPU的性能。
发明内容
本申请的主要目的在于提供一种多核处理器的核间通信系统、方法、设备及存储介质，旨在解决如何降低核间通信时的CPU占用，提高CPU的性能的技术问题。
为实现上述目的，本申请提供一种多核处理器的核间通信方法系统，包括与多个系统连接的核间通信装置，多个所述系统包括第一系统和第二系统，所述核间通信装置包括：
内存管理模块，用于接收所述第一系统发送的描述符申请指令，确定所述描述符申请指令对应的描述符指针，其中，所述第一系统将待传输数据存储至所述描述符指针对应的内存；
队列管理模块，用于在接收到所述第一系统发送的入队申请之后，将所述描述符指针入队到指定队列；
中断模块，用于在所述指定队列对应的入队次数达到预设阈值之后，通 过所述第二系统的中断服务程序进行所述指定队列中的描述符出队，其中，所述第二系统读取出队后的所述描述符指令对应的内存中的待传输数据。
此外，为实现上述目的，本申请还提供一种多核处理器的核间通信方法，应用于如上述所述的多核处理器的核间通信系统，包括：
接收第一系统发送的描述符申请指令，确定所述描述符申请指令对应的描述符指针，其中，所述第一系统将待传输数据存储至所述描述符指针对应的内存；
在接收到所述第一系统发送的入队申请之后，将所述描述符指针入队到指定队列；
在所述指定队列对应的入队次数达到预设阈值之后，通过第二系统的中断服务程序进行所述指定队列中的描述符出队，其中，所述第二系统读取出队后的所述描述符指令对应的内存中的待传输数据。
此外，为实现上述目的，本申请还提供一种多核处理器的核间通信设备，多核处理器的核间通信设备包括存储器、处理器及存储在存储器上并可在处理器上运行的多核处理器的核间通信程序，多核处理器的核间通信程序被处理器执行时实现如上述的多核处理器的核间通信方法的步骤。
此外，为实现上述目的，本申请还提供一种存储介质，包括计算机可读存储介质，计算机可读存储介质上存储有多核处理器的核间通信程序，多核处理器的核间通信程序被处理器执行时实现如上述的多核处理器的核间通信方法的步骤。
本申请通过提供一种与多个系统连接的核间通信装置，并通过将各个系统进行核间通信时的消息数据与消息空间的管理交给内存管理模块和队列管理模块进行处理，并且是通过内存管理模块完成描述符指针的申请，通过队列管理模块完成描述符指针对应的队列管理，无需系统自身内部的CPU进行处理，从而在保障各个系统之间的数据正常传输的情况下，降低了核间通信时的CPU占用，提高了CPU的性能。
附图说明
图1是本申请实施例方案涉及的硬件运行环境的终端\装置结构示意图；
图2为本申请多核处理器的核间通信系统中的整体框架示意图；
图3为本申请多核处理器的核间通信系统中核间通信装置的内部结构示 意图；
图4为本申请多核处理器的核间通信系统中内存管理模块的内部结构示意图；
图5为本申请多核处理器的核间通信系统中队列管理模块的内部结构示意图；
图6为本申请多核处理器的核间通信系统中进行核间通信的流程示意图；
图7为本申请多核处理器的核间通信系统中多系统同时访问核间通信装置的流程示意图；
图8为本申请多核处理器的核间通信系统中队列告警中断示意图；
图9为本申请多核处理器的核间通信方法的流程示意图。
附图标号说明：
本申请目的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
如图1所示，图1是本申请实施例方案涉及的硬件运行环境的终端结构示意图。
本申请实施例终端为多核处理器的核间通信设备。
如图1所示，该终端可以包括：处理器1001，例如CPU，网络接口1004，用户接口1003，存储器1005，通信总线1002。其中，通信总线1002用于实现这些组件之间的连接通信。用户接口1003可以包括显示屏(Display)、输入单元比如键盘(Keyboard)，用户接口1003还可以包括标准的有线接口、无线接口。网络接口1004可以包括标准的有线接口、无线接口(如WI-FI接口)。存储器1005可以是高速存储器，也可以是稳定的存储器(non-volatile memory)，例如磁盘存储器。存储器1005还可以是独立于前述处理器1001的存储装置。
在一些实施例中，终端还可以包括摄像头、RF(Radio Frequency，射频)电路，传感器、音频电路、WiFi模块等等。其中，传感器比如光传感器、运动传感器以及其他传感器。具体地，光传感器可包括环境光传感器及接近传感器，其中，环境光传感器可根据环境光线的明暗来调节显示屏的亮度，接近传感器可在终端设备移动到耳边时，关闭显示屏和/或背光。当然，终端设备还可配置陀螺仪、气压计、湿度计、温度计、红外线传感器等其他传感器，在此不再赘述。
本领域技术人员可以理解，图1中示出的终端结构并不构成对终端的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
如图1所示，作为一种计算机存储介质的存储器1005中可以包括操作系统、网络通信模块、用户接口模块以及多核处理器的核间通信程序。
在图1所示的终端中，网络接口1004主要用于连接后台服务器，与后台服务器进行数据通信；用户接口1003主要用于连接客户端(用户端)，与客户端进行数据通信；而处理器1001可以用于调用存储器1005中存储的多核处理器的核间通信程序，并执行以下操作：
接收第一系统发送的描述符申请指令，确定所述描述符申请指令对应的描述符指针，其中，所述第一系统将待传输数据存储至所述描述符指针对应的内存；
在接收到所述第一系统发送的入队申请之后，将所述描述符指针入队到指定队列；
在所述指定队列对应的入队次数达到预设阈值之后，通过第二系统的中断服务程序进行所述指定队列中的描述符出队，其中，所述第二系统读取出队后的所述描述符指令对应的内存中的待传输数据。
参照图2，本申请提供一种多核处理器的核间通信系统，在多核处理器的核间通信系统的第一实施例中，多核处理器的核间通信系统包括与多个系统连接的核间通信装置300，多个所述系统包括第一系统100和第二系统200，核间通信装置300包括：
内存管理模块310，用于接收所述第一系统发送的描述符申请指令，确定所述描述符申请指令对应的描述符指针，其中，所述第一系统将待传输数据存储至所述描述符指针对应的内存；
队列管理模块320，用于在接收到所述第一系统发送的入队申请之后，将所述描述符指针入队到指定队列；
中断模块330，用于在所述指定队列对应的入队次数达到预设阈值之后，通过所述第二系统的中断服务程序进行所述指定队列中的描述符出队，其中，所述第二系统读取出队后的所述描述符指令对应的内存中的待传输数据。
由于目前的核间通信方式，需要CPU参与消息的拷贝、队列空间的维护、消息通道访问仲裁等操作，增加了线程占用，降低了CPU的性能。因此，在本实施例中，可以在进行核间通信时，基于共享内存加中断服务的机制实现，并且在核间通信装置300中主要具备内存管理模块310和队列管理模块320，并且在内存管理模块310和队列管理模块320中都设置有片内缓冲池，通过AXI(Advanced eXtensible Interface，总线协议)总线接口主动访问片外DDR(Double Data Rate，双倍速率)以读写内存的描述符指针，同时CPU通过AXI总线接口对内存管理模块310与队列管理模块320进行配置。并且内存管理模块310可以以FIFO(First Input First Output，先进先出)的方式管理描 述符指针，并向CPU提供描述符指针的申请及释放接口。并且队列管理模块320是以先入先出的队列方式来管理描述符指针，并向CPU提供描述符指针的入队及出队接口。因此在本实施例中，通信的一核CPU可以是通过内存管理模块310后获取描述符指针，并入队到队列管理模块320，通信的另一核CPU可以是从队列管理模块320中出队获得该描述符指针，以根据描述符指针读取到通信数据。
并且在本实施例中，在进行多核处理器的核间通信之前，需要进行多核处理器的核间通信系统的配置，可以包括模块初始化和中断注册两部分。其中，在模块初始化部分，若在多核处理器的核间通信系统中设置了两个系统，即第一系统100和第二系统200，且第一系统100存在CPU0这一个核，第二系统200存在CPU1这一个核。因此可以通过CPU0或者CPU1对各个模块进行初始化配置。例如，若以CPU0对各个模块进行初始化配置，则可以是CPU0通过AXI_Slave接口访问内存管理模块310的控制寄存器，将不同类型缓冲块的数量配置到寄存器中，并由此计算出缓冲块所占用的DDR内存大小，CPU0分配该段内存并将起始地址及结束地址配置到控制寄存器中。CPU0通过AXI_Slave接口访问队列管理模块320的控制寄存器，将各队列的队列元素的数量配置到本模块寄存器中，然后根据队列数量、各队列中队列元素的数量、队列元素的大小三者乘积计算出队列管理模块320所需要管理的DDR内存大小，CPU0分配该段内存后将起内存的始地址及结束地址配置到模块控制寄存器中。CPU0将模块使能写入控制寄存器后，完成内存管理模块310与队列管理模块320的初始化配置。
在中断注册部分，内存管理模块310的内存申请接口及内存释放接口都具备异常中断源，在CPU0通过AXI_Slave接口对内存管理模块310进行初始化时，对描述符申请及释放异常中断源进行使能配置(即能够进行配置功能)；队列管理模块320的各个队列都具备入队申请中断源、出队申请异常中断源及队列告警中断源，在CPU0通过AXI_Slave接口对队列管理模块320进行初始化时，除了对异常中断源及告警中断源进行使能配置之外，还配置队列告警中断的告警深度。入队过程中的队列告警中断工作机制如附图2所示，当CPU0配置的0号队列告警深度n＝1时，CPU0向0号队列进行一次入队后就会触发告警中断，此中断可称为队列非空中断；当CPU0配置的0号 队列告警深度n>1时，CPU0向0号队列进行n次入队后才会触发告警中断，此中断可称为队列满中断。队列产生中断后，可通过配置相关寄存器进行中断状态的清除。本实施例中，CPU1注册指定队列的告警中断，当CPU0向该队列中入队次数达到告警深度时，便触发告警中断，进入CPU1的中断服务程序中。其中，本实施例中的各个中断服务流程的触发均通过中断模块330实现。
在本实施例中，当完成各个模块的模块初始化配置和中断注册后，就可以进行后续的核间通信操作。此时，可以进行描述符入队操作。也就是可以让CPU0根据第一系统100需要进行传输的待传输数据的数据大小来访问内存管理模块310，以向内存管理模块310发送描述符申请指令，内存管理模块310在接收到描述符申请指令后，进行判断当前内存是否充足，并在内存充足时，确定描述符申请指令对应的描述符指针，并将描述符指针申请成功的信息反馈至第一系统100中的CPU0。CPU0将待传输数据存储至描述符指针所指的内存中。但是当内存管理模块310判断当前内存不足，或存在其它异常时，则会确定申请描述符指针申请失败，并在确定申请失败时，且提前注册了描述符申请异常中断之后，会进入CPU0的申请异常中断服务程序，进行中断服务处理，即此时中断模块330会被触发。
当第一系统100申请到描述符指针后，会进行描述符入队操作，可以是CPU0通过访问队列管理模块320的描述符入队寄存器，将描述符指针入队到队列管理模块320的指定队列中。例如，第一系统100发送入队申请到队列管理模块320。同样，若注册了入队异常中断则入队失败时会进入CPU0的入队异常中断服务程序中。
当描述符指针入队到指定队列后，中断模块330会检测该指定队列的队列深度，并在入队次数达到预设阈值(用户提前设置的任意阈值)之后，触发该指定队列的告警中断。第二系统200中的CPU1注册此队列的告警中断，因此将进入CPU1的中断服务程序中。再进行描述符出队，CPU1在中断服务程序中，通过访问队列管理模块320获取该指定队列的队列深度，即CPU0传输的数据次数，并根据队列深度进行描述符指针的出队操作，即可以将指定队列中的所有描述符指针按照顺序进行出队。最后进入描述符释放阶段，此时，CPU1获得描述符指针后，即可从该描述符指针所指内存中读取到CPU0 写入的数据；CPU1使用完该内存空间后，将描述符指针写入描述符释放寄存器，将描述符指针再归还到内存管理模块310，即完成了多核异构平台中CPU0与CPU1的核间数据交互过程，也就是完成了第一系统100与第二系统200之间的核间数据交互。
例如，如图6所示，包括先进行模块初始化配置，可以通过第一系统100中的CPU0配置内存管理模块和队列管理模块中，通过CPU0注册中断并使能进行配置，通过CPU1注册中断并使能配置，通过CPU0进行内存申请，内存管理模块缓冲申请操作，若否，则确定异常中断。若是，则CPU0获得内存描述符指针，CPU0向内存中写入数据，CPU0进行入队申请。通过队列管理模块入队操作。若否，则异常中断，若是，检测队列深度是否达到告警深度，若否，队列深度+1，若是，队列触发告警中断，CPU1进行出队申请。通过队列管理模块出队操作，若否，则异常中断。若是，则CPU1获得内存描述符指针，CPU1进行内存释放，内存管理模块缓冲释放操作，若否，则进行异常中断，若是，则进行下一次的核间数据通信。
在本实施例中，通过将各个系统进行核间通信时的消息数据与消息空间的管理交给内存管理模块和队列管理模块进行处理，并且是通过内存管理模块完成描述符指针的申请，通过队列管理模块完成描述符指针对应的队列管理，无需系统自身内部的CPU进行处理，从而在保障各个系统之间的数据正常传输的情况下，降低了核间通信时的CPU占用，提高了CPU的性能。
基于上述第一实施例，提出了本申请多核处理器的核间通信系统的第二实施例，参照图4，在多核处理器的核间通信系统中，内存管理模块310包括第一总线接口311、第一寄存器312、缓冲器313和片内存储器314，所述内存管理模块310通过所述第一总线接口311与各所述系统以及片外存储器400连接，
所述第一寄存器312，用于在接收到所述第一系统100发送的描述符指针申请指令之后，确定所述描述符申请指令对应的描述符指针，并将所述描述符指针存储至所述片内存储器314；
所述缓冲器313，用于在所述片内存储器314中的描述符指针的数量小于预设数量之后，读取所述片外存储器400中的描述符指针到所述片内存储器 314，并在所述片内存储器314中的描述符指针的数量大于预设数量之后，读取所述片内存储器314中的描述符指针到所述片外存储器400。
在本实施例中，内存管理模块310中的第一总线接口311可以包括两种第一总线接口311如两种AXI总线接口。且缓冲器313可以是FIFO缓冲器，以及片内存储器314的片内存储器结构。其中，两种AXI总线接口可以包括AXI Slave接口和AXI Master接口。并且AXI Slave接口用于CPU0读写内存管理模块310的寄存器，AXI Master接口用于内存管理模块310主动访问片外存储器400。
并且，在本实施例中，内存管理模块310是以二级存储的方式管理描述符指针，即将一部分描述符指针存储至片内存储器314中，另一部分存储至片外存储器400中。FIFO缓冲器用于对片内存储器中描述符指针的数量进行控制。当片内RAM中的描述指针数量少于预设数量(用户提前设置的任意数量)时，FIFO控制器将通过AXI_Master接口访问片外存储器400，从中读取部分描述符指针到片内存储器314中；相反，当片内存储器314的描述符指针数量超过预设数量时，FIFO控制器会将多余的描述符指针写到片外存储器400中。
在本实施例中，通过在内存管理模块314设置第一总线接口311、第一寄存器312、缓冲器313和片内存储器314，以便第一系统100和第二系统200在进行核间通信时，能通过第一寄存器312进行描述符指针的申请，并通过缓冲器313进行描述符指针的存储，以便第一系统能将待传输数据存储至描述符指针对应的内存中，从而保障了核间通信的有效进行。
在一实施方式中，参照图4，第一寄存器312包括：
控制寄存器3121，用于在接收到所述第一系统100发送的描述符指针申请指令之后，确定所述描述符申请指令对应的描述符指针，并将所述描述符指针存储至所述片内存储器314；
描述符申请寄存器3122，用于向所述第一系统100提供描述符指针的申请接口；
描述符释放寄存器3123，用于向所述第一系统100提供描述符指针的释放接口；
统计寄存器3124，用于统计所述描述符指针的操作次数。
在本实施例中，控制寄存器3121，用于CPU对内存管理模块310的配置；描述符申请寄存器3122与描述符释放寄存器3123，用于向CPU提供内存描述符的申请与释放接口；统计寄存器3124，用于统计描述符操作次数。
在本实施例中，通过在第一寄存器312中按照不同的功能划分为多个寄存器，包括控制寄存器3121、描述符申请寄存器3122、描述符释放寄存器3123和统计寄存器3124，以便第一系统100能在内存管理模块310中顺序地申请到描述符指针，以便根据描述符指针进行后续的核间通信操作。
在一实施方式中，参照图5，队列管理模块320包括第二总线接口321、第二寄存器322、队列控制器323和片内存储器314，所述队列管理模块320通过所述第二总线接口321与各所述系统以及片外存储器400连接，
所述第二寄存器322，用于在接收到所述第一系统100发送的入队申请之后，通过所述队列控制器323确定所述描述符指针对应的指定队列，并将所述描述符指针入队到所述指定队列；
所述队列控制器323，用于在所述片内存储器314中的描述符指针小于预设数量之后，读取所述片外存储器400中的描述符指针。
在本实施例中，如图5所示，队列管理模块320中的第二总线接口321同样可以包括两种，且可以是两种AXI总线接口。其中，两种AXI总线接口可以包括AXI Slave接口和AXI Master接口。并且AXI Slave接口用于CPU0读写队列管理模块320的寄存器，AXI Master接口用于队列管理模块320主动访问片外内存400。并且本实施例中的队列管理模块320的结构与内存管理模块310的结构相似。是将队列中的描述符指针存储至片内存储器314中，并且是按照队头到队尾的方式进行存储。并且队列控制器323会对片内存储器314中每个队列对应的描述符指针的数量进行维护，且是以先入先出的方式对片内存储器314中每个队列对应的描述符指针进行入队、出队操作。当片内存储器314中指定队列的描述符指针小于预设数量(用户提前设置的任意数量)之后，将通过AXI Master接口主动访问片外存储器400中的描述符指针，以将其读取到片内存储器中。其中，描述符入队与出队寄存器，用于向CPU提供内存描述符的入队与出队接口，统计寄存器用于队列出队、入队次数的统计。其中，队列管理模块320中的第二寄存器322与内存管理模块310中的第一寄存器312的结构相似，同样包括控制寄存器、描述符入队寄存 器、描述符出队寄存器和统计寄存器。
并且在第一系统100进行入队操作时，可以通过访问队列管理模块320中的第二寄存器322来实现入队操作的，并且第二寄存器在接收到入队申请之后，会先确定描述符指针对应的指定队列，若无法确定到指定队列，注册了入队异常中断则入队失败时会进入第一系统100中CPU0的入队异常中断服务程序中。若能确定指定队列，则将描述符指针入队到指定队列中。
在本实施例中，通过在队列管理模块320中设置第二总线接口321、第二寄存器322、队列控制器323和片内存储器314，以便在第一系统100申请到描述符指针后，能够顺序地将其存储到指定队列中，方便后续第二系统200到指定队列中进行提取，从而完成核间通信的操作。
在一实施方式中，参照图3，核间通信装置300还包括：总线接口模块340，所述内存管理模块310和所述队列管理模块320通过所述总线接口模块340与各所述系统连接。
在本实施例中，总线接口模块340可以是AXI Slave模块和AXI Master模块，并且通过AXI Slave模块分别与内存管理模块310中的AXI Slave接口以及队列管理模块320中的AXI Slave接口连接，通过AXI Master模块分别与内存管理模块310中的AXI Master接口以及队列管理模块320中的AXI Master接口连接。并且AXI Slave模块和AXI Master模块通过外部设置的AXI系统总线与各个系统连接，从而实现本实施例中的各个模块与各个系统之间的连接。
在本实施例中，核间通信装置中还设置有总线接口模块340，通过总线接口模块340来建立外部系统和核间通信装置300的连接，从而保障了后续核间通信的正常进行。
在一实施方式中，参照图3，核间通信装置300还包括：仲裁模块350，所述仲裁模块350分别与所述内存管理模块310和所述队列管理模块320连接，所述仲裁模块350，用于在检测到多个系统同时访问所述核间通信装置300，根据预设的通信顺序对各所述系统的访问进行访问仲裁，并依次响应每个所述系统的访问。
在本实施例中，当出现多核同时访问内存管理模块与310队列管理模块320情形时，如图2所示，第一系统100中的CPU0与第二系统中的CPU1出 现同时申请大小相同的描述符情形，即同时访问内存管理模块的同一个内存申请接口，此时仲裁模块350按照预先的设定，按照串行访问的方式先响应CPU0的访问请求，待内存管理模块310成功分配相应大小缓冲块描述符后，再响应CPU1的访问请求。此外，对于多核通过相同内存释放接口进行描述符释放、以及通过相同出队接口进行队列元素入队、出队的情形，仲裁模块350的工作流程与上述多核内存申请时的情形相同。例如如图3所示，仲裁模块350分别与内存管理模块310和队列管理模块320连接，中断模块330分别与内存管理模块310和队列管理模块320连接，且内存管理模块310和队列管理模块320都与总线接口模块340连接，其中，总线接口模块340包括AXI Slave模块和AXI Master模块。
例如，如图7所示，包括CPU0进行缓冲块0的内存申请，同时CPU1进行缓冲块0的内存申请，则会先确定缓冲块0的内存申请接口，通过仲裁模块进行申请中断，若确定先进行CPU0的内存申请，则内存管理模块响应CPU0的内存申请，然后内存管理模块响应CPU1的内存申请。而在队列管理模块中，若同时存在CPU0进行队列0的入队申请，CPU1进行队列0的入队申请，则先确定队列0的入队申请接口，然后通过仲裁模块进行申请仲裁，然后队列管理模块响应CPU0的入队申请，并在响应完成后，队列管理模块响应CPU1的入队申请。
在本实施例中，通过在核间通信装置中还设置有仲裁模块，以便在多个系统同时访问核间通信装置时，能通过仲裁模块按照提前设置好的通信顺序进行访问仲裁，保障了系统访问核间通信装置的有效进行。
在一实施方式中，中断模块330，还用于在所述内存管理模块310存在异常之后，进行异常中断，在所述队列管理模块320存在异常之后，进行异常中断。
在本实施例中，中断模块330中的各个中断可以包括内存管理模块310中申请内存或释放内存时的异常中断，队列管理模块320中申请入队或申请出队时的异常中断，以及队列非空告警中断和队列满载告警中断。例如，如图8所示，CPU0配置队列告警深度＝1，CPU1注册队列告警中断并使能告警中断，在CPU0申请入队0号队列后，队列管理模块入队申请操作，若否，则通过中断模块触发错误中断，若是，CPU1获得内存描述符指针。
在本实施例中，中断模块330还可以用于在内存管理模块310和队列管理模块320存在异常时，进行异常中断，从而保障了核间通信的有效进行，避免出现异常，而影响到多核处理器的核间通信系统的安全性。
参照图9，本申请提供一种多核处理器的核间通信方法，在多核处理器的核间通信方法的第三实施例中，多核处理器的核间通信方法应用于上述任一实施例中的多核处理器的核间通信系统，包括：
步骤S10，接收第一系统发送的描述符申请指令，确定所述描述符申请指令对应的描述符指针，其中，所述第一系统将待传输数据存储至所述描述符指针对应的内存；
步骤S20，在接收到所述第一系统发送的入队申请之后，将所述描述符指针入队到指定队列；
步骤S30，在所述指定队列对应的入队次数达到预设阈值之后，通过第二系统的中断服务程序进行所述指定队列中的描述符出队，其中，所述第二系统读取出队后的所述描述符指令对应的内存中的待传输数据。
其中，多核处理器的核间通信方法的各个步骤实现的过程可参照本申请多核处理器的核间通信系统中的各个实施例，此处不再赘述。
此外，本申请还提供一种多核处理器的核间通信设备，所述多核处理器的核间通信设备包括：存储器、处理器及存储在所述存储器上的多核处理器的核间通信程序；所述处理器用于执行所述多核处理器的核间通信程序，以实现上述多核处理器的核间通信方法各实施例的步骤。
本申请还提供了一种存储介质，可以为计算机可读存储介质，所述计算机可读存储介质存储有一个或者一个以上程序，所述一个或者一个以上程序还可被一个或者一个以上的处理器执行以用于实现上述多核处理器的核间通信方法各实施例的步骤。
本申请计算机可读存储介质具体实施方式与上述多核处理器的核间通信方法各实施例基本相同，在此不再赘述。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者系统不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者系统所固有的要素。在没有更多限制的情况下， 由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者系统中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在如上所述的一个存储介质(如ROM/存储器、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
以上仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

  1. 一种多核处理器的核间通信系统，包括与多个系统连接的核间通信装置，多个所述系统包括第一系统和第二系统，所述核间通信装置包括：
    内存管理模块，设置为接收所述第一系统发送的描述符申请指令，确定所述描述符申请指令对应的描述符指针，其中，所述第一系统将待传输数据存储至所述描述符指针对应的内存；
    队列管理模块，设置为在接收到所述第一系统发送的入队申请之后，将所述描述符指针入队到指定队列；
    中断模块，设置为在所述指定队列对应的入队次数达到预设阈值之后，通过所述第二系统的中断服务程序进行所述指定队列中的描述符出队，其中，所述第二系统读取出队后的所述描述符指令对应的内存中的待传输数据。
  2. 如权利要求1所述的多核处理器的核间通信系统，其中，所述内存管理模块包括第一总线接口、第一寄存器、缓冲器和片内存储器，所述内存管理模块通过所述第一总线接口与各所述系统以及片外存储器连接，
    所述第一寄存器，设置为在接收到所述第一系统发送的描述符指针申请指令之后，确定所述描述符申请指令对应的描述符指针，并将所述描述符指针存储至所述片内存储器；
    所述缓冲器，设置为在所述片内存储器中的描述符指针的数量小于预设数量之后，读取所述片外存储器中的描述符指针到所述片内存储器，并在所述片内存储器中的描述符指针的数量大于预设数量之后，读取所述片内存储器中的描述符指针到所述片外存储器。
  3. 如权利要求2所述的多核处理器的核间通信系统，其中，所述第一寄存器包括：
    控制寄存器，设置为在接收到所述第一系统发送的描述符指针申请指令之后，确定所述描述符申请指令对应的描述符指针，并将所述描述符指针存储至所述片内存储器；
    描述符申请寄存器，设置为向所述第一系统提供描述符指针的申请接口；
    描述符释放寄存器，设置为向所述第一系统提供描述符指针的释放接口；
    统计寄存器，设置为统计所述描述符指针的操作次数。
  4. 如权利要求1所述的多核处理器的核间通信系统，其中，所述队列管理模块包括第二总线接口、第二寄存器、队列控制器和片内存储器，所述队列管理模块通过所述第二总线接口与各所述系统以及片外存储器连接，
    所述第二寄存器，设置为在接收到所述第一系统发送的入队申请之后，通过所述队列控制器确定所述描述符指针对应的指定队列，并将所述描述符指针入队到所述指定队列；
    所述队列控制器，设置为在所述片内存储器中的描述符指针小于预设数量之后，读取所述片外存储器中的描述符指针。
  5. 如权利要求1所述的多核处理器的核间通信系统，其中，所述核间通信装置还包括：总线接口模块，所述内存管理模块和所述队列管理模块通过所述总线接口模块与各所述系统连接。
  6. 如权利要求1所述的多核处理器的核间通信系统，其中，所述核间通信装置还包括：仲裁模块，所述仲裁模块分别与所述内存管理模块和所述队列管理模块连接，所述仲裁模块，设置为在检测到多个系统同时访问所述核间通信装置，根据预设的通信顺序对各所述系统的访问进行访问仲裁，并依次响应每个所述系统的访问。
  7. 如权利要求1所述的多核处理器的核间通信系统，其中，所述中断模块，还设置为在所述内存管理模块存在异常之后，进行异常中断，在所述队列管理模块存在异常之后，进行异常中断。
  8. 一种多核处理器的核间通信方法，应用于如权利要求1-7任一项所述的多核处理器的核间通信系统，包括：
    接收第一系统发送的描述符申请指令，确定所述描述符申请指令对应的描述符指针，其中，所述第一系统将待传输数据存储至所述描述符指针对应 的内存；
    在接收到所述第一系统发送的入队申请之后，将所述描述符指针入队到指定队列；
    在所述指定队列对应的入队次数达到预设阈值之后，通过第二系统的中断服务程序进行所述指定队列中的描述符出队，其中，所述第二系统读取出队后的所述描述符指令对应的内存中的待传输数据。
  9. 一种多核处理器的核间通信设备，其中，所述多核处理器的核间通信设备包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的多核处理器的核间通信程序，所述多核处理器的核间通信程序被所述处理器执行时实现如权利要求8所述的多核处理器的核间通信方法的步骤。
  10. 一种存储介质，其中，所述存储介质上存储有多核处理器的核间通信程序，所述多核处理器的核间通信程序被处理器执行时实现如权利要求8所述的多核处理器的核间通信方法的步骤。
PCT/CN2023/088744 2022-10-11 2023-04-17 多核处理器的核间通信系统、方法、设备及存储介质 WO2024077914A1 (zh)

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CN110825690A (zh) * 2019-11-14 2020-02-21 北京华捷艾米科技有限公司 多核处理器的核间通信方法及装置
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