WO2024072873A2 - Dispositif électroluminescent comprenant une matrice de del ayant des parties situées dans des pixels adjacents et son procédé de fabrication - Google Patents

Dispositif électroluminescent comprenant une matrice de del ayant des parties situées dans des pixels adjacents et son procédé de fabrication Download PDF

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Publication number
WO2024072873A2
WO2024072873A2 PCT/US2023/033836 US2023033836W WO2024072873A2 WO 2024072873 A2 WO2024072873 A2 WO 2024072873A2 US 2023033836 W US2023033836 W US 2023033836W WO 2024072873 A2 WO2024072873 A2 WO 2024072873A2
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Prior art keywords
micro
led
leds
light emitting
led dies
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PCT/US2023/033836
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English (en)
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WO2024072873A3 (fr
Inventor
Ansel S. REED
Saket Chadda
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Glo Technologies Llc
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Publication of WO2024072873A2 publication Critical patent/WO2024072873A2/fr
Publication of WO2024072873A3 publication Critical patent/WO2024072873A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/10—Dealing with defective pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits

Definitions

  • the present invention relates to light emitting devices, and particularly to a light emitting device including a light emitting diode (LED) die having different portions located in different adjacent pixels, and methods of fabricating the same.
  • LED light emitting diode
  • a size of microLEDs e.g., LEDs having a size in the micron or sub-micron range
  • a size of microLEDs used in the light emitting devices may also decrease in order to maintain a high resolution.
  • the size of micro-LEDs decreases, it may become more difficult to manufacture the micro-LEDs, both on the wafer fabrication and mass transfer sides of processing.
  • a light emitting device includes a backplane, a plurality of light emitting diode (LED) dies mounted on the backplane, such that each of the LED dies includes a plurality of LEDs, and a pixel containing adjacent micro- LEDs of the plurality of LEDs located in adj cent LED dies of the plurality of LED dies.
  • LED light emitting diode
  • a method of forming a light emitting device comprises providing a backplane, providing a plurality of light emitting diode (LED) dies, each comprising a plurality of LEDs, and mounting the plurality of LED dies on the backplane such that adjacent LEDs of the plurality of LEDs in adjacent LED dies of the plurality of LED dies constitute a pixel.
  • LED light emitting diode
  • FIG. 1A is a plan view (e.g., top-down view showing a layout overview) of a light emitting device according to one or more embodiments.
  • FIG. IB is a top perspective view of the left half of the light emitting device in FIG. 1A, according to one or more embodiments.
  • FIG. 1C is a vertical cross-sectional view of the light emitting device along the line I-F in FIG. 1 A, according to one or more embodiments.
  • FIG. ID is a bottom perspective view of the LED die according to one or more embodiments.
  • FIG. 2A is a schematic diagram of a pixel that may include a portion of four adjacent LED dies in the light emitting device according to one or more embodiments.
  • FIG. 2B is a schematic diagram of a portion of a pixel array that may be included in the display module of the backplane according to one or more embodiments.
  • FIG. 3A is a schematic diagram of a defect repair system for repairing a defective micro-LED in the light emitting device according to one or more embodiments.
  • FIG. 3B is a flow chart illustrating a method of repairing a defective micro-LED according to one or more embodiments.
  • FIG. 4 is a schematic diagram of the light emitting device having an alternative layout pattern for the LED dies according to one or more embodiments.
  • FIG. 5 is a vertical cross-sectional view of a backplane, according to one or more embodiments.
  • FIG. 6A is a vertical cross-sectional view of an exemplary intermediate structure including an LED die base layer formed on a substrate, according to one or more embodiments.
  • FIG. 6B is a vertical cross-sectional view of an exemplary intermediate structure including various layers of a micro-LED on the LED die base layer, according to one or more embodiments.
  • FIG. 6C is a vertical cross-sectional view of an exemplary intermediate structure including micro-LEDs on the LED die base layer, according to one or more embodiments.
  • FIG. 6D is another vertical cross-sectional view of an exemplary intermediate structure including micro-LEDs on the LED die base layer, according to one or more embodiments.
  • FIG. 6E is vertical cross-sectional view of an exemplary intermediate structure including the LED die mounted on the backplane and separated from the substrate, according to one or more embodiments.
  • FIG. 7 is vertical cross-sectional view of an exemplary intermediate structure including the LED die mounted on the backplane after separation from the substrate, according to one or more embodiments.
  • FIG. 8 is a flow chart illustrating a method of making the light emitting device according to one or more embodiments.
  • the embodiments of the present disclosure are directed to light emitting devices, and particularly to a light emitting device including a LED die having different portions located in different adjacent pixels, and methods of fabricating the same, the various aspects of which are discussed herein in detail.
  • the drawings are not necessarily drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure.
  • the same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition.
  • a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element.
  • a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element.
  • a “layer” refers to a continuous portion of at least one material including a region having a thickness. A layer may consist of a single material portion having a homogeneous composition, or may include multiple material portions having different compositions.
  • a “conductive material” refers to a material having electrical conductivity greater than 1.0 x 10 5 S/cm.
  • an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0 x 10" 5 S/cm.
  • a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0 x 10’ 5 S/cm to 1.0 x 10 5 S/cm.
  • a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.
  • a light emitting device such as a display device (e.g., direct view display) can be formed from an ordered array of pixels.
  • Each pixel can include a set of subpixels that emit light at a respective peak wavelength.
  • a pixel can include a red subpixel, a green subpixel, and a blue subpixel.
  • Each subpixel can include one or more light emitting diodes that emit light of a particular wavelength.
  • Each pixel may be driven by a backplane circuit such that any combination of colors within a color gamut may be shown on the display for each pixel.
  • the display e.g., display panel
  • the display can be formed by a process in which light emitting diode (LED) subpixels are soldered to, or otherwise electrically attached to, a bonding pad on a surface of a backplane.
  • the bonding pad may be electrically driven by the backplane circuit and other driving electronics.
  • micro-LED In a typical red/green/blue (RGB) mass transfer technique, one micro-LED may be transferred per one sub-pixel. Thus, a size of the micro-LED size may shrink with a decrease in sub-pixel size.
  • Common mass transfer techniques such as elastomeric stamps and electrostatic pick-up, may struggle to achieve high yields at micro-LED sizes below about 5 microns and sub-pixel pitches below about 10 microns.
  • One or more embodiments of the present disclosure may include a light emitting device (e.g., a RGB micro-LED display) that may help to alleviate the problems of typical light emitting devices (e.g., displays) and methods of fabricating the light emitting device.
  • the light emitting device may include, for example, a plurality of LED dies (e.g., micro- monolithic micro-LEDs) that may each include a plurality of micro-LEDs.
  • a micro-LED has a width and/or length of 20 microns or less, such as 5 microns or less, for example 500 nm to 3 microns.
  • the light emitting device may be referred to as a micro- monolithic micro-LED display (e.g., a micro-monolithic RGB micro-LED display).
  • the micro-monolithic micro-LEDs may each include four separate mesas that may be connected to separate backplane electrical connections and form four adjacent sub-pixels located in four separate adjacent pixels.
  • a larger micro-LED may be easier to transfer than a smaller micro- LED.
  • one or more embodiments may divide the backplane facing portion of the larger LED die (which may be easy to transfer) into smaller sub-units.
  • the sub-units of the larger LED die may be located in multiple adjacent pixels such that one LED die can be separately addressed by the backplane as multiple individual micro-LED subpixels. This may allow a high pixel-per-inch (PPI) resolution to be maintained while transferring larger LED die with large wafer- level pitches to the backplane.
  • PPI pixel-per-inch
  • the transferred LED die size (e.g., length and width for square die) and pitch may be 7 microns and 32 microns, respectively, to achieve a subpixel size of 3 microns and pixel pitch of 16 microns.
  • the transferred LED die size and pitch may be 7 microns and 32 microns, respectively, to achieve a subpixel size of 3 microns and pixel pitch of 16 microns.
  • existing transfer technology nodes may be leveraged and instantly access nodes that may double the resolution (e.g., a 7 micron node can be utilized for a 3 micron node).
  • the embodiments may include several advantages over typical light emitting devices and typical methods of forming light emitting devices.
  • the embodiments may help to eliminate a back-end of line (BEOL) process entirely.
  • the embodiments may need only one transfer step per four sub-pixels.
  • the embodiments may provide a local cathode (e.g., substantially no voltage (IR) drop when using a common cathode ring).
  • IR substantially no voltage
  • the embodiments may allow for multiple use of coupons and may also allow for low PPI displays to successfully use micro-LEDs and still maintain high utilization of the donor LED wafers.
  • One or more embodiments of the present disclosure may also provide for a mechanism for repairing defective micro-LEDs without needing to physically repair the light emitting device.
  • the defective micro-LEDs may be “repaired” in the present disclosure by using a software-based approach or a hardware-based approach.
  • Typical light emitting devices may not provide a capability of repairing defective pixels without physically repairing the light emitting device.
  • a front side electrode e.g., a transparent electrode, such as an indium tin oxide (ITO) electrode
  • ITO indium tin oxide
  • the embodiments of the present disclosure may provide an alternative that may be facilitated by the architecture of most silicon backplanes (e.g., a 2x2 configuration).
  • every three RGB pixels can have an extra R, G, or B redundant micro- LED. If it is determined (e.g., at the end of fabrication) that a certain micro-LED is defective, then current (or voltage) originally intended for the defective micro-LED may be turned off in software and re-directed (e.g., re-routed) to the closest micro-LED of the same color.
  • FIG. 1A is a plan view (e.g., top-down view, layout overview) of a light emitting device 100 according to one or more embodiments.
  • FIG. IB is a top perspective view of the lower side of the light emitting device 100 in FIG. 1A, according to one or more embodiments. It should be noted that some elements of the light emitting device 100 have been omitted in FIGS. 1A and IB for ease of explanation.
  • the light emitting device 100 may comprise a direct view display.
  • the light emitting device 100 may include a backplane 1 10 including a backplane substrate 11 1 and bonding pads 1 12 formed on the substrate 11 1.
  • One or more pixel driving circuits may be formed on the backplane substrate 111 and electrically connected to the bonding pads 112.
  • the light emitting device 100 may also include a plurality of light emitting diode (LED) dies 10 (e.g., micro-monolithic micro-LEDs) mounted on the backplane 100.
  • the plurality of LED dies 10 may include a plurality of micro-LEDs 12.
  • the light emitting device 100 may also include a pixel 130 including adjacent micro-LEDs 12 in adjacent LED dies 10. The pixel 130 may be driven by a pixel driving circuit on the backplane 110.
  • the backplane 110 may include an active matrix display backplane or a passive matrix display backplane.
  • the backplane 110 may include a display module (not shown) for controlling the micro-LEDs 12 of the pixel 130.
  • the display module may include, for example, complementary metal oxide semiconductor (CMOS) circuitry.
  • CMOS complementary metal oxide semiconductor
  • the display module may include, for example, a pixel array (e.g., a two-dimensional pixel circuit arrangement) including the pixel driving circuits.
  • the display module may also include a data driver and a scanning driver for activating the micro-LEDs 12 through the pixel driving circuits.
  • the display module may include control circuitry including logic elements for filling the data driver and scanning driver with data for displaying an image and a brightness of the image to be displayed. Brightness of the micro-LEDs 12 can be controlled by either using a pulse width modulation (PWM) scheme or by current modulation across the micro-LEDs 12.
  • PWM pulse width modulation
  • the backplane 110 may have a rectangular shape in the plan view. However, other shapes are within the contemplated scope of disclosure.
  • the backplane substrate 111 may include one or more layers of insulating material (e.g., dielectric material, such as a polymer material used in printed circuit boards) and/or semiconductor material (e.g., silicon, germanium, silicon germanium, etc.).
  • the bonding pads 112 may be arranged on and/or in the backplane substrate 111 in a form of a bonding pad array (e.g., a 16 x 8 array is shown in FIG. 1A for ease of illustration).
  • the bonding pad array may include, for example, one or more rows of bonding pads 112 extending in the x-direction and one or more columns of bonding pads 112 extending in the y-direction.
  • the bonding pads 112 may have a pitch of about 8 pm or less corresponding to a sub-pixel pitch (e.g., about 8 pm) of the backplane 110.
  • the bonding pads 112 may have a rectangular shape in the plan view. However, other shapes are within the contemplated scope of disclosure.
  • the bonding pads 112 may include copper or another suitable metal (e.g., silver, chromium, nickel, tin, tungsten, titanium, gold, etc.), a copper alloy, or other suitable metal alloy. Other suitable metal materials are within the contemplated scope of disclosure.
  • the LED dies 10 may be mounted on (e.g., bonded to) the bonding pads 112 of the backplane 110.
  • the LED dies 10 may be mounted on the backplane 110 so as to substantially overlie the bonding pads 112.
  • the LED dies 10 may be bonded by a solder material portion (e.g., solder bumps) to a surface of the bonding pads 112.
  • the LED dies 10 may include, for example, one or more semiconductor material layers.
  • the LED dies 10 may include one or more layers of Group III-V compound semiconductor material layers.
  • the LED dies 10 may be mounted on the backplane 110 in a form of an LED die array.
  • a size and shape of the LED die array may be substantially the same as a size and shape of the bonding pad array.
  • the LED die array may include, for example, one or more LED die rows extending in the x-direction and one or more LED die columns extending in the y-direction.
  • the LED die rows may include a first LED die row 121, a second LED die row 122, a third LED die row 123 and a fourth LED die row 124.
  • the LED dies 10 may include one or more micro-LEDs 12 which may also be referred to herein as “sub-pixels” or “sub-units”.
  • micro-LEDs 12 may be on an underside of the LED dies 10 and may not be visible from a top view of the light emitting device 100 (see FIG. IB).
  • FIG. 1A shows a location of the micro-LEDs 12 on the underside of the LED dies 10.
  • the LED dies 10 may each include four (4) micro-LEDs 12. However, other numbers of micro-LEDs 12 may be within the contemplated scope of disclosure.
  • the LED dies 10 may be mounted on the backplane 110 so that the micro-LEDs 12 are substantially located over the bonding pads 112, respectively.
  • the micro-LEDs 12 may be bonded to the bonding pads 112 by the solder material portion.
  • the micro-LEDs 12 may be electrically connected to the pixel driving circuit through the bonding pads 112 to which the micro-LEDs 12 are bonded, respectively.
  • the micro-LEDs 12 may include one or more Group III-V compound semiconductor material layers.
  • the one or more Group III-V compound semiconductor material layers may include one or more light emitting layers (e.g., active layers for emitting light).
  • a color of the light emitted by the light emitting layers of the micro-LEDs 12 may be indicated as either “R” for red, “G” for green or “B” for blue.
  • a micro-LED 12 that emits light having a red color may be referred to as a red micro-LED 12R.
  • a micro-LED 12 that emits light having a green color may be referred to as a green micro-LED 12G.
  • a micro-LED 12 that emits light having a blue color may be referred to herein as a blue micro- LED 12B.
  • Other colors of light or different radiation wavelengths e.g., ultraviolet or infrared
  • the micro-LEDs 12 on an LED die 10 may emit the same color light (i.e., light having the same peak wavelength).
  • An LED die 10 that includes only red micro-LEDs 12R may be referred to herein as a red LED die 10R.
  • An LED die 10 that includes only green micro-LEDs 12G may be referred to herein as a green LED die 10G.
  • An LED die 10 that includes only blue micro-LEDs 12B may be referred to herein as a blue LED die 10B.
  • the first LED die row 121 and third LED die row 123 may include alternating red LED dies 10R and blue LED dies 10B.
  • the second LED die row 122 and fourth LED die row 124 may include alternating green LED dies 10G and red LED dies 10R.
  • the red LED dies 10R in adjacent rows may be staggered in the x-direction.
  • the light emitting device 100 may include one or more pixels 130 which are indicated by dashed lines.
  • the pixels 130 may be driven by one or more of the pixel driving circuits in the backplane 110.
  • the pixels 130 may include adjacent micro-LEDs 12 from adjacent LED dies 10.
  • the pixels 130 may include two red micro-LEDs 12R, a green micro-LED 12G and a blue micro-LED 12B.
  • the pixels 130 may be referred to as RRGB pixels 130.
  • each pixel 130 may include two green micro-LEDs 12G or two blue micro-LEDs 12B.
  • the pixels 130 may be arranged on the backplane 110 in the form of a pixel array.
  • the pixel array may include, for example, one or more pixel rows extending in the x-direction.
  • the pixel rows may include a first pixel row 131, a second pixel row 132, and a third pixel row 133.
  • the pixel array may also include one or more columns of the pixels 130 extending in the y- direction.
  • the pixels 130 in the first pixel row 131 may include adjacent micro-LEDs 12 from adjacent LED dies 10 in the first LED die row 121 and the second LED die row 122.
  • the pixels 130 in the first pixel row 131 may include a red micro-LED 12R from a red LED die 10R in the first LED die row 121, a blue microLED 12B from a blue LED die 10B in the first LED die row 121, a green micro-LED 12G from a green LED die 10G in the second LED die row 122, and a red micro-LED 12R from a red LED die 10R in the second LED die row 122.
  • the pixels 130 in the second pixel row 132 may include adjacent micro-LEDs 12 from adjacent LED dies 10 in the second LED die row 122 and the third LED die row 123.
  • the pixels 130 in the second pixel row 132 may include a red micro-LED 12R from a red LED die 10R in the second LED die row 122, a green micro-LED 12G from a green LED die 10G in the second LED die row 122, a blue micro-LED 12B from a blue LED die 10B in the third LED die row 123, and a red micro-LED 12R from a red LED die 10R in the third LED die row 123.
  • the pixels 130 in the third pixel row 133 may include adjacent micro-LEDs 12 from adjacent LED dies 10 in the third LED die row 123 and the fourth LED die row 124.
  • the pixels 130 in the third pixel row 133 may have a configuration similar to the configuration of the pixels 130 in the first pixel row 131.
  • the pixels 130 in the third pixel row 133 may include a red micro-LED 12R from a red LED die 10R in the third LED die row 123, a blue micro-LED 12B from a blue LED die 10B in the third LED die row 123, a green micro-LED 12G from a green LED die 10G in the fourth LED die row 124, and a red micro-LED 12R from a red LED die 10R in the fourth LED die row 124.
  • each LED die 10 includes plural micro-LEDs 12 located in different adjacent pixels.
  • each LED die 10 may include four micro-LEDs 12 which emit the same color light (i.e., emit radiation with the same peak wavelength) and which are located in four different pixels 130.
  • a size of the red LED dies 10, green LED dies 10 and blue LED dies 10B may be about 7 pm or less, and a size of the micro-LEDs 12 on the LED dies 10 may be about 3 pm or less.
  • a pitch between the LED dies may be about 16 pm or less, and a transferred pitch (PT) between like LED dies (e.g., a pitch between green LED dies 10G; see FIG. IB) may be about 32 pm or less.
  • the size of the LED dies 10 and pitch (e.g., 16 pm or less) between LED dies 10 in the light emitting device 100 may provide a large diagonal distance between the blue micro-LEDs 12B and a large diagonal distance between the green micro-LEDs 12G (as indicated by the arrows in FIG. 1A).
  • the size and pitch of the LED dies 10 may also help to alleviate the problems associated with fabricating typical light emitting devices that may require transferring small (e.g., 5 pm or less) devices.
  • the transferred device size e.g., about 7 pm or less
  • the transferred pitch PT e.g., about 32 pm or less
  • a subpixel size e.g., a size of the micro-LED 12
  • devices at a size and pitch of 3 pm and 16 pm, respectively, would need to be transferred.
  • existing transfer technology nodes e.g., in the backplane 110
  • a 7 pm node can he utilized for a next-gen 3 pm node
  • a resolution of the light emitting device 100 may be twice a resolution of a typical light emitting device.
  • layout lattice e.g., square lattice, triangular lattice, hexagonal lattice
  • a location of colors with the LED die array e.g., a location of colors with the LED die array
  • aspects of the micro-LED wafer-level integration may be within the contemplated scope of disclosure.
  • each LED die 10 in the light emitting device 100 in FIG. 1A may instead be configured as GGRB pixels by replacing the red LED dies 10R in FIG. 1A with green LED dies 10G and replacing the green LED dies 10G in FIG. 1A with red LED dies 10R.
  • each LED die 10 may include more or less than four subpixels 12.
  • each LED die 10 may include two, three, five or six subpixels which are located in two, three, five or six different pixels 130.
  • FIG. 1C is a vertical cross-sectional view of the light emitting device 100 along the line LI’ in FIG. 1 A, according to one or more embodiments.
  • FIG. 1C is a view along a column of the LED die array that includes red LED dies 10R and blue LED dies 10B.
  • the LED dies 10 may be flip chip mounted to the respective bonding pads 112 of the backplane 110.
  • Each micro-LED 12 may be mounted to a separate bonding pad 112 which may be driven separately by the backplane 110.
  • a solder material portion 90 may be formed between the micro-LEDs 12 and the bonding pads 112.
  • the solder material portion 90 may include, for example, a tin-silver-copper alloy including about 3 ⁇ 1% silver, 0.5-0.7% copper, and the balance (95%+) tin.
  • a fourth metal such as indium, antimony, bismuth, zinc, or manganese may be added to the tin-silver-copper alloy.
  • a p-type layer (not shown) of the micro-LEDs 12 may be electrically connected to the bonding pads 112.
  • each micro-LED is bonded p-side down to the backplane 110 and has a common n-side with the other micro-LEDs 12 (e.g., with three other micro-LEDs 12) in the same LED die 10.
  • the bonding pads 112 may serve as an anode in the light emitting device 100.
  • the light emitting device 100 may include one or more dielectric material layers 150 formed between the LED dies 10 so as to substantially surround (in the x-y direction) the LED dies 10.
  • the LED dies 10 may be substantially embedded in the dielectric material layer 150.
  • An upper surface of the dielectric material layer 150 may be substantially coplanar with an upper surface of the LED dies 10.
  • the dielectric material may include, for example, a polymer material, silicon oxide or aluminum oxide. However, other dielectric materials may be within the contemplated scope of disclosure.
  • the light emitting device 100 may further include a continuous n-type (i.e., n-type side) contact layer 160 (e.g., first conductivity type contact layer) formed on the upper surface of a plurality of the LED dies 10 and the upper surface of the dielectric material layer 150.
  • the n-type contact layer 160 may be electrically connected to an n-type layer of the micro-LEDs 12 and, therefore, may serve as a shared cathode for plural LED die 10 in the light emitting device 100.
  • the n-type contact layer 160 may include an optically transparent material.
  • the n-type contact layer 160 may include indium tin oxide (ITO) or another transparent, conductive metal oxide.
  • a light emitted by the micro- LEDs 12 may be directed through the n-type contact layer 160 in an area of the pixels 130, as indicated by the arrows extending in the z-direction in FIG. 1C.
  • an upper surface of the n-type contact layer 160 may serve as a light emitting surface of the light emitting device 100.
  • the light emitting device 100 may also include a frame 170.
  • the frame 170 may be formed around an outer periphery of the light emitting device 100 (e.g., an outer periphery of the backplane 110, the dielectric material layer 150 and the n-type contact layer 160).
  • the frame 170 may wrap continuously around the periphery of the light emitting device 100 (e.g., from a front side to a back side).
  • the frame 170 may include one or more metal or plastic materials. However, other materials may be within the contemplated scope of disclosure.
  • a voltage or current may be applied across one of the micro-LEDs 12 (e.g., a selected micro-LED 12) in the LED die 10 while the other micro-LEDs 12 (e.g., unselected micro-LEDs 12) in the same LED die 10 may be electrically inactive.
  • This may be accomplished by applying a voltage or current to the bonding pad 112 bonded to the selected micro-LED 12 relative to the n-type contact layer 160, while no voltage or current is applied to the bonding pads 112 bonded to the unselected micro-LEDs 12 of the same LED die 10.
  • This causes the selected micro-LED 12 (i.e., subpixel) in one pixel 130 to emit light while the unselected micro-LEDs 12 of the same LED die 10 which are subpixels located in other pixels do not emit light.
  • FIG. ID is a bottom perspective view of the LED die 10 according to one or more embodiments.
  • the LED die 10 may include an LED die base layer 15 (e.g., a strap layer) and one or more micro-LEDs 12 formed on the LED die base layer 15.
  • the LED die base layer 15 may have a shape of a trapezoidal prism. However, other shapes are within the contemplated scope of disclosure.
  • the LED die base layer 15 may have a first surface 15S i and a second surface 15S2 opposite the first surface 15Si.
  • the first surface 15Si may include a light emitting surface as indicated by the unidirectional arrows in FIG. ID.
  • An area of the first surface 15S i may be greater than an area of the second surface 15S2.
  • the LED die base layer 15 may have a width W15 in the x-direction and a length L15 in the y-direction.
  • the width W15 may be substantially equal to the length L15.
  • the width W15 and/or length L15 may be 20 pm or less, such as 7 to 10 pm.
  • the LED die base layer 15 may include one or more layers of n-type semiconductor material.
  • the n-type semiconductor layer may include a n-type Group III-V compound semiconductor material layer, such as n-type GaN.
  • a light emitted by the micro-LEDs 12 may be directed through the LED die base layer 15 as indicated by the unidirectional arrows.
  • the first surface 15S 1 of the LED die base layer 15 may serve as a light emitting surface of the LED die 10.
  • the micro-LEDs 12 may be formed on the second surface 15S2 of the LED die base layer 15.
  • the micro-LEDS 12 may be formed as discrete mesas on the second surface 15S2.
  • the micro-LEDs 12 (e.g., mesas) may have a tapered shape that is substantially similar to the tapered shape of the LED die base layer 15.
  • the micro-LEDs 12 may also have the shape of a trapezoidal prism.
  • other shapes are within the contemplated scope of disclosure.
  • the micro-LEDs 12 may have a width W12 in the x-direction and a length L12 in the y-direction. In at least one embodiment, the width W 12 may be substantially equal to the length L12.
  • the width W12 and/or length L12 may be about 3 pm or less, such as 500 nm to 3 pm.
  • the micro-LEDs 12 may include, for example, a light emitting layer (e.g., an active layer; not shown) and other layers (not shown) on the light emitting layer.
  • the light emitting layer may have a quantum well (QW) or multiple quantum well (MQW) configuration.
  • the light emitting layer may include indium gallium nitride (InGaN), which has a narrower band gap than GaN, which allows the light emitted from the InGaN to pass through the n-type GaN base layer 115.
  • the contact portion may include a p-type semiconductor material (e.g., second conductivity type semiconductor material).
  • the contact portion may include a p-type Group III-V compound semiconductor material layer such as p-type GaN.
  • the other layers may also include a reflective layer (not shown) for reflecting light from the light emitting layer back toward the first surface 15Si of the LED die base layer 15.
  • the reflective layer may include a metal such as aluminum, silver, etc.
  • FIG. 2A is a schematic diagram of a pixel 130 that may include a portion of four adjacent LED dies 10 in the light emitting device 100 according to one or more embodiments.
  • the four adjacent LED dies 10 may include a first red LED die 10R-1 including four red micro-LEDs 12R which may be referred to as Rn, R 12, R13 and R14, a blue LED die 10B including four blue micro-LEDs 12B which may be referred to as Bi, B2, B3 and B4, a green LED die 10G including four green micro-LEDs 12G which may be referred to as Gi, G2, G3 and G4, and a second red LED die 10R-2 including four red micro- LEDs 12R which may be referred to as R21 , R22, R23 and R24.
  • the pixel 130 may be formed of the four adjacent micro-LEDs 12R in the adjacent LED dies 10.
  • the pixel 130 may be formed of the red micro-LED R14, blue micro-LED B3, green micro-
  • FIG. 2B is a schematic diagram of a portion of a pixel array 20 that may be included in the display module of the backplane 110 according to one or more embodiments.
  • the pixel array 20 may include an active matrix pixel array.
  • pixel array 20 may alternatively include a passive matrix pixel array.
  • the pixel array 20 may include data lines 251 (251a, 251b) and select lines 252 (252a, 252b).
  • a pixel driving circuit 200 may be located at an intersection of a data line 251 and select line 252.
  • the pixel driving circuits 200 may include micro-LEDs 12, respectively. As illustrated in FIG.
  • a pixel driving circuit 200 for the red micro-LED 12R may be connected to data line 251a and select line 252a.
  • a pixel driving circuit 200 for the green micro-LED 12G may be connected to data line 25 la and select line 252b.
  • a pixel driving circuit 200 for the blue micro-LED 12B (Bs) may be connected to data line 251b and select line 252a.
  • a pixel driving circuit 200 for the red micro-LED 12R (R21) may be connected to data line 251b and select line 252b.
  • the pixel driving circuit 200 may have a 2-Transistor, 1 -Capacitor (2T1C) configuration located on the backplane 110.
  • 2T1C 2-Transistor, 1 -Capacitor
  • the pixel driving circuit 200 may include a first transistor 201 (e.g., switching transistor), a second transistor 202 (e.g., driving transistor) and a capacitor 203 (e.g., storage capacitor).
  • the first transistor 201 and second transistor 202 may include thin film transistors (TFTs).
  • the first transistor 201 (e.g., first TFT) may be connected to a data line 251 in the pixel array 20 of the backplane 110.
  • a control gate of the first transistor 201 may be connected to a select line 252 in the pixel array 20.
  • the second transistor 202 (e.g., second TFT) may be connected between a power supply Vdd and the micro-LED 12.
  • a control gate of the second transistor 202 may be connected to the data line 251 through the first transistor 201.
  • the capacitor 203 may be connected between the power supply Vdd and the control gate of the second transistor 202.
  • the first transistor 201 (e.g., switching TFT) may, therefore, serve as a pass gate for passing data on the data line 251 to the storage capacitor 203 and turning on the second transistor 202 (e.g., driving TFT) when a select signal is transmitted on the select line 252.
  • the second transistor 202 When the second transistor 202 is turned on, micro-LED 12 may be activated and emit light from its light emitting layer.
  • FIG. 3A is a schematic diagram of a defect repair system 300 for repairing a defective micro-LED 12 in the light emitting device 100 according to one or more embodiments.
  • the defect repair system 300 may be used to implement a software-based approach to repairing a defective micro-LED 12. However, a hardware-based approach may alternatively be used to repair a defective micro-LED 12. At least a portion of the defect repair system 300 may be connected to or included within the backplane 110.
  • the light emitting device 100 may be designed to substantially eliminate defective micro-LEDs 12. That is, the light emitting device 100 may provide zero light-up parts per million (PPM) defectivity without requiring physical repair.
  • PPM light-up parts per million
  • the software-based approach that may be facilitated by the architecture of most silicon backplanes (e.g., a 2x2 configuration).
  • current to the defective micro-LED 12 may be turned off using software.
  • the current may then be routed to a micro-LED 12 of the same color that is near (e.g., closest to) the defective micro-LED 12.
  • the current may be routed to the redundant micro-LED in the pixel 130 having the defective micro-LED 12.
  • one or more embodiments may provide a zero PPM light-up detectivity (e.g., a perfect panel) even if the original light emitting device 100 has up to 5000 ppm light-up.
  • the current may be routed to a redundant micro-LED that is outside the pixel 130 having the defective micro-LED 12.
  • the defect repair system 300 may be included as part of a control system for the light emitting device 100.
  • the defect repair system 300 may include, for example, a defective micro-LED detector 310, a processing device 320 and a memory device 330.
  • the defective micro-LED detector 310 may be connected to the pixel array 20 that is included in a display module 340 of the light emitting device 100.
  • the defective micro-LED detector 310 may detect a defective micro-LED 12 in the pixel array 20.
  • the defective micro-LED detector 310 may include, for example, a sensing circuit that senses a voltage or current on a power supply line that supplies power (Vdd) to the micro- LED 12.
  • the defective micro-LED detector 310 may transmit a defect notification signal Sd to the processing device 320.
  • the defect notification signal Sd may include an identity and/or location of the defective micro-LED 12 in the pixel array 20.
  • the memory device 330 may include, for example, read-only memory (ROM) and/or random access memory (RAM).
  • the memory device 330 may be physically located in a location that is remote from the processing device 320.
  • the memory device 330 may store a defect repair program including instructions for repairing the defective micro-LED in the pixel array 20.
  • the processing device 320 may include a central processing device (CPU), microcontroller, microprocessor, etc.
  • the processing device 320 may access the memory device 330 and execute the instructions in the defect repair program stored in the memory device 330.
  • the defect repair program may include, for example, a lookup table that indicates a redundant and/or adjacent micro-LED 12 associated with the defective micro-LED 12.
  • the display module 340 may include a data driver 351 for driving the data lines 251 (see FIG. 2B) with data in the pixel array 20.
  • the display module 340 may also include a scanning driver 352 for driving the select lines 252 (see FIG. 2B) with a select signal in the pixel array 20.
  • the processing device 320 may control the data driver 351 to re-route the data on the data lines 251 from the defective micro-LED 12 to the redundant micro-LED 12.
  • the processing device 320 may also control the scanning driver 351 to re-route the select signal on the select lines 252 from the defective micro-LED 12 to the redundant micro-LED 12.
  • the red micro-LED 12R (R ) may be activated by transmitting data on the data line 251a and a transmitting a select signal on select line 252a.
  • the red micro-LED 12R (R21) (e.g., the redundant red micro-LED 12 in the pixel 130) may be activated by transmitting data on the data line 25 lb and a transmitting a select signal on select line 252b. If the defective micro-LED detector 310 detects that the red micro-LED 12R (RM) is defective, then the defective micro-LED detector 310 may notify the processing device 320.
  • the processing device 320 may execute the instructions of the defect repair program stored in the memory device 330.
  • the processing device 320 may then operate pursuant to the executed instructions to control the data driver 351 and scanning driver 352 to activate the redundant red micro-LED 12R (R21) instead of the red micro-LED 12R (R ). That is, under the control of the processing device 320, instead of the data driver 351 transmitting data on data line 251a and the scanning driver 352 transmitting a select signal on select line 252a, the data driver 351 may transmit data on data line 251b and the scanning driver 352 may transmit a select signal on select line 252b.
  • the processing device 320 may also store repair data in the memory device 330 so that the redundant red micro-LED 12R (R21) may permanently replace red micro-LED 12R (RM) in the pixel 130.
  • the data driver 351 and scanning driver 352 may continue to activate the redundant red micro-LED 12R (R21) in place of the red micro-LED 12R (RM) in the pixel 130 indefinitely.
  • FIG. 3B is a flow chart illustrating a method of repairing a defective micro-LED 12 according to one or more embodiments. The method may be performed, for example, using the defect repair system 300.
  • Step 310 includes detecting a defective micro-LED 12 in a pixel array.
  • Step 320 includes identifying a redundant micro-LED 12 associated with the defective micro-LED 12.
  • Step 330 includes activating the redundant micro-LED 12 in place of the defective micro-LED 12.
  • FIG. 4 is a schematic diagram of the light emitting device 100 having an alternative layout pattern for the LED dies 10 according to one or more embodiments. In the alternative layout pattern of FIG.
  • the LED dies 10 may be referred to collectively as “RGB LED dies 10” because each of the LED dies 10 may include at least one red micro-LED 12R, at least one green micro-LED 12G and at least one blue micro-LED 12B.
  • the RGB LED dies 10 may also include one redundant micro-LED 12.
  • some of the RGB LED dies 10 may include a redundant red micro-LED 12R and may therefore be referred to as RRGB LED dies 10.
  • Some of the RGB LED dies 10 may include a redundant green micro- LED 12G and may therefore be referred to as RGGB LED dies 10.
  • Some of the RGB LED dies 10 may include a redundant blue micro-LED 12B and may therefore be referred to as RGBB LED dies 10.
  • the light emitting device 100 may include a first LED die column 30a including RRGB LED dies 10, a second LED die column 30b including RGGB LED dies 10 and a third LED die column 30c including RGBB LED dies 10.
  • the pattern of first LED die column 30a, second LED die column 30b and third LED die column 30c may be repeated one time to form a 12 x 12 array of LED dies 10.
  • the LED dies 10 may also constitute pixels 130 in the light emitting device 100.
  • the light emitting device 100 may include at least a 12 x 12 array of pixels 130 (e.g., 144 pixels).
  • every third RGB LED die 10 (e.g., RGB pixel 130) can have an extra R, G, and B redundant micro-LED 12. That is, the pixels 130 in the first LED die column 30a may include a redundant red micro-LED 12R, the pixels 130 in the second LED die column 30b may include a redundant green micro-LED 12G and the pixels 130 in the third LED die column 30c may include a redundant blue micro-LED 12B.
  • the alternative layout pattern may be implemented with the defect repair system 300 (see FIG. 3 A) to efficiently and effectively repair defective micro-LEDs 12 in the light emitting device 100.
  • the defect repair system 300 may cause the redundant red micro-LED 12R2 in the same pixel 130 to be activated in place of the defective red micro- LED 12R1.
  • the LED dies 10 e.g., pixels 130
  • defect repair system 300 may identify a redundant red micro-LED 12R outside of LED die column 30b. For example, the defect repair system 300 may identify the red micro-LED 12R2 or the red micro-LED 12R4 as the redundant red micro-LED 12R.
  • the backplane 110 may include a backplane lower substrate 610.
  • the backplane lower substrate 610 may include, for example, an insulating material (e.g., dielectric material) and/or semiconductor material (e.g., silicon, germanium, silicon germanium, etc.).
  • Control circuitry for controlling an operation of the light emitting device 100 may be formed on the backplane lower substrate 610.
  • Such control circuitry may include, for example, the display module 340 (e.g., see FIG. 3A) and in particular, the pixel array 20 of the display module 340. As illustrated in FIG.
  • the second transistor 202 (e.g., driving transistor; second TFT) of the pixel driving circuit 200 may be formed on the backplane lower substrate 610.
  • the second transistors 202 may be formed on the backplane lower substrate 610 in a l6 x 8 array configuration, so as to accommodate the later formation of the 16 x 8 array configuration of bonding pads 112 (e.g., see FIG. 1A). It should be noted that there may be more than 16 8 bonding pads in the display device.
  • the second transistor 202 may include a gate electrode 620, a gate dielectric 630, a channel region 642, a source region 646, and a drain region 644. While the second transistor 202 is depicted in FIG. 5 as an inverted staggered TFT, other types of TFTs, such as inverted coplanar, top gated staggered and top gated coplanar TFTs can be used instead. Source interconnect wiring 656 and drain interconnect wiring 654 may also be formed on the second transistor 202.
  • the backplane 110 may include other interconnect wiring to connect the second transistors 202 to electrical interfaces on the backplane lower substrate 610.
  • An encapsulation dielectric layer 665 may be formed on backplane lower substrate 610 and may encapsulate the second transistors 202.
  • First-level metal interconnect structures 660 may be formed through the encapsulation dielectric layer 4665 to a node of the second transistor 202 such as a drain region 644 (or source region 646).
  • An interconnect level dielectric layer 675 may be formed over the encapsulation dielectric layer 665.
  • the backplane lower substrate 610, encapsulation dielectric layer 665 and interconnect level dielectric layer 675 may together constitute the backplane substrate 111.
  • the bonding pads 112 e.g., second-level metal interconnect structures
  • the bonding pads 112 may be connected to the first-level metal interconnect structures 660 through an opening in the interconnect level dielectric layer 675.
  • FIGS. 6A-6E illustrate a method of forming an LED die 10 (e.g., micro- monolithic micro-LED) according to one or more embodiments.
  • the method illustrated in FIGS. 6A-6E may be used to form the LED die 10 in the light emitting device 100 of FIG. 1 A. That is, the LED die 10 in FIGS. 6A-6E may include a red LED die 10R, a green LED die 10G or a blue LED die 10B.
  • FIG. 6A is a vertical cross-sectional view of an exemplary intermediate structure including an LED die base layer 15 formed on a substrate 22, according to one or more embodiments.
  • the substrate 22 may be referred to as a growth substrate.
  • the substrate 22 may include a single crystalline growth substrate material such as AI2O3 (sapphire) using either basal plane or r-plane growing surfaces, diamond, Si, Ge, GaN, AIN, SiC in both wurtzite (a) and zincblende (P) forms, InN, GaP, GaAsP, GaAs, InP, ZnO, ZnS, and ZnSe.
  • AI2O3 single crystalline growth substrate material
  • Si Si, Ge, GaN, AIN, SiC in both wurtzite (a) and zincblende (P) forms, InN, GaP, GaAsP, GaAs, InP, ZnO, ZnS, and ZnSe.
  • the substrate 22 may include sapphire (i.e., single crystalline aluminum oxide) with a suitable surface orientation.
  • the substrate 22 may include a patterned sapphire substrate (PSS) having a patterned (e.g., rough) growth surface. Bumps, dimples, and/or angled cuts may, or may not, be provided on the top surface of the substrate 22 to facilitate epitaxial growth of an upper layer on the substrate 22, and/or to facilitate separation of an upper layer from the substrate 22 in a subsequent separation process.
  • PSS patterned sapphire substrate
  • the LED die base layer 15 may include one or more layers of semiconductor material grown on the substrate 22.
  • the semiconductor material may include, for example, a Group IILV compound semiconductor material.
  • the semiconductor material may include a Group III nitride compound semiconductor material such as n-type GaN.
  • the LED die base layer 15 may be formed by any suitable method such as metalorganic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), metal-organic molecular beam epitaxy (MOMBE), and atomic layer deposition (ALD).
  • MOVPE metalorganic vapor phase epitaxy
  • MBE molecular beam epitaxy
  • HVPE hydride vapor phase epitaxy
  • LPE liquid phase epitaxy
  • MOMBE metal-organic molecular beam epitaxy
  • ALD atomic layer deposition
  • FIG. 6B is a vertical cross-sectional view of an exemplary intermediate structure including various layers of a micro-LED 12 on the LED die base layer 15, according to one or more embodiments.
  • a single crystalline buffer semiconductor layer 24 may be formed on the LED die base layer 15 by a suitable method including, for example, MOVPE, MBE, HVPE, LPE, MOMBE, and ALD.
  • the single crystalline compound semiconductor material 24 may include, for example, a Group III-V compound semiconductor material, and in particular, a Group Ill-nitride compound semiconductor material.
  • the single crystalline buffer semiconductor layer 24 may include one or more of gallium nitride (GaN), aluminum nitride (AIN), indium nitride (InN), gallium aluminum nitride, and gallium indium nitride, as well as other IILV materials, such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), Indium phosphide (InP), indium arsenide (InAs), and indium antimonide (InSb).
  • GaN gallium nitride
  • AIN aluminum nitride
  • InN gallium aluminum nitride
  • GaAs gallium antimonide
  • InP Indium phosphide
  • InAsenide InAsenide
  • InSb indium antimonide
  • An n-doped compound semiconductor substrate layer 26 may be formed on the single crystalline buffer semiconductor layer 24.
  • the n-doped compound semiconductor substrate layer 26 may be formed as a continuous material layer having a uniform thickness over the entire top surface of the single crystalline buffer semiconductor layer 24.
  • the n- doped compound semiconductor substrate layer 26 may be lattice matched with the single crystalline compound semiconductor material of the top portion of the single crystalline buffer semiconductor layer 24.
  • the n-doped compound semiconductor substrate layer 26 may, or may not, include the same compound semiconductor material as the top portion of the single crystalline buffer semiconductor layer 24.
  • the n-doped compound semiconductor substrate layer 26 can include an n-doped direct band gap compound semiconductor material.
  • the n-doped compound semiconductor substrate layer 26 can include n-doped gallium nitride (GaN), indium gallium nitride (InGaN) or other III-V compound semiconductor materials, such as gallium phosphide or its ternary or quaternary compounds.
  • the n-doped compound semiconductor substrate layer 26 may be formed by any suitable method including, for example, MOVPE, MBE, HVPE, LPE, MOMBE, and ALD.
  • An n-doped compound semiconductor region 32 may be grown on the n-doped compound semiconductor substrate layer 26.
  • An optional patterned growth mask layer (not shown) may be formed the n-doped compound semiconductor substrate layer 26, in which case the n-doped compound semiconductor region 32 may be grown through openings in the patterned growth mask layer.
  • the n-doped compound semiconductor region 32 may be grown, for example, by a selective compound semiconductor deposition process which may include a selective epitaxy process. If the optional patterned growth mask layer is present, then the shapes and sizes of the n-doped compound semiconductor region 32 may be determined based on the shapes and dimensions of the openings through the patterned growth mask layer and by the process conditions of the selective compound semiconductor deposition process.
  • the n-doped compound semiconductor region 32 may be formed with various crystallographic facets located within a respective crystallographic plane.
  • the n- doped compound semiconductor region 32 may include a microdisc, nanodisc, nanowire cores, microwire cores, nanopyramids, micropyramids, nanofrustums, microfrustums, combinations thereof, or other nanoscale structures or microscale structures.
  • the n-doped compound semiconductor region 32 may comprise a continuous planar semiconductor layer.
  • An active region 34 may be formed (e.g., by selective epitaxy process) on the n- doped compound semiconductor region 32.
  • the active region 34 may include an optically active compound semiconductor layer stack configured to emit light.
  • the active region 34 may include one or more layers (e.g., active layers) of semiconductor material that emit light upon application of a suitable electrical bias.
  • the active region 34 may include one or more layers of Group III-V compound semiconductor material such as gallium nitride, indium gallium nitride well, aluminum gallium nitride, etc.
  • the active region 34 may include any other suitable semiconductor layer (e.g., such as gallium phosphide or its ternary or quaternary compounds) or stack of layers for light emitting diode applications provided that it can be grown on the n-doped compound semiconductor region 32.
  • the active region 34 may include a quantum well (QW) or a multi-quantum well (MQW) structure that emits light upon application of an electrical bias thereacross.
  • QW quantum well
  • MQW multi-quantum well
  • the active region 34 may include indium gallium nitride well(s) located between gallium nitride or aluminum gallium nitride barrier layers.
  • a p-doped semiconductor material layer 36 may be formed (e.g., by selective deposition such as selective epitaxy) on the active region 34 (e.g., on the planar top surfaces and, if present, on the faceted outer surfaces of the active region 34).
  • the p-doped semiconductor material layer 36 may include a doped semiconductor material having a doping of a second conductivity type, which is the opposite of the first conductivity type.
  • the p-doped semiconductor material layer 36 can include a compound semiconductor material.
  • the compound semiconductor material of the p-doped semiconductor material layer 36 can be any suitable semiconductor material, such as p-type Group Ill-nitride compound semiconductor material, e.g., gallium nitride and/or aluminum gallium nitride.
  • the n-doped compound semiconductor region 32 can include n-doped GaN or InGaN
  • the p-doped semiconductor material layer 36 can include p-doped AlGaN and/or GaN.
  • the n-doped compound semiconductor region 32 and/or the p-doped semiconductor material layer 36 can include other semiconductor materials, such as such as gallium phosphide or its ternary or quaternary compounds.
  • An anode contact layer 50 may be formed on the p-doped semiconductor material layer 36.
  • the anode contact layer 50 may include one or more layers (e.g., a layer stack) including one or more of a nickel layer, a platinum layer, a silver layer and/or a transparent conductive oxide layer. The layers may be formed by conformal or non-conformal deposition.
  • the transparent conductive oxide layer may include a material selected from doped zinc oxide, indium tin oxide, cadmium tin oxide (CdsSnC ), zinc stannate (Z ⁇ SnOA, and doped titanium dioxide (TiOz).
  • the anode contact layer 50 can include a layer stack including an adhesion metal layer (e.g., platinum layer, nickel layer, etc.) and a silver layer.
  • the anode contact layer 50 may be formed, for example, by physical vapor deposition.
  • FIG. 6C is a vertical cross-sectional view of an exemplary intermediate structure including micro-LEDs 12 on the LED die base layer 15, according to one or more embodiments.
  • the micro-LEDs 12 may be formed by forming a photoresist layer on the anode contact layer 50, and lithographically patterning the photoresist layer to cover each discrete area that corresponds to the area of a micro-LED 12.
  • the photoresist layer can include a two- dimensional array of discrete portions that are laterally spaced apart from each other. For example, two sets of line trenches extending along orthogonal horizontal directions can be provided among the patterned portions of the photoresist layer.
  • An anisotropic etch process that may include multiple etch steps can be performed to etch through unmasked portions of the anode contact layer 50, the p-doped semiconductor material layer 36, the active region 34, the n-doped compound semiconductor region 32, and optionally the n-doped compound semiconductor substrate layer 26 and/or the single crystalline buffer semiconductor layer 24.
  • the multiple etch steps can be employed to etch through the various material portions.
  • Each of the anode contact layer 50, the p-doped semiconductor material layer 36, the active region 34, the n-doped compound semiconductor region 32, and optionally the n-doped compound semiconductor substrate layer 26 and/or the single crystalline buffer semiconductor layer 24 may be divided into multiple discrete portions that underlie a respective one of the patterned portions of the photoresist layer.
  • the stack of the anode contact layer 50, the p-doped semiconductor material layer 36, the active region 34, the n-doped compound semiconductor region 32, and optionally the n- doped compound semiconductor substrate layer 26 and/or the single crystalline buffer semiconductor layer 24 may be patterned by a combination of a lithographic process and an anisotropic etch process.
  • Each continuous set of remaining portions of the anode contact layer 50, the p- doped semiconductor material layer 36, the active region 34, the n-doped compound semiconductor region 32, and optionally the n-doped compound semiconductor substrate layer 26 and/or the single crystalline buffer semiconductor layer 24 may constitute components of a respective micro-LED 12.
  • the sidewalls of the n-doped compound semiconductor substrate layer 26 and the single crystalline buffer semiconductor layer 24 of each light emitting diode 10 can be formed with a finite taper angle due to the less than infinite selectivity of the anisotropic etch process that is employed to etch the materials of the n-doped compound semiconductor substrate layer 26 and the single crystalline buffer semiconductor layer 24.
  • the taper angle can be in a range from 1 degree to 15 degrees, such as from 2 degrees to 10 degrees and/or from 3 degrees to 6 degrees, although lesser and greater taper angles can also be employed.
  • the LED die base layer 15 may also be separated into sections, with each section including a group of four (4) adjacent micro-LEDs 12 (e.g., see FIG. ID).
  • the LED die base layer 15 may be separated, for example, concurrently with the forming of the micro-LEDs 12 That is, the LED die base layer 15 may be separated by the same photolithographic process used to form the micro-LEDs 12.
  • the LED die base layer 15 may be separated before or after forming of the micro-LEDs 12 by a photolithographic process similar to the photolithographic process used to form the micro-LEDs 12.
  • FIG. 6D is another vertical cross-sectional view of an exemplary intermediate structure including micro-LEDs 12 on the LED die base layer 15, according to one or more embodiments.
  • an optional reflective metal layer 70 can be formed on the anode contact layer 50.
  • the reflective metal layer 70 may be formed as a planar structure that entirely overlies the top surface of an underlying anode contact layer 50. In such configurations, the entirety of the reflective material layer 70 is more distal from the n-doped compound semiconductor substrate layer 26 than a most distal surface of the n-doped compound semiconductor region 32 is from the n- doped compound semiconductor substrate layer 26. In such embodiments, the reflective material layer 70 may have a smaller area than the anode contact layer 50.
  • the reflective metal layer 70 may be formed with a laterally- extending portion that is more distal from the n-doped compound semiconductor substrate layer 26 than a most distal surface of the p-doped semiconductor material layer 36 (which is in contact with an anode contact layer 50) is from the n-doped compound semiconductor substrate layer 26, and a sidewall portion adjoined to a periphery of the laterally-extending portion, extending downward therefrom, and laterally surrounding the n-doped compound semiconductor region 32, the n-doped compound semiconductor substrate layer 26, and the single crystalline buffer semiconductor layer 24.
  • the reflective material layer 70 can be patterned to provide a suitable lateral extent for each micro-LED 12.
  • Bonding pads 80 including an underbump metallurgy (UBM) layer stack can be formed on each reflective material layer 70 (or on each anode contact layer 50 in case the reflective material layer 70 is not employed).
  • the UBM layer stack can include any metallic layer stack known in the art that can be employed as a bonding pad structure that enables attachment of a solder material thereupon.
  • the solder material portion 90 can be formed on the bonding pad 80 by a suitable process, such as electroplating.
  • FIG. 6E is vertical cross-sectional view of an exemplary intermediate structure including the LED die 10 being separated from the substrate 22, according to one or more embodiments.
  • the LED die 10 is placed in contact with the backplane 110 such that the solder material portion 90 on the micro-LEDs 12 may be facing the backplane 110 and contact the bonding pads 112.
  • the four (4) solder material portions 90 on the four (4) micro-LEDs 12 of the LED die 10 may contact four (4) bonding pads 112, respectively.
  • the solder material portion 90 may then be reflowed so that micro-LEDs 12 of the LED die 10 are bonded by the solder material portion 90 to the bonding pads 112, respectively.
  • the reflow may be performed by heating the solder material portion 90 by irradiating by an infrared laser beam through the LED dies 10 onto the solder material portion 90.
  • the reflow may alternatively be performed by annealing the light emitting device 10 in a furnace or similar heating apparatus above the melting temperature of the solder material portion 90.
  • a laser lift-off process is performed to separate each bonded LED die 10 from the substrate 22.
  • ultraviolet laser radiation 600 may be irradiated through the substrate 22 to an interface between the LED die 10 and the substrate 22.
  • the laser radiation 600 may heat a portion of the LED die base 15 (e.g., a GaN layer) at the interface between the LED die 10 and the substrate 22, causing the LED die 10 to be released from the substrate 22.
  • the laser lift-off may be performed before or after bonding the LED die 10 to the backplane 110. If the laser lift-off is performed before bonding the LED die 10 to the backplane 110, then the LED die 10 may be clamped to the backplane by any clamping device.
  • FIG. 7 is vertical cross-sectional view of an exemplary intermediate structure including the LED die 10 mounted on the backplane 110 after removing the substrate 22, according to one or more embodiments.
  • the method of transferring the LED dies 10 from the substrate 22 to the backplane 110 may be substantially the same for both the RGB LED dies 10 in the alternative layout pattern of FIG. 4 and the single-color LED dies 10 in FIG. 1A.
  • the dielectric material layer 150 may be formed in the gaps between the backplane 110 and the LED dies 10.
  • the dielectric material layer 150 may be formed so as to substantially embed the LED dies 10 in the dielectric material layer 150.
  • the dielectric material layer 150 may be formed, for example, by a suitable deposition process, such as spin coating.
  • the n-type contact layer 160 (e.g., shared cathode) may then be formed on the substantially coplanar surface 15S i of the LED die base layer 15 and surface of the dielectric material layer 150.
  • the n-type contact layer 160 may be formed by a suitable process including, for example, MOVPE, MBE, HVPE, LPE, MOMBE, and ALD.
  • the frame 170 (e.g., metal frame) may then be formed around an outer periphery of the light emitting device 100 to complete the fabrication of the light emitting device 100.
  • FIG. 8 is a flow chart illustrating a method of making the light emitting device 100 according to one or more embodiments.
  • Step 810 includes providing a backplane including a pixel driving circuit.
  • Step 820 includes forming a plurality of light emitting diode (LED) dies 10 including a plurality of micro-LEDs 12.
  • Step 830 includes mounting the plurality of LED dies 10 on the backplane 110, such that adjacent micro-LEDs 12 of the plurality of micro-LEDs in adjacent LED dies 10 of the plurality of LED dies constitute a pixel 130 to be driven by the pixel driving circuit.
  • LED light emitting diode
  • the light emitting device 100 comprises a display device containing a plurality of the pixels 130.
  • the pixel driving circuit is configured to drive the pixels to form an image in the display device.
  • a computer program product which may include, for example, a computer readable storage medium (hereinafter, the “storage medium”) that may store computer readable program instructions (hereinafter, the "computer program” or “instructions”) for performing the features and functions of the defective micro-LED detector 310, processing device 320, the memory device 330 or the display module 340.
  • the computer readable storage medium may store the instructions thereon for causing the processing device 320 (e.g., computer, instruction execution device, computing device, computer processor, central processing unit (CPU), microprocessor, etc.) to perform a feature or function of the present disclosure.
  • the processing device 320 e.g., computer, instruction execution device, computing device, computer processor, central processing unit (CPU), microprocessor, etc.
  • At least one embodiment may include a programmable storage medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus to perform the method of repairing a defective micro-LED, the method including detecting a defective micro-LED in a pixel array, identifying a redundant micro- LED associated with the defective micro-LED, and activating the redundant micro- LED in place of the defective micro-LED.
  • the computer readable storage medium can be a tangible device that can retain and store the instructions for execution by the processing device 320.
  • the computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.
  • a non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing.
  • RAM random access memory
  • ROM read-only memory
  • EPROM or Flash memory erasable programmable read-only memory
  • SRAM static random access memory
  • CD-ROM compact disc read-only memory
  • DVD digital versatile disk
  • memory stick a floppy disk
  • mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon
  • the computer readable storage medium should not be construed as merely being a "transitory signal" such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or an electrical signal transmitted through a wire.
  • the processing device 320 can access the instructions on the computer readable storage medium. Alternatively, the processing device 320 can access (e.g., download) the instructions from an external computer or external storage device via a network such as the Internet, a local area network, a wide area network and/or a wireless network.
  • the network may include, for example, copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers.
  • the processing device 320 may include a network adapter card or network interface which receives the instructions from the network and forwards the instructions to the computer readable storage medium within the processing device which stores the instructions.
  • the instructions for performing the features and functions of the present disclosure may include, for example, assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in one or more programming languages (or combination of programming languages), including an object oriented programming language such as Java, Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages.
  • ISA instruction-set-architecture
  • machine instructions machine dependent instructions
  • microcode firmware instructions
  • state-setting data or either source code or object code written in one or more programming languages (or combination of programming languages), including an object oriented programming language such as Java, Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages.
  • the instructions may execute entirely on the processing device 320 (e.g., a user's computer), partly on the processing device 320, as a stand-alone software package, partly on the processing device 320 and partly on a remote computer or entirely on the remote computer or a server.
  • the instructions may execute on a remote computer which is connected to the processing device (e.g., user's computer) through a network such as a local area network (LAN) or a wide area network (WAN), or may execute on an external computer which is connected to the processing device 320 through the Internet using an Internet Service Provider.
  • LAN local area network
  • WAN wide area network
  • the processing device 320 may include, for example, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PL A) that may execute the instructions by utilizing state information of the instructions to personalize the electronic circuitry, in order to perform a feature or function of the present disclosure.
  • electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PL A) that may execute the instructions by utilizing state information of the instructions to personalize the electronic circuitry, in order to perform a feature or function of the present disclosure.
  • the instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
  • These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
  • the instructions may be executed by the processing device 320 to cause a series of operational steps to be performed by the processing device 320 to produce a computer-implemented process, so that the executed instructions implement the features/functions/acts described above with respect to the flowchart and/or block diagram block or blocks of FIGS. 2A-3B.
  • the flowchart and block diagrams in the FIGS. 2A-3B illustrate not only a method, system, apparatus or device, but also illustrate the architecture, functionality, and operation of the processing device 320 executing the instructions.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of the instructions, which includes one or more executable instructions for implementing the specified logical function(s).
  • the features or functions in the block may occur out of the order noted in the figures.
  • two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
  • each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

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Abstract

Un dispositif électroluminescent comprend un fond de panier, une pluralité de matrices de diodes électroluminescentes (DEL) montées sur le fond de panier, de telle sorte que chacune des matrices de DEL comprend une pluralité de DEL, et un pixel contenant des micro-DEL adjacentes de la pluralité de DEL situées dans des matrices de DEL adjacentes de la pluralité de matrices de DEL.
PCT/US2023/033836 2022-09-29 2023-09-27 Dispositif électroluminescent comprenant une matrice de del ayant des parties situées dans des pixels adjacents et son procédé de fabrication WO2024072873A2 (fr)

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GB2437110B (en) * 2006-04-12 2009-01-28 Cambridge Display Tech Ltd Optoelectronic display and method of manufacturing the same
WO2011024705A1 (fr) * 2009-08-24 2011-03-03 シャープ株式会社 Dispositif d’affichage et substrat à filtres colorés
GB201413578D0 (en) * 2014-07-31 2014-09-17 Infiniled Ltd A colour iled display on silicon
GB201413604D0 (en) * 2014-07-31 2014-09-17 Infiniled Ltd A colour inorganic LED display for display devices with a high number of pixel
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