WO2024072056A1

WO2024072056A1 - Electronic device for controlling pulse signal from processor to display

Info

Publication number: WO2024072056A1
Application number: PCT/KR2023/014940
Authority: WO
Inventors: 이재성; 권경환; 배종곤; 김동휘; 양병덕
Original assignee: 삼성전자주식회사
Priority date: 2022-09-30
Filing date: 2023-09-26
Publication date: 2024-04-04

Abstract

An electronic device is provided. The electronic device may include a processor. The electronic device may include a display including a display driving circuit and a display panel. The electronic device may include a first path for connecting the processor and the display driving circuit. The electronic device may include a second path which connects the processor and the display driving circuit and is separated from the first path. The processor may be configured to transmit, to the display driving circuit through the second path, a pulse signal for synchronization of a first time period within the processor, which is used for displaying, on the display panel, an image transmitted to the display driving circuit through the first path and the first time period within the display driving circuit, which used for displaying the image on the display panel, on the basis of a first cycle. The processor may be configured to change a waveform of the pulse signal from a first waveform to a second waveform, on the basis of a second cycle different from the first cycle, the pulse signal being transmitted based on the first cycle for synchronization of a second time period within the processor used for the displaying of the image and the second time period within the display driving circuit used for the displaying of the image.

Description

Electronic device that controls pulse signals from the processor to the display

This disclosure relates to an electronic device that controls pulse signals from a processor to a display.

An electronic device may include a display panel. For example, the electronic device may include a display driving circuit operably or operatively coupled to the display panel. For example, the display driving circuit may display an image obtained from a processor of the electronic device on the display panel.

The above information may be provided as background art for the purpose of aiding understanding of the present disclosure. No claim or determination is made as to whether any of the foregoing can be applied as prior art to the present disclosure.

An electronic device is provided. The electronic device may include a processor. The electronic device may include a display including a display driving circuit and a display panel. The electronic device may include a first path connecting the processor and the display driving circuit. The electronic device may include a second path that connects the processor and the display driving circuit and is separated from the first path. The processor includes a first time period within the processor used to display on the display panel an image transmitted to the display driving circuit through the first path and a first time period used to display the image on the display panel. It may be configured to transmit a pulse signal to the display driving circuit through the second path, based on a first period, to synchronize the first time period in the display driving circuit. The processor is configured to synchronize the second time period within the processor used for the display of the image with the second time period within the display driving circuit used for the display of the image. The waveform of the pulse signal transmitted based on one cycle may be configured to change from a first waveform to a second waveform based on a second cycle different from the first cycle.

An electronic device is provided. The electronic device may include a processor. The electronic device may include a display including a display driving circuit and a display panel. The electronic device may include a first path connecting the processor and the display driving circuit. The electronic device may include a second path that connects the processor and the display driving circuit and is separated from the first path. The processor may be configured to determine a time interval within the processor used to display on the display panel an image transmitted to the display driving circuit through the first path and the display used to display the image on the display panel. It may be configured to periodically transmit a pulse signal to the display driving circuit through the second path to synchronize the time period within the driving circuit. The processor may be configured to identify control instructions to be provided to the display driving circuitry in connection with the display of the image on the display panel. The processor may be configured to change the waveform of the pulse signal periodically transmitted to the display driving circuit from a first waveform to a second waveform to indicate the control command to the display driving circuit based on the identification. there is.

The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

1 is a simplified block diagram of an example electronic device.

Figure 2 shows an example of a first path and a second path connecting a processor and a display driving circuit, respectively.

Figure 3 shows examples of pulse signals indicating the timing of the horizontal synchronization signal and the timing of the light emission synchronization signal.

Figure 4 shows examples of pulse signals indicating the timing of the horizontal synchronization signal and the timing of the vertical synchronization signal.

Figure 5 shows an example method of changing the waveform of a pulse signal according to changing the timing of the vertical synchronization signal.

6 illustrates an example method of changing the waveform of a pulse signal to represent a control command.

FIG. 7 is a block diagram of an electronic device in a network environment, according to various embodiments.

Figure 8 is a block diagram of a display module, according to various embodiments.

1 is a simplified block diagram of an example electronic device.

Referring to FIG. 1 , the electronic device 100 may include a processor 120 (eg, including a processing circuit) and a display 130. The display 130 may include a display driving circuit 131 and a display panel 132.

The processor 120 may include at least a portion of the processor 720 of FIG. 7 . The display 130 may include at least a portion of the display module 760. The display driving circuit 131 may include at least a portion of the DDI 830 of FIG. 8. The display panel 132 may include at least a portion of the display 810 of FIG. 8 .

The processor 120 may be operably or operatively coupled to the display 130 (or the display driving circuit 131). The fact that the processor 120 is operatively coupled to the display 130 (or the display driving circuit 131) may indicate that the processor 120 is directly connected to the display 130 (or the display driving circuit 131). there is. The processor 120 is operatively coupled to the display 130 (or display driving circuit 131), meaning that the processor 120 operates on the display 130 (or It may indicate that it is connected to the display driving circuit 131). The processor 120 is operatively coupled to the display 130 (or the display driving circuit 131), meaning that the processor 120 operates the display 130 (or the display driving circuit 131) for displaying an image. It can indicate partial control. The processor 120 is operatively coupled to the display 130 (or display driving circuit 131), meaning that the processor 120 is connected to the display driving circuit 130 (or display driving circuit 130) for display on the display panel 132. It may indicate that an image acquired or rendered by the processor 120 is transmitted to the driving circuit 131. However, it is not limited to this.

For example, processor 120 is operatively coupled to display 130, but some of the operations of processor 120 may be out of synchronization with some of the operations of display 130.

As a non-limiting example, some of the operations of the display 130 may be transparent or unnoticeable to the processor 120. Some of the operations may be out of synchronization with some of the operations of processor 120. As a non-limiting example, because some of the operations of display 130 are independent of processor 120, some of the operations of display 130 are synchronized with some of the operations of processor 120. It may not work. By way of non-limiting example, some of the above operations of display 130 may be performed or executed while processor 120 is in an inactive state (e.g., low power state, sleep state, and/or turned off state). Therefore, some of the operations of the display 130 may not be synchronized with some of the operations of the processor 120. As a non-limiting example, some of the operations of the display 130 may be performed or executed while transmission of images from the processor 120 to the display 130 is suspended. Some may be out of sync with some of the operations of processor 120. As a non-limiting example, some of the operations of the display 130 may be performed or executed while the path used for the transmission is deactivated, so the portion of the operations of the display 130 may be performed by the processor 120. ) may not be synchronized with some of the above operations. By way of non-limiting example, some of the above operations may be performed while the transmission is interrupted or the path is deactivated, by using a graphic random access memory (GRAM) within the display driver circuit 131 (e.g., GRAM 220 of FIG. 2 or It may include displaying the image stored in the memory 833 of 8 on the display panel 132.

By way of non-limiting example, the portion of the operations of the processor 120 being out of synchronization with the portion of the operations of the display 130 may mean the display 130 (or display) being out of synchronization with the reference time of the processor 120. This may be caused by the reference time of the driving circuit 131). By way of non-limiting example, the portion of the operations of the processor 120 being out of synchronization with the portion of the operations of the display 130 may include the display being out of synchronization with the operation of a clock for the processor 120 ( This may be caused by the operation of the clock for 130) (or the display driving circuit 131). By way of non-limiting example, non-synchronization of the portion of the operations of the processor 120 with the portion of the operations of the display 130 may include counting of the processor 120 associated with an indication on the display panel 132. ) may be caused by counting of the display driving circuit 131 out of synchronization.

For example, the processor 120 may send a pulse signal to the display driving circuit 131 to synchronize the portion of the operations of the display 130 with the portion of the operations of the processor 120. It can be transmitted periodically. As a non-limiting example, since the pulse signal is transmitted for synchronization of the display 130 from outside the display 130 (e.g., the processor 120), the pulse signal is an external synchronization signal (Esync). ) can be referred to.

For example, the transmission path of the pulse signal may be different from the transmission path of the image to be displayed on the display panel 132. For example, the pulse signal is transmitted to the processor 120 through a second path different from the first path used to transmit the image to be displayed on the display panel 132 from the processor 120 to the display driving circuit 131. ) can be transmitted to the display driving circuit 131. The first path and the second path may be illustrated in more detail below with reference to FIG. 2.

Figure 2 shows an example of a first path and a second path respectively connecting a processor and a display driving circuit.

Referring to FIG. 2, the electronic device 100 includes a first path 201 configured to connect the display driving circuit 131 with the processor 120, and a first path 201 configured to connect the display driving circuit 131 with the processor 120. , may include a second path 202, separated from the first path 201.

The first path 201 may be used to transmit an image to be displayed on the display panel 132 (not shown in FIG. 2). For example, the processor 120 may transmit an image to be displayed on the display panel 132 to the display driving circuit 131 through the first path 201. For example, the first path 201 may include a mobile industry process interface (MIPI). For example, the first path 201 is as represented by state 211, within the time interval in which the image to be displayed on the display panel 132 is transmitted from the processor 120 to the display driving circuit 131. Likewise, it can be enabled. For example, first path 201 may be disabled, as indicated by state 212, within at least a portion of the time interval during which transmission is suspended. For example, the first path 201 may cause the display driving circuit 131 to execute display on the display panel 132 based on scanning the image stored in the GRAM 220 in the display driving circuit 131. Within at least a portion of the time interval, it may be deactivated, as indicated by state 212.

By way of non-limiting example, the first path 201 being activated indicates that normal power is provided to the first path 201, the first path 201 being deactivated indicates that low power is provided to the first path 201, or It may indicate that providing power to the first path 201 is stopped. As a non-limiting example, activation of the first path 201 and deactivation of the first path 201 may be performed based on control of the processor 120 .

The second path 202 may be used for transmission of the pulse signal. For example, transmitting the pulse signal via the second path 202 can be maintained even if transmitting the image via the first path 201 is stopped. For example, transmission of the pulse signal via second path 202 can be maintained even if first path 201 is deactivated. For example, transmission of the pulse signal via the second path 202 can be maintained while the image stored in the GRAM 220 is scanned by the display drive circuit 131.

According to various embodiments, the pulse signal is transmitted from the processor 120 to the display driving circuit 131 through the first path 201 while the first path 201 is activated, and the first path 201 ) may be transmitted from the processor 110 to the display driving circuit 131 through the second path 202 while being deactivated. For example, the processor 120 may adaptively identify a path for transmitting the pulse signal among the first path 201 and the second path 202 according to the state of the first path 201.

According to one embodiment, the second path 202 may be a path dedicated for (only) the pulse signal. According to one embodiment, the second path 202 may be used for a signal transmitted from the display driving circuit 131 to the processor 120 as well as the pulse signal. For example, the signal may be a signal that is transmitted from the display driving circuit 131 to the processor 120 and indicates the state of the display driving circuit 131. For example, the signal may be a TE (tearing effect) signal. However, it is not limited to this.

Referring back to FIG. 1, the transmission period of the pulse signal may correspond to the period of the synchronization signal for the processor 120 to be identified or used for display on the display panel 132. As a non-limiting example, the transmission period may correspond to the period of the horizontal synchronization signal for processor 120 used for display on display panel 132. As a non-limiting example, the transmission period may be the period of the emission synchronization signal for the processor 120, which indicates the timing of the emission signal from the display driving circuit 131 to the display panel 132. We can respond.

The waveform of the pulse signal is distinct from the synchronization signal represented by the transmission period and represents the period of another synchronization signal for the processor 120, which is used or identified for display on the display panel 132. may be subject to change. As a non-limiting example, when the synchronization signal for the processor 120 represented by the transmission period is the horizontal synchronization signal for the processor 120, the waveform may be a vertical synchronization signal for the processor 120 and/or Based on the period of the light emission synchronization signal for the processor 120, it may be changed. For example, transmitted at a start timing of the horizontal sync signal for processor 120 that corresponds to (or overlaps) the start timing of the vertical sync signal (and/or the emission sync signal) for processor 120. The waveform of the pulse signal is different from (or does not overlap) the start timing of the vertical synchronization signal for the processor 120 and/or the luminescence synchronization signal for the processor 120. It may be a second waveform (and/or a third waveform) that is different from the first waveform, which is the waveform of the pulse signal transmitted at the start timing of the horizontal synchronization signal. As a non-limiting example, when the synchronization signal for the processor 120 represented by the transmission period is the emission synchronization signal for the processor 120, the waveform is the period of the vertical synchronization signal for the processor 120. It may be changed based on. For example, the waveform of the pulse signal transmitted at the start timing of the light emission synchronization signal for processor 120 corresponding to (or overlapping) the start timing of the vertical synchronization signal for processor 120 is: Different from the first waveform, which is the waveform of the pulse signal transmitted at a start timing of the light emission synchronization signal for processor 120 that is different from (or does not overlap) the start timing of the vertical synchronization signal for 120, It may be a second waveform.

The transmission period of the pulse signal and the waveform of the pulse signal can be illustrated in more detail below with reference to FIGS. 3, 4, and 5.

Referring to FIG. 3, the transmission period 301 of the pulse signal 393 may correspond to the period 302 of the horizontal synchronization signal 391 for the processor 120. For example, the transmission period 301 of the pulse signal 393 may represent the period 302 of the horizontal synchronization signal 391. For example, the pulse signal 393 may be a first time interval within the processor 120 corresponding to the period 302 of the horizontal synchronization signal 391 and the period of the horizontal synchronization signal for the display driving circuit 131. In order to synchronize the first time period within the display driving circuit 131 corresponding to, a transmission period 301 may be provided.

For example, the waveform of the pulse signal 393 may determine at least in part whether the start timing of the horizontal synchronization signal 391 overlaps (or corresponds to) the start timing of the emission synchronization signal 392 for the processor 120. Based on this, it may vary. For example, the width of the pulse signal 393 transmitted at the start timing of the horizontal synchronization signal 391 that overlaps the start timing of the light emission synchronization signal 392 is the start timing of the light emission synchronization signal 392. The width of the pulse signal 393 transmitted at the start timing of the horizontal synchronization signal 391 that does not overlap with the timing may be different.

For example, the waveform of the pulse signal 393 transmitted from the processor 120 to the display driving circuit 131 at the start timing 321 of the horizontal synchronization signal 391 that overlaps the start timing of the light emission synchronization signal 392. may be a second waveform, different from the first waveform, which is the waveform of the pulse signal 393 transmitted at the start timing 322 of the horizontal synchronization signal 391 that does not overlap with the start timing of the light emission synchronization signal 392. . For example, the width 312 of the pulse signal 393 transmitted at the start timing 321 of the horizontal synchronization signal 391 is the width 312 of the pulse signal 393 transmitted at the start timing 322 of the horizontal synchronization signal 391. ) may be different from the width (311). For example, the processor 120 changes the width of the pulse signal 393 to be transmitted from the width 311 to the width 312 at the start timing 321 of the horizontal synchronization signal 391, thereby generating the pulse signal 393. The above waveform can be changed. For example, the processor 120 changes the width of the pulse signal 393 to be transmitted from the width 312 to the width 311 at the start timing 322 of the horizontal synchronization signal 391, thereby generating the pulse signal 393. The above waveform can be changed.

For example, the start timing of the emission synchronization signal 392 identified according to the counting of the horizontal synchronization signal 391 within the processor 120 and the horizontal synchronization signal for the display driving circuit 131 within the display driving circuit 131. Since the start timing of the light emission synchronization signal for the display driving circuit 131 identified according to the counting of the synchronization signal may vary depending on the state of the processor 120 and/or the state of the display driving circuit 131, the processor 120 can provide information about the light emission synchronization signal 392 to the display driving circuit 131 by changing the waveform.

As a non-limiting example, when the processor 120 and the display 130 update the image according to the timing (or transmission timing) of the light emission signal, the pulse signal 393 is horizontally synchronized through the transmission period 301. The period 302 of the signal 391 may be indicated, and the period 303 of the emission synchronization signal 392 may be indicated through the width (eg, width 311 or width 312). However, it is not limited to this.

4 shows examples of pulse signals representing the timing of the horizontal synchronization signal and the timing of the vertical synchronization signal.

Referring to FIG. 4, the transmission period 401 of the pulse signal 493 may correspond to the period 402 of the horizontal synchronization signal 491 for the processor 120. For example, the transmission period 401 of the pulse signal 493 may represent the period 402 of the horizontal synchronization signal 491. For example, the pulse signal 493 may include a first time interval within the processor 120 corresponding to the period 402 of the horizontal synchronization signal 491 and the period of the horizontal synchronization signal for the display driving circuit 131. In order to synchronize the first time period within the display driving circuit 131 corresponding to, a transmission period 401 may be provided.

For example, the waveform of the pulse signal 493 may determine at least in part whether the start timing of the horizontal sync signal 491 overlaps (or corresponds to) the start timing of the vertical sync signal 492 for the processor 120. Based on this, it may vary. For example, the width of the pulse signal 493 transmitted at the start timing of the horizontal synchronization signal 491 that overlaps the start timing of the vertical synchronization signal 492 is the start timing of the vertical synchronization signal 492. The width of the pulse signal 493 transmitted at the start timing of the horizontal synchronization signal 491 that does not overlap with the timing may be different.

For example, the waveform of the pulse signal 493 transmitted from the processor 120 to the display driving circuit 131 at the start timing 421 of the horizontal synchronization signal 491 that overlaps the start timing of the vertical synchronization signal 492. may be a second waveform, different from the first waveform of the pulse signal 493 transmitted at the start timing 422 of the horizontal synchronization signal 491 that does not overlap with the start timing of the vertical synchronization signal 492. . For example, the width 412 of the pulse signal 493 transmitted at the start timing 421 of the horizontal synchronization signal 491 is the width 412 of the pulse signal 493 transmitted at the start timing 422 of the horizontal synchronization signal 491. ) may be different from the width 411. For example, the processor 120 changes the width of the pulse signal 493 to be transmitted from the width 411 to the width 412 at the start timing 421 of the horizontal synchronization signal 491, thereby generating the pulse signal 493. The above waveform can be changed. For example, the processor 120 changes the width of the pulse signal 493 to be transmitted from the width 412 to the width 411 at the start timing 422 of the horizontal synchronization signal 491, thereby generating the pulse signal 493. The above waveform can be changed.

For example, the start timing of the vertical synchronization signal 492 identified according to the counting of the horizontal synchronization signal 491 within the processor 120 and the horizontal synchronization signal for the display driving circuit 131 within the display driving circuit 131. Since the start timing of the vertical synchronization signal for the display driving circuit 131 identified according to the counting of the synchronization signal may vary depending on the state of the processor 120 and/or the state of the display driving circuit 131, the processor 120 can provide information about the vertical synchronization signal 492 to the display driving circuit 131 by changing the waveform.

5 illustrates an example method of changing the waveform of a pulse signal according to changes in the timing of the vertical sync signal.

Referring to FIG. 5, the processor 120 displays a period 502 (or timing (or start timing) of the horizontal synchronization signal 591) of the horizontal synchronization signal 591 for the processor 120, The pulse signal 594 can be transmitted to the display driving circuit 131 based on the transmission period 501. For example, the processor 120 may change the width of the pulse signal 594 to indicate the start timing (or timing) of the emission synchronization signal 592 for the processor 120. For example, processor 120 may change the width of pulse signal 594 to indicate the start timing of vertical sync signal 593 for processor 120. For example, the processor 120, at the start timing 521 of the horizontal synchronization signal 591 that does not overlap with the start timing of the light emission synchronization signal 592 and the start timing of the vertical synchronization signal 593, the width 512 ) and a pulse signal 594 having a width 511 different from the width 513 is transmitted to the display driving circuit 131, overlaps with the start timing of the light emission synchronization signal 592, and starts the vertical synchronization signal 593. At the start timing 522 of the horizontal synchronization signal 591 that does not overlap with the timing, a pulse signal 594 having a width 512 different from the width 511 and the width 513 is transmitted to the display driving circuit 131. And, at the start timing 523 of the horizontal synchronization signal 591 that overlaps the start timing of the light emission synchronization signal 592 and the start timing of the vertical synchronization signal 593, the width is different from the width 511 and the width 512. A pulse signal 594 having (513) can be transmitted.

For example, the processor 120 may change the timing of changing the waveform of the pulse signal in response to a change in the timing of the synchronization signal. For example, the timing (or start timing) of the vertical sync signal 593 may be changed. For example, if there is a delay in acquiring an image to be displayed on display panel 132 and/or rendering an image to be displayed on display panel 132, the timing of vertical synchronization signal 593 may be changed. . As a non-limiting example, the delay may be caused by the timing at which user input is received. As a non-limiting example, the delay may be caused by the load of the processor 120. As a non-limiting example, the delay may be caused by the number of layers that make up the image to be displayed on the display panel 132. As another example, the timing of the vertical synchronization signal 593 may change according to changes in the refresh rate. However, it is not limited to this.

For example, the processor 120 may change the start timing of the vertical synchronization signal 593 from the targeted timing 551 to the timing 552. Each of the targeted

timings

551 and 552 may overlap with the start timing of the light emission synchronization signal 592 for the processor 120. For example, timing 552 can be identified among the start timings of the light emission synchronization signal 592 after the desired timing 551.

For example, the processor 120 may change the waveform of the pulse signal 594 based on identifying the starting timing of the vertical sync signal 593 as a changed timing 552 from the desired timing 551. there is. For example, the processor 120 may generate a pulse signal 594 having a width 513 based on changing the start timing of the vertical synchronization signal 593 from the desired timing 551 to the changed timing 552. ) can be changed. For example, the processor 120 may determine the width 513 at the desired timing 551 based on identifying the starting timing of the vertical sync signal 593 as a changed timing 552 from the desired timing 551. ) to refrain from or bypass transmitting the pulse signal 594 with a width 513 to the display driving circuit 131 and transmit the pulse signal 594 with a width 513 to the display driving circuit 131 at timing 552. You can. For example, the processor 120 may determine the timing of the vertical synchronization signal for the display driving circuit 131 by transmitting a pulse signal 594 having a width 513 at timing 552 to the display driving circuit 131. You can request or notify the display driving circuit 131 to change .

As a non-limiting example, after the start timing of the vertical synchronization signal 593 is changed to timing 552, the period 503 of the vertical synchronization signal 593 may be restored. For example, when the period 503 is restored, the processor 120 may transmit a pulse signal 594 with a width 513 for each period 503.

Referring again to FIG. 1, the pulse signal is transmitted from the processor 120 to the display driver circuit 131 to provide a control command (or command) related to display on the display panel 132. It may be transmitted to the driving circuit 131. For example, the control command can be expressed by changing the waveform (or width) of the pulse signal. For example, the processor 120 may identify the control command to be provided to the display driving circuit 131 in connection with the display of an image on the display panel 132. For example, processor 120 may identify the control command to be synchronized with an image on display panel 132. For example, based on the identification, the processor 120 may change the waveform of the pulse signal periodically transmitted to the display driving circuit 131 to indicate the control command to the display driving circuit 131. there is. For example, the control command may be a control command (e.g., still indication (sticky flag) indicating storing the image in the GRAM (e.g., GRAM 220 of FIG. 2) in the display driving circuit 131. It may include an indication (sticky flag indication) and/or an on-the-fly indication. For example, the control command may include the refresh rate of the display panel 132 (or the processor ( 120) may include a control command indicating a change in the refresh rate of the image provided to the display driving circuit 131. For example, the control command may include a control indicating a change in the interface with respect to the image. It may include, but is not limited to, commands.

The waveform of the pulse signal that changes to represent the control command may be illustrated through a non-limiting example with reference to FIG. 6.

Referring to FIG. 6 , the processor 120 may transmit the first image to the display driving circuit 131 through the first path 201, as in state 601. The display driving circuit 131 may display the first image received from the processor 120 through the first path 201 on the display panel 132, as indicated by the arrow 611.

The processor 120 may transmit the second image to the display driving circuit 131 through the first path 201, as in state 602. The display driving circuit 131 may display the second image received from the processor 120 through the first path 201 on the display panel 132, as indicated by the arrow 612. As a non-limiting example, the second image may be at least partially different from the first image. As a non-limiting example, the second image may be the same as the first image. For example, the second image may be the first image transmitted again from the processor 120.

The processor 120 may identify a control command indicating storing the second image in the GRAM 220 to be provided to the display driving circuit 131 based on the second image. For example, the control command may be identified based on identifying that the time at which the first image was displayed on the display panel 132 is greater than or equal to a reference time. However, it is not limited to this. For example, the processor 120 displays the control command by changing the width of the pulse signal 692 transmitted to the display driving circuit 131 through the second path 202 based on the period 690. It can be provided to the driving circuit 131. For example, the processor 120 changes the width of the pulse signal 692 transmitted at timing 694 before the second image is provided to the display driving circuit 131 from width 693 to width 695. By changing, the control command can be provided to the display driving circuit 131. For example, timing 694 may be before the start timing 696 of the vertical synchronization signal 691 for the second image.

For example, the display driving circuit 131 may receive a pulse signal 692 having a width 695 from the processor 120. For example, display drive circuit 131 may, in response to a pulse signal 692 having a width 695 different from width 693, convert the second image to a GRAM, as indicated by arrow 613. It can be stored within (220). For example, the display drive circuit 131 may change from the first image to the second image, as indicated by arrow 614 (and/or generate a pulse signal 692 having a width 695). ), the second image stored in the GRAM 220 can be scanned. For example, display driving circuit 131 may re-display the second image on display panel 132, as indicated by arrow 615, based on scanning the second image. . For example, displaying the second image again on the display panel 132 is to reduce afterimages that may be caused on the display panel 132 due to a change from the first image to the second image. It can be executed. However, it is not limited to this.

Although not shown in Figure 6. The pulse signal 692 may further indicate the start timing (or timing) of the vertical synchronization signal 691. For example, the processor 120 may determine the width 693 and A pulse signal 692 having a width different from that of 695 may be transmitted to the display driving circuit 131 through the second path 202.

Although not shown in FIG. 6 , the pulse signal 692 may further indicate the start timing of the light emission synchronization signal for the processor 120 . For example, the processor 120, at the start timing of the horizontal synchronization signal that overlaps the start timing of the light emission synchronization signal, the start timing of the width 693, width 695, and vertical synchronization signal 691 ( A pulse signal 692 having a width different from the width for representing 696) may be transmitted to the display driving circuit 131 through the second path 202.

FIG. 7 is a block diagram of an electronic device 701 in a network environment 700, according to various embodiments. Referring to FIG. 7, in the network environment 700, the electronic device 701 communicates with the electronic device 702 through a first network 798 (e.g., a short-range wireless communication network) or a second network 799. It is possible to communicate with at least one of the electronic device 704 or the server 708 through (e.g., a long-distance wireless communication network). According to one embodiment, the electronic device 701 may communicate with the electronic device 704 through the server 708. According to one embodiment, the electronic device 701 includes a processor 720, a memory 730, an input module 750, an audio output module 755, a display module 760, an audio module 770, and a sensor module ( 776), interface 777, connection terminal 778, haptic module 779, camera module 780, power management module 788, battery 789, communication module 790, subscriber identification module 796 , or may include an antenna module 797. In various embodiments, at least one of these components (eg, the connection terminal 778) may be omitted, or one or more other components may be added to the electronic device 701. In various embodiments, some of these components (e.g., sensor module 776, camera module 780, or antenna module 797) are integrated into one component (e.g., display module 760). It can be.

The processor 720, for example, executes software (e.g., program 740) to operate at least one other component (e.g., hardware or software component) of the electronic device 701 connected to the processor 720. It can be controlled and various data processing or calculations can be performed. According to one embodiment, as at least part of data processing or computation, the processor 720 stores commands or data received from another component (e.g., sensor module 776 or communication module 790) in volatile memory 732. The commands or data stored in the volatile memory 732 can be processed, and the resulting data can be stored in the non-volatile memory 734. According to one embodiment, the processor 720 may include a main processor 721 (e.g., a central processing unit or an application processor) or an auxiliary processor 723 that can operate independently or together (e.g., a graphics processing unit, a neural network processing unit ( It may include a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor). For example, if the electronic device 701 includes a main processor 721 and a auxiliary processor 723, the auxiliary processor 723 may be set to use lower power than the main processor 721 or be specialized for a designated function. You can. The auxiliary processor 723 may be implemented separately from the main processor 721 or as part of it.

The auxiliary processor 723 may, for example, act on behalf of the main processor 721 while the main processor 721 is in an inactive (e.g., sleep) state, or while the main processor 721 is in an active (e.g., application execution) state. ), together with the main processor 721, at least one of the components of the electronic device 701 (e.g., the display module 760, the sensor module 776, or the communication module 790) At least some of the functions or states related to can be controlled. According to one embodiment, coprocessor 723 (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module 780 or communication module 790). there is. According to one embodiment, the auxiliary processor 723 (eg, neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. Artificial intelligence models can be created through machine learning. This learning may be performed, for example, in the electronic device 701 itself on which the artificial intelligence model is performed, or may be performed through a separate server (e.g., server 708). Learning algorithms may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but It is not limited. An artificial intelligence model may include multiple artificial neural network layers. Artificial neural networks include deep neural network (DNN), convolutional neural network (CNN), recurrent neural network (RNN), restricted boltzmann machine (RBM), belief deep network (DBN), bidirectional recurrent deep neural network (BRDNN), It may be one of deep Q-networks or a combination of two or more of the above, but is not limited to the examples described above. In addition to hardware structures, artificial intelligence models may additionally or alternatively include software structures.

The memory 730 may store various data used by at least one component (eg, the processor 720 or the sensor module 776) of the electronic device 701. Data may include, for example, input data or output data for software (e.g., program 740) and instructions related thereto. Memory 730 may include volatile memory 732 or non-volatile memory 734.

The program 740 may be stored as software in the memory 730 and may include, for example, an operating system 742, middleware 744, or application 746.

The input module 750 may receive commands or data to be used in a component of the electronic device 701 (e.g., the processor 720) from outside the electronic device 701 (e.g., a user). The input module 750 may include, for example, a microphone, mouse, keyboard, keys (eg, buttons), or digital pen (eg, stylus pen).

The sound output module 755 may output sound signals to the outside of the electronic device 701. The sound output module 755 may include, for example, a speaker or receiver. Speakers can be used for general purposes such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part of it.

The display module 760 can visually provide information to the outside of the electronic device 701 (eg, a user). The display module 760 may include, for example, a display, a hologram device, or a projector, and a control circuit for controlling the device. According to one embodiment, the display module 760 may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of force generated by the touch.

The audio module 770 can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module 770 acquires sound through the input module 750, the sound output module 755, or an external electronic device (e.g., directly or wirelessly connected to the electronic device 701). Sound may be output through an electronic device 702 (e.g., speaker or headphone).

The sensor module 776 detects the operating state (e.g., power or temperature) of the electronic device 701 or the external environmental state (e.g., user state) and generates an electrical signal or data value corresponding to the detected state. can do. According to one embodiment, the sensor module 776 includes, for example, a gesture sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, It may include a temperature sensor, humidity sensor, or light sensor.

The interface 777 may support one or more designated protocols that can be used to connect the electronic device 701 directly or wirelessly with an external electronic device (e.g., the electronic device 702). According to one embodiment, the interface 777 may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

The connection terminal 778 may include a connector through which the electronic device 701 can be physically connected to an external electronic device (eg, the electronic device 702). According to one embodiment, the connection terminal 778 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).

The haptic module 779 can convert electrical signals into mechanical stimulation (e.g., vibration or movement) or electrical stimulation that the user can perceive through tactile or kinesthetic senses. According to one embodiment, the haptic module 779 may include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

The camera module 780 can capture still images and moving images. According to one embodiment, the camera module 780 may include one or more lenses, image sensors, image signal processors, or flashes.

The power management module 788 can manage power supplied to the electronic device 701. According to one embodiment, the power management module 788 may be implemented as at least a part of, for example, a power management integrated circuit (PMIC).

Battery 789 may supply power to at least one component of electronic device 701. According to one embodiment, the battery 789 may include, for example, a non-rechargeable primary cell, a rechargeable secondary cell, or a fuel cell.

Communication module 790 is configured to provide a direct (e.g., wired) communication channel or wireless communication channel between electronic device 701 and an external electronic device (e.g., electronic device 702, electronic device 704, or server 708). It can support establishment and communication through established communication channels. Communication module 790 operates independently of processor 720 (e.g., an application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module 790 is a wireless communication module 792 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 794 (e.g., : LAN (local area network) communication module, or power line communication module) may be included. Among these communication modules, the corresponding communication module is a first network 798 (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network 799 (e.g., legacy It may communicate with an external electronic device 704 through a telecommunication network such as a cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., LAN or WAN). These various types of communication modules may be integrated into one component (e.g., a single chip) or may be implemented as a plurality of separate components (e.g., multiple chips). The wireless communication module 792 uses subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module 796 within a communication network such as the first network 798 or the second network 799. The electronic device 701 can be confirmed or authenticated.

The wireless communication module 792 may support 5G networks after 4G networks and next-generation communication technologies, for example, NR access technology (new radio access technology). NR access technology provides high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and access to multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low latency). -latency communications)) can be supported. The wireless communication module 792 may support high frequency bands (e.g., mmWave bands), for example, to achieve high data rates. The wireless communication module 792 uses various technologies to secure performance in high frequency bands, for example, beamforming, massive array multiple-input and multiple-output (MIMO), and full-dimensional multiplexing. It can support technologies such as input/output (FD-MIMO: full dimensional MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module 792 may support various requirements specified in the electronic device 701, an external electronic device (e.g., electronic device 704), or a network system (e.g., second network 799). According to one embodiment, the wireless communication module 792 supports peak data rate (e.g., 20 Gbps or more) for realizing eMBB, loss coverage (e.g., 164 dB or less) for realizing mmTC, or U-plane latency (e.g., 164 dB or less) for realizing URLLC. Example: Downlink (DL) and uplink (UL) each of 0.5 ms or less, or round trip 1 ms or less) can be supported.

The antenna module 797 may transmit or receive signals or power to or from the outside (e.g., an external electronic device). According to one embodiment, the antenna module 797 may include an antenna including a radiator including a conductor or a conductive pattern formed on a substrate (eg, PCB). According to one embodiment, the antenna module 797 may include a plurality of antennas (eg, an array antenna). In this case, at least one antenna suitable for the communication method used in the communication network, such as the first network 798 or the second network 799, is connected to the plurality of antennas by, for example, the communication module 790. can be selected Signals or power may be transmitted or received between the communication module 790 and an external electronic device through the at least one selected antenna. According to some embodiments, in addition to the radiator, other components (eg, radio frequency integrated circuit (RFIC)) may be additionally formed as part of the antenna module 797.

According to various embodiments, antenna module 797 may form a mmWave antenna module. According to one embodiment, a mmWave antenna module includes: a printed circuit board, an RFIC disposed on or adjacent to a first side (e.g., bottom side) of the printed circuit board and capable of supporting a designated high frequency band (e.g., mmWave band); And a plurality of antennas (e.g., array antennas) disposed on or adjacent to the second side (e.g., top or side) of the printed circuit board and capable of transmitting or receiving signals in the designated high frequency band. can do.

At least some of the components are connected to each other through a communication method between peripheral devices (e.g., bus, general purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)) and signal ( (e.g. commands or data) can be exchanged with each other.

According to one embodiment, commands or data may be transmitted or received between the electronic device 701 and the external electronic device 704 through the server 708 connected to the second network 799. Each of the external

electronic devices

702 or 704 may be of the same or different type as the electronic device 701. According to one embodiment, all or part of the operations performed in the electronic device 701 may be executed in one or more of the external

electronic devices

702, 704, or 708. For example, when the electronic device 701 needs to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device 701 may perform the function or service instead of executing the function or service on its own. Alternatively, or additionally, one or more external electronic devices may be requested to perform at least part of the function or service. One or more external electronic devices that have received the request may execute at least part of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device 701. The electronic device 701 may process the result as is or additionally and provide it as at least part of a response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology can be used. The electronic device 701 may provide an ultra-low latency service using, for example, distributed computing or mobile edge computing. In another embodiment, the external electronic device 704 may include an Internet of Things (IoT) device. Server 708 may be an intelligent server using machine learning and/or neural networks. According to one embodiment, the external electronic device 704 or server 708 may be included in the second network 799. The electronic device 701 may be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

Figure 8 is a block diagram 800 of the display module 760, according to various embodiments. Referring to FIG. 8, the display module 760 may include a display 810 and a display driver IC (DDI) 830 for controlling the display 810. The DDI 830 may include an interface module 831, a memory 833 (eg, buffer memory), an image processing module 835, or a mapping module 837. The various modules of DDI may include various processing circuits and/or executable program instructions. For example, the DDI 830 receives image information including image data or an image control signal corresponding to a command for controlling the image data from other components of the electronic device 701 through the interface module 831. can do. For example, according to one embodiment, image information is stored in the processor 720 (e.g., the main processor 721 (e.g., an application processor) or an auxiliary processor 723 (e.g., an application processor) that operates independently of the functions of the main processor 721 ( For example: a graphics processing unit). The DDI 830 can communicate with the touch circuit 850 or the sensor module 776, etc. through the interface module 831. In addition, the DDI 830 can communicate with the touch circuit 850 or the sensor module 776, etc. At least a portion of the received image information may be stored, for example, in frame units, in the memory 833. The image processing module 835 may, for example, store at least a portion of the image data in accordance with the characteristics or characteristics of the image data. Preprocessing or postprocessing (e.g., resolution, brightness, or size adjustment) may be performed based at least on the characteristics of the display 810. The mapping module 837 performs preprocessing or postprocessing through the image processing module 835. A voltage value or current value corresponding to the image data may be generated. According to one embodiment, the generation of the voltage value or current value may be performed by, for example, an attribute of the pixels of the display 810 (e.g., an array of pixels ( RGB stripe or pentile structure), or the size of each subpixel). At least some pixels of the display 810 may be performed at least in part based on, for example, the voltage value or the current value. When driven, visual information (eg, text, image, or icon) corresponding to the image data may be displayed through the display 810.

According to one embodiment, the display module 760 may further include a touch circuit 850. The touch circuit 850 may include a touch sensor 851 and a touch sensor IC 853 for controlling the touch sensor 851. For example, the touch sensor IC 853 may control the touch sensor 851 to detect a touch input or hovering input for a specific position of the display 810. For example, the touch sensor IC 853 may detect a touch input or hovering input by measuring a change in a signal (e.g., voltage, light amount, resistance, or charge amount) for a specific position of the display 810. The touch sensor IC 853 may provide information (e.g., location, area, pressure, or time) about the detected touch input or hovering input to the processor 720. According to one embodiment, at least a portion of the touch circuit 850 (e.g., touch sensor IC 853) is disposed as part of the display driver IC 830, the display 810, or outside the display module 760. It may be included as part of other components (e.g., auxiliary processor 723).

According to one embodiment, the display module 760 may further include at least one sensor (eg, a fingerprint sensor, an iris sensor, a pressure sensor, or an illumination sensor) of the sensor module 776, or a control circuit therefor. In this case, the at least one sensor or control circuit therefor may be embedded in a part of the display module 760 (eg, the display 810 or the DDI 830) or a part of the touch circuit 850. For example, when the sensor module 776 embedded in the display module 760 includes a biometric sensor (e.g., a fingerprint sensor), the biometric sensor records biometric information associated with a touch input through a portion of the display 810. (e.g. fingerprint image) can be acquired. For another example, if the sensor module 776 embedded in the display module 760 includes a pressure sensor, the pressure sensor may acquire pressure information associated with a touch input through part or the entire area of the display 810. You can. According to one embodiment, the touch sensor 851 or the sensor module 776 may be disposed between pixels of a pixel layer of the display 810, or above or below the pixel layer.

As described above, the electronic device includes a processor, a display including a display driving circuit and a display panel, a first path connecting the processor and the display driving circuit, and connecting the processor and the display driving circuit, It may include a second path, separated from the first path. According to one embodiment, the processor, a first time period within the processor used to display an image transmitted to the display driving circuit through the first path on the display panel, and a first time period within the processor used to display the image on the display panel. and transmit, based on a first period, a pulse signal to the display driving circuit through the second path to synchronize the first time period in the display driving circuit used for display on the display. . According to one embodiment, the processor is configured to: a second time period within the processor used for the display of the image and a second time period within the display driving circuit used for the display of the image. It may be configured to change the waveform of the pulse signal transmitted based on the first cycle from the first waveform to the second waveform based on a second cycle different from the first cycle in order to synchronize.

According to one embodiment, the first path may be deactivated within at least a portion of the time period during which it stops transmitting images from the processor to the display driving circuit. According to one embodiment, the processor may be configured to maintain transmitting the pulse signal to the display driving circuit through the second path while the first path is deactivated.

According to one embodiment, the display driving circuit may include graphic random access memory (GRAM). According to one embodiment, the first path is disabled within at least a portion of a time period in which the display driving circuit performs display on the display panel by scanning an image in the GRAM received from the processor. You can. According to one embodiment, the processor may be configured to maintain transmitting the pulse signal to the display driving circuit through the second path while the first path is deactivated.

According to one embodiment, the second time period may be longer than the first time period.

According to one embodiment, the first time period may correspond to the period of the horizontal synchronization signal. According to one embodiment, the second time period may correspond to the period of the vertical synchronization signal. According to one embodiment, the processor converts the pulse signal having the second waveform into a first signal corresponding to a start timing of the vertical synchronization signal used in the processor among transmission timings according to the first period. At transmission timings, it may be configured to transmit to the display driving circuit via the second path. According to one embodiment, the processor transmits the pulse signal having the first waveform to the display driving circuit through the second path at second transmission timings that are each different from the start timing among the transmission timings. , may be configured to transmit.

According to one embodiment, the first time period may correspond to the period of the horizontal synchronization signal. According to one embodiment, the second time period may correspond to a period of a light emission synchronization signal indicating a transmission timing of a light emission signal from the display driving circuit to the display panel. According to one embodiment, the processor may convert the pulse signal having the second waveform into a first signal corresponding to a start timing of the light emission synchronization signal used within the processor among transmission timings according to the first period. At transmission timings, it may be configured to transmit to the display driving circuit via the second path. According to one embodiment, the processor transmits the pulse signal having the first waveform to the display driving circuit through the second path at second transmission timings that are each different from the start timing among the transmission timings. , may be configured to transmit.

According to one embodiment, the processor may be configured to change the waveform from the first waveform to the second waveform by changing the width of the pulse signal.

According to one embodiment, the processor may be configured to identify control commands to be provided to the display driving circuitry in connection with the display of the image on the display panel. According to one embodiment, the processor may be configured to change the waveform into a third waveform different from the first waveform and the second waveform to indicate the control command to the display driving circuit.

According to one embodiment, the control command may include a control command indicating storing the image in the GRAM.

According to one embodiment, the control command may include a control command indicating changing the refresh rate of the image provided from the processor to the display driving circuit.

As described above, the electronic device includes a processor, a display including a display driving circuit and a display panel, a first path connecting the processor and the display driving circuit, and connecting the processor and the display driving circuit, It may include a second path, separated from the first path. According to one embodiment, the processor is configured to display the image on the display panel and a time interval within the processor used to display the image transmitted to the display driving circuit through the first path on the display panel. and may be configured to periodically transmit a pulse signal to the display driving circuit through the second path to synchronize the time interval within the display driving circuit used to do so. According to one embodiment, the processor may be configured to identify control commands to be provided to the display driving circuitry in connection with the display of the image on the display panel. According to one embodiment, the processor changes the waveform of the pulse signal periodically transmitted to the display driving circuit from a first waveform to a second waveform to indicate the control command to the display driving circuit based on the identification. It can be configured to change.

According to one embodiment, the display driving circuit may include graphic random access memory (GRAM). According to one embodiment, the control command may include a control command indicating storing the image in the GRAM.

According to one embodiment, the first path is disabled within at least a portion of a time period in which the display driving circuit performs display on the display panel by scanning an image in the GRAM received from the processor. You can. According to one embodiment, the processor may be configured to maintain transmitting the pulse signal to the display driving circuit through the second path while the first path is deactivated.

According to one embodiment, the processor may be configured to periodically transmit the pulse signal by transmitting the pulse signal based on the first period. According to one embodiment, the processor synchronizes the different time intervals within the processor used for the display of the image with the different time intervals within the display driving circuit used for the display of the image. In order to do so, the waveform of the pulse signal transmitted based on the first cycle may be configured to change from the first waveform or the second waveform to a third waveform based on a second cycle different from the first cycle. there is.

According to one embodiment, the other time section may be longer than the time section.

According to one embodiment, the time section may correspond to the period of the horizontal synchronization signal. According to one embodiment, the different time intervals may correspond to the period of the vertical synchronization signal. According to one embodiment, the processor converts the pulse signal having the third waveform into a first signal corresponding to a start timing of the vertical synchronization signal used in the processor among transmission timings according to the first period. At transmission timings, it may be configured to transmit to the display driving circuit via the second path. According to one embodiment, the processor transmits the pulse signal having the first waveform to the display driving circuit through the second path at second transmission timings that are each different from the start timing among the transmission timings. , may be configured to transmit.

According to one embodiment, the second transmission timings may be different from third transmission timings for indicating the control command among the transmission timings.

Electronic devices according to various embodiments disclosed in this document may be of various types. Electronic devices may include, for example, portable communication devices (eg, smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, home appliances, etc. Electronic devices according to embodiments of this document are not limited to the above-described devices.

The various embodiments of this document and the terms used herein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various changes, equivalents, or replacements of the embodiments. In connection with the description of the drawings, similar reference numbers may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the above items, unless the relevant context clearly indicates otherwise. As used herein, “A or B”, “at least one of A and B”, “at least one of A or B”, “A, B or C”, “at least one of A, B and C”, and “A Each of phrases such as “at least one of , B, or C” may include any one of the items listed together in the corresponding phrase, or any possible combination thereof. Terms such as "first", "second", or "first" or "second" may be used simply to distinguish one component from another, and to refer to that component in other respects (e.g., importance or order) is not limited. One (e.g., first) component is said to be “coupled” or “connected” to another (e.g., second) component, with or without the terms “functionally” or “communicatively.” Where mentioned, it may be that any of the components can be connected to the other components directly (e.g. wired), wirelessly, or through a third component.

The term “module” used in various embodiments of this document may include a unit implemented with hardware, software, firmware, or a combination thereof, for example, terms such as logic, logic block, component, or circuit. Can be used interchangeably with . A module may be an integrated part or a minimum unit of the parts or a part thereof that performs one or more functions. For example, according to one embodiment, the module may be implemented in the form of an application-specific integrated circuit (ASIC).

Various embodiments of this document are one or more instructions stored in a storage medium (e.g., built-in memory 736 or external memory 738) that can be read by a machine (e.g., electronic device 701). It may be implemented as software (e.g., program 740) including these. For example, a processor (e.g., processor 720) of a device (e.g., electronic device 701) may call at least one command among one or more commands stored from a storage medium and execute it. This allows the device to be operated to perform at least one function according to the at least one instruction called. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. A storage medium that can be read by a device may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' means that the storage medium is a tangible device and does not contain signals (e.g. electromagnetic waves). This term refers to cases where data is stored semi-permanently in the storage medium and data stored temporarily. There is no distinction between cases.

According to one embodiment, methods according to various embodiments disclosed in this document may be included and provided in a computer program product. Computer program products are commodities and can be traded between sellers and buyers. The computer program product may be distributed in the form of a machine-readable storage medium (e.g. compact disc read only memory (CD-ROM)) or through an application store (e.g. Play Store™) or on two user devices (e.g. It can be distributed (e.g. downloaded or uploaded) directly between smart phones) or online. In the case of online distribution, at least a portion of the computer program product may be at least temporarily stored or temporarily created in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

According to various embodiments, each component (e.g., module or program) of the above-described components may include a single or plural entity, and some of the plurality of entities may be separately placed in other components. there is. According to various embodiments, one or more of the components or operations described above may be omitted, or one or more other components or operations may be added. Alternatively or additionally, multiple components (eg, modules or programs) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each component of the plurality of components in the same or similar manner as those performed by the corresponding component of the plurality of components prior to the integration. . According to various embodiments, operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, or omitted. Alternatively, one or more other operations may be added.

Claims

In electronic devices,

processor;

A display including a display driving circuit and a display panel;

a first path connecting the processor and the display driving circuit; and

A second path connects the processor and the display driving circuit and is separated from the first path,

The processor,

A first time period in the processor used to display on the display panel an image transmitted to the display driving circuit through the first path and the display driving circuit used to display the image on the display panel transmitting, based on a first period, a pulse signal to the display driving circuit through the second path to synchronize the first time interval within the first period;

Based on the first period to synchronize the second time period in the processor used for the display of the image with the second time period in the display driver circuit used for the display of the image configured to change the waveform of the transmitted pulse signal from a first waveform to a second waveform based on a second period different from the first period,

Electronic devices.
The method of claim 1, wherein the first path is:

configured to be deactivated within at least a portion of the time period that stops transmitting images from the processor to the display driving circuit;

The processor,

configured to maintain transmitting the pulse signal to the display driving circuit via the second path while the first path is deactivated,

Electronic devices.
The method according to claim 1, wherein the display driving circuit:

Contains graphic random access memory (GRAM),

The first path is,

wherein the display drive circuit is configured to be disabled within at least a portion of a time interval for performing display on the display panel by scanning images in the GRAM received from the processor,

The processor,

configured to maintain transmitting the pulse signal to the display driving circuit via the second path while the first path is deactivated,

Electronic devices.
The method of claim 1, wherein the second time period is,

longer than the first time interval,

Electronic devices.
The method of claim 4, wherein the first time period is,

Corresponds to the period of the horizontal synchronization signal,

The second time section is,

Corresponds to the period of the vertical synchronization signal,

The processor,

The pulse signal having the second waveform is transmitted through the second path at first transmission timings that respectively correspond to the start timing of the vertical synchronization signal used within the processor among transmission timings according to the first cycle. transmitting to the display driving circuit through,

configured to transmit the pulse signal having the first waveform to the display driving circuit through the second path at second transmission timings that are each different from the start timing among the transmission timings,

Electronic devices.
The method of claim 4, wherein the first time period is,

Corresponds to the period of the horizontal synchronization signal,

The second time section is,

Corresponds to the period of the light emission synchronization signal indicating the transmission timing of the light emission signal from the display driving circuit to the display panel,

The processor,

The pulse signal having the second waveform is transmitted through the second path at first transmission timings that respectively correspond to the start timing of the light emission synchronization signal used within the processor among transmission timings according to the first cycle. transmitting to the display driving circuit through,

configured to transmit the pulse signal having the first waveform to the display driving circuit through the second path at second transmission timings that are each different from the start timing among the transmission timings,

Electronic devices.
The method of claim 1, wherein the processor:

configured to change the waveform from the first waveform to the second waveform by changing the width of the pulse signal,

Electronic devices.
The method of claim 1, wherein the processor:

identify control instructions to be provided to the display driving circuitry in connection with the display of the image on the display panel;

further configured to change the waveform to a third waveform different from the first waveform and the second waveform to indicate the control command to the display driving circuit,

Electronic devices.
The method of claim 8, wherein the display driving circuit:

Contains graphic random access memory (GRAM),

The control command is,

Containing a control command indicating storing the image in the GRAM,

Electronic devices.
The method of claim 8, wherein the control command is:

Comprising a control command indicating changing the refresh rate of the image provided from the processor to the display driving circuit,

Electronic devices.
A display including a processor, a display driving circuit, and a display panel, a first path connecting the processor and the display driving circuit, connecting the processor and the display driving circuit, and being separated from the first path. from), in a method executed within an electronic device comprising a second path,

A first time period in the processor used to display on the display panel an image transmitted to the display driving circuit through the first path and the display driving circuit used to display the image on the display panel An operation of the processor transmitting, based on a first period, a pulse signal to the display driving circuit through the second path to synchronize the first time period within the first period;

Based on the first period to synchronize the second time period in the processor used for the display of the image with the second time period in the display driver circuit used for the display of the image A method comprising an operation of the processor changing the waveform of the transmitted pulse signal from a first waveform to a second waveform based on a second period different from the first period.
The method of claim 11, wherein the first path is:

configured to be deactivated within at least a portion of the time period that stops transmitting images from the processor to the display driving circuit;

The operation of transmitting the pulse signal is,

comprising the processor maintaining transmission of the pulse signal to the display driving circuit through the second path while the first path is deactivated,

method.
In claim 11,

The second time section is,

longer than the first time interval,

method.
The method of claim 11, wherein the operation of changing the waveform comprises:

Including an operation of the processor changing the waveform from the first waveform to the second waveform by changing the width of the pulse signal,

method.
In claim 11,

an operation of the processor identifying control instructions to be provided to the display driving circuit in connection with the display of the image on the display panel;

Including an operation of the processor changing the waveform to a third waveform different from the first waveform and the second waveform to indicate the control command to the display driving circuit,

method.