WO2024067226A1 - 一种平衡式射频功率放大器、射频前端模块及电子设备 - Google Patents

一种平衡式射频功率放大器、射频前端模块及电子设备 Download PDF

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WO2024067226A1
WO2024067226A1 PCT/CN2023/119549 CN2023119549W WO2024067226A1 WO 2024067226 A1 WO2024067226 A1 WO 2024067226A1 CN 2023119549 W CN2023119549 W CN 2023119549W WO 2024067226 A1 WO2024067226 A1 WO 2024067226A1
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power amplifier
output
capacitor
inductor
power
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PCT/CN2023/119549
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English (en)
French (fr)
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陈岗
白云芳
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唯捷创芯(天津)电子技术股份有限公司
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Publication of WO2024067226A1 publication Critical patent/WO2024067226A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present invention relates to a balanced radio frequency power amplifier, and also relates to a radio frequency front-end module including the balanced radio frequency power amplifier and corresponding electronic equipment, belonging to the technical field of radio frequency integrated circuits.
  • the RF power amplifier (RF power amplifier) is an important component of the RF front-end module, and its main technical performance indicators such as bandwidth, gain, loss, linearity, transmission power and efficiency, as well as service life and area size are particularly important.
  • the RF power amplifier is the device with the highest power consumption, and reducing the power consumption of the RF power amplifier is also the most effective way to increase the service life of the equipment.
  • the RF power amplifier architecture and the antenna standing wave ratio are two crucial factors to improve the efficiency of the RF power amplifier.
  • the antenna standing wave ratio will change with the change of the usage scenario, and its change will directly affect the load line of the RF power amplifier, and then affect its transmission power and transmission efficiency.
  • the three frequency bands of n41, n77 and n79 have high frequencies and large spatial path attenuation.
  • the mobile standard requires that the three frequency bands need to transmit PC2 level transmission power, that is, the antenna transmission power is 26dBm.
  • This high transmission power will cause the DC power consumption of the RF power amplifier to increase, and under the condition of the same transmission efficiency, the heating of the RF power amplifier will also be more serious, causing the battery to consume faster and the standby time to be shortened. Therefore, in the case of PC2 level transmission power, it is necessary to further optimize the linearity of the RF power amplifier and improve the efficiency of the RF power amplifier to solve the above problems.
  • the bandwidths of the three frequency bands of n41, n77 and n79 are 200MHz, 900MHz and 600MHz respectively, and the maximum bandwidth of the RF signal is 200MHz. Therefore, it is also necessary to increase the bandwidth of the RF power amplifier and improve the linearity of the RF power amplifier under broadband signals.
  • the primary technical problem to be solved by the present invention is to provide a balanced radio frequency power amplifier Great talent.
  • Another technical problem to be solved by the present invention is to provide a radio frequency front-end module including the balanced radio frequency power amplifier and corresponding electronic equipment.
  • a balanced radio frequency power amplifier comprising a driving stage power unit, an inter-stage power divider, a main power amplifier, an auxiliary power amplifier, a first output matching network A, a second output matching network B and an output power synthesizer; wherein,
  • the input end of the driving stage power unit receives the input radio frequency signal, and the output end is connected to the input end of the inter-stage power distributor, and is used to drive and amplify the input radio frequency signal;
  • the in-phase output end of the inter-stage power divider is connected to the input end of the main power amplifier, and the orthogonal phase output end is connected to the input end of the auxiliary power amplifier, so as to generate two RF signals with equal amplitude and 90° phase difference;
  • the output end of the main power amplifier is connected to the input end of the first output matching network A, and the output end of the auxiliary power amplifier is connected to the input end of the second output matching network B;
  • the output end of the first output matching network A is connected to the in-phase input end of the output power synthesizer, and the output end of the second output matching network B is connected to the orthogonal phase input end of the output power synthesizer;
  • the output power synthesizer is used to receive two radio frequency signals with the same amplitude and a phase difference of 90°, and synthesize one output radio frequency signal.
  • the inter-stage power divider is composed of a 3dB distributed orthogonal coupler composed of metal coupling lines on a chip, wherein a chip metal stacked coupling structure or a same-layer coupling structure is adopted.
  • the output power combiner is composed of a 3dB distributed orthogonal coupler composed of metal coupling lines on a substrate, wherein a substrate metal stacked coupling structure or a same-layer coupling structure is adopted.
  • the main power amplifier is composed of a first capacitor C9, a first inductor L9, a first transistor M1, a linearization circuit and a bias circuit; wherein the input end of the main power amplifier is connected to the first capacitor C9, the first inductor L9 and the linearization circuit, the other end of the first inductor L9 is connected to the ground potential end, the other end of the first capacitor C9 is connected to the gate of the first transistor M1 and the bias circuit, the source of the first transistor M1 is connected to the ground potential end The drain of the first transistor M1 is connected to the output end of the main power amplifier; wherein the first capacitor C9 and the first inductor L9 form an input matching network.
  • the linearization circuit is composed of a resistor connected in series and a diode group connected in forward and reverse parallel; wherein the resistor end is connected to the input end of the power amplifier circuit, and the diode end is connected to the ground potential end;
  • the linearization circuit reduces the pre-distortion amplitude by increasing the number of diodes connected in series, and strengthens the pre-distortion amplitude by increasing the number of diodes connected in parallel or the area of the diodes.
  • the bias circuit is composed of a seventh resistor R7, an eighth resistor R8, a third capacitor C5, a third transistor T1, and a fourth transistor T2; wherein the drain of the third transistor T1 is connected to the seventh resistor R7 and then connected to the bias voltage terminal, the gate of the third transistor T1 is connected to the other end of the seventh resistor R7 and the third capacitor C5 and the drain of the fourth transistor T2, the other end of the third capacitor C5 is connected to the ground potential terminal, the source of the fourth transistor T2 is connected to the ground potential terminal, and the gate of the fourth transistor T2 is connected to the source of the third transistor T1 and the bias current output terminal through the eighth resistor R8;
  • the third transistor T1 is an emitter follower transistor, and the fourth transistor T2 is a feedback amplifier transistor.
  • the first output matching network A and the second output matching network B are both high-bandwidth matching networks composed of lumped components;
  • the first output matching network A is composed of a fourth capacitor C1, a fifth capacitor C2, a sixth capacitor C3, a seventh capacitor C4, and a third inductor L1, a fourth inductor L2, a fifth inductor L3 and a sixth inductor L4; wherein the input end of the first output matching network A is connected to the fifth capacitor C2, the sixth capacitor C3 and the third inductor L1 respectively; the other end of the fifth capacitor C2 is connected to the fourth inductor L2, and the other end of the fourth inductor L2 is connected to the ground potential end; the other end of the third inductor L1 is connected to the power supply voltage end and the fourth capacitor C1, and the other end of the fourth capacitor C1 is connected to the ground potential end; the other end of the sixth capacitor C3 is connected to the fifth inductor L3 and the sixth inductor L4, the other end of the fifth inductor L3 is connected to the ground potential end, the other end of the sixth inductor L4 is connected to the seventh capacitor C4 and the output end
  • the fourth capacitor C1 is a power supply filter capacitor, and the first output matching network A and the second output matching network B share a power supply filter capacitor;
  • the fifth capacitor C2 and the fourth inductor L2 are connected in series to form a harmonic Vibration network, the fifth capacitor C2 is a variable capacitor;
  • the sixth capacitor C3, the seventh capacitor C4, the fifth inductor L3 and the sixth inductor L4 form a CLLC type impedance matching network.
  • the load line impedance of the main power amplification unit and the load line impedance of the auxiliary power amplification unit of the balanced RF power amplifier change alternately, and the output power and output current of the two power amplification units also change alternately, so that the changes compensate each other.
  • a radio frequency front-end module which is implemented based on the above-mentioned balanced radio frequency power amplifier, and includes a substrate, at least one radio frequency power amplifier chip, at least one power supply and control chip, and a group of output matching networks and output power synthesizers; wherein,
  • the driving stage power unit, the inter-stage power distributor, the main power amplifier and the auxiliary power amplifier in the balanced RF power amplifier are all integrated on the RF power amplifier chip;
  • the radio frequency power amplifier chip and the substrate are packaged in a face-up packaging manner or a flip-chip packaging manner;
  • the output ends of the main power amplifier and the auxiliary power amplifier are respectively connected to the first output matching network A and the second output matching network B through metal wire bonding, and are respectively directly connected to the first output matching network A and the second output matching network B through copper pillars or implant balls.
  • an electronic device comprising the above-mentioned balanced radio frequency power amplifier.
  • the balanced RF power amplifier provided by the present invention, on the one hand, overcomes the influence of the change of the antenna standing wave ratio on the transmission power and transmission efficiency to the greatest extent by adopting a balanced design in which the main power amplifier unit and the auxiliary power amplifier unit are symmetrical to each other.
  • a 3dB distributed orthogonal coupler to design the power divider and the power combiner, and implementing them at the chip level and on the substrate respectively, the area size and bandwidth, insertion loss, transmission efficiency and other performance indicators of the RF power amplifier are optimally compromised and optimized.
  • the gain distortion and phase distortion of the power amplifier are improved, and better linearity is obtained.
  • the balanced RF power amplifier provided by the present invention has the beneficial effects of ingenious and reasonable circuit design, strong flexibility, and excellent circuit performance, and is more in line with the requirements of the technical performance indicators of the 5G communication system.
  • FIG1 is a structural block diagram of a balanced RF power amplifier provided by an embodiment of the present invention.
  • FIG2 is a circuit diagram of a balanced RF power amplifier in an embodiment of the present invention.
  • FIG3( a ) is a schematic circuit diagram of a first solution of a linearization circuit in an embodiment of the present invention
  • FIG3( b ) is a circuit diagram of a second solution of a linearization circuit in an embodiment of the present invention.
  • FIG3( c ) is a circuit schematic diagram of a third solution of a linearization circuit in an embodiment of the present invention.
  • FIG4 is a diagram showing the predistortion behavior of a linearization circuit in an embodiment of the present invention.
  • FIG5( a) is a circuit schematic diagram of a bias circuit in an embodiment of the present invention.
  • FIG5( b ) is a circuit schematic diagram of a typical bias circuit in the prior art
  • FIG6 is a comparison diagram of simulation tests of the output impedance of the bias circuit of the technical solution of the present invention and the prior art solution;
  • FIG. 7 is a schematic structural diagram of a 3dB distributed orthogonal coupler using a stacked circuit design in an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a 3dB distributed orthogonal coupler using a same-layer circuit design in an embodiment of the present invention.
  • FIG. 9 is a simulation test diagram of performance indicators such as insertion loss, isolation and reflection coefficient of the output power synthesizer in the n77 operating frequency band in an embodiment of the present invention.
  • FIG. 10 is a simulation test curve diagram of load line impedance of the main power amplification unit and the auxiliary power amplification unit as the antenna phase changes in an embodiment of the present invention
  • FIG11 is a simulation test curve diagram showing the output power of a balanced RF power amplifier changing with antenna phase in an embodiment of the present invention
  • FIG12 is a simulation test curve diagram of the operating current of a balanced RF power amplifier changing with antenna phase in an embodiment of the present invention
  • 13 is a simulation test diagram of performance indicators such as gain, efficiency, and linearity of a balanced RF power amplifier in the n77 frequency band in an embodiment of the present invention
  • FIG14 is a schematic diagram of the layout of a balanced RF power amplifier in an embodiment of the present invention.
  • FIG. 15 is an electronic device of a balanced RF power amplifier according to an embodiment of the present invention. Example diagram of the equipment.
  • a balanced RF power amplifier provided in an embodiment of the present invention includes a driving stage power unit 101, an inter-stage power divider 102, a main power amplifier 103, an auxiliary power amplifier 104, a first output matching network A105, a second output matching network B106 and an output power synthesizer 107, as well as an RF signal input terminal and an RF signal output terminal.
  • the RF signal input end is connected to the input end of the driving stage power unit 101, and the output end of the driving stage power unit 101 is connected to the input end of the inter-stage power divider 102;
  • the in-phase output end of the inter-stage power divider 102 is connected to the input end of the main power amplifier 103, the output end of the main power amplifier 103 is connected to the input end of the first output matching network A105, and the output end of the first output matching network A105 is connected to the in-phase input end of the output power synthesizer 107;
  • the orthogonal phase output end of the inter-stage power divider 102 is connected to the input end of the auxiliary power amplifier 104, the output end of the auxiliary power amplifier 104 is connected to the input end of the second output matching network B106, and the output end of the second output matching network B106 is connected to the orthogonal phase input end of the output power synthesizer 107;
  • the output end of the output power synthesizer 107 is connected to the RF signal output end
  • the driving stage power unit 101 is used to drive and amplify the input radio frequency signal and then output it to the inter-stage power divider 102. It can be a single-stage power unit or a two-stage power unit.
  • the interstage power divider 102 is used to generate two RF signals with equal amplitude and 90° phase difference after receiving one input RF signal, and output them to the main power amplifier 103 and the auxiliary power amplifier 104 respectively. It is realized by a 3dB distributed orthogonal coupler composed of metal coupling lines on the chip.
  • the main power amplifier 103 and the auxiliary power amplifier 104 are mainly used to amplify the respective input radio frequency signals. They are both single-stage amplifiers with linearization circuits and bias circuits, and the circuit structures are symmetrical to each other, and the circuit element parameters are equal or close.
  • the first output matching network A105 and the second output matching network B106 are used to match the output impedance of the main power amplifier 103 and the auxiliary power amplifier 104 to the characteristic impedance of the output power combiner 107. They are both high-bandwidth LC matching networks composed of lumped components.
  • the output power synthesizer 107 is used to receive two RF signals with the same amplitude and a phase difference of 90° and then synthesize one RF signal for output. It is implemented by a 3dB distributed orthogonal coupler composed of metal coupling lines on the substrate.
  • the driving stage power unit 101 when the RF signal input end receives the input RF signal, the driving stage power unit 101 first drives and amplifies the input RF signal, and outputs the amplified RF signal to the inter-stage power divider 102; the inter-stage power divider 102 divides the RF signal into two RF signals with the same amplitude and a phase difference of 90°, wherein the RF signal with a phase of +45° (in phase) is output to the main power amplifier 103, and the RF signal with a phase of -45° (orthogonal phase) is output to the auxiliary power amplifier 104; after the two RF signals with a phase difference of 90° are amplified by the main power amplifier 103 and the auxiliary power amplifier 104 respectively, the two amplified RF signals enter the two input ends of the output power synthesizer 107 respectively through the first output matching network A105 and the second output matching network B106, and the output power synthesizer 107 synthesizes
  • a balanced RF power amplifier includes a driver stage power unit 201, an inter-stage power divider 202, a main power amplifier 203, an auxiliary power amplifier 204, a first output matching network A 205, a second output matching network B 206, and an output power synthesizer 207.
  • a driver stage power unit 201 includes a driver stage power unit 201, an inter-stage power divider 202, a main power amplifier 203, an auxiliary power amplifier 204, a first output matching network A 205, a second output matching network B 206, and an output power synthesizer 207.
  • the driving stage power unit 201 can be composed of a single-stage power unit or a two-stage power unit, whose input end is connected to the RF signal input end, and whose output end is connected to the input end of the inter-stage power divider 202. Its main function is to drive and amplify the input RF signal.
  • the inter-stage power divider 202 is composed of a 3dB distributed orthogonal coupler composed of metal coupling lines on the chip, and has four terminals. Among them, the first terminal is the input terminal, which is connected to the output terminal of the driving stage power unit 201; the second terminal is the ground terminal, which is connected to the ground potential terminal through the first resistor R1; the third terminal is the in-phase output terminal, which is connected to the input terminal of the main power amplifier 203; the fourth terminal is the orthogonal phase output terminal, which is connected to the input terminal of the auxiliary power amplifier 204.
  • the main function of the interstage power divider 202 is to generate two output RF signals with equal amplitudes and a phase difference of 90° after receiving one input RF signal.
  • the coupler is composed of a chip metal stacked coupling structure or a same-layer coupling structure, and the coupling coefficient of the coupler can be changed by adding capacitor components. Its circuit structure has excellent performances of large bandwidth, small area, and convergent port impedance. The disadvantage is that the insertion loss is slightly large, but it is acceptable in mobile communication terminals.
  • the main power amplifier 203 is composed of a first capacitor C9, a first inductor L9, a first transistor M1, a linearization circuit and a bias circuit.
  • the in-phase output end of the inter-stage power distributor 202 is connected to the input end of the main power amplifier 203, the input end of the main power amplifier 203 is connected to the first capacitor C9, the first inductor L9 and the linearization circuit, the other end of the first inductor L9 is connected to the ground potential end, the other end of the first capacitor C9 is connected to the gate of the first transistor M1 and the bias circuit, the source of the first transistor M1 is connected to the ground potential end, the drain of the first transistor M1 is connected to the output end of the main power amplifier 203, and the output end of the main power amplifier 203 is connected to the input end of the first output matching network A205.
  • the first capacitor C9 and the first inductor L9 form an input matching network.
  • the auxiliary power amplifier 204 is composed of a second capacitor C10, a second inductor L10, a second transistor M2, a linearization circuit and a bias circuit.
  • the orthogonal phase output end of the inter-stage power divider 202 is connected to the input end of the auxiliary power amplifier 204, the input end of the auxiliary power amplifier 204 is connected to the second capacitor C10, the second inductor L10 and the linearization circuit, the other end of the second inductor L10 is connected to the ground potential end, the other end of the second capacitor C10 is connected to the gate of the second transistor M2 and the bias circuit, the source of the second transistor M2 is connected to the ground potential end, the drain of the second transistor M2 is connected to the output end of the auxiliary power amplifier 204, and the output end of the auxiliary power amplifier 204 is connected to the input end of the second output matching network B206.
  • the second capacitor C10 and the second inductor L10 form an input matching network.
  • the circuit structures of the main power amplifier 203 and the auxiliary power amplifier 204 are symmetrical, both are single-stage amplifiers, and the input ends are both provided with linearization circuits with the same or similar structures and parameters.
  • the areas of the amplifying transistors are equal or similar, and the bias currents are both provided by bias circuits with the same or similar structures and parameters.
  • the structures and parameters of the input matching networks are consistent.
  • the linearization circuit provides three circuit structure schemes, all of which are composed of a resistor connected in series and a diode group connected in forward and reverse parallel, and the resistor end is connected to the input end of the amplifier circuit. Its main function is to optimize the linearity of the RF power amplifier circuit.
  • the linearization circuit of the first solution is composed of a third resistor R3, a first diode D1, and a second diode D2.
  • the first diode D1 and the second diode D2 are connected in parallel with each other in forward and reverse directions, and one end is connected to the other end of the third resistor R3, and the other end is connected to the ground potential end.
  • the linearization circuit of the second solution is composed of a fourth resistor R4, a fifth resistor R5, a third diode D3, and a fourth diode D4.
  • the fourth resistor R4 is connected to the cathode of the third diode D3
  • the fifth resistor R5 is connected to the anode of the fourth diode D4
  • the other end of the fourth resistor R4 is connected in parallel with the other end of the fifth resistor R5 and then connected to the input end of the power amplifier circuit
  • the anode of the third diode D3 is connected in parallel with the cathode of the fourth diode D4 and then connected to the ground end.
  • the linearization circuit of the third scheme is composed of a sixth resistor R6, a fifth diode D5, a sixth diode D6, ..., an nth diode Dn, and an n+1th diode Dn+1, wherein n is an odd number greater than or equal to 7.
  • the following takes n as 9 as an example for explanation.
  • There are 6 diodes in the circuit namely, a fifth diode D5, a sixth diode D6, a seventh diode D7, an eighth diode D8, a ninth diode D9, and a tenth diode D10.
  • the fifth diode D5, the seventh diode D7, and the ninth diode D9 are connected in series with their positive and negative poles in sequence to form a first branch
  • the sixth diode D6, the eighth diode D8, and the tenth diode D10 are connected in series with their positive and negative poles in sequence to form a second branch
  • the negative terminal of the first branch is connected in parallel with the positive terminal of the second branch and then connected to the input terminal of the power amplifier circuit
  • the positive terminal of the first branch is connected in parallel with the negative terminal of the second branch and then connected to the ground potential terminal.
  • the working principle of the linearization circuit is shown in FIG4.
  • the power amplifier circuit inputs an RF signal
  • the input RF signal is waveform-shaped through the rectification effect of the forward and reverse parallel diodes, and the input RF signal is distorted in advance.
  • the distortion of the power amplifier transistor is used to compensate for the pre-distortion of the input RF signal caused by the linearization circuit, and finally the distortion of the RF signal at the output end of the power amplifier circuit is reduced, and the gain distortion and phase distortion are improved. Therefore, the power amplifier circuit can obtain better linearity.
  • the linearization circuit of the second scheme adjusts the rectification effect and the pre-distortion amplitude by changing the resistance value or the resistance connection method; the linearization circuit of the third scheme weakens the pre-distortion amplitude by increasing the number of diodes connected in series; in addition, the pre-distortion amplitude can be enhanced by increasing the number of diodes connected in parallel or the area of the diodes.
  • the bias circuit is composed of a seventh circuit
  • the fourth transistor T2 is composed of a resistor R7, an eighth resistor R8, a third capacitor C5, a third transistor T1, and a fourth transistor T2.
  • the drain of the third transistor T1 is connected to the seventh resistor R7 and then connected to the bias voltage terminal, the gate of the third transistor T1 is connected to the other end of the seventh resistor R7 and the third capacitor C5 and the drain of the fourth transistor T2, the other end of the third capacitor C5 is connected to the ground potential terminal, the source of the fourth transistor T2 is connected to the ground potential terminal, and the gate of the fourth transistor T2 is connected to the source of the third transistor T1 and the bias current output terminal through the eighth resistor R8.
  • the third transistor T1 is an emitter follower transistor
  • the fourth transistor T2 is a feedback amplifier transistor.
  • the bias circuit realizes low impedance output and provides bias current for the main power tube of the power amplifier circuit. At the same time, it improves the linearity of the broadband signal of the power amplifier circuit and enhances the processing capability of the broadband signal of the power amplifier circuit.
  • the inventors conducted simulation tests on the output impedance of the bias circuit of the technical solution provided by the present invention and the prior art solution as shown in FIG5(b).
  • the simulation test results are shown in FIG6 , in which the horizontal axis is the frequency, the vertical axis is the impedance, the curve 202 is the output impedance of the bias circuit of the technical solution provided by the present invention, and the curve 201 is the output impedance of the bias circuit of the prior art solution.
  • bias circuit provided in the embodiment of the present invention may also adopt other similar circuit structures to achieve low impedance output and provide bias current for the power amplifier circuit.
  • the first output matching network A205 is composed of a fourth capacitor C1, a fifth capacitor C2, a sixth capacitor C3, a seventh capacitor C4, and a third inductor L1, a fourth inductor L2, a fifth inductor L3 and a sixth inductor L4.
  • the output end of the main power amplifier 203 is connected to the input end of the first output matching network A205, and the input end of the first output matching network A205 is respectively connected to the fifth capacitor C2, the sixth capacitor C3 and the third inductor L1; the other end of the fifth capacitor C2 is connected to the fourth inductor L2, and the other end of the fourth inductor L2 is connected to the ground potential end; the other end of the third inductor L1 is connected to the power supply voltage end and the fourth capacitor C1, and the other end of the fourth capacitor C1 is connected to the ground potential end; the other end of the sixth capacitor C3 is connected to the fifth inductor L3 and the sixth inductor L4, and the other end of the fifth inductor L3 is connected to the ground potential end, and the sixth inductor L4 is connected to the ground potential end.
  • the other end is connected to the seventh capacitor C4 and the output end of the first output matching network A205, the other end of the seventh capacitor C4 is connected to the ground potential end, and the output end of the first output matching network A205 is connected to the non-inverting input end of the output power synthesizer 207.
  • the fourth capacitor C1 is a power filter capacitor.
  • the fifth capacitor C2 and the fourth inductor L2 are connected in series to form a resonant network for adjusting harmonic impedance, wherein the fifth capacitor C2 can be a variable capacitor.
  • the sixth capacitor C3, the seventh capacitor C4, the fifth inductor L3 and the sixth inductor L4 form a CLLC type impedance matching network. It should be noted that in other embodiments of the present invention, the impedance matching network can also adopt an LCCL type impedance matching network.
  • the second output matching network B206 is composed of an eighth capacitor C6, a ninth capacitor C7, a tenth capacitor C8, and a seventh inductor L5, an eighth inductor L6, a ninth inductor L7 and a tenth inductor L8.
  • the output end of the auxiliary power amplifier 204 is connected to the input end of the second output matching network B206, the input end of the second output matching network B206 is respectively connected to the eighth capacitor C6, the ninth capacitor C7 and the seventh inductor L5, the other end of the eighth capacitor C6 is connected to the eighth inductor L6, and the other end of the eighth inductor L6 is connected to the ground potential end; the other end of the seventh inductor L5 is connected to the power supply voltage end; the other end of the ninth capacitor C7 is connected to the ninth inductor L7 and the tenth inductor L8, the other end of the ninth inductor L7 is connected to the ground potential end, the other end of the tenth inductor L8 is connected to the tenth capacitor C8 and the output end of the second output matching network B206, the other end of the tenth capacitor C8 is connected to the ground potential end, and the output end of the second output matching network B206 is connected to the quadrature phase input end of the output power synthesizer 207.
  • the eighth capacitor C6 and the eighth inductor L6 are connected in series to form a resonant network for adjusting harmonic impedance, wherein the eighth capacitor C6 can be a variable capacitor.
  • the ninth capacitor C7, the tenth capacitor C8, the ninth inductor L7 and the tenth inductor L8 form a CLLC type impedance matching network. It should be noted that in other embodiments of the present invention, the impedance matching network can also adopt an LCCL type impedance matching network.
  • the first output matching network A205 and the second output matching network B206 are both high-bandwidth LC matching networks composed of lumped components, and their function is to match the output impedance of the main power amplifier 203 and the auxiliary power amplifier 204 to the characteristic impedance of the output power combiner 207 respectively.
  • the output power synthesizer 207 is composed of a 3dB distributed orthogonal coupler composed of metal coupling lines on a substrate, and has four terminals.
  • the first terminal is the in-phase input terminal, which is connected to the output terminal of the first output matching network A205; the second terminal is the orthogonal phase input terminal, It is connected to the output end of the second output matching network B206; the third terminal is the output end, which is connected to the output end of the RF power amplifier circuit; the fourth terminal is the grounding terminal, which is connected to the ground potential terminal through the second resistor R2.
  • the main function of the output power synthesizer 207 is to receive two input RF signals with the same amplitude and a phase difference of 90°, and synthesize them into one RF signal for output.
  • the 3dB distributed orthogonal coupler is composed of a substrate metal stacked coupling structure or a same-layer coupling structure. Since the thickness of the substrate metal is much greater than the chip metal, and the conductivity of the copper substrate is good, the insertion loss can be optimized. Its circuit structure has the excellent performance of large bandwidth, small insertion loss, and convergent port impedance. The disadvantage is that the area is slightly larger, but it is acceptable in mobile communication terminals.
  • the 3dB distributed orthogonal coupler in FIG7 is an inter-stage power divider structure using metal coupling lines on a chip, which has a signal input terminal and two signal output terminals.
  • the 3dB distributed orthogonal coupler of the stacked circuit design is used for an output power synthesizer, it is composed of metal coupling lines on a substrate and has two signal input terminals and one signal output terminal.
  • a 3dB distributed orthogonal coupler with a same-layer circuit design is used.
  • the 3dB distributed orthogonal coupler in FIG8 is an inter-stage power divider structure composed of metal coupling lines on a chip, which has a signal input terminal and two signal output terminals.
  • the 3dB distributed orthogonal coupler with a same-layer circuit design is used for an output power synthesizer, it is composed of metal coupling lines on a substrate and has two signal input terminals and one signal output terminal.
  • curve 401 is the insertion loss of the 3dB distributed orthogonal coupler designed with substrate metal, which is about 0.1dBc
  • curve 402 is the insertion loss of the 3dB distributed orthogonal coupler designed with chip metal, which is about 0.5dBc
  • Curve 403 is the isolation of the two input RF ports, all below -25dBc.
  • Curves 404, 405, and 406 are the reflection coefficients of the three RF ports, all below -25dBc, indicating that the port impedance converges and the reflection coefficient is small.
  • Curve 407 is the phase difference of the two input RF ports, and the phase difference is maintained at 90°.
  • the above simulation test results show that within the n77 operating frequency band, the present invention
  • the output power combiner composed of 3dB distributed orthogonal couplers with a substrate metal design provided by the embodiment has excellent effects on performance indicators such as insertion loss, isolation, reflection coefficient and phase difference.
  • the saturation power P RF_SAT and the efficiency ⁇ RF_rated at the back-off power of a single-ended RF power amplifier are:
  • P RF_rated is the power amplifier back-off power
  • V CC is the power supply voltage
  • RL is the power amplifier load line.
  • R ANT is the antenna load line
  • R L is the power amplifier load line
  • R L 50 ⁇ .
  • the balanced RF power amplifier provided in the embodiment of the present invention has a good antenna standing wave ratio.
  • the load line impedances of the two power amplifier units of the balanced RF power amplifier are:
  • Z A is the load line impedance of the main power amplifier unit
  • Z B is the load line impedance of the auxiliary power amplifier unit
  • Z 0 is the system characteristic impedance, generally 50 ⁇
  • ⁇ L is the antenna transmission coefficient
  • ⁇ L is the antenna phase.
  • the load line impedances of the two power amplification units of the balanced RF power amplifier provided by the embodiment of the present invention show a mutual compensation effect as the antenna phase changes.
  • curve 301 is the load line impedance of the main power amplification unit
  • curve 302 is the load line impedance of the auxiliary power amplification unit.
  • the alternating changes of the two load impedances cause the output power and output current of the two power amplification units to also change alternately, showing a mutual compensation effect.
  • the specific changes in impedance, current, and output power of the main power amplification unit and the auxiliary power amplification unit of a balanced RF power amplifier are as follows:
  • the current and output power of the main power amplifier unit and the auxiliary power amplifier unit are also equal, and the output power of the output end of the balanced RF power amplifier is the sum of the output powers of the main power amplifier unit and the auxiliary power amplifier unit.
  • the output power of the balanced RF power amplifier provided by the embodiment of the present invention changes by about 1 dB as the antenna phase changes.
  • curve 303 is a curve showing the output power of the balanced power amplifier provided by the present invention changing with the antenna phase
  • curve 304 is a curve showing the output power of the single-ended power amplifier in the prior art changing with the antenna phase, and the output power changes by about 8 dB.
  • the balanced RF power amplifier provided by the present invention can well maintain a stable output power when the antenna phase changes.
  • the operating current of the balanced RF power amplifier provided by the embodiment of the present invention changes by about 30 mA as the antenna phase changes.
  • curve 305 is a curve showing the operating current of the balanced power amplifier provided by the present invention changing with the antenna phase
  • curve 306 is a curve showing the operating current of the single-ended power amplifier in the prior art changing with the antenna phase, and the operating current changes by about 300 mA.
  • the balanced RF power amplifier provided by the present invention can well maintain a stable operating current when the antenna phase changes.
  • the balanced RF power amplifier provided by the present invention can effectively improve the transmission power and transmission efficiency when the antenna standing wave ratio changes.
  • the inventors further conducted simulation tests on the balanced RF power amplifier provided in the embodiment of the present invention, using multiple performance indicators such as gain, efficiency, and linearity in the n77 frequency band.
  • the simulation test results are shown in Figure 13.
  • Curve 501 is the gain curve of the balanced RF power amplifier, and the gain deviation is within ⁇ 1dB in the n77 frequency band;
  • Curve 502 is the linearity curve of the balanced RF power amplifier, and the linearity deviation is within ⁇ 1dB in the n77 frequency band.
  • Curve 503 is the efficiency curve of the balanced RF power amplifier, and the efficiency deviation is within 2% in the n77 frequency band;
  • Curve 504 is the saturation power curve of the balanced RF power amplifier, and the saturation power deviation is within ⁇ 1dB in the n77 frequency band. From the simulation test results, it can be seen that the balanced RF power amplifier provided by the embodiment of the present invention can meet the system requirements in terms of gain, efficiency, linearity and other performances in the n77 frequency band.
  • the embodiment of the present invention also provides a radio frequency front-end module, which includes the balanced radio frequency power amplifier provided by the embodiment of the present invention, and can be used in a wireless communication system as an important component of a mobile communication terminal.
  • the radio frequency front-end module includes a substrate, at least one radio frequency power amplifier chip, at least one power supply and control chip, and an output matching network composed of a group of lumped surface mount components and an output power synthesizer formed by metal wires on the substrate.
  • the radio frequency power amplifier chip is composed of at least one driving stage power unit, an inter-stage power divider, a main power amplifier and an auxiliary power amplifier.
  • the layout of the balanced RF power amplifier is that the driving stage power unit, the inter-stage power divider, the main power amplifier and the auxiliary power amplifier are all arranged on the RF power amplifier chip, and the power supply and control chip A, the power supply and control chip B, the power supply and control chip C, and the first output matching network A, the second output matching network B and the output power synthesizer are all arranged on the substrate.
  • the power supply and control circuit A provides power and control signals for the driving stage power unit
  • the power supply and control circuit B provides power and control signals for the main power amplifier
  • the power supply and control circuit C provides power and control signals for the auxiliary power amplifier.
  • the packaging method of the RF power amplifier chip and the substrate is a positive packaging method, and the output ends of the main power amplifier and the auxiliary power amplifier are respectively connected to the first output matching network A and the second output matching network B through metal wire bonding.
  • FIG14 also provides the flow direction of the input RF signal. As shown by the arrow, the RF input signal enters the RF power amplifier chip from the input end of the driving stage power unit and is finally transmitted from the output end of the output power synthesizer.
  • the power supply and control chip A, the power supply and control chip B and the power supply and control chip C can be arranged on the same chip, or can be three completely independent chips or integrated into one or two chips.
  • the packaging method of the RF power amplifier chip and the substrate can also adopt a flip-chip packaging method, and the output ends of the main power amplifier and the auxiliary power amplifier are directly connected to the first output matching network A and the second output matching network B through copper pillars or planting balls.
  • the output power combiner can be arranged at the side or below the first output matching network A and the second output matching network B.
  • the balanced RF power amplifier provided by the embodiment of the present invention can also be used in electronic devices as an important component of communication components.
  • the electronic equipment mentioned here refers to computer equipment that can be used in a mobile environment and supports multiple communication formats such as GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE, 5G, etc., including mobile phones, laptops, tablet computers, car computers, etc.
  • the technical solution provided by the present invention is also applicable to other occasions where RF front-end modules are applied, such as communication base stations, smart connected vehicles, etc.
  • the electronic device includes at least a processor and a memory, and may further include a communication component, a sensor component, a power component, a multimedia component and an input/output interface according to actual needs.
  • the memory, communication component, sensor component, power component, multimedia component and input/output interface are all connected to the processor.
  • the memory can be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc.
  • the processor can be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable logic gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc.
  • CPU central processing unit
  • GPU graphics processing unit
  • FPGA field programmable logic gate array
  • ASIC application-specific integrated circuit
  • DSP digital signal processing
  • the balanced RF power amplifier provided by the present invention, on the one hand, overcomes the influence of the change of antenna standing wave ratio on the transmission power and transmission efficiency to the greatest extent by adopting a balanced design in which the main power amplifier unit and the auxiliary power amplifier unit are symmetrical to each other.
  • the performance indicators such as the area size and bandwidth, insertion loss, and transmission efficiency of the RF power amplifier are optimally compromised and optimized.
  • the gain distortion and phase distortion of the power amplifier are improved, and better linearity is obtained.
  • the balanced RF power amplifier provided by the present invention has the beneficial effects of ingenious and reasonable circuit design, strong flexibility, and excellent circuit performance, and is more in line with the requirements of the technical performance indicators of the 5G communication system.

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Abstract

一种平衡式射频功率放大器、前端模块及相应的电子设备。平衡式射频功率放大器包括驱动级功率单元(101，201)、级间功率分配器(102，202)、主路功率放大器(103，203)、辅路功率放大器(104，204)、第一输出匹配网络(A105，A205)、第二输出匹配网络(B106，B206)和输出功率合成器(107，207)。其中，主路功率放大单元(103，203)和辅路功率放大器(104，204)采用相互对称的平衡式设计，最大程度地克服了天线驻波比(VSWR)变化对发射功率和发射效率的影响。同时，级间功率分配器(102，202)和输出功率合成器(107，207)采用3dB分布式正交耦合器，使得射频功率放大器的面积尺寸和带宽、插入损耗、发射效率等性能指标得到最佳的折中与优化。

Description

一种平衡式射频功率放大器、射频前端模块及电子设备 技术领域
本发明涉及一种平衡式射频功率放大器，同时也涉及包括该平衡式射频功率放大器的射频前端模块及相应的电子设备，属于射频集成电路技术领域。
背景技术
随着通信技术的不断发展，移动通信终端对射频前端模块的性能要求越来越高。其中，射频功率放大器(RF power amplifier)作为射频前端模块中的一个重要组成部分，其带宽、增益、损耗、线性度、发射功率和效率，以及使用寿命和面积尺寸等主要技术性能指标就显得尤为重要。在移动通信终端的射频前端模块中，射频功率放大器是功耗最高的器件，降低射频功率放大器的功耗也是提高设备使用寿命最有效的方法。在影响射频功率放大器性能的诸多因素中，射频功率放大器架构以及天线驻波比是提射频高功率放大器效率的两个至关重要的因素。其中，天线驻波比会随着使用场景的变化而变化，其变化直接影响射频功率放大器的负载线，进而影响其发射功率和发射效率。
在5G通信系统的移动通信终端中，n41、n77和n79三个频段由于频率较高，空间路径衰减较大，移动制式要求该三个频段都需要发射PC2等级的发射功率，即天线发射功率为26dBm。这种高发射功率会引起射频功率放大器消耗的直流功耗变大，并且在发射效率相同的条件下，射频功率放大器的发热也会更加严重，使得电池消耗更快、待机时间缩短。因此，在PC2等级发射功率的情况下，需要进一步优化射频功率放大器的线性度，以及提高射频功率放大器的效率来解决上述存在的问题。另一方面，n41、n77和n79三个频段的带宽分别为200MHz、900MHz和600MHz，射频信号带宽最大为200MHz，因此，还需要提高射频功率放大器的带宽，以及提高宽带信号下射频功率放大器的线性度。
发明内容
本发明所要解决的首要技术问题在于提供一种平衡式射频功率放 大器。
本发明所要解决的另一技术问题在于提供一种包括该平衡式射频功率放大器的射频前端模块及相应的电子设备。
为了实现上述目的，本发明采用下述的技术方案：
根据本发明实施例的第一方面，提供一种平衡式射频功率放大器，包括驱动级功率单元、级间功率分配器、主路功率放大器、辅路功率放大器、第一输出匹配网络A、第二输出匹配网络B和输出功率合成器；其中，
所述驱动级功率单元的输入端接收输入射频信号，输出端与所述级间功率分配器的输入端连接，用于对输入射频信号进行驱动放大；
所述级间功率分配器的同相输出端与所述主路功率放大器的输入端连接，正交相输出端与所述辅路功率放大器的输入端连接，用于产生两路振幅相等、相位相差90°的射频信号；
所述主路功率放大器的输出端与所述第一输出匹配网络A的输入端连接，所述辅路功率放大器的输出端与所述第二输出匹配网络B的输入端连接；所述第一输出匹配网络A的输出端与所述输出功率合成器的同相输入端连接，所述第二输出匹配网络B的输出端与所述输出功率合成器的正交相输入端连接；
所述输出功率合成器用于接收两路振幅相同、相位相差90°的射频信号，合成一路输出射频信号。
其中较优地，所述级间功率分配器由芯片上金属耦合线组成的3dB分布式正交耦合器构成，其中采用芯片金属叠层耦合结构或者同层耦合结构。
其中较优地，所述输出功率合成器由基板上金属耦合线组成的3dB分布式正交耦合器构成，其中采用基板金属叠层耦合结构或者同层耦合结构。
其中较优地，所述主路功率放大器由第一电容C9、第一电感L9、第一晶体管M1，以及线性化电路和偏置电路构成；其中，所述主路功率放大器的输入端与第一电容C9、第一电感L9、线性化电路连接，第一电感L9的另一端与地电位端连接，第一电容C9的另一端与第一晶体管M1的栅极及偏置电路连接，第一晶体管M1的源极与地电位端连 接，第一晶体管M1的漏极与所述主路功率放大器的输出端连接；其中，第一电容C9和第一电感L9组成输入匹配网络。
其中较优地，所述线性化电路由电阻串联正反向并联的二极管组构成；其中，电阻端连接功率放大器电路的输入端，二极管端与地电位端连接；
所述线性化电路通过增加二极管串联数量来减弱预失真幅度，通过增加二极管并联数量或者二极管面积来加强预失真幅度。
其中较优地，所述偏置电路由第七电阻R7、第八电阻R8、第三电容C5、第三晶体管T1、第四晶体管T2构成；其中，第三晶体管T1的漏极与第七电阻R7连接后共同与偏置电压端连接，第三晶体管T1的栅极与第七电阻R7的另一端及第三电容C5、第四晶体管T2的漏极连接，第三电容C5的另一端与地电位端连接，第四晶体管T2的源极与地电位端连接，第四晶体管T2的栅极通过第八电阻R8与第三晶体管T1的源极及偏置电流输出端连接；
其中，所述第三晶体管T1为射级跟随器晶体管，所述第四晶体管T2为反馈放大晶体管。
其中较优地，所述第一输出匹配网络A和所述第二输出匹配网络B均为集总器件构成的高带宽匹配网络；
所述第一输出匹配网络A由第四电容C1、第五电容C2、第六电容C3、第七电容C4，以及第三电感L1、第四电感L2、第五电感L3和第六电感L4构成；其中，第一输出匹配网络A的输入端分别与第五电容C2、第六电容C3及第三电感L1连接；第五电容C2的另一端与第四电感L2连接，第四电感L2的另一端与地电位端连接；第三电感L1的另一端与电源电压端及第四电容C1连接，第四电容C1的另一端与地电位端连接；第六电容C3的另一端与第五电感L3、第六电感L4连接，第五电感L3的另一端与地电位端连接，第六电感L4的另一端与第七电容C4及第一输出匹配网络A的输出端连接，第七电容C4的另一端与地电位端连接；其中，
所述第四电容C1为电源滤波电容，所述第一输出匹配网络A和所述第二输出匹配网络B合用一个电源滤波电容；
所述第五电容C2和所述第四电感L2串联构成调节谐波阻抗的谐 振网络，所述第五电容C2采用可变电容；
所述第六电容C3、第七电容C4和第五电感L3和第六电感L4构成CLLC型阻抗匹配网络。
其中较优地，当天线相位发生变化时，所述平衡式射频功率放大器的主路功率放大单元的负载线阻抗和辅路功率放大单元的负载线阻抗发生交替变化，该两路功率放大单元的输出功率和输出电流也发生交替变化，使得变化量相互补偿。
根据本发明实施例的第二方面，提供一种射频前端模块，基于上述平衡式射频功率放大器实现，包括一个基板、至少一个射频功率放大器芯片、至少一个供电和控制芯片，以及一组输出匹配网络和输出功率合成器；其中，
所述平衡式射频功率放大器中的所述驱动级功率单元、所述级间功率分配器、所述主路功率放大器和所述辅路功率放大器均集成在所述射频功率放大器芯片上；
所述射频功率放大器芯片与所述基板之间采用正装封装方式或者倒装封装方式；
所述主路功率放大器和所述辅路功率放大器的输出端分别通过金属线键合连接到第一输出匹配网络A和第二输出匹配网络B，并分别通过铜柱或者植球直接连接到第一输出匹配网络A和第二输出匹配网络B。
根据本发明实施例的第三方面，提供一种电子设备，其中包括上述平衡式射频功率放大器。
与现有技术相比较，本发明所提供的平衡式射频功率放大器，一方面，通过采用主路功率放大单元和辅路功率放大单元相互对称的平衡式设计，最大程度地克服了天线驻波比变化对发射功率和发射效率的影响。另一方面，通过采用3dB分布式正交耦合器来设计功率分配器和功率合成器，并分别在芯片级和基板上来实现，使得射频功率放大器的面积尺寸和带宽、插入损耗、发射效率等性能指标得到最佳的折中与优化。同时，通过采用线性化电路的技术方案，改善了功率放大器的增益失真和相位失真，得到较好的线性度。通过采用低阻抗输出的偏置电路的技术方案改善了功率放大器电路宽带信号的线性度，提升了宽带信号 的处理能力。因此，本发明所提供的平衡式射频功率放大器具有电路设计巧妙合理、灵活性强，以及电路性能优异等有益效果，更加符合5G通信系统技术性能指标的要求。
附图说明
图1为本发明实施例提供的一种平衡式射频功率放大器的结构框图；
图2为本发明实施例中，平衡式射频功率放大器的电路原理图；
图3(a)为本发明实施例中，线性化电路的第一方案电路原理图；
图3(b)为本发明实施例中，线性化电路的第二方案电路原理图；
图3(c)为本发明实施例中，线性化电路的第三方案电路原理图；
图4为本发明实施例中，线性化电路的预失真行为图；
图5(a)为本发明实施例中，偏置电路的电路原理图；
图5(b)为现有技术中，典型偏置电路的电路原理图；
图6为本发明技术方案与现有技术方案的偏置电路输出阻抗的仿真测试对比图；
图7为本发明实施例中，采用叠层电路设计的3dB分布式正交耦合器的结构示意图；
图8为本发明实施例中，采用同层电路设计的3dB分布式正交耦合器的结构示意图；
图9为本发明实施例中，输出功率合成器在n77工作频带内的插入损耗、隔离度和反射系数等性能指标的仿真测试图；
图10为本发明实施例中，主路功率放大单元和辅路功率放大单元的负载线阻抗随天线相位变化的仿真测试曲线图；
图11为本发明实施例中，平衡式射频功率放大器的输出功率随天线相位变化的仿真测试曲线图；
图12为本发明实施例中，平衡式射频功率放大器的工作电流随天线相位变化的仿真测试曲线图；
图13为本发明实施例中，平衡式射频功率放大器在n77频段中的增益、效率、线性度等性能指标的仿真测试图；
图14为本发明实施例中，平衡式射频功率放大器的布局示意图；
图15为采用本发明实施例提供的平衡式射频功率放大器的电子设 备的示例图。
具体实施方式
下面结合附图和具体实施例对本发明的技术方案做进一步的详细说明。
如图1所示，本发明实施例提供的一种平衡式射频功率放大器包括驱动级功率单元101、级间功率分配器102、主路功率放大器103、辅路功率放大器104、第一输出匹配网络A105、第二输出匹配网络B106和输出功率合成器107，以及射频信号输入端和射频信号输出端。其中，射频信号输入端与驱动级功率单元101的输入端连接，驱动级功率单元101的输出端与级间功率分配器102输入端连接；级间功率分配器102的同相输出端与主路功率放大器103的输入端连接，主路功率放大器103的输出端与第一输出匹配网络A105的输入端连接，第一输出匹配网络A105的输出端与输出功率合成器107的同相输入端连接；级间功率分配器102的正交相输出端与辅路功率放大器104的输入端连接，辅路功率放大器104的输出端与第二输出匹配网络B106的输入端连接，第二输出匹配网络B106的输出端与输出功率合成器107的正交相输入端连接；输出功率合成器107的输出端与射频信号输出端连接。
驱动级功率单元101用于对输入射频信号进行驱动放大后输出至级间功率分配器102。其可以为单级功率单元或者两级功率单元。
级间功率分配器102用于接收一路输入射频信号后，产生两路振幅相等、相位相差90°的射频信号，分别输出至主路功率放大器103和辅路功率放大器104。其由芯片上金属耦合线组成的3dB分布式正交耦合器实现。
主路功率放大器103和辅路功率放大器104主要用于对各自输入射频信号的放大。其均为带有线性化电路和偏置电路的单级放大器，并且电路结构相互对称，电路元件参数相等或接近。
第一输出匹配网络A105和第二输出匹配网络B106用于将主路功率放大器103和辅路功率放大器104的输出阻抗分别匹配至输出功率合成器107的特征阻抗上。其均为集总器件组成的高带宽LC匹配网络。
输出功率合成器107用于接收两路振幅相同、相位相差90°的射频信号后合成一路射频信号输出。其由基板上金属耦合线组成的3dB分布式正交耦合器实现。
在本发明实施例提供的平衡式射频功率放大器中，当射频信号输入端接收到输入射频信号时，驱动级功率单元101首先对输入射频信号进行驱动放大，并将放大后的射频信号输出至级间功率分配器102；级间功率分配器102将该射频信号分成两路振幅相同、相位相差90°的射频信号，其中，相位为+45°(同相)的射频信号输出至主路功率放大器103，相位为－45°(正交相)的射频信号输出至辅路功率放大器104；两路相位相差90°的射频信号分别经过主路功率放大器103和辅路功率放大器104进行放大后，该两路放大后的射频信号分别通过第一输出匹配网络A105和第二输出匹配网络B106进入输出功率合成器107的两个输入端，输出功率合成器107将该两路射频信号合成一路射频信号后通过射频信号输出端将该射频信号输出。
下面，通过具体实施例对本发明所提供的一种平衡式射频功率放大器的组成结构、工作原理以及电路性能等方面进行详细说明。
如图2所示，在本发明的一个实施例中，平衡式射频功率放大器包括驱动级功率单元201、级间功率分配器202、主路功率放大器203、辅路功率放大器204、第一输出匹配网络A205、第二输出匹配网络B206和输出功率合成器207。下面分别对各单元电路进行详细说明。
驱动级功率单元201可以由单级功率单元或者两级功率单元构成，其输入端与射频信号输入端连接，输出端与级间功率分配器202的输入端连接。其主要作用是对输入射频信号进行驱动放大。
级间功率分配器202由芯片上金属耦合线组成的3dB分布式正交耦合器构成，具有四个接线端。其中，第一接线端为输入端，其与驱动级功率单元201的输出端连接；第二接线端为接地端，其通过第一电阻R1与地电位端连接；第三接线端为同相输出端，其与主路功率放大器203的输入端连接；第四接线端为正交相输出端，其与辅路功率放大器204的输入端连接。
级间功率分配器202的主要作用是接收一路输入射频信号后，产生两路振幅相等、相位相差90°的输出射频信号。3dB分布式正交耦 合器采用芯片金属叠层耦合结构或者同层耦合结构组成，还可以通过增加电容器件来改变耦合器的耦合系数。其电路结构具有带宽大、面积小、端口阻抗收敛的优异性能，缺点是插入损耗(insertionloss)稍大，但在移动通信终端中可以接受。
主路功率放大器203由第一电容C9、第一电感L9、第一晶体管M1，以及线性化电路和偏置电路构成。其中，级间功率分配器202的同相输出端与主路功率放大器203的输入端连接，主路功率放大器203的输入端与第一电容C9、第一电感L9、线性化电路连接，第一电感L9的另一端与地电位端连接，第一电容C9的另一端与第一晶体管M1的栅极及偏置电路连接，第一晶体管M1的源极与地电位端连接，第一晶体管M1的漏极与主路功率放大器203的输出端连接，主路功率放大器203的输出端与第一输出匹配网络A205的输入端连接。其中，第一电容C9和第一电感L9组成输入匹配网络。
辅路功率放大器204由第二电容C10、第二电感L10、第二晶体管M2，以及线性化电路和偏置电路构成。其中，级间功率分配器202的正交相输出端与辅路功率放大器204的输入端连接，辅路功率放大器204的输入端与第二电容C10、第二电感L10及线性化电路连接，第二电感L10的另一端与地电位端连接，第二电容C10的另一端与第二晶体管M2的栅极及偏置电路连接，第二晶体管M2的源极与地电位端连接，第二晶体管M2的漏极与辅路功率放大器204的输出端连接，辅路功率放大器204的输出端与第二输出匹配网络B206的输入端连接。其中，第二电容C10和第二电感L10组成输入匹配网络。
主路功率放大器203和辅路功率放大器204的电路结构对称，均为单级放大器，输入端均设有结构、参数相同或接近的线性化电路，放大晶体管的面积相等或接近，并且均由结构、参数相同或接近的偏置电路提供偏置电流，输入匹配网络的结构和参数均一致。
在本发明的一个实施例中，线性化电路提供了三种电路结构方案，其均由电阻串联正反向并联的二极管组构成，电阻端接入放大器电路的输入端，其主要作用是优化射频功率放大器电路的线性度。
如图3(a)所示，第一方案的线性化电路由第三电阻R3、第一二极管D1、第二二极管D2构成。其中，第三电阻R3的一端与功率放 大器电路的输入端连接，第一二极管D1和第二二极管D2正反向相互并联后，一端与第三电阻R3的另一端连接，另一端与地电位端连接。
如图3(b)所示，第二方案的线性化电路由第四电阻R4、第五电阻R5、第三二极管D3、第四二极管D4构成。其中，第四电阻R4与第三二极管D3的负极连接，第五电阻R5与第四二极管D4的正极连接，第四电阻R4的另一端与第五电阻R5的另一端并联连接后与功率放大器电路的输入端连接，第三二极管D3的正极与第四二极管D4的负极并联连接后与接地端连接。
如图3(c)所示，第三方案的线性化电路由第六电阻R6、第五二极管D5、第六二极管D6……第n二极管Dn、第n+1二极管Dn+1构成，其中，n为大于等于7的奇数。下面以n取9为例进行说明，电路中二极管共6只，分别为第五二极管D5、第六二极管D6、第七二极管D7、第八二极管D8、第九二极管D9、第十二极管D10。其中，第五二极管D5、第七二极管D7和第九二极管D9依次正负极串联连接形成第一支路，第六二极管D6、第八二极管D8和第十二极管D10依次正负极串联连接形成第二支路，第一支路的负极端与第二支路的正极端并联连接后与功率放大器电路的输入端连接，第一支路的正极端与第二支路的负极端并联连接后与地电位端连接。
线性化电路的工作原理如图4所示，当功率放大电路输入射频信号时，通过正反向并联二极管的整流效应，对输入射频信号进行波形整形，预先使输入射频信号失真，该预失真的射频信号经过功率放大器晶体管放大后，利用功率放大器晶体管的失真，补偿了线性化电路引起的输入射频信号的预失真，最终使得功率放大器电路输出端的射频信号失真度降低，改善了增益失真和相位失真，因此，功率放大器电路可以得到较好的线性度。
在上述三个线性化电路结构的方案设计中，第二方案的线性化电路通过改变电阻值或者电阻连结方式来调整整流效应和预失真幅度；第三方案的线性化电路通过增加二极管串联数量来减弱预失真幅度；此外，还可以通过增加二极管并联数量或者二极管面积来加强预失真幅度。
在本发明的一个实施例中，如图5(a)所示，偏置电路由第七电 阻R7、第八电阻R8、第三电容C5、第三晶体管T1、第四晶体管T2构成。其中，第三晶体管T1的漏极与第七电阻R7连接后共同与偏置电压端连接，第三晶体管T1的栅极与第七电阻R7的另一端及第三电容C5、第四晶体管T2的漏极连接，第三电容C5的另一端与地电位端连接，第四晶体管T2的源极与地电位端连接，第四晶体管T2的栅极通过第八电阻R8与第三晶体管T1的源极及偏置电流输出端连接。
在偏置电路结构中，第三晶体管T1为射级跟随器晶体管，第四晶体管T2为反馈放大晶体管，该偏置电路实现了低阻抗输出，为功率放大器电路主功率管提供偏置电流，同时，改善了功率放大器电路宽带信号的线性度，提升了功率放大器电路宽带信号的处理能力。
为了验证本发明实施例提供的偏置电路技术方案的有益效果，发明人对本发明提供的技术方案与如图5(b)所示现有技术方案的偏置电路分别进行了输出阻抗的仿真测试。仿真测试结果如图6所示，图6中，横坐标为频率，纵坐标为阻抗，曲线202为本发明提供的技术方案偏置电路的输出阻抗，曲线201为现有技术方案偏置电路的输出阻抗。从图6中可以看出，在小于200MHz的低频区域，本发明提供的技术方案中偏置电路的输出阻抗非常小、接近0Ω，而现有技术方案偏置电路的输出阻抗大于50Ω。因此，本发明提供的技术方案中偏置电路实现低阻抗输出的效果非常明显。
需要说明的是，本发明实施例提供的偏置电路，也可以采用其他类似的不同电路结构来实现低阻抗输出，为功率放大器电路提供偏置电流。
第一输出匹配网络A205由第四电容C1、第五电容C2、第六电容C3、第七电容C4，以及第三电感L1、第四电感L2、第五电感L3和第六电感L4构成。其中，主路功率放大器203的输出端与第一输出匹配网络A205的输入端连接，第一输出匹配网络A205的输入端分别与第五电容C2、第六电容C3及第三电感L1连接；第五电容C2的另一端与第四电感L2连接，第四电感L2的另一端与地电位端连接；第三电感L1的另一端与电源电压端及第四电容C1连接，第四电容C1的另一端与地电位端连接；第六电容C3的另一端与第五电感L3、第六电感L4连接，第五电感L3的另一端与地电位端连接，第六电感L4 的另一端与第七电容C4及第一输出匹配网络A205的输出端连接，第七电容C4的另一端与地电位端连接，第一输出匹配网络A205的输出端与输出功率合成器207的同相输入端连接。
其中，第四电容C1为电源滤波电容。第五电容C2和第四电感L2串联构成调节谐波阻抗的谐振网络，其中，第五电容C2可以采用可变电容。第六电容C3、第七电容C4和第五电感L3和第六电感L4构成CLLC型阻抗匹配网络。需要说明的是，在本发明的其他实施例中，阻抗匹配网络也可以采用LCCL型阻抗匹配网络。
第二输出匹配网络B206由第八电容C6、第九电容C7、第十电容C8，以及第七电感L5、第八电感L6、第九电感L7和第十电感L8构成。其中，辅路功率放大器204的输出端与第二输出匹配网络B206的输入端连接，第二输出匹配网络B206的输入端分别与第八电容C6、第九电容C7及第七电感L5连接，第八电容C6的另一端与第八电感L6连接，第八电感L6的另一端与地电位端连接；第七电感L5的另一端与电源电压端连接；第九电容C7的另一端与第九电感L7、第十电感L8连接，第九电感L7的另一端与地电位端连接，第十电感L8的另一端与第十电容C8及第二输出匹配网络B206的输出端连接，第十电容C8的另一端与地电位端连接，第二输出匹配网络B206的输出端与输出功率合成器207的正交相输入端连接。
其中，第八电容C6和第八电感L6串联构成调节谐波阻抗的谐振网络，其中，第八电容C6可以采用可变电容。第九电容C7、第十电容C8和第九电感L7和第十电感L8构成CLLC型阻抗匹配网络。需要说明的是，在本发明的其他实施例中，阻抗匹配网络也可以采用LCCL型阻抗匹配网络。
第一输出匹配网络A205和第二输出匹配网络B206均为集总器件组成的高带宽LC匹配网络，其作用是将主路功率放大器203和辅路功率放大器204的输出阻抗分别匹配至输出功率合成器207的特征阻抗上。
输出功率合成器207由基板上金属耦合线组成的3dB分布式正交耦合器构成，具有四个接线端。其中，第一接线端为同相输入端，其与第一输出匹配网络A205的输出端连接；第二接线端为正交相输入端， 其与第二输出匹配网络B206的输出端连接；第三接线端为输出端，其与射频功率放大器电路的输出端连接；第四接线端为接地端，其通过第二电阻R2与地电位端连接。
输出功率合成器207的主要作用是接收两路振幅相同、相位相差90°的输入射频信号后，将其合成一路射频信号输出。该3dB分布式正交耦合器采用基板金属叠层耦合结构或者同层耦合结构组成，由于基板金属的厚度远大于芯片金属，并且，铜材质基板的导电率较好，因此，可以将插入损耗进行最优化。其电路结构具有带宽大、插入损耗较小、端口阻抗收敛的优异性能，缺点是面积稍大，但在移动通信终端中可以接受。
如图7所示，为采用叠层电路设计的3dB分布式正交耦合器。图7中3dB分布式正交耦合器为采用芯片上金属耦合线组成的级间功率分配器结构，其具有一个信号输入端和二个信号输出端。当该叠层电路设计的3dB分布式正交耦合器用于输出功率合成器时，则采用基板上金属耦合线组成，并具有二个信号输入端和一个信号输出端。
如图8所示，采用同层电路设计的3dB分布式正交耦合器。图8中3dB分布式正交耦合器为采用芯片上金属耦合线组成的级间功率分配器结构，其具有一个信号输入端和二个信号输出端。当该同层电路设计的3dB分布式正交耦合器用于输出功率合成器时，则采用基板上金属耦合线组成，并具有二个信号输入端和一个信号输出端。
为了验证本发明实施例所提供的输出功率合成器技术方案的有益效果，发明人在n77工作频带内对其进行了插入损耗、隔离度和反射系数等性能指标的仿真测试。测试结果如图9所示，其中，曲线401为基板金属设计的3dB分布式正交耦合器的插入损耗，大约为0.1dBc；曲线402为芯片金属设计的3dB分布式正交耦合器的插入损耗，大约为0.5dBc；与芯片金属设计相对比，基板金属设计的3dB分布式正交耦合器的插入损耗减小了大约0.4dBc。曲线403为两路输入射频端口的隔离度，均在-25dBc以下。曲线404、405、406为三路射频端口的反射系数，均在-25dBc以下，说明端口阻抗收敛、反射系数小。曲线407为两路输入射频端口的相位差，相位差保持在90°。
通过上述仿真测试的结果可以看出，在在n77工作频带内，本发 明实施例所提供的采用基板金属设计的3dB分布式正交耦合器构成的输出功率合成器，其插入损耗、隔离度、反射系数和相位差等性能指标的优异效果非常明显。
以上对本发明实施例提供的平衡式射频功率放大器中的各单元电路进行了详细说明，下面对天线驻波比发生变化时，平衡式射频功率放大器的发射功率和效率情况进行分析说明。
在现有技术中，单端射频功率放大器的饱和功率PRF_SAT以及回退功率处的效率ηRF_rated为：

其中，PRF_rated是功率放大器回退处功率；VCC为电源电压；RL为功率放大器负载线。
由公式1和公式2可知，当功率放大器负载线RL增大时，回退功率处的效率ηRF_rated会提高，但功率放大器的饱和功率PRF_SAT会减小；当功率放大器负载线RL减小时，功率放大器的饱和功率PRF_SAT会增大，但回退功率处的效率ηRF_rated会降低。
天线驻波比VSWR的数学表达式为：
其中，RANT为天线负载线；RL为功率放大器负载线，通常设计取值为RL＝50Ω。
当天线负载线RANT与功率放大器负载线RL相等时，即天线驻波比VSWR为1，单端功率放大器的发射功率和发射效率为最优状况。当天线负载线RANT与功率放大器负载线RL不相等时，即天线驻波比VSWR大于1的情况下，功率放大器的发射功率或者发射效率会发生改变降低，发射功率的降低会导致发射指标失效。为了满足在天线驻波比VSWR<3条件下发射功率的要求，单端功率放大器设计一般通过提高天线驻波比VSWR＝1条件下的发射功率，来满足在天线驻波比VSWR<3条件下发射功率的要求。这种方法会降低功率放大器的发射效率，进而增加了器件的发热，以及减小待机时间。
本发明实施例提供的平衡式射频功率放大器，对于天线驻波比 VSWR发生变化时，其输出功率GA为：
GA＝20·log(e-j2θ)＝0dBc       (4)
其中，2θ为耦合器传输臂的相位。
由公式4可知，平衡式射频功率放大器，天线驻波比VSWR发生变化时，对其输出功率不产生影响，能够保持恒定的输出功率。
平衡式射频功率放大器的两路功率放大单元的负载线阻抗分别为：

其中，ZA为主路功率放大单元的负载线阻抗；ZB为辅路功率放大单元的负载线阻抗；Z0为系统特征阻抗，一般为50Ω；ΓL为天线发射系数；θL为天线相位。
天线发射系数ΓL与天线驻波比VSWR的数学关系式为：
由公式5和公式6可以看出，功率放大单元的负载线阻抗随着天线相位的变化而变化，进一步会直接影响功率放大器的工作电流和输出功率。下面通过负载线阻抗、输出功率和工作电流等仿真测试来验证本发明实施例提供的平衡式射频功率放大器的性能指标。
如图10所示，在天线驻波比VSWR为3的条件下，本发明实施例提供的平衡式射频功率放大器的两路功率放大单元的负载线阻抗，随着天线相位的变化呈现相互补偿的效果。图10中，曲线301为主路功率放大单元的负载线阻抗，曲线302为辅路功率放大单元的负载线阻抗，两路负载阻抗的交替变化，使得两路功率放大单元的输出功率和输出电流也交替变化，呈现相互补偿的效果。
在上述仿真测试中，当天线相位在0°～180°范围内发生变化时，本发明实施例提供的一种平衡式射频功率放大器的主路功率放大单元和辅路功率放大单元的阻抗、电流和输出功率的具体变化情况如下：
当天线相位角为0°、90°和180°时，主路负载阻抗和辅路负载阻抗相等，即ZA＝ZB＝81Ω，此时，主路功率放大单元和辅路功率放大单元的电流和输出功率也分别相等，平衡式射频功率放大器输出端的输出功率为主路功率放大单元和辅路功率放大单元的输出功率之和。
当天线相位角偏离0°、90°和180°时，以45°为例，主路负载阻抗ZA＝142Ω，与天线相位角为0°、90°和180°时相比增大了61Ω；辅路负载阻抗ZB＝20Ω，与天线相位角为0°、90°和180°时相比减小了61Ω；此时，主路功率放大单元的电流和输出功率与天线相位角为0°、90°和180°时相比均相应减小，辅路功率放大单元的电流和输出功率与天线相位角为0°、90°和180°时相比均相应增大，前者的减小量与后者的增大量分别相等，因此，平衡式射频功率放大器输出端的输出功率，即主路功率放大单元和辅路功率放大单元的输出功率之和保持恒定不变。
如图11所示，在天线驻波比VSWR为3的条件下，随天线相位的变化，本发明实施例提供的平衡式射频功率放大器的输出功率变化大约为1dB。图11中，曲线303为本发明所提供的平衡式功率放大器的输出功率随天线相位的变化曲线；曲线304为现有技术中单端功率放大器的输出功率随天线相位的变化曲线，其输出功率的变化大约为8dB。与现有技术相比较，本发明所提供的平衡式射频功率放大器在天线相位变化的情况下，能够很好地保持稳定的输出功率。
如图12所示，在天线驻波比VSWR为3的条件下，随天线相位的变化，本发明实施例提供的平衡式射频功率放大器工作电流的变化大约30mA。图12中，曲线305为本发明所提供的平衡式功率放大器的工作电流随天线相位的变化曲线；曲线306为现有技术中单端功率放大器的工作电流随天线相位的变化曲线，其工作电流的变化大约为300mA。与现有技术相比较，本发明所提供的平衡式射频功率放大器在天线相位变化的情况下，能够很好地保持稳定的工作电流。
通过上述分析及仿真测试结果可以看出，本发明所提供的平衡式射频功率放大器，在天线驻波比发生变化的情况下，能够有效地提高发射功率和发射效率。
另外，发明人进一步对本发明实施例所提供的平衡式射频功率放大器，应用n77频段中的增益、效率、线性度等多项性能指标进行了仿真测试，仿真测试结果如图13所示。其中，曲线501为平衡式射频功率放大器的增益曲线，在n77频段内增益偏差在±1dB以内；曲线502为平衡式射频功率放大器的线性度曲线，在n77频段内线性度偏差在 ±2dB以内；曲线503为平衡式射频功率放大器的效率曲线，在n77频段内效率偏差在2％以内；曲线504为平衡式射频功率放大器的饱和功率曲线，在n77频段内饱和功率偏差在±1dB以内。从仿真测试结果可以看出本发明实施例所提供的平衡式射频功率放大器在n77频段内增益、效率、线性度等多项性能均能够满足系统要求。
本发明实施例还提供一种射频前端模块，该射频前端模块中包括上述本发明实施例提供的平衡式射频功率放大器，可用于无线通信系统中作为移动通信终端的重要组成部分。该射频前端模块包括一个基板、至少一个射频功率放大器芯片、至少一个供电和控制芯片，以及一组由集总表面贴装元器件构成的输出匹配网络和由基板上金属线形成的输出功率合成器。其中，射频功率放大器芯片由至少一级驱动级功率单元、级间功率分配器、主路功率放大器和辅路功率放大器构成。
如图14所示，在该射频前端模块中，平衡式射频功率放大器的布局方式为，驱动级功率单元、级间功率分配器、主路功率放大器和辅路功率放大器均设置在射频功率放大器芯片上，供电和控制芯片A、供电和控制芯片B、供电和控制芯片C，以及第一输出匹配网络A、第二输出匹配网络B和输出功率合成器均设置在基板上。其中，供电和控制线路A为驱动级功率单元提供电源和控制信号，供电和控制线路B为主路功率放大器提供电源和控制信号，供电和控制线路C为辅路功率放大器提供电源和控制信号。射频功率放大器芯片与基板的封装方式为正装封装方式，主路功率放大器和辅路功率放大器的输出端分别通过金属线键合连接到第一输出匹配网络A和第二输出匹配网络B。图14中还提供了输入射频信号的流向，如箭头所示，射频输入信号从驱动级功率单元的输入端进入射频功率放大器芯片，最终由输出功率合成器的输出端传输出去。
另外，需要说明的是，在本发明的其他实施例中，供电和控制芯片A、供电和控制芯片B和供电和控制芯片C可以设置在同一颗芯片上，还可以是完全独立的三颗芯片或集成为一颗、两颗芯片。射频功率放大器芯片与基板的封装方式还可以采用倒装封装方式，主路功率放大器和辅路功率放大器的输出端分别通过铜柱或者植球直接连接到第一输出匹配网络A和第二输出匹配网络B。同样，为了节省面积， 输出功率合成器可以设置在第一输出匹配网络A和第二输出匹配网络B的侧面或者下方。
另外，本发明实施例提供的平衡式射频功率放大器还可以被用在电子设备中，作为通信组件的重要组成部分。这里所说的电子设备是指可以在移动环境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE、5G等多种通信制式的计算机设备，包括移动电话、笔记本电脑、平板电脑、车载电脑等。此外，本发明所提供的技术方案也适用于其他射频前端模块应用的场合，例如通信基站、智能网联汽车等。
如图15所示，该电子设备至少包括处理器和存储器，还可以根据实际需要进一步包括通信组件、传感器组件、电源组件、多媒体组件及输入/输出接口。其中，存储器、通信组件、传感器组件、电源组件、多媒体组件及输入/输出接口均与该处理器连接。存储器可以是静态随机存取存储器(SRAM)、电可擦除可编程只读存储器(EEPROM)、可擦除可编程只读存储器(EPROM)、可编程只读存储器(PROM)、只读存储器(ROM)、磁存储器、快闪存储器等，处理器可以是中央处理器(CPU)、图形处理器(GPU)、现场可编程逻辑门阵列(FPGA)、专用集成电路(ASIC)、数字信号处理(DSP)芯片等。其它传感器组件、电源组件、多媒体组件等均可以采用现有常规器件实现，在此就不具体说明了。
与现有技术相比较，本发明所提供的平衡式射频功率放大器，一方面，通过采用主路功率放大单元和辅路功率放大单元相互对称的平衡式设计，最大程度地克服了天线驻波比变化对发射功率和发射效率的影响。另一方面，通过采用3dB分布式正交耦合器来设计功率分配器和功率合成器，并分别在芯片级和基板上来实现，使得射频功率放大器的面积尺寸和带宽、插入损耗、发射效率等性能指标得到最佳的折中与优化。同时，通过采用线性化电路的技术方案，改善了功率放大器的增益失真和相位失真，得到较好的线性度。通过采用低阻抗输出的偏置电路的技术方案改善了功率放大器电路宽带信号的线性度，提升了宽带信号的处理能力。因此，本发明所提供的平衡式射频功率放大器具有电路设计巧妙合理、灵活性强，以及电路性能优异等有益效果，更加符合5G通信系统技术性能指标的要求。
以上对本发明所提供的平衡式射频功率放大器、射频前端模块及 电子设备进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质内容的前提下对它所做的任何显而易见的改动，都将属于本发明专利权的保护范围。

Claims (10)

  1. 一种平衡式射频功率放大器，其特征在于包括驱动级功率单元、级间功率分配器、主路功率放大器、辅路功率放大器、第一输出匹配网络(A)、第二输出匹配网络(B)和输出功率合成器；其中，
    所述驱动级功率单元的输入端接收输入射频信号，输出端与所述级间功率分配器的输入端连接，用于对输入射频信号进行驱动放大；
    所述级间功率分配器的同相输出端与所述主路功率放大器的输入端连接，正交相输出端与所述辅路功率放大器的输入端连接，用于产生两路振幅相等、相位相差90°的射频信号；
    所述主路功率放大器的输出端与所述第一输出匹配网络(A)的输入端连接，所述辅路功率放大器的输出端与所述第二输出匹配网络(B)的输入端连接；所述第一输出匹配网络(A)的输出端与所述输出功率合成器的同相输入端连接，所述第二输出匹配网络(B)的输出端与所述输出功率合成器的正交相输入端连接；
    所述输出功率合成器用于接收两路振幅相同、相位相差90°的射频信号，合成一路输出射频信号。
  2. 如权利要求1所述的平衡式射频功率放大器，其特征在于：
    所述级间功率分配器由芯片上金属耦合线组成的3dB分布式正交耦合器构成，其中采用芯片金属叠层耦合结构或者同层耦合结构。
  3. 如权利要求1所述的平衡式射频功率放大器，其特征在于：
    所述输出功率合成器由基板上金属耦合线组成的3dB分布式正交耦合器构成，其中采用基板金属叠层耦合结构或者同层耦合结构。
  4. 如权利要求1所述的平衡式射频功率放大器，其特征在于：
    所述主路功率放大器由第一电容(C9)、第一电感(L9)、第一晶体管(M1)，以及线性化电路和偏置电路构成；其中，所述主路功率放大器的输入端与第一电容(C9)、第一电感(L9)、线性化电路连接，第一电感(L9)的另一端与地电位端连接，第一电容(C9)的另一端与第一晶体管(M1)的栅极及偏置电路连接，第一晶体管(M1)的源极与地电位端连接，第一晶体管(M1)的漏极与所述主路功率放大器的输出端连接；其中，第一电容(C9)和第一电感(L9)组成输入匹 配网络。
  5. 如权利要求4所述的平衡式射频功率放大器，其特征在于：
    所述线性化电路由电阻串联正反向并联的二极管组构成；其中，电阻端连接功率放大器电路的输入端，二极管端与地电位端连接；
    所述线性化电路通过增加二极管串联数量来减弱预失真幅度，通过增加二极管并联数量或者二极管面积来加强预失真幅度。
  6. 如权利要求4所述的平衡式射频功率放大器，其特征在于：
    所述偏置电路由第七电阻(R7)、第八电阻(R8)、第三电容(C5)、第三晶体管(T1)、第四晶体管(T2)构成；其中，第三晶体管(T1)的漏极与第七电阻(R7)连接后共同与偏置电压端连接，第三晶体管(T1)的栅极与第七电阻(R7)的另一端及第三电容(C5)、第四晶体管(T2)的漏极连接，第三电容(C5)的另一端与地电位端连接，第四晶体管(T2)的源极与地电位端连接，第四晶体管(T2)的栅极通过第八电阻(R8)与第三晶体管(T1)的源极及偏置电流输出端连接；
    其中，所述第三晶体管(T1)为射级跟随器晶体管，所述第四晶体管(T2)为反馈放大晶体管。
  7. 如权利要求1所述的平衡式射频功率放大器，其特征在于：
    所述第一输出匹配网络(A)和所述第二输出匹配网络(B)均为集总器件构成的高带宽匹配网络；
    所述第一输出匹配网络(A)由第四电容(C1)、第五电容(C2)、第六电容(C3)、第七电容(C4)，以及第三电感(L1)、第四电感(L2)、第五电感(L3)和第六电感(L4)构成；其中，所述第一输出匹配网络(A)的输入端分别与第五电容(C2)、第六电容(C3)及第三电感(L1)连接；第五电容(C2)的另一端与第四电感(L2)连接，第四电感(L2)的另一端与地电位端连接；第三电感(L1)的另一端与电源电压端及第四电容(C1)连接，第四电容(C1)的另一端与地电位端连接；第六电容(C3)的另一端与第五电感(L3)、第六电感(L4)连接，第五电感(L3)的另一端与地电位端连接，第六电感(L4)的另一端与第七电容(C4)及所述第一输出匹配网络(A)的输出端连接，第七电容(C4)的另一端与地电位端连接；其中，
    所述第四电容(C1)为电源滤波电容，所述第一输出匹配网络(A)和所述第二输出匹配网络(B)合用一个电源滤波电容；
    所述第五电容(C2)和所述第四电感(L2)串联构成调节谐波阻抗的谐振网络，所述第五电容(C2)采用可变电容；
    所述第六电容(C3)、第七电容(C4)和第五电感(L3)和第六电感(L4)构成CLLC型阻抗匹配网络。
  8. 如权利要求1所述的平衡式射频功率放大器，其特征在于：
    当天线相位发生变化时，所述平衡式射频功率放大器的主路功率放大单元的负载线阻抗和辅路功率放大单元的负载线阻抗发生交替变化，该两路功率放大单元的输出功率和输出电流也发生交替变化，使得变化量相互补偿。
  9. 一种射频前端模块，基于权利要求1～8中任意一项所述的平衡式射频功率放大器实现，其特征在于包括基板、至少一个射频功率放大器芯片、至少一组输出匹配网络和输出功率合成器；其中，
    所述平衡式射频功率放大器中的所述驱动级功率单元、所述级间功率分配器、所述主路功率放大器和所述辅路功率放大器均集成在所述射频功率放大器芯片上；
    所述射频功率放大器芯片与所述基板之间采用正装封装方式或者倒装封装方式；
    所述主路功率放大器和所述辅路功率放大器的输出端分别通过金属线键合连接到第一输出匹配网络(A)和第二输出匹配网络(B)，并分别通过铜柱或者植球直接连接到第一输出匹配网络(A)和第二输出匹配网络(B)。
  10. 一种电子设备，其特征在于其中包括权利要求1～8中任意一项所述的平衡式射频功率放大器。
PCT/CN2023/119549 2022-09-30 2023-09-18 一种平衡式射频功率放大器、射频前端模块及电子设备 WO2024067226A1 (zh)

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