WO2024066699A1 - 时钟同步方法及装置 - Google Patents

时钟同步方法及装置 Download PDF

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Publication number
WO2024066699A1
WO2024066699A1 PCT/CN2023/108936 CN2023108936W WO2024066699A1 WO 2024066699 A1 WO2024066699 A1 WO 2024066699A1 CN 2023108936 W CN2023108936 W CN 2023108936W WO 2024066699 A1 WO2024066699 A1 WO 2024066699A1
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Prior art keywords
clock
adjustment
offset
proportional
integral
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PCT/CN2023/108936
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English (en)
French (fr)
Inventor
李政
王一凡
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三维通信股份有限公司
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Publication of WO2024066699A1 publication Critical patent/WO2024066699A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Definitions

  • the present application relates to the field of communication technology, and in particular to a clock synchronization method and device.
  • Clock synchronization technology is a basic technology of communication system.
  • the purpose of clock synchronization is to ensure that the time of the transmitter and the receiver are in step with each other to achieve correct and reliable communication.
  • Each device in the communication network usually performs time synchronization based on the Precision Time Protocol (PTP).
  • PTP Precision Time Protocol
  • the clock synchronization algorithm commonly used in the related art mainly includes obtaining the clock offset of the local clock relative to the reference clock through PTP, then counting the clock offset through a counter, and obtaining the specific number of clock cycles of the offset, and finally calibrating the local clock according to the number of clock cycles of the offset.
  • the counter and the module for calibration are usually two different modules.
  • the counter can be implemented using a Field Programmable Gate Array (FPGA) module
  • the module for calibration can be implemented using a high-performance RISC machine (Advanced RISC Machines, ARM) module.
  • the above clock synchronization method not only has many processes, but also involves many modules. Especially in the counter counting link, it often takes a lot of time, resulting in a long time consumption of the entire time synchronization process. The longer the time synchronization consumes, the greater the error of the time offset, which cannot meet the time synchronization requirements of the communication system. On the other hand, due to its own characteristics, the counter will also have certain errors in the counting process, resulting in large errors in the calibrated clock data.
  • the present application provides a clock synchronization method and device.
  • an embodiment of the present application provides a clock synchronization method, including:
  • the local clock is adjusted using the clock adjustment amount.
  • the proportional adjustment and integration of the clock offset further comprises:
  • a clock adjustment amount for the local clock is determined according to the offset difference, the proportional adjustment coefficient, and the integral adjustment coefficient.
  • determining the clock adjustment amount for the local clock according to the offset difference, the proportional adjustment coefficient, and the integral adjustment coefficient includes:
  • P is the proportional adjustment coefficient
  • I is the integral adjustment coefficient
  • timeoffset(k) is the clock offset at the kth moment
  • timeoffset(k-1) is the clock offset at the (k-1)th moment.
  • the proportional adjustment coefficient and the integral adjustment coefficient are generated in the following manner:
  • the historical data including a clock offset before adjustment of the local clock, an offset difference between the clock offset and the clock offset at a previous moment, and a clock adjustment amount for the local clock;
  • the proportional-integral regulation mathematical model is trained using the historical data, and numerical values of the proportional regulation coefficient and the integral regulation coefficient are obtained by fitting.
  • the method further includes:
  • a predicted adjustment amount for the local clock is determined according to the adjustment rule.
  • an embodiment of the present application provides a clock synchronization device, including:
  • a clock offset acquisition module used to obtain the clock offset between the local clock and the reference clock
  • An adjustment amount determination module configured to generate a clock adjustment amount for the local clock based on proportional adjustment and integral adjustment of the clock offset
  • a clock adjustment module is used to adjust the local clock using the clock adjustment amount.
  • the adjustment amount determination module is specifically used to:
  • an embodiment of the present application further proposes a processing device, comprising a processor and a memory for storing processor executable instructions, wherein the processor is configured to implement the clock synchronization method when executing the instructions.
  • an embodiment of the present application further proposes a non-volatile computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions implement the clock synchronization method when executed by a processor.
  • an embodiment of the present application provides a computer program product, comprising a computer-readable code, or a non-volatile computer-readable storage medium carrying a computer-readable code.
  • the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the clock synchronization method.
  • FIG1 is a schematic diagram of a method flow of a clock synchronization method according to one or more embodiments.
  • FIG. 2 is a schematic diagram of a module structure of a clock synchronization device according to one or more embodiments.
  • FIG3 is a schematic diagram of a module structure of a processing device according to one or more embodiments.
  • FIG. 4 is a conceptual partial view of a computer program product according to one or more embodiments.
  • the present application provides a clock synchronization method, comprising the following steps S101-S105.
  • the local clock includes a clock signal to be corrected, which can be integrated into the internal
  • the circuit signal generated by the clock circuit on the local chip or circuit board may also be a circuit signal generated by the clock circuit on the external chip or circuit board, and the present application does not limit this.
  • the reference clock may include a clock signal that can be used as a calibration of the local clock, for example, it may include a clock signal based on GPS, and the clock signal based on GPS includes a clock signal that can be highly synchronized with the Beidou satellite or GPS. Based on the local clock and the reference clock, the clock offset of the local clock and the reference clock can be obtained. In one embodiment, the clock offset between the local clock and the reference clock can be determined based on the Precision Time Protocol (PTP).
  • PTP Precision Time Protocol
  • two time nodes i.e., the nodes of the local clock and the reference clock
  • PTP protocol a physical layer chip (PHY chip) that supports the PTP protocol (such as the IEEE1588 protocol) can be used to record the time when the network receives the time synchronization message or sends the time synchronization message.
  • the intermediate network nodes such as switches and routers can record the time when the time synchronization message stays, realize the accurate calculation of the link delay, and thus determine the clock offset between the local clock and the reference clock.
  • the clock offset between the local clock and the reference clock may also be determined based on the Network Time Protocol (NTP), Synchronized Ethernet (SyncE), etc., and this application does not limit this.
  • NTP Network Time Protocol
  • Synchronized Ethernet Synchronized Ethernet
  • the clock offset between the local clock and the reference clock can be obtained according to a preset time rule, and the adjustment amount of the local clock can be determined, for example, the local clock is adjusted every 30 seconds, 1 minute, or 5 minutes.
  • the local clock can also be adjusted in an irregular or user-specified manner, and this application does not limit this.
  • S103 Generate an adjustment amount for the local clock based on proportional adjustment and integral adjustment of the clock offset.
  • the clock offset after determining the clock offset, can be proportionally adjusted and integrally adjusted, and based on the results of the proportional adjustment and the integral adjustment, an adjustment amount for the local clock can be generated.
  • the clock offset between the local clock and the reference clock is adjusted through the two links of proportional adjustment and the integral adjustment, wherein the proportional adjustment link can reduce the deviation of the local clock by adjusting the local clock, and the integral adjustment link can eliminate the steady-state error of the clock offset and improve the error-free degree.
  • the generating of the clock adjustment amount for the local clock based on the proportional adjustment and the integral adjustment of the clock offset may include:
  • S203 Determine a clock adjustment amount for the local clock according to the offset difference, the proportional adjustment coefficient, and the integral adjustment coefficient.
  • the error of the local clock is not only reflected in the clock offset at the current moment, but also in the offset difference between the clock offset at the current moment and the clock offset at the previous moment. Therefore, the error adjustment for the local clock can be performed by using the offset difference to improve the accuracy of the adjustment.
  • the proportional adjustment coefficient and the integral adjustment coefficient of the proportional adjustment and the integral adjustment coefficient are used to determine the clock adjustment amount for the local clock according to the offset difference, the proportional adjustment coefficient and the integral adjustment coefficient.
  • the accuracy of the proportional adjustment coefficient and the integral adjustment coefficient determines the accuracy of the proportional adjustment and the integral adjustment.
  • the proportional adjustment coefficient if the proportional adjustment coefficient is set so that the proportional adjustment effect is too large, although it can speed up the adjustment and reduce the error, it may cause the stability of the clock system to decrease.
  • the proportional adjustment coefficient and the integral adjustment coefficient can be determined respectively according to historical data. Specifically, first, historical data can be obtained, and the historical data can include the clock offset before the local clock is adjusted, the offset difference between the clock offset and the clock offset at the previous moment, and the clock adjustment amount of the local clock.
  • a proportional-integral adjustment mathematical model can be constructed, and the proportional-integral adjustment mathematical model is provided with a proportional adjustment coefficient and an integral adjustment coefficient.
  • the proportional adjustment coefficient and the integral adjustment coefficient are unknown parameters to be adjusted.
  • the proportional-integral adjustment mathematical model can be trained using the historical data, and the numerical values of the proportional adjustment coefficient and the integral adjustment coefficient can be obtained by fitting.
  • the training method can include mathematical fitting algorithm, machine learning, etc., which are not limited in this application.
  • a specific formula may be provided to determine the clock adjustment amount for the local clock.
  • the determining the clock adjustment amount for the local clock according to the offset difference, the proportional adjustment coefficient and the integral adjustment coefficient may include:
  • P is the proportional adjustment coefficient
  • I is the integral adjustment coefficient
  • time offset(k) is the clock offset at the kth moment
  • time offset(k-1) is the clock offset at the (k-1)th moment.
  • time offset(k) -time offset(k-1) is the offset difference between the clock error at the current moment and the clock error at the previous moment.
  • the above formula adjusts the offset difference according to the proportional adjustment coefficient based on I ⁇ time offset(k) , which can not only reduce the error of local clock adjustment, but also eliminate the steady-state error of the clock system.
  • the local clock can be adjusted according to the adjustment amount, so as to achieve the local Precise synchronization between the clock and the reference clock.
  • the clock offset between the local clock and the reference clock can be first obtained, and then the clock adjustment amount for the local clock can be generated based on the proportional adjustment and integral adjustment of the clock offset.
  • the clock offset between the local clock and the reference clock is adjusted through the two links of proportional adjustment and integral adjustment, wherein the proportional adjustment link can reduce the deviation of the local clock by adjusting the local clock, and the integral adjustment link can eliminate the steady-state error of the clock offset and improve the error-free degree.
  • the external clock source GPS, etc.
  • the device enters the punctual state, that is, the holdover state, which can keep the clock system of the device stable and will not cause continuous clock discreteness.
  • the method further includes:
  • the clock adjustment amount of the local clock for multiple times within a preset time period before the local clock enters the holdover mode can be obtained.
  • the clock adjustment amount for the local clock N times within the time period (tt 0 , t) can be obtained.
  • the clock offset between the local clock and the reference clock during this time period can also be obtained, and then the final adjustment amount for the local clock is determined according to formula (1). Since formula (1) is a linear adjustment method, it is equivalent to obtain the clock adjustment amount and clock offset within the time period t 0 .
  • the adjustment rules for the clock adjustment values for the local clock can be determined.
  • the rule of the change of the clock adjustment value over time within the preset time period can be determined, such as fitting the clock adjustment value into a curve and determining the expression of the curve.
  • the adjustment rule can also be determined by machine learning. Law, for example, building a machine learning model to learn the adjustment law of the clock adjustment amount for the local clock within the preset time period. This application does not limit the method for determining the adjustment law.
  • the predicted adjustment amount for the local clock can be determined according to the adjustment rule. For example, the predicted adjustment amount for the local clock at a future time can be determined according to the fitted curve, and of course, the predicted adjustment amount for the local clock at a future time can also be determined according to a machine learning model.
  • the predicted adjustment amount of the local clock when it is determined that the local clock enters the holdover mode, can be predicted based on the adjustment rule of the clock adjustment amount of the local clock in the normal mode, thereby solving the technical problem of having no reference clock as a reference in the holdover mode.
  • the present application further provides a clock synchronization device 200, as shown in FIG2, the clock synchronization device 200 comprises:
  • the clock offset acquisition module 201 is used to acquire the clock offset between the local clock and the reference clock;
  • An adjustment amount determination module 203 configured to generate a clock adjustment amount for the local clock based on proportional adjustment and integral adjustment of the clock offset;
  • the clock adjustment module 205 is configured to adjust the local clock using the clock adjustment amount.
  • the adjustment amount determination module 203 is specifically configured to:
  • a clock adjustment amount for the local clock is determined according to the offset difference, the proportional adjustment coefficient, and the integral adjustment coefficient.
  • the embodiments described above are merely illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.
  • the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.
  • an embodiment of the present application further provides a processing device 600, which includes: a processor and a memory for storing processor executable instructions; wherein the processor is configured to implement the above method when executing the instructions.
  • the processing device 600 includes a memory 601, a processor 603, a bus 605, and a communication interface 607.
  • the memory 601, the processor 603 and the communication interface 607 communicate through the bus 605.
  • the bus 605 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in FIG3 , but it does not mean that there is only one bus or one type of bus. line.
  • the communication interface 607 is used to communicate with the outside.
  • the processor 603 can be a central processing unit (CPU).
  • the memory 601 can include a volatile memory (volatile memory), such as a random access memory (random access memory, RAM).
  • the memory 601 can also include a non-volatile memory (non-volatile memory), such as a read-only memory (read-only memory, ROM), a flash memory, a HDD or a SSD.
  • the memory 601 stores an executable code, and the processor 603 executes the executable code to execute the aforementioned clock synchronization method.
  • An embodiment of the present application provides a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above method is implemented.
  • An embodiment of the present application provides a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code.
  • the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.
  • FIG. 4 schematically illustrates a conceptual partial view of an example computer program product arranged according to at least some of the embodiments presented herein, the example computer program product comprising a computer program for executing a computer process on a computing device.
  • the example computer program product 700 is provided using a signal-bearing medium 701.
  • the signal-bearing medium 701 may include one or more program instructions 702, which when executed by one or more processors may provide the functions or portions of the functions described above for FIG. 1.
  • the program instructions 702 in FIG. 4 also describe example instructions.
  • the signal bearing medium 701 may include a computer readable medium 703, such as, but not limited to, a hard drive, a compact disk (CD), a digital video disk (DVD), a digital tape, a memory, a read-only memory (ROM) or a random access memory (RAM), etc.
  • the signal bearing medium 701 may include a computer recordable medium 704, such as, but not limited to, a memory, a read/write (R/W) CD, a R/W DVD, etc.
  • the signal bearing medium 701 may include a communication medium 705, such as, but not limited to, a digital and/or analog communication medium (e.g., a fiber optic cable, a waveguide, a wired communication link, a wireless communication link, etc.).
  • a communication medium 705 such as, but not limited to, a digital and/or analog communication medium (e.g., a fiber optic cable, a waveguide, a wired communication link, a wireless communication link, etc.).
  • the signal bearing medium 701 may be communicated by a wireless form of the communication medium 705 (e.g., a wireless communication medium that complies with the IEEE 802.11 standard or other transmission protocol).
  • One or more program instructions 702 may be, for example, computer executable instructions or logic implementation instructions.
  • such as a computing device may be configured to provide various operations, functions, or actions in response to program instructions 702 communicated to the computing device via one or more of computer-readable media 703, computer-recordable media 704, and/or communication media 705.
  • program instructions 702 communicated to the computing device via one or more of computer-readable media 703, computer-recordable media 704, and/or communication media 705.
  • each square frame in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification.
  • the function marked in the square frame can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square frames can actually be executed substantially in parallel, and they can also be executed in reverse order sometimes, depending on the function involved.
  • each box in the block diagram and/or flowchart, and the combination of boxes in the block diagram and/or flowchart can be implemented by hardware (such as circuits or ASICs (Application Specific Integrated Circuit)) that performs the corresponding function or action, or can be implemented by a combination of hardware and software, such as firmware.
  • HDL There is not only one HDL, but many types, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc.
  • VHDL Very-High-Speed Integrated Circuit Hardware Description Language
  • the adjustment amount determination module 203 can be implemented in any appropriate manner.
  • the adjustment amount determination module 203 can be in the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) executable by the (micro)processor, a logic gate, a switch, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller.
  • a computer-readable program code such as software or firmware
  • ASIC application specific integrated circuit
  • the adjustment amount determination module 203 include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320.
  • the memory controller can also be implemented as part of the control logic of the memory.
  • the adjustment amount determination module 203 can be implemented in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps to achieve the same function. Therefore, the adjustment amount determination module 203 can be considered as a hardware component, and the means for implementing various functions included therein can also be considered as a structure within the hardware component. Or even, the means for implementing various functions can be considered as both a software module for implementing the method and a structure within the hardware component.

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Abstract

一种时钟同步方法及装置。方法包括：获取本地时钟与基准时钟的时钟偏移；基于对所述时钟偏移的比例调节和积分调节，生成针对所述本地时钟的时钟调整量；利用所述时钟调整量对所述本地时钟进行调整。

Description

时钟同步方法及装置
相关申请
本申请要求2022年9月26日申请的，申请号为202211172113.0，名称为“一种时钟同步方法及装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及通信技术领域，尤其涉及一种时钟同步方法及装置。
背景技术
时钟同步技术是通信系统的基本技术，时钟同步的目的在于确保发送端与接收端的时间步调一致，以实现正确可靠的通信。通信网络中的各设备通常基于精确时间协议(Precision Time Protocol，PTP)进行时间同步。相关技术中常用的时钟同步算法主要包括，通过PTP获取本地时钟相对于基准时钟的时钟偏移，然后通过计数器对所述时钟偏移进行计数，并得到具体的偏移的时钟周期数，最后，根据偏移的时钟周期数对本地时钟进行校准。另外，计数器和用于校准的模块通常是两个不同的模块，例如，计数器可以利用现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)模块实现，用于校准的模块可以利用高性能RISC机器(Advanced RISC Machines，ARM)模块实现。
不难发现，上述时钟同步方法不仅流程较多，涉及到的模块也较多，尤其在计数器计数环节中，往往需要消耗较多的时间，导致整个时间同步过程消耗的时间较长，时间同步消耗的时间越长，导致时间偏移的误差越大，无法满足通信系统中对于时间同步的需求。另一方面，计数器由于自身特性在计数过程中也会出现一定的误差，从而导致校准的时钟数据的误差较大。
发明内容
本申请提供一种时钟同步方法及装置。
第一方面，本申请实施例提出一种时钟同步方法，包括：
获取本地时钟与基准时钟的时钟偏移；
基于对所述时钟偏移的比例调节和积分调节，生成针对所述本地时钟的时钟调整量；
利用所述时钟调整量对所述本地时钟进行调整。
在一实施例中，在本申请的一个实施例中，所述基于对所述时钟偏移的比例调节和积 分调节，生成针对所述本地时钟的时钟调整量，包括：
获取所述时钟偏移与上一时刻时钟偏移之间的偏移差、比例调节系数和积分调节系数；
根据所述偏移差、所述比例调节系数和所述积分调节系数，确定针对所述本地时钟的时钟调整量。
在一实施例中，在本申请的一个实施例中，所述根据所述偏移差、所述比例调节系数和所述积分调节系数，确定针对所述本地时钟的时钟调整量，包括：
构建用于确定针对所述本地时钟的时钟调整量Δoutput的表达式：
Δoutput＝P×(timeoffset(k)-timeoffset(k-1))+I×timeoffset(k)
其中，P为比例调节系数，I为积分调节系数，timeoffset(k)为第k时刻的时钟偏移，timeoffset(k-1)为第(k-1)时刻的时钟偏移。
在一实施例中，在本申请的一个实施例中，所述比例调节系数和所述积分调节系数按照下述方式生成：
获取历史数据，所述历史数据包括历史上对本地时钟调整前的时钟偏移、所述时钟偏移与上一时刻时钟偏移之间的偏移差以及对本地时钟的时钟调整量；
构建比例积分调节数学模型，所述比例积分调节数学模型中设置有比例调节系数和积分调节系数；
利用所述历史数据对所述比例积分调节数学模型进行训练，并拟合得到所述比例调节系数和所述积分调节系数的数值。
在一实施例中，在本申请的一个实施例中，所述方法还包括：
在确定所述本地时钟进入holdover模式的情况下，获取所述本地时钟在进入holdover模式前的预设时间段内多次针对所述本地时钟的时钟调整量；
确定所述多次针对所述本地时钟的时钟调整量的调整规律；
根据所述调整规律确定针对所述本地时钟的预测调整量。
第二方面，本申请实施例提出一种时钟同步装置，包括：
时钟偏移获取模块，用于获取本地时钟与基准时钟的时钟偏移；
调整量确定模块，用于基于对所述时钟偏移的比例调节和积分调节，生成针对所述本地时钟的时钟调整量；
时钟调整模块，用于利用所述时钟调整量对所述本地时钟进行调整。
在一实施例中，在本申请的一个实施例中，所述调整量确定模块，具体用于：
获取所述时钟偏移与上一时刻时钟偏移之间的偏移差、比例调节系数和积分调节系数；
根据所述偏移差、所述比例调节系数和所述积分调节系数，确定针对所述本地时钟的 时钟调整量。
第三方面，本申请实施例还提出一种处理设备，包括处理器以及用于存储处理器可执行指令的存储器，其中，所述处理器，用于被配置为执行所述指令时实现所述的时钟同步方法。
第四方面，本申请实施例还提出一种非易失性计算机可读存储介质，其上存储有计算机程序指令，所述计算机程序指令被处理器执行时实现所述的时钟同步方法。
第五方面，本申请实施例一种计算机程序产品，包括计算机可读代码，或者承载有计算机可读代码的非易失性计算机可读存储介质，当所述计算机可读代码在电子设备的处理器中运行时，所述电子设备中的处理器执行所述的时钟同步方法。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是根据一个或多个实施例的一种时钟同步方法的方法流程示意图。
图2是根据一个或多个实施例的一种时钟同步装置的模块结构示意图。
图3是根据一个或多个实施例的一种处理设备的模块结构示意图。
图4是根据一个或多个实施例的一种计算机程序产品的一种概念性局部视图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置的例子。
为了方便本领域技术人员理解本申请实施例提供的技术方案，下面首先通过图1对技术方案实现的技术环境进行说明。
本申请提供了一种时钟同步方法，包括以下步骤S101-S105。
S101：获取本地时钟与基准时钟的时钟偏移。
本申请实施例中，所述本地时钟包括待校正的时钟信号，该时钟信号可以为集成于内 部芯片或者电路板上的时钟电路所产生的电路信号，也可以为外部芯片或者电路板上的时钟电路所产生的电路信号，本申请在此不做限制。所述基准时钟可以包括能够作为校准所述本地时钟的时钟信号，例如可以包括基于GPS的时钟信号，基于GPS的时钟信号包括能够与北斗卫星或者GPS高度同步的时钟信号。基于所述本地时钟与所述基准时钟，可以获取所述本地时钟与所述基准时钟的时钟偏移。在一种实施例中，可以基于精确时间同步协议(Precision Time Protocol，PTP)确定所述本地时钟与所述基准时钟之间的时钟偏移。在PTP协议中，两个时间节点(即本地时钟与基准时钟的节点)可以在网络链路层打上时间戳，并利用支持PTP协议(如IEEE1588协议)的物理层芯片(PHY芯片)记录网络接收时间同步报文或发送时间同步报文的时刻。而交换机、路由器等网络中间节点可以记录时间同步报文停留的时间，实现对链路时延的准确计算，从而确定本地时钟与基准时钟之间的时钟偏移。当然，在其他实施例中，还可以基于网络时间协议(Network Time Protocol，NTP)、同步以太网(Synchronized Ethernet，SyncE)等确定所述本地时钟与基准时钟之间的时钟偏移，本申请在此不做限制。
需要说明的是，可以按照预设的时间规律获取本地时钟与基准时钟的时钟偏移，并确定对本地时钟的调整量，例如每隔30秒、1分钟、5分钟调整一次本地时钟。当然，也可以按照不定期的或者用户指定的方式调整所述本地时钟，本申请在此不做限制。
S103：基于对所述时钟偏移的比例调节和积分调节，生成针对所述本地时钟的调整量。
本申请实施例中，在确定所述时钟偏移后，可以基于对所述时钟偏移进行比例调节和积分调节，并基于所述比例调节和所述积分调节的结果，生成针对所述本地时钟的调整量。通过比例调节和所述积分调节两个环节对所述本地时钟和所述基准时钟之间的时钟偏移进行调节，其中，所述比例调节环节可以通过调节本地时钟以减少本地时钟的偏差量，而所述积分调节环节可以消除所述时钟偏移的稳态误差，提高无误差度。
在本申请的一个实施例中，所述基于对所述时钟偏移的比例调节和积分调节，生成针对所述本地时钟的时钟调整量，可以包括：
S201：获取所述时钟偏移与上一时刻时钟偏移之间的偏移差、比例调节系数和积分调节系数；
S203：根据所述偏移差、所述比例调节系数和所述积分调节系数，确定针对所述本地时钟的时钟调整量。
本申请实施例中，所述本地时钟的误差不仅体现在当前时刻的时钟偏移，还体现在当前时刻的时钟偏移与上一时刻的时钟偏移之间的偏移差，因此，利用所述偏移差参与针对本地时钟的误差调节，能够提升调节的准确性。不仅如此，本申请实施例还可以分别设置 比例调节和积分调节的比例调节系数和积分调节系数，并根据所述偏移差、所述比例调节系数和所述积分调节系数，确定针对所述本地时钟的时钟调整量。
在实际情况中，所述比例调节系数和所述积分调节系数的准确性决定了比例调节和积分调节的准确度，例如，对于比例调节系数来说，若设置的比例调节系数使得比例调节作用过大，虽然可以加快调节、减少误差，但是可能会导致时钟系统的稳定性降低。基于此，在本申请的一个实施例中，可以根据历史数据分别确定所述比例调节系数和所述积分调节系数。具体来说，首先，可以获取历史数据，所述历史数据可以包括历史上对本地时钟调整前的时钟偏移、所述时钟偏移与上一时刻时钟偏移之间的偏移差以及对本地时钟的时钟调整量。然后，可以构建比例积分调节数学模型，所述比例积分调节数学模型中设置有比例调节系数和积分调节系数。当然，对应所述比例积分调节数学模型的初始模型中，所述比例调节系数和所述积分调节系数为待调节的未知参数。在此基础上，可以利用所述历史数据对所述比例积分调节数学模型进行训练，并拟合得到所述比例调节系数和所述积分调节系数的数值。其中，训练的方式可以包括数学拟合算法、机器学习等等，本申请在此不做限制。
通过上述实施例的方式，能够获取到准确的比例调节系数和积分调节系数，这是由于所述历史数据均为大量的真实数据，基于对历史数据的学习，能够确定得到更加符合实际情况的比例调节系数和积分调节系数，相比于相关技术中利用经验值确定所述比例调节系数和所述积分调节系数的方式，更加准确、可靠。
在本申请的一个实施例中，可以提供一种具体的公式确定针对所述本地时钟的时钟调整量。具体地，所述根据所述偏移差、所述比例调节系数和所述积分调节系数，确定针对所述本地时钟的时钟调整量，可以包括：
构建用于确定针对所述本地时钟的时钟调整量Δoutput的表达式：
Δoutput＝P×(timeoffset(k)-timeoffset(k-1))+I×timeoffset(k)         (1)
其中，P为比例调节系数，I为积分调节系数，timeoffset(k)为第k时刻的时钟偏移，timeoffset(k-1)为第(k-1)时刻的时钟偏移。
利用上述公式，(timeoffset(k)-timeoffset(k-1))即为当前时刻的时钟误差与其上一时刻的时钟误差之间的偏移差。上述公式在I×timeoffset(k)的基础上，按照比例调节系数对所述偏移差进行调节，不仅可以减少对本地时钟调节的误差，还可以消除时钟系统的稳态误差。
S105：利用所述调整量对所述本地时钟进行调整。
本申请实施例中，可以根据所述调整量对所述本地时钟进行调整，从而实现所述本地 时钟与所述基准时钟之间的精准同步。
通过上述步骤，可以解决相关技术中时间同步消耗的时间越长，导致时间偏移的误差越大，无法满足通信系统中对于时间同步需求的问题，以及解决因计数器等中间环节消耗较多的时间导致校准误差的问题。
本申请实施例中，首先可以获取本地时钟与基准时钟的时钟偏移，再基于对所述时钟偏移的比例调节和积分调节，生成针对所述本地时钟的时钟调整量。通过比例调节和所述积分调节两个环节对所述本地时钟和所述基准时钟之间的时钟偏移进行调节，其中，所述比例调节环节可以通过调节本地时钟以减少本地时钟的偏差量，而所述积分调节环节可以消除所述时钟偏移的稳态误差，提高无误差度。另外，在时钟同步后，移除外部时钟源(GPS等)，设备进入守时状态，即holdover状态，可以保持设备的时钟系统稳定，不会产生时钟持续离散。
需要说明的是，设备进入holdover状态，是指设备的时钟系统与外部时钟源失去联系，而使用内置的时钟源继续计时的状态。
在实际应用中，在系统运行过程中，用于校正所述本地时钟的所述基准时钟可能出现丢失的情况，即本地时钟进入holdover模式，此时系统将出现无法校正的状态。基于此，在本申请的一个实施例中，所述方法还包括：
S301：在确定所述本地时钟进入holdover模式的情况下，获取所述本地时钟在进入holdover模式前的预设时间段内多次针对所述本地时钟的时钟调整量；
S303：确定所述多次针对所述本地时钟的时钟调整量的调整规律；
S305：根据所述调整规律确定针对所述本地时钟的预测调整量。
本申请实施例中，在识别到所述本地时钟进入holdover模式的情况下，可以获取所述本地时钟在进入holdover模式前的预设时间段内多次针对所述本地时钟的时钟调整量。在一个具体示例中，在t时刻确定本地时钟进入holdover模式的情况下，可以获取(t-t0,t)这段时间内N次针对所述本地时钟的时钟调整量。当然，在其他实施例中，也可以获取在这段时间内所述本地时钟与所述基准时钟之间的时钟偏移，再根据公式(1)的方式确定最终对所述本地时钟的调整量，由于公式(1)为线性调整方式，因此，获取t0时间段内的时钟调整量和时钟偏移是等效的。
在获取到所述预设时间段内多次针对所述本地时钟的时钟调整量后，可以确定所述多次针对所述本地时钟的时钟调整量的调整规律。在其中的一个实施例中，可以确定在所述预设时间段内所述时钟调整量随时间变化的规律，如将所述时钟调整量拟合成曲线，并确定该曲线的表达式。当然，在其他实施例中，还可以利用机器学习的方式确定所述调整规 律，例如构建一个机器学习模型，以学习在所述预设时间段内针对本地时钟的时钟调整量的调整规律，本申请对于确定所述调整规律的方式不做限定。
在确定所述调整规律之后，可以根据所述调整规律确定针对所述本地时钟的预测调整量。例如，可以根据拟合得到的曲线确定在未来时间对本地时钟的预测调整量，当然，还可以根据机器学习模型确定在未来时间对本地时钟的预测调整量。
本申请实施例中，在确定所述本地时钟进入holdover模式的情况下，能够根据在正常模式下对本地时钟的时钟调整量的调整规律，预测对本地时钟的预测调整量，从而解决在holdover模式下没有基准时钟作为参考的技术问题。
本申请另一方面还提供一种时钟同步装置200，如图2所示，所述时钟同步装置200包括：
时钟偏移获取模块201，用于获取本地时钟与基准时钟的时钟偏移；
调整量确定模块203，用于基于对所述时钟偏移的比例调节和积分调节，生成针对所述本地时钟的时钟调整量；
时钟调整模块205，用于利用所述时钟调整量对所述本地时钟进行调整。
可选的，在本申请的一个实施例中，所述调整量确定模块203，具体用于：
获取所述时钟偏移与上一时刻时钟偏移之间的偏移差、比例调节系数和积分调节系数；
根据所述偏移差、所述比例调节系数和所述积分调节系数，确定针对所述本地时钟的时钟调整量。
另外需说明的是，以上所描述的实施例仅仅是示意性的，其中所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。另外，本申请提供的装置实施例附图中，模块之间的连接关系表示它们之间具有通信连接，具体可以实现为一条或多条通信总线或信号线。
如图3所示，本申请的实施例还提供了一种处理设备600，该处理设备600包括：处理器以及用于存储处理器可执行指令的存储器；其中，所述处理器被配置为执行所述指令时实现上述方法。处理设备600包括存储器601、处理器603、总线605、通信接口607。存储器601、处理器603和通信接口607之间通过总线605通信。总线605可以是外设部件互连标准(peripheral component interconnect，PCI)总线或扩展工业标准结构(extended industry standard architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图3中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总 线。通信接口607用于与外部通信。其中，处理器603可以为中央处理器(central processing unit，CPU)。存储器601可以包括易失性存储器(volatile memory)，例如随机存取存储器(random access memory，RAM)。存储器601还可以包括非易失性存储器(non-volatile memory)，例如只读存储器(read-only memory，ROM)，快闪存储器，HDD或SSD。存储器601中存储有可执行代码，处理器603执行该可执行代码以执行前述时钟同步的方法。
本申请的实施例提供了一种计算机可读存储介质，其上存储有计算机程序指令，所述计算机程序指令被处理器执行时实现上述方法。
本申请的实施例提供了一种计算机程序产品，包括计算机可读代码，或者承载有计算机可读代码的非易失性计算机可读存储介质，当所述计算机可读代码在电子设备的处理器中运行时，所述电子设备中的处理器执行上述方法。
在一些实施例中，所公开的方法可以实施为以机器可读格式被编码在计算机可读存储介质上的或者被编码在其它非瞬时性介质或者制品上的计算机程序指令。图4示意性地示出根据这里展示的至少一些实施例而布置的示例计算机程序产品的概念性局部视图，所述示例计算机程序产品包括用于在计算设备上执行计算机进程的计算机程序。在一个实施例中，示例计算机程序产品700是使用信号承载介质701来提供的。所述信号承载介质701可以包括一个或多个程序指令702，其当被一个或多个处理器运行时可以提供以上针对图1描述的功能或者部分功能。此外，图4中的程序指令702也描述示例指令。
在一些示例中，信号承载介质701可以包含计算机可读介质703，诸如但不限于，硬盘驱动器、紧密盘(CD)、数字视频光盘(DVD)、数字磁带、存储器、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等等。在一些实施方式中，信号承载介质701可以包含计算机可记录介质704，诸如但不限于，存储器、读/写(R/W)CD、R/W DVD、等等。在一些实施方式中，信号承载介质701可以包含通信介质705,诸如但不限于，数字和/或模拟通信介质(例如，光纤电缆、波导、有线通信链路、无线通信链路、等等)。因此，例如，信号承载介质701可以由无线形式的通信介质705(例如，遵守IEEE 802.11标准或者其它传输协议的无线通信介质)来传达。一个或多个程序指令702可以是，例如，计算机可执行指令或者逻辑实施指令。在一些示例中，诸如计算设备可以被配置为，响应于通过计算机可读介质703、计算机可记录介质704、和/或通信介质705中的一个或多个传达到计算设备的程序指令702，提供各种操作、功能、或者动作。应该理解，这里描述的布置仅仅是用于示例的目的。因而，本领域技术人员将理解，其它布置和其它元素(例如，机器、接口、功能、顺序、和功能组等等)能够被取而代之地使用，并且一些元素可以根据所期望的结果而一并省略。另外，所描述的元 素中的许多是可以被实现为离散的或者分布式的组件的、或者以任何适当的组合和位置来结合其它组件实施的功能实体。
附图中的流程图和框图显示了根据本申请的多个实施例的装置、系统和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段或指令的一部分，所述模块、程序段或指令的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个连续的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。
也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行相应的功能或动作的硬件(例如电路或ASIC(Application Specific Integrated Circuit，专用集成电路))来实现，或者可以用硬件和软件的组合，如固件等来实现。
尽管在此结合各实施例对本申请进行了描述，然而，在实施所要求保护的本申请过程中，本领域技术人员通过查看所述附图、公开内容、所附权利要求书，可理解并实现所述公开实施例的其它变化。单个处理器或其它单元可以实现权利要求中列举的若干项功能。相互不同的从属权利要求中记载了某些措施，但这并不表示这些措施不能组合起来产生良好的效果。
以上已经描述了本申请的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。
需要说明的是，对于所述时钟同步装置200，由用户自行编程将一个数字系统“集成”在一片PLD上，可以不需要请芯片制造厂商来设计和制作专用的集成电路芯片。而且，如今，取代手工地制作集成电路芯片，这种编程也多半改用“逻辑编译器(logic compiler)”软件来实现，它与程序开发撰写时所用的软件编译器相类似，而要编译之前的原始代码也得用特定的编程语言来撰写，此称之为硬件描述语言(Hardware Description Language，HDL)，而HDL也并非仅有一种，而是有许多种，如ABEL(Advanced Boolean Expression Language)、AHDL(Altera Hardware Description Language)、Confluence、CUPL(Cornell University Programming Language)、HDCal、JHDL(Java Hardware Description Language)、Lava、Lola、MyHDL、PALASM、RHDL(Ruby Hardware Description Language)等，目前最普遍使用的是VHDL(Very-High-Speed Integrated Circuit Hardware Description Language) 与Verilog。本领域技术人员也应该清楚，只需要将方法流程用上述几种硬件描述语言稍作逻辑编程并编程到集成电路中，就可以很容易得到实现该逻辑方法流程的硬件电路。
对于所述调整量确定模块203，可以按任何适当的方式实现，例如，所述调整量确定模块203可以采取例如微处理器或处理器以及存储可由该(微)处理器执行的计算机可读程序代码(例如软件或固件)的计算机可读介质、逻辑门、开关、专用集成电路(Application Specific Integrated Circuit，ASIC)、可编程逻辑控制器和嵌入微控制器的形式，所述调整量确定模块203的例子包括但不限于以下微控制器：ARC 625D、Atmel AT91SAM、Microchip PIC18F26K20以及Silicone Labs C8051F320，存储器控制器还可以被实现为存储器的控制逻辑的一部分。本领域技术人员也知道，除了以纯计算机可读程序代码方式实现所述调整量确定模块203以外，完全可以通过将方法步骤进行逻辑编程来使得所述调整量确定模块203以逻辑门、开关、专用集成电路、可编程逻辑控制器和嵌入微控制器等的形式来实现相同功能。因此这种所述调整量确定模块203可以被认为是一种硬件部件，而对其内包括的用于实现各种功能的装置也可以视为硬件部件内的结构。或者甚至，可以将用于实现各种功能的装置视为既可以是实现方法的软件模块又可以是硬件部件内的结构。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (10)

  1. 一种时钟同步方法，其特征在于，包括：
    获取本地时钟与基准时钟的时钟偏移；
    基于对所述时钟偏移的比例调节和积分调节，生成针对所述本地时钟的时钟调整量；
    利用所述时钟调整量对所述本地时钟进行调整。
  2. 根据权利要求1所述的时钟同步方法，其中，所述基于对所述时钟偏移的比例调节和积分调节，生成针对所述本地时钟的时钟调整量，包括：
    获取所述时钟偏移与上一时刻时钟偏移之间的偏移差、比例调节系数和积分调节系数；
    根据所述偏移差、所述比例调节系数和所述积分调节系数，确定针对所述本地时钟的时钟调整量。
  3. 根据权利要求2所述的时钟同步方法，其中，所述根据所述偏移差、所述比例调节系数和所述积分调节系数，确定针对所述本地时钟的时钟调整量，包括：
    构建用于确定针对所述本地时钟的时钟调整量Δoutput的表达式：
    Δoutput＝P×(timeoffset(k)-timeoffset(k-1))+I×timeoffset(k)
    其中，P为比例调节系数，I为积分调节系数，timeoffset(k)为第k时刻的时钟偏移，timeoffset(k-1)为第(k-1)时刻的时钟偏移。
  4. 根据权利要求2或3所述的时钟同步方法，其中，所述比例调节系数和所述积分调节系数按照下述方式生成：
    获取历史数据，所述历史数据包括历史上对本地时钟调整前的时钟偏移、所述时钟偏移与上一时刻时钟偏移之间的偏移差以及对本地时钟的时钟调整量；
    构建比例积分调节数学模型，所述比例积分调节数学模型中设置有比例调节系数和积分调节系数；
    利用所述历史数据对所述比例积分调节数学模型进行训练，并拟合得到所述比例调节系数和所述积分调节系数的数值。
  5. 根据权利要求1所述的时钟同步方法，其中，还包括：
    在确定所述本地时钟进入holdover模式的情况下，获取所述本地时钟在进入holdover模式前的预设时间段内多次针对所述本地时钟的时钟调整量；
    确定所述多次针对所述本地时钟的时钟调整量的调整规律；
    根据所述调整规律确定针对所述本地时钟的预测调整量。
  6. 一种时钟同步装置，其特征在于，包括：
    时钟偏移获取模块，用于获取本地时钟与基准时钟的时钟偏移；
    调整量确定模块，用于基于对所述时钟偏移的比例调节和积分调节，生成针对所述本地时钟的时钟调整量；
    时钟调整模块，用于利用所述时钟调整量对所述本地时钟进行调整。
  7. 根据权利要求6所述的时钟同步装置，其中，所述调整量确定模块，具体用于：
    获取所述时钟偏移与上一时刻时钟偏移之间的偏移差、比例调节系数和积分调节系数；
    根据所述偏移差、所述比例调节系数和所述积分调节系数，确定针对所述本地时钟的时钟调整量。
  8. 一种处理设备，其特征在于，包括处理器以及用于存储处理器可执行指令的存储器，其中，所述处理器，用于被配置为执行所述指令时实现权利要求1-5中任意一项所述的方法。
  9. 一种非易失性计算机可读存储介质，其上存储有计算机程序指令，其特征在于，所述计算机程序指令被处理器执行时实现权利要求1-5中任意一项所述的方法。
  10. 一种计算机程序产品，其特征在于，包括计算机可读代码，或者承载有计算机可读代码的非易失性计算机可读存储介质，当所述计算机可读代码在电子设备的处理器中运行时，所述电子设备中的处理器执行上述权利要求1-5中任意一项所述的方法。
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