WO2024066617A1

WO2024066617A1 - Semiconductor package and electronic device

Info

Publication number: WO2024066617A1
Application number: PCT/CN2023/104992
Authority: WO
Inventors: 任亦纬; 刘国文; 郭茂
Original assignee: 华为技术有限公司
Priority date: 2022-09-29
Filing date: 2023-06-30
Publication date: 2024-04-04
Also published as: CN117832187A

Abstract

Provided in the present application are a semiconductor package and an electronic device. The semiconductor package comprises a back-end-of-line interposer layer. The back-end-of-line interposer layer is divided into at least one interconnecting interposer portion and at least one redundant interposer portion, which are independent of each other, wherein a first filler fills the space between any two adjacent interposer portions; and each interconnecting interposer portion is provided with at least one chip, which is electrically connected to the interconnecting interposer portion. In the semiconductor package, the back-end-of-line interposer layer is used to connect to the chip, such that a TSV-related process can be omitted, and packaging costs can be reduced. Moreover, the back-end-of-line interposer layer is divided into at least one interconnecting interposer portion and at least one redundant interposer portion, which are independent of each other, such that the problems of deformation and excessive residual stress of the back-end-of-line interposer layer can be mitigated, and packaging reliability risks such as cracking of the back-end-of-line interposer layer can be reduced.

Description

Semiconductor packaging and electronic equipment

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of the Chinese patent application filed with the China Patent Office on September 29, 2022, with application number 202211196509.9 and application name “A Semiconductor Package and Electronic Device”, all contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of semiconductor packaging technology, and in particular to a semiconductor package and electronic equipment.

Background technique

High-speed and high-density interconnection between chips is the key to achieving higher integration, shorter latency, and better electrical performance in semiconductor packaging. Among them, 2.5D packaging and its variant interconnection methods have received widespread attention and application in recent years.

As shown in FIG1 , in a 2.5D package, the chip 01 is placed side by side on a silicon-based interposer 02, and the chip 01 is interconnected through a micro-bump 03 and wiring in the silicon-based interposer 02. The silicon-based interposer 02 is interconnected on the upper and lower surfaces through a through silicon via 021 (TSV), and the silicon-based interposer 02 is soldered to the package substrate 05 through a controlled collapse of chip connection (C4) solder ball 04. However, in a 2.5D package, the connection reliability problem between the silicon-based interposer 02 and the package substrate 05 becomes increasingly prominent as the package size increases, and the TSV process with a high aspect ratio is difficult and expensive.

In view of the high cost of TSV, as shown in FIG2 , the related art proposes that a transfer layer can be formed by the semiconductor manufacturing plant (Fab) back-end process (BEOL) technology, wherein the BEOL transfer layer 06 is mainly formed by a plurality of metal layers 061 and a plurality of dielectric layers 062 alternately stacked, and adjacent metal layers 061 are electrically connected through micro-vias in the dielectric layer 062. Then, one or more chips 01 are welded on it through micro-bumps 03, so that high-density interconnection between chips 01 and 01 can be achieved. Signals can be exported below the BEOL transfer layer 06 through a directly formed redistribution layer (RDL) 07 or a ball grid array (BGA). Since the micro-vias in the BEOL transfer layer 06 are shallower and smaller in size than the TSVs in the silicon-based transfer board 02, the packaging cost is naturally reduced.

However, as the package size increases, the difference in coefficient of thermal expansion (CET) between the BEOL transfer layer and the redistribution line layer can cause deformation and excessive residual stress in the BEOL transfer layer, resulting in packaging reliability risks such as cracks in the BEOL transfer layer, limiting the large-scale application of the BEOL transfer layer.

Summary of the invention

The present application provides a semiconductor package and an electronic device, which are used to improve the deformation and excessive residual stress problems existing in the BEOL transfer layer.

In the first aspect, an embodiment of the present application provides a semiconductor package, which mainly includes a BEOL transfer layer and at least one chip located on the BEOL transfer layer. The BEOL transfer layer includes multiple wiring layers and multiple interlayer dielectric layers that are alternately stacked. The BEOL transfer layer is divided into at least one interconnect transfer part and at least one redundant transfer part that are independently arranged. The "independent arrangement" here means that they are physically independent of each other and have no direct physical connection with each other. At least one interlayer dielectric layer in the interconnect transfer part is provided with a micro-through hole, wherein the micro-through hole generally refers to a through hole with an aperture of less than 0.15 mm, and each interconnect transfer part is provided with at least one chip electrically connected to the interconnect transfer part, while the redundant transfer part is not electrically connected to the chip. The semiconductor package also includes a first filler filled between any two adjacent transfer parts in at least one interconnect transfer part and at least one redundant transfer part, for example, the first filler glue is filled between any two adjacent interconnect transfer parts, between any two adjacent redundant transfer parts, and between any adjacent redundant transfer parts and the interconnect transfer part. In the semiconductor package, the BEOL transfer layer is used to interconnect with the chip, which can save TSV related processes, thereby reducing the packaging cost. In addition, since the BEOL transfer layer is divided into at least one interconnection transfer part and at least one redundant transfer part that are independent of each other, the problem of deformation and excessive residual stress of the BEOL transfer layer can be alleviated, and the risk of packaging reliability such as cracks in the BEOL transfer layer can be reduced.

The chip manufacturing process generally includes the front end of line (FEOL) and BEOL. The process flow of making devices on the substrate (for example, the device can be an active device or a passive device) is called FEOL, and the process flow of forming multiple layers of conductive metal wires on the device is called BEOL. With the development of semiconductor packaging technology, BEOL is also used in chip packaging to form a transfer layer, such as the BEOL transfer layer in this application. The BEOL transfer layer is not the BEOL layer in a conventional chip. It is different from the BEOL layer in a conventional chip. The only difference is that the same process flow is used.

The present application does not limit the material of the first filler. Exemplarily, the first filler may be a filling glue.

Exemplarily, the wiring layer may be formed of metal, such as copper (Cu), aluminum (Al), tungsten (W), etc., which are not limited here. The interlayer dielectric layer may be formed of silicon-based compounds, such as silicon oxide, silicon nitride, etc., which are not limited here.

Exemplarily, the semiconductor package further comprises at least one micro-bump located on each interconnection transfer portion of at least one interconnection transfer portion, and at least one chip located on the interconnection transfer portion is electrically connected to the interconnection transfer portion through the at least one micro-bump. In this embodiment, since the BEOL transfer layer is divided into at least one interconnection transfer portion and at least one redundant transfer portion that are independent of each other, the area of a single interconnection transfer portion is smaller than the area of the entire BEOL transfer layer, the coplanarity of the micro-bumps on the single interconnection transfer portion can be improved, thereby improving the bonding yield of the chip.

Exemplarily, the BEOL transfer layer generally includes a passivation layer covering the top wiring layer, the passivation layer has a plurality of openings, a first pad is provided in the opening, and the first pad is used to weld the micro-bumps. Thus, the chip on the BEOL transfer layer can be electrically connected to the BEOL transfer layer through the micro-bumps.

Exemplarily, the passivation layer may be formed of insulating materials such as silicon dioxide, which is not limited here.

Exemplarily, in the present application, in order to increase the packaging reliability of the semiconductor package, the semiconductor package may further include a second filler filled between the chip and the BEOL transfer layer. The second filler may serve as a buffer layer, which may reduce the force transmitted to the BEOL transfer layer and the chip when the semiconductor package falls, thereby improving the safety of the entire semiconductor package. Exemplarily, in the present application, the second filler may be a filling glue, which is not limited here.

Exemplarily, the first filler and the second filler may be made of the same material, so that the gap between the chip and the BEOL transfer layer and the gap in the BEOL transfer layer can be filled with filler at the same time during preparation, thereby simplifying the process.

Exemplarily, the BEOL transfer layer may include at least one first interconnect transfer portion and/or at least one second interconnect transfer portion and/or at least one third interconnect transfer portion. Each interconnect transfer portion is provided with at least one micro bump electrically connected to the interconnect transfer portion, so that the chip in the semiconductor package can be electrically connected to the corresponding interconnect transfer portion through the micro bump.

The first interconnection transfer section has at least one interlayer interconnection line that conducts on both sides of the first interconnection transfer section. The interlayer interconnection line is composed of wiring in each wiring layer and micro-vias in each interlayer dielectric layer. Each interlayer interconnection line is electrically connected to a micro-bump located on the first interconnection transfer section, and is electrically connected to the chip through the micro-bump; thereby, the chip above the first interconnection transfer section can transmit signals to the bottom of the first interconnection transfer section through the interlayer interconnection line.

The second interconnection transition portion has at least one chip-to-chip interconnection line, and the two ends of each chip-to-chip interconnection line are respectively electrically connected to two different micro-bumps located on the second interconnection transition portion. The two different micro-bumps can connect two chips, so that the two chips can be interconnected through the chip-to-chip interconnection line.

The third interconnect transition portion comprises at least one interlayer interconnect line connecting two sides of the third interconnect transition portion and at least one chip-to-chip interconnect line, each interlayer interconnect line in the at least one interlayer interconnect line is respectively electrically connected to a micro-bump located on the third interconnect transition portion; and both ends of each chip-to-chip interconnect line in the at least one chip-to-chip interconnect line are respectively electrically connected to two different micro-bumps located on the third interconnect transition portion.

It should be noted that the present application does not limit the number of interconnection transfer parts and redundant transfer parts in the BEOL transfer layer. On the basis of ensuring the interconnection performance of each interconnection transfer part, it can be set according to the horizontal area of the semiconductor package. The larger the horizontal area of the semiconductor package, the greater the number of interconnection transfer parts and redundant transfer parts can be.

It should be noted that the chip in this application can be a bare die. A bare die is a crystal grain before the chip is packaged. Each bare die is a chip with independent functions that has not been packaged. It can be composed of one or more circuits. The bare die in the specific embodiment includes but is not limited to application specific integrated circuits (ASIC), memory bare die, storage bare die, etc. Of course, the chip can also be a packaged chip, which is not limited here.

Exemplarily, the semiconductor package may further include a first plastic encapsulation layer located on a side of the BEOL transfer layer facing the chip and used for plastic encapsulating each chip.

The present application does not limit the material of the first plastic sealing layer. For example, the material of the first plastic sealing layer may be epoxy molding compound (EMC) or the like.

Furthermore, the semiconductor package may also include a redistribution circuit layer located on the side of the BEOL transfer layer away from the chip, and the pads may be arranged in a new area with a looser and more favorable pitch by using the redistribution circuit layer. The BEOL transfer layer is electrically connected to the redistribution circuit layer through the first solder ball, thereby decoupling the manufacturing process of the BEOL transfer layer and the redistribution circuit layer, reducing the negative impact of the high-temperature process of the redistribution circuit layer on the reliability of the connection between the chip and the BEOL transfer layer, which is conducive to improving the yield and reliability.

In a specific implementation, the redistribution circuit layer may be composed of a dielectric layer and at least one conductive layer, the conductive layer is provided with circuit wiring, and the dielectric layer is provided with dielectric perforations for connecting circuit wiring on different layers. The material of the dielectric layer is generally polyimide, and the material of the conductive layer is generally metal. The present application does not limit the number of conductive layers included in the redistribution wiring layer, and can be designed according to actual needs.

Exemplarily, a second pad is generally provided on the redistribution circuit layer, the first solder ball is soldered to the second pad, and the second pad is electrically connected to the circuit wiring in the redistribution circuit layer.

Optionally, the semiconductor package may further include a third filler filled between the BEOL transfer layer and the redistribution circuit layer. The third filler may serve as a buffer layer to reduce the force transferred to the BEOL transfer layer and the redistribution circuit layer when the semiconductor package falls, thereby improving the safety of the entire semiconductor package.

Illustratively, in the present application, the third filler may be a filling glue, which is not limited herein.

Exemplarily, the semiconductor package may further include a second plastic encapsulation layer for encapsulating the BEOL transfer layer, at least one chip, and the redistribution circuit layer. The present application does not limit the material of the second plastic encapsulation layer. For example, the material of the second plastic encapsulation layer may be an epoxy molding compound (EMC) or the like.

Illustratively, in the present application, the first plastic encapsulation layer and the second plastic encapsulation layer may be formed by using the same plastic encapsulation material, which is not limited herein.

Furthermore, the semiconductor package also includes a packaging substrate located on a side of the redistribution circuit layer away from the BEOL transfer layer; the redistribution circuit layer can be electrically connected to the packaging substrate through the second solder balls.

Exemplarily, the size of the second solder ball is generally larger than that of the first solder ball. The first solder ball may be a micro solder ball or a chip connection (Chip Connection, C2) solder ball, and the second solder ball may be a C4 solder ball.

Exemplarily, the semiconductor package may further include a fourth filler filled between the redistribution circuit layer and the package substrate. The fourth filler may serve as a buffer layer to reduce the force transferred to the package substrate and the redistribution circuit layer when the semiconductor package falls, thereby improving the safety of the entire semiconductor package.

Illustratively, in the present application, the fourth filler may be a filling glue, which is not limited herein.

It can be understood that the materials of the first filler, the second filler, the third filler and the fourth filler in the present application can be completely the same, partially the same, or completely different, which is not limited here.

In a second aspect, an embodiment of the present application further provides an electronic device, comprising a circuit board and a semiconductor package as described in the first aspect or various embodiments of the first aspect, which is electrically connected to the circuit board. Since the principle of the electronic device is similar to that of the aforementioned semiconductor package, the implementation of the electronic device can refer to the implementation of the aforementioned semiconductor package, and the repeated parts will not be repeated.

The technical effects that can be achieved in the above-mentioned second aspect can be referred to the description of the technical effects that can be achieved by any possible design in the above-mentioned first aspect, and will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a 2.5D package structure proposed in the related art;

FIG2 is a schematic structural diagram of another 2.5D package provided in the related art;

FIG3 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

FIG4 is a schematic diagram of the structure of a semiconductor package provided by an embodiment of the present application;

FIG5 is a schematic diagram of the structure of a BEOL transfer layer provided in an embodiment of the present application;

FIG6 is a schematic structural diagram of a first interconnect transfer portion in a BEOL transfer layer provided in an embodiment of the present application;

FIG7 is a schematic structural diagram of a second interconnect transfer portion in a BEOL transfer layer provided in an embodiment of the present application;

FIG8 is a schematic structural diagram of a third interconnect transfer portion in a BEOL transfer layer provided in an embodiment of the present application;

FIG9 is a schematic structural diagram of another semiconductor package provided in an embodiment of the present application;

FIG10 is a schematic structural diagram of another semiconductor package provided in an embodiment of the present application;

FIG11 is a schematic structural diagram of another semiconductor package provided in an embodiment of the present application;

12a to 12j are schematic structural diagrams of a semiconductor package preparation process provided in an embodiment of the present application.

Description of Figure Numbers:

1-electronic device; 10-semiconductor package; 20-housing; 30-circuit board; 11-BEOL transfer layer; 110-redundant transfer part; 111-first interconnection transfer part; 112-second interconnection transfer part; 113-third interconnection transfer part; Dn-wiring layer; Dk-interlayer dielectric layer; P1-passivation layer; Vk-micro via; L1-interlayer interconnection line; L2-chip-to-chip interconnection line; 121-first filler; 122-second filler; 123-third filler; 124-fourth filler; 131-first pad; 132-micro bump; 14-chip; 15-redistribution circuit layer; 151-dielectric layer; 152-conductive layer; 153-second pad; 161-first solder ball; 162-second solder ball; 171-first plastic layer; 172-second plastic layer; 18-packaging substrate; 100 - a first base substrate; 150 - a second base substrate.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present application more clear, the present application will be further described in detail below in conjunction with the accompanying drawings.

The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to be limiting of the present application. As used in the specification and appended claims of the present application, the singular expressions "a", "an", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The words expressing position and direction described in the present application are all explained using the accompanying drawings as examples, but changes may be made as needed, and all changes are included in the scope of protection of the present invention. The drawings of the present application are only used to illustrate relative positional relationships and do not represent true proportions. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

In order to facilitate the understanding of the technical solution provided by the embodiment of the present application, its specific application scenario is first described below. The semiconductor package proposed in the embodiment of the present application can be applied to various electronic devices. For example, it can be applied to smart phones, smart TVs, smart TV set-top boxes, personal computers (PCs), wearable devices, smart broadband, etc. It should be noted that the semiconductor package proposed in the embodiment of the present application is intended to include but is not limited to application in these and any other suitable types of electronic devices. Exemplarily, as shown in Figure 3, the electronic device 1 may include a housing 20, a circuit board 30 disposed in the housing 20, and a semiconductor package 10 electrically connected to the circuit board 30. The present application will be further described in detail below in conjunction with the accompanying drawings.

4 is a schematic diagram of a semiconductor package according to an embodiment of the present application. The semiconductor package 10 may include a BEOL transfer layer 11 and at least one chip 14 located on the BEOL transfer layer 11 .

As shown in FIG5 , the BEOL transfer layer 11 includes alternately stacked multi-layer wiring layers: M1 to MN (N is shown as an example in the figure) and multi-layer interlayer dielectric layers: D1 to DK (K is shown as an example in the figure). The BEOL transfer layer 11 is divided into at least one interconnect transfer part (three interconnect transfer parts 111 to 113 are shown as an example in the figure) and at least one redundant transfer part 110 (two redundant transfer parts 110 are shown as an example in the figure). The "independent arrangement" here means that they are physically independent of each other and have no direct physical connection with each other. At least one interlayer dielectric layer Dk (k is any number from 1 to K) in the interconnection transfer part 111, 112 or 113 is provided with a micro-via Vk, wherein the micro-via Vk generally refers to a through hole with a hole diameter less than 0.15 mm. The interconnection transfer part 111, 112 or 113 is electrically connected to the chip, while the redundant transfer part 110 is not electrically connected to the chip 14, and is generally located at the edge, with the top thereof being used for plastic sealing.

The chip manufacturing process generally includes the front end of line (FEOL) and BEOL. The process flow of making devices on the substrate (for example, the device can be an active device or a passive device) is called FEOL, and the process flow of forming multiple layers of conductive metal wires on the device is called BEOL. With the development of semiconductor packaging technology, BEOL is also used in chip packaging to form a transfer layer, such as the BEOL transfer layer in this application. The BEOL transfer layer is not the BEOL layer in a conventional chip. Compared with the BEOL layer in a conventional chip, it only uses the same process flow.

For example, in the present application, the wiring layer Mn (n is any number from 1 to N) can be formed of metal, such as copper (Cu), aluminum (Al), tungsten (W), etc., which is not limited here. The interlayer dielectric layer Dk can be formed of a silicon-based compound, such as silicon oxide, silicon nitride, etc., which is not limited here.

Exemplarily, as shown in FIG5 , the BEOL transfer layer 11 generally further includes a passivation layer P1 covering the topmost wiring layer MN, and the passivation layer P1 has a plurality of openings, in which a first pad 131 is provided, and the first pad 131 is used to weld a micro bump 132. Thus, the chip 14 on the BEOL transfer layer 11 can be electrically connected to the BEOL transfer layer 11 through the micro bump 132.

Exemplarily, the passivation layer P1 may be formed of insulating materials such as silicon dioxide, which is not limited here.

Exemplarily, as shown in FIG5 , the BEOL transfer layer 11 may include at least one first interconnect transfer portion 111 and/or at least one second interconnect transfer portion 112 and/or at least one third interconnect transfer portion 113. Each interconnect transfer portion (111, 112 or 113) is provided with at least one micro bump 132 electrically connected to the interconnect transfer portion (111, 112 or 113), so that the chip 14 in the semiconductor package can be electrically connected to the corresponding interconnect transfer portion (111, 112 or 113) through the micro bump 132.

Referring to FIG. 6 , the first interconnection transition portion 111 has at least one interlayer interconnection line L1 that conducts the upper and lower surfaces of the first interconnection transition portion 111. The interlayer interconnection line L1 is composed of wiring in each wiring layer Mn and micro-vias Vk in each interlayer dielectric layer Dk. Each interlayer interconnection line L1 is electrically connected to a micro-bump 132 located on the first interconnection transition portion 111, thereby being electrically connected to the chip 14 through the micro-bump 132. Thus, the chip 14 above the first interconnection transition portion 111 can transmit signals to the first interconnection transition portion through the interlayer interconnection line L1. Below 111.

Referring to FIG. 7 , the second interconnection transition portion 112 has at least one chip-to-chip interconnection line L2, and both ends of each chip-to-chip interconnection line L2 are electrically connected to two different micro-bumps 132 located on the second interconnection transition portion 112, respectively. The two different micro-bumps 132 can connect two chips 14, so that the two chips 14 can be interconnected through the chip-to-chip interconnection line L2.

8 , the third interconnect transition portion 113 includes at least one interlayer interconnect line L1 connecting two sides of the third interconnect transition portion 113 and at least one chip-to-chip interconnect line L2. Each interlayer interconnect line L1 in the at least one interlayer interconnect line L1 is electrically connected to a micro-bump 132 located on the third interconnect transition portion 113, respectively; and both ends of each chip-to-chip interconnect line L2 in the at least one chip-to-chip interconnect line L2 are electrically connected to two different micro-bumps 132 located on the third interconnect transition portion 113, respectively.

Referring to FIG. 4 , the semiconductor package 10 may further include a first filler 121 filled between any two adjacent transitions in at least one interconnect transition (111, 112 or 113) and at least one redundant transition 110, for example, the first filler 121 is filled between any two adjacent interconnect transitions, between any two adjacent redundant transitions 110, and between any adjacent redundant transition 110 and the interconnect transition. The present application does not limit the material of the first filler 121, and illustratively, the first filler 121 may be a filling glue.

4, each interconnection transition portion (111, 112 or 113) is also provided with at least one chip 14 electrically connected to the interconnection transition portion. Exemplarily, each chip 14 in the at least one chip 14 can be electrically connected to the interconnection transition portion through at least one micro bump 132 provided on each interconnection transition portion.

It should be noted that the chip 14 in the present application may be a bare die, which is a crystal grain before the chip 14 is packaged. Each bare die is a chip 14 with independent functions that has not been packaged yet, and it may be composed of one or more circuits. The bare die in the specific embodiment includes but is not limited to application specific integrated circuits (ASIC), memory bare die, storage bare die, etc. Of course, the chip 14 may also be a packaged chip 14, which is not limited here.

In the semiconductor package 10, the BEOL transfer layer 11 is used to interconnect with the chip 14, which can save TSV related processes, thereby reducing the packaging cost. In addition, since the BEOL transfer layer 11 is divided into at least one independent interconnection transfer part (111, 112 or 113) and at least one redundant transfer part 110, the problem of deformation and excessive residual stress of the BEOL transfer layer 11 can be alleviated, and the risk of cracks in the BEOL transfer layer 11 and other packaging reliability risks can be reduced.

Furthermore, since the BEOL transfer layer 11 is divided into at least one independent interconnect transfer portion (111, 112 or 113) and at least one redundant transfer portion 110, the area of a single interconnect transfer portion (111, 112 or 113) is smaller than the area of the entire BEOL transfer layer 11, the coplanarity of the micro-bumps 132 on the single interconnect transfer portion (111, 112 or 113) can be improved, thereby improving the bonding yield of the chip 14.

By way of example, in the present application, in order to increase the packaging reliability of the semiconductor package 10, as shown in FIG4 , the semiconductor package 10 may further include a second filler 122 filled between the chip 14 and the BEOL transfer layer 11. The second filler 122 may serve as a buffer layer, and when the semiconductor package 10 falls, the force transmitted to the BEOL transfer layer 11 and the chip 14 may be reduced, thereby improving the safety of the entire semiconductor package 10. By way of example, in the present application, the second filler 122 may be a filling glue, which is not limited here.

Exemplarily, the first filler 121 and the second filler 122 may be made of the same material. In this way, the gap between the chip 14 and the BEOL transfer layer 11 and the gap in the BEOL transfer layer 11 may be filled with fillers at the same time during preparation, thereby simplifying the process.

For example, see Figure 9, which is a schematic diagram of another semiconductor package provided by an embodiment of the present application. The semiconductor package 10 may also include a first plastic encapsulation layer 171 located on the side of the BEOL transfer layer 11 facing the chip 14 and used to encapsulate each chip 14.

The present application does not limit the material of the first plastic sealing layer 171. For example, the material of the first plastic sealing layer 171 can be epoxy molding compound (EMC) or the like.

Continuing to refer to FIG. 9 , the semiconductor package 10 may further include a redistribution circuit layer 15 located on the side of the BEOL transfer layer 11 away from the chip 14. The redistribution circuit layer 15 may be used to arrange the pads to a new area with a looser and more favorable pitch. The BEOL transfer layer 11 is electrically connected to the redistribution circuit layer 15 through the first solder ball 161, thereby decoupling the manufacturing process of the BEOL transfer layer 11 and the redistribution circuit layer 15, reducing the negative impact of the high-temperature process of the redistribution circuit layer 15 on the reliability of the connection between the chip 14 and the BEOL transfer layer 11, which is conducive to improving the yield and reliability.

In a specific implementation, the redistribution circuit layer 15 may be composed of a dielectric layer 151 and at least one conductive layer 152. Circuit wiring is arranged on the conductive layer 152, and dielectric perforations are arranged in the dielectric layer 151 for connecting circuit wiring on different layers. The material of the dielectric layer 151 is generally polyimide, and the material of the conductive layer 152 is generally metal. The present application does not specify the number of conductive layers 152 included in the redistribution circuit layer 15. It can be designed according to actual needs.

Exemplarily, a second pad 153 is generally provided on the redistribution circuit layer 15 . The second pad 153 is electrically connected to the circuit wiring in the redistribution circuit layer 15 , and the first solder ball 161 is soldered on the second pad 153 .

9 , the semiconductor package 10 may further include a third filler 123 filled between the BEOL transfer layer 11 and the redistribution circuit layer 15. The third filler 123 may serve as a buffer layer, and when the semiconductor package 10 falls, the force transferred to the BEOL transfer layer 11 and the redistribution circuit layer 15 may be reduced, thereby improving the safety of the entire semiconductor package 10.

Illustratively, in the present application, the third filler 123 may be a filling glue, which is not limited herein.

10 is a schematic diagram of the structure of another semiconductor package provided by an embodiment of the present application. The semiconductor package 10 may further include a second plastic encapsulation layer 172 for encapsulating the BEOL transfer layer 11 , at least one chip 14 and the redistribution circuit layer 15 .

The present application does not limit the material of the second plastic sealing layer 172. For example, the material of the second plastic sealing layer 172 may be an epoxy molding compound (EMC) or the like.

For example, in the present application, the first plastic encapsulation layer 171 and the second plastic encapsulation layer 172 may be formed by using the same plastic encapsulation material, which is not limited herein.

Referring to Fig. 11, Fig. 11 is a schematic diagram of the structure of another semiconductor package 10 provided in an embodiment of the present application. The semiconductor package 10 further includes a package substrate located on the side of the redistribution circuit layer 15 away from the BEOL transfer layer 11; the redistribution circuit layer 15 can be electrically connected to the package substrate 18 through the second solder ball 162.

Exemplarily, the size of the second solder ball 162 is generally larger than the size of the first solder ball 161. The first solder ball 161 may be a micro solder ball or a chip connection (C2) solder ball, and the second solder ball 162 may be a C4 solder ball.

Exemplarily, referring to FIG11 , the semiconductor package 10 may further include a fourth filler 124 filled between the redistribution circuit layer 15 and the package substrate 18. The fourth filler 124 may serve as a buffer layer, and when the semiconductor package 10 falls, the force transmitted to the package substrate 18 and the redistribution circuit layer 15 may be reduced, thereby improving the safety of the entire semiconductor package 10.

Illustratively, in the present application, the fourth filler 124 may be a filling glue, which is not limited herein.

It can be understood that the materials of the first filler 121 , the second filler 122 , the third filler 123 and the fourth filler 124 in the present application can be completely the same, partially the same, or completely different, which is not limited here.

To facilitate understanding of the semiconductor package provided in the embodiment of the present application, the semiconductor package provided in the embodiment of the present application is further described below in conjunction with a preparation method. The preparation of the semiconductor package may include the following steps:

As shown in FIG12a, a BEOL transfer layer 11 is formed on the first substrate 100 by using the BEOL process, and micro bumps 132 are welded on the BEOL transfer layer 11. The BEOL transfer layer 11 includes multiple wiring layers: M1 to M5 and multiple interlayer dielectric layers: D1 to D4 that are alternately stacked, and a passivation layer P1 located at the top. Micro vias Vk are provided in the interlayer dielectric layer Dk, and the BEOL transfer layer 11 has interlayer interconnection lines L1 and chip-to-chip interconnection lines L2 formed by wiring in the wiring layer Mn and micro vias Vk. The passivation layer P1 has multiple openings, and a first pad 131 is provided in the opening, and the micro bumps 132 are welded on the first pad 131.

As shown in FIG. 12 b , the BEOL transfer layer 11 is divided into at least one first interconnection transfer portion 111 and/or at least one second interconnection transfer portion 112 and/or at least one third interconnection transfer portion 113 that are independently arranged.

As shown in FIG. 12 c , the chip 14 is bonded to the BEOL transfer layer 11 , and fillers are filled between the chip 14 and the BEOL transfer layer 11 and in the gaps in the BEOL transfer layer 11 , thereby forming a first filler 121 and a second filler 122 .

As shown in FIG. 12 d , a first plastic encapsulation layer 171 for encapsulating each chip 14 is formed on the side of the BEOL transfer layer 11 facing the chip 14 , and the first plastic encapsulation layer 171 is ground until the chip 14 is exposed.

As shown in FIG. 12 e , the first base substrate 100 below the BEOL transfer layer 11 is polished until the BEOL transfer layer 11 is exposed.

As shown in FIG. 12 f , a first solder ball 161 is soldered on a side of the BEOL transfer layer 11 away from the chip 14 .

As shown in Figure 12g, a redistribution circuit layer 15 is formed on the second base substrate 150. The redistribution circuit layer 15 may be composed of a dielectric layer 151 and at least one conductive layer 152. Circuit wiring is provided on the conductive layer 152. Dielectric perforations are provided in the dielectric layer 151 for connecting circuit wiring on different layers. A second solder pad 153 is provided on the upper surface of the redistribution circuit layer 15.

As shown in FIG. 12 h , the redistribution circuit layer 15 and the BEOL transfer layer 11 are bonded, and a third filler 123 is filled between the redistribution circuit layer 15 and the BEOL transfer layer 11 .

As shown in FIG. 12 i , the second substrate 150 under the redistribution circuit layer 15 is removed, and a second solder ball 162 is soldered on a side of the redistribution circuit layer 15 away from the BEOL transfer layer 11 .

As shown in FIG. 12 j , a packaging substrate 18 is mounted on the side of the redistribution circuit layer 15 away from the BEOL transfer layer 11 , and a fourth filler 124 is filled between the redistribution circuit layer 15 and the packaging substrate 18 .

In the semiconductor package 10 provided in the embodiment of the present application, the BEOL transfer layer 11 is used to interconnect with the chip 14, which can save TSV related processes, thereby reducing the packaging cost. And because the BEOL transfer layer 11 is divided into at least one interconnection transfer part and at least one redundant transfer part 110 that are independent of each other, the problem of deformation and excessive residual stress of the BEOL transfer layer 11 can be alleviated, and the risk of packaging reliability such as cracks in the BEOL transfer layer 11 can be reduced. In addition, because the BEOL transfer layer 11 is divided into at least one interconnection transfer part (111, 112 or 113) that is independent of each other and at least one redundant transfer part 110, the area of a single interconnection transfer part (111, 112 or 113) is smaller than the area of the entire BEOL transfer layer 11, the coplanarity of the micro bumps 132 on the single interconnection transfer part (111, 112 or 113) can be improved, thereby improving the bonding yield of the chip 14.

In addition, the present application decouples the manufacturing process of the BEOL transfer layer 11 and the redistribution circuit layer 15, which can reduce the negative impact of the high-temperature process of the redistribution circuit layer 15 on the reliability of the connection between the chip 14 and the BEOL transfer layer 11, which is beneficial to improving the yield and reliability.

The semiconductor package 10 provided in the embodiment of the present application is suitable for any product that requires high-density, high-bandwidth interconnection between chips 14 .

Accordingly, the present application also provides an electronic device, as shown in FIG3 , the electronic device 1 includes a circuit board 30 and a semiconductor package 10 in any of the above technical solutions arranged on the circuit board 30. The electronic device 1 proposed in the embodiment of the present application includes but is not limited to smart phones, smart TVs, smart TV set-top boxes, personal computers, wearable devices, smart broadband, etc., which are not listed here one by one. Since the principle of solving the problem of the electronic device 1 is similar to that of the aforementioned semiconductor package 10, the implementation of the electronic device 1 can refer to the implementation of the aforementioned semiconductor package 10, and the repeated parts will not be repeated.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

A semiconductor package, comprising:

A back-end process transfer layer, the back-end process transfer layer comprises multiple wiring layers and multiple interlayer dielectric layers alternately stacked, and the back-end process transfer layer is divided into at least one interconnect transfer section and at least one virtual redundant transfer section independently arranged from each other, and at least one interlayer dielectric layer in the interconnect transfer section is provided with a micro-via;

A first filling material filled between any two adjacent transition portions of the at least one interconnected transition portion and the at least one redundant transition portion;

At least one chip is located on each of the at least one interconnection transition and is electrically connected to the interconnection transition.
The semiconductor package as described in claim 1 is characterized in that the semiconductor package also includes at least one micro bump located on each of the at least one interconnect transition portion, and the at least one chip located on the interconnect transition portion is electrically connected to the interconnect transition portion through the at least one micro bump.
The semiconductor package according to claim 2, characterized in that the semiconductor package further comprises a second filler filled between the chip and the back-end process transfer layer.
The semiconductor package according to any one of claims 1 to 3, characterized in that the at least one interconnect transition portion includes at least one first interconnect transition portion and/or at least one second interconnect transition portion and/or at least one third interconnect transition portion;

The first interconnection transition portion has at least one interlayer interconnection line conducting two sides of the first interconnection transition portion, and each of the at least one interlayer interconnection line is electrically connected to the chip located on the first interconnection transition portion;

The second interconnection transition portion has at least one chip-to-chip interconnection line, and two ends of each of the at least one chip-to-chip interconnection line are electrically connected to the two chips located on the second interconnection transition portion respectively;

The third interconnect transition portion has at least one interlayer interconnect line conducting the two sides of the third interconnect transition portion and at least one chip-to-chip interconnect line, each of the at least one interlayer interconnect line is electrically connected to the chip located on the third interconnect transition portion, and both ends of each of the at least one chip-to-chip interconnect line are electrically connected to the two chips located on the third interconnect transition portion.
The semiconductor package according to any one of claims 1 to 4, characterized in that the semiconductor package further comprises a redistribution circuit layer located on a side of the back-end process transfer layer away from the chip;

The back-end process transfer layer is connected to the redistribution circuit layer through a first solder ball.
The semiconductor package as claimed in claim 5, characterized in that the semiconductor package further comprises a third filler filled between the back-end process transfer layer and the redistribution circuit layer.
The semiconductor package according to claim 5 or 6, characterized in that the semiconductor package further comprises a packaging substrate located on a side of the redistribution circuit layer away from the back-end process transfer layer;

The redistribution circuit layer is electrically connected to the packaging substrate through a second solder ball.
The semiconductor package according to any one of claims 1 to 7, characterized in that the semiconductor package further comprises a first plastic encapsulation layer located at a side of a back-end process transfer layer facing the chip and used for plastic encapsulating the at least one chip.
The semiconductor package as described in claim 8 is characterized in that when the semiconductor package also includes a redistribution circuit layer located on a side of the back-end process transfer layer away from the chip, the semiconductor package also includes a second plastic encapsulation layer for plastic encapsulating the back-end process transfer layer, the at least one chip and the redistribution circuit layer.
An electronic device, characterized in that it comprises a circuit board and a semiconductor package as described in any one of claims 1 to 9 electrically connected to the circuit board.