WO2024066613A1 - Procédé et appareil d'accès et procédé et appareil de stockage de données pour système de mémoire cache multiniveau - Google Patents

Procédé et appareil d'accès et procédé et appareil de stockage de données pour système de mémoire cache multiniveau Download PDF

Info

Publication number
WO2024066613A1
WO2024066613A1 PCT/CN2023/104895 CN2023104895W WO2024066613A1 WO 2024066613 A1 WO2024066613 A1 WO 2024066613A1 CN 2023104895 W CN2023104895 W CN 2023104895W WO 2024066613 A1 WO2024066613 A1 WO 2024066613A1
Authority
WO
WIPO (PCT)
Prior art keywords
cache
information
data block
subsidiary
target
Prior art date
Application number
PCT/CN2023/104895
Other languages
English (en)
Chinese (zh)
Inventor
郇丹丹
李祖松
Original Assignee
北京微核芯科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京微核芯科技有限公司 filed Critical 北京微核芯科技有限公司
Publication of WO2024066613A1 publication Critical patent/WO2024066613A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache

Definitions

  • the present disclosure relates to the field of data processing technology, and in particular to a method and device for accessing a multi-level cache system, a method and device for storing data, an electronic device, a storage medium, a computer program product, and a computer program.
  • the multi-level cache system may cause a large load on the operation of the multi-level cache system when responding to a large batch of access requests, thereby affecting the performance of the multi-level cache, and further leading to the occurrence of related abnormal situations such as access delays in access requests.
  • the present disclosure aims to solve one of the technical problems in the related art at least to some extent.
  • a first aspect of the present disclosure provides an access method for a multi-level cache system.
  • a second aspect of the present disclosure provides a data storage method for a multi-level cache system.
  • a third aspect of the present disclosure provides an access device for a multi-level cache system.
  • a fourth aspect of the present disclosure provides a data storage device for a multi-level cache system.
  • a fifth aspect of the present disclosure provides an electronic device.
  • a sixth aspect of the present disclosure provides a computer-readable storage medium.
  • a seventh aspect of the present disclosure provides a computer program product.
  • An eighth aspect of the present disclosure provides a computer program.
  • the first aspect of the present disclosure proposes a method for accessing a multi-level cache system, the method comprising: obtaining an access request for the multi-level cache system; obtaining, based on the access request, a target access data block of the access request in the multi-level cache system and target subsidiary information of the target access data block from a subsidiary directory of the multi-level cache system, wherein the subsidiary directory is stored on a shared cache in the multi-level cache system; and responding to the access request based on the target subsidiary information.
  • the access method of the multi-level cache system proposed in the embodiment of the first aspect of the present disclosure may also have the following technical features:
  • responding to an access request according to target attached information includes: determining an access status of the access request according to the target attached information; and the shared cache responding to the access request in the access status.
  • the subsidiary directory is stored in a tag field on a shared cache in a multi-level cache system.
  • the access status of an access request is determined based on target subsidiary information, including: obtaining an access request sent by a first private cache to a second private cache in a multi-level cache system, wherein the first private cache and the second private cache are private caches of a multi-core processor, and each processor core in the multi-core processor includes at least one first private cache and/or at least one second private cache; determining, in an subsidiary directory of a shared cache, subsidiary information corresponding to a target access data block of the access request in the multi-level cache system as target subsidiary information; obtaining subsidiary information on a subsidiary identification bit of the target subsidiary information, and obtaining the access status of the access request based on the subsidiary information on the subsidiary identification bit.
  • the access status of an access request is determined based on target attached information, including: in response to an indication by the target attached information that an access request sent by a first private cache to a second private cache does not hit in the first private cache, determining that the access status of the access request is access failure.
  • a shared cache responds to an access request in an access state, including: in response to an access state of an access request sent by a first private cache to a second private cache in a multi-level cache system being access invalid, the first private cache sends an invalidation processing request to a shared cache in the multi-level cache system; the shared cache responds to the invalidation processing request based on target attachment information.
  • the first private cache in response to an access request sent by a first private cache to a second private cache in a multi-level cache system having an access status of access failure, sends an invalidation processing request to a shared cache in the multi-level cache system, including: in response to the access request being a read access request and the read access request not hitting the first private cache, determining that the first private cache has read-failed the read access request, the first private cache generating a first read invalidation processing request corresponding to the read access request, and sending it to the shared cache; in response to the access request being a write access request and the write access request not hitting the first private cache, determining that the first private cache has write-failed the write access request, the first private cache generating a first write invalidation processing request corresponding to the write access request, and sending it to the shared cache.
  • the first private cache after the first private cache generates a first read invalidation processing request corresponding to the read access request and sends it to the shared cache, it also includes: in response to the target subsidiary information indicating that the target access data block does not exist in the first private cache, after obtaining the data corresponding to the target access data block, the shared cache generates a corresponding read invalidation response and sends it to the first private cache that issued the first read invalidation processing request; or, in response to the target subsidiary information indicating that the target access data block in the first private cache is in a dirty state, after receiving the first write back response, the shared cache generates a corresponding read invalidation response and sends it to the first private cache that issued the first read invalidation processing request.
  • the first private cache after the first private cache generates a first write-invalidation processing request corresponding to a write access request and sends it to the shared cache, it also includes: in response to the target subsidiary information indicating that the target access data block does not exist in the first private cache, after obtaining the data corresponding to the target access data block, the shared cache generates a corresponding write-invalidation response and sends it to the first private cache that issued the first write-invalidation processing request; or, in response to the target subsidiary information indicating that the target access data block in the first private cache is valid and clean, after the shared cache receives the first invalid response, it generates a corresponding write-invalidation response and sends it to the first private cache that issued the first write-invalidation processing request; or, in response to the target subsidiary information indicating that the target access data block in the first private cache is valid and clean, after the shared cache receives the first invalid and write-back response, it generates a corresponding write-invalidation response and sends it to the first
  • the method further includes: in response to a data block in the first private cache being replaced, the first private cache sending a replacement request to the shared cache.
  • the first private cache in response to a data block in a first private cache being replaced, after the first private cache sends a replacement request to a shared cache, it also includes: in response to a replacement data block corresponding to the replacement request being stored in the shared cache, the shared cache performs replacement processing on the replacement data block corresponding to the replacement request, and generates a corresponding response and sends it to the processor core to which the corresponding first private cache belongs; in response to the fact that the replacement data block corresponding to the replacement request does not exist in the shared cache, in a next-level storage system of the shared cache, determining the replacement data block corresponding to the replacement request, the next-level storage system performs replacement processing on the replacement data block corresponding to the replacement request, and generates a corresponding response and sends it to the processor core to which the corresponding first private cache belongs.
  • auxiliary information corresponding to a target access data block of an access request in a multi-level cache system is determined as target auxiliary information, including: in response to a processor core to which a first private cache belongs being a backup processor core of the target access data block, determining target auxiliary information corresponding to the target access data block in the auxiliary directory based on identification information on a backup bit in the auxiliary directory; in response to a processor core to which the first private cache belongs being an owner processor core of the target access data block, determining target auxiliary information corresponding to the target access data block in the auxiliary directory based on identification information on a corresponding owner bit in the auxiliary directory.
  • a shared cache responds to an invalidation processing request based on target attachment information, including: the shared cache obtains identification information on a valid bit of a data block to be stored and a target owner bit in the target attachment information, and determines a target state of the target access data block; the shared cache responds to the invalidation processing request based on the target state.
  • a shared cache obtains identification information on a valid bit of a data block to be stored and a target owner bit in target subsidiary information, and determines a target state of a target access data block, including: in response to the identification of the valid bit of the data block to be stored as valid, and the identification of the target owner bit as a state in which an owner processor core of the data block to be stored exists, determining that the target state of the target access data block is valid and dirty; in response to the identification of the valid bit of the data block to be stored as valid, and the identification of the target owner bit as a state in which an owner processor core of the data block to be stored does not exist, determining that the target state of the target access data block is valid and clean.
  • a shared cache responds to an invalidation processing request according to a target state, including: in response to the target state being valid and dirty, the shared cache generates a first write-back request corresponding to the first read invalidation processing request, and sends it to a first private cache on an owner processor core corresponding to a target access data block; in response to the target state being valid and clean, the shared cache generates a second write-back request corresponding to the first read invalidation processing request, and sends it to a first private cache on any backup processor core corresponding to the target access data block.
  • the shared cache in response to the target state being valid and dirty, the shared cache generates a first write-back request corresponding to the first read invalidation processing request and sends it to the first private cache on the owner processor core corresponding to the target access data block, further comprising: In response to identifying that the second private cache stores a backup data block corresponding to the target access data block, the first private cache generates a third write-back request and sends it to the second private cache; based on the third write-back request, the second private cache adjusts the backup data block to a shared state, and writes the adjusted backup data block back to the first private cache; the first private cache adjusts the target access data block to a shared state.
  • the first private cache after the first private cache adjusts the target access data block to a shared state, it also includes: marking the processor core where the first private cache to which the target access data block in the adjusted state belongs is located as the owner processor core of the target access data block adjusted to a shared state, and updating it in the subsidiary directory of the shared cache.
  • the shared cache in response to the target state being valid and clean, the shared cache generates a second write-back request corresponding to the first read invalidation processing request, and sends it to the first private cache on any backup processor core corresponding to the target access data block, and also includes: the first private cache sends the data in the target access data block to the shared cache.
  • a shared cache responds to an invalidation processing request according to a target state, including: in response to the target state being valid and dirty, the shared cache generates a first invalidation and write-back request corresponding to the first write invalidation processing request, and sends it to the first private cache on the owner processor core corresponding to the target access data block; in response to the target state being valid and clean, the shared cache generates a first invalidation request corresponding to the first write invalidation processing request, and sends it to the first private caches on all backup processor cores corresponding to the target access data block.
  • the shared cache in response to the target state being valid and dirty, the shared cache generates a first invalidation and write-back request corresponding to the first write invalidation processing request, and sends it to the first private cache on the owner processor core corresponding to the target access data block, and also includes: in response to identifying that the backup data block corresponding to the target access data block is stored in the second private cache, the first private cache generates a second invalidation and write-back request and sends it to the second private cache; according to the second invalidation and write-back request, the second private cache adjusts the backup data block to an invalid state, and writes the adjusted backup data block back to the first private cache; the first private cache adjusts the target access data block to an invalid state, and generates a first invalidation and write-back response and sends it to the shared cache.
  • the shared cache in response to the target state being valid and clean, the shared cache generates a first invalidation request corresponding to the first write invalidation processing request, and sends it to the first private cache on all backup processor cores corresponding to the target access data block, and also includes: in response to identifying that the backup data block of the target access data block is stored in the second private cache, the first private cache generates a second invalidation request and sends it to the second private cache; according to the second invalidation request, the second private cache adjusts the backup data block to an invalid state, and writes the adjusted backup data block back to the first private cache; the first private cache adjusts the target access data block to an invalid state, and generates a first invalidation response and sends it to the shared cache.
  • the method further includes: a first private cache on the owner processor core sends the data in the target access data block to the shared cache.
  • the method also includes: in response to the target subsidiary information indicating that the target access data block does not exist in the first private cache of the multi-level cache system, obtaining the replacement strategy of the subsidiary directory of the shared cache, and updating the subsidiary directory of the shared cache according to the replacement strategy; and updating the first private cache according to the updated subsidiary information in the updated subsidiary directory.
  • information is updated on the first private cache according to the updated subsidiary information in the updated subsidiary directory, including: in response to an indication of updated subsidiary information, the data block corresponding to the subsidiary information in the first private cache is valid and in a clean state, the shared cache generates a third invalidation request, and sends the third invalidation request to the first private cache on the owner processor core corresponding to the data block corresponding to the subsidiary information; in response to an indication of updated subsidiary information, the data block corresponding to the subsidiary information in the first private cache is valid and in a dirty state, the shared cache generates a fourth invalidation request, and sends the fourth invalidation request to the first private cache on the non-owner processor core corresponding to the data block corresponding to the subsidiary information.
  • the first private cache is updated according to the updated subsidiary information in the updated subsidiary directory, and the information is also updated, and the following also includes: in response to the indication of the updated subsidiary information, the data block corresponding to the subsidiary information in the first private cache is valid and dirty, the shared cache generates a third invalidation and write-back request, and sends the third invalidation and write-back request to the first private cache on the owner processor core corresponding to the data block corresponding to the subsidiary information, or, sends it to the first private cache on the backup processor core that exclusively owns the data block corresponding to the subsidiary information.
  • the method also includes: in response to the shared cache storing a backup data block corresponding to the data block corresponding to the subsidiary information, and the identification information of the updated subsidiary information does not match the post-write information of the data block corresponding to the subsidiary information in the first private cache, the shared cache replaces the backup data block stored in the data domain in its own data storage array.
  • a second aspect of the present disclosure provides a data storage method for a multi-level cache system, the method comprising: writing data to be stored into the multi-level cache system, and obtaining post-write information of the data to be stored in the multi-level cache system; generating an attachment corresponding to the post-write information of the data to be stored; The subsidiary information is written into the subsidiary directory of the multi-level cache system, wherein the subsidiary directory is stored in the shared cache in the multi-level cache system.
  • the data storage method of the multi-level cache system proposed in the second aspect of the present disclosure may also have the following technical features:
  • a multi-level cache system includes a shared cache, a first private cache, and a second private cache.
  • the shared cache is a shared cache in a multi-core processor to which the multi-level cache system belongs, and the first private cache and the second private cache are private caches of the multi-core processor; wherein each processor core in the multi-core processor includes at least one first private cache and/or at least one second private cache.
  • the subsidiary directory is stored in a tag field on a shared cache in a multi-level cache system.
  • a multi-level cache system includes a first private cache, wherein the first private cache is a shared cache of some processor cores in a multi-core processor to which the multi-level cache system belongs.
  • generating subsidiary information corresponding to post-write information of data to be stored includes: obtaining subsidiary identification bits in the initial subsidiary information of the shared cache; obtaining identification information of the data to be stored in the subsidiary identification bits from the post-write information, and marking the identification information to the corresponding subsidiary identification bits to generate the subsidiary information of the data to be stored.
  • the subsidiary identification bits in the initial subsidiary information include: a write address bit, used to indicate the write address of a data block storing data to be stored; an address valid bit, used to indicate whether the write address of the stored data block is valid; a first valid bit, used to indicate whether the first data block stored in the shared cache is valid, wherein the first data block is a data block storing data to be stored in the shared cache; a first status bit, used to indicate whether the data to be stored has been written in the shared cache; and a data domain row number bit, used to indicate the storage row number of the first data block in the data domain of the data storage array of the shared cache.
  • the attachment identification bit in the initial attachment information also includes: a second valid bit, used to indicate whether the second data block stored in the first private cache is valid, wherein the second data block is a data block storing data to be stored in the first private cache; a second status bit, used to indicate the second data status of the second data block in all first private caches of the multi-core processor, wherein the second data status is an exclusive status (EXC) or a shared status (SHD); a backup bit, used to indicate a backup processor core in the multi-core processor that stores a backup data block of the second data block; a first owner bit, used to indicate whether there is an owner processor core of the second data block in the multi-core processor; and a second owner bit, used to indicate the owner processor core of the second data block in the multi-core processor.
  • EXC exclusive status
  • SHD shared status
  • the method includes: determining a target cache in a multi-level cache system to which data to be stored is written; obtaining target identification information corresponding to initial subsidiary information of a shared cache based on the target cache; in response to generating data to be stored in the target cache based on the target identification information, writing the target subsidiary information into a subsidiary directory.
  • obtaining target identification information corresponding to initial subsidiary information of a shared cache according to a target cache includes: in response to storing data to be stored in the shared cache, obtaining first identification information corresponding to the initial subsidiary information.
  • target subsidiary information in a subsidiary directory in response to generating data to be stored according to target identification information and storing it in a target cache, target subsidiary information in a subsidiary directory is written, including: in response to marking first identification information to a subsidiary identification bit and generating data to be stored in a shared cache, the first subsidiary information in the subsidiary directory is written.
  • obtaining target identification information corresponding to initial subsidiary information of a shared cache according to a target cache includes: in response to data to be stored being written into a first private cache, obtaining second identification information of the initial subsidiary information.
  • writing target subsidiary information in a subsidiary directory includes: in response to marking second identification information to a subsidiary identification bit and generating data to be stored in a first private cache, writing second subsidiary information in the subsidiary directory.
  • obtaining target identification information corresponding to initial subsidiary information of a shared cache according to a target cache includes: in response to writing data to be stored into the shared cache and the first private cache, obtaining third identification information of the initial subsidiary information.
  • target subsidiary information in response to generating data to be stored according to target identification information and storing it in a target cache, target subsidiary information is written into a subsidiary directory, including: in response to marking third identification information to the subsidiary identification bit and generating data to be stored in a shared cache and a first private cache, the third subsidiary information is written into the subsidiary directory.
  • the subsidiary information after writing the subsidiary information into the subsidiary directory of the multi-level cache system, it also includes: in response to the data to be stored being stored in the shared cache, obtaining the subsidiary information path number and the subsidiary information row number in the subsidiary directory; writing the subsidiary information path number and the subsidiary information row number into the information field of the data storage array of the shared cache.
  • the method further includes: in response to the fact that there is no corresponding row in the subsidiary directory for writing the subsidiary information corresponding to the data to be stored, obtaining a first replacement strategy for the subsidiary directory; determining the first replacement information in the subsidiary directory according to the first replacement strategy, deleting The first replacement information is written and the supplementary information is written into the corresponding row of the first replacement information, and the data block corresponding to the first replacement information is deleted synchronously.
  • the method also includes: in response to the fact that there is no corresponding location for storing the first data block of data to be stored in the data domain of the data storage array of the shared cache, obtaining a second replacement strategy of the shared cache; determining the second replacement data block in the data domain according to the second replacement strategy, storing the first data block to the second replacement position to which the second replacement data block belongs, and deleting the second replacement data block at the second replacement position; determining the second replacement information corresponding to the second replacement data block in the subsidiary directory; determining the corresponding row in the subsidiary directory where the second replacement information is deleted, and writing the subsidiary information corresponding to the first data block into the corresponding row deleted.
  • determining the second replacement information corresponding to the second replacement data block in the subsidiary directory includes: obtaining the replacement subsidiary information row number and the replacement subsidiary information path number of the second replacement information corresponding to the second replacement data block from the information domain of the data storage array; and determining the second replacement information from the subsidiary directory of the shared cache according to the replacement subsidiary information row number and the replacement subsidiary information path number.
  • the third aspect embodiment of the present disclosure proposes an access device for a multi-level cache system, characterized in that the device includes: an acquisition module, used to obtain an access request for the multi-level cache system; an access module, used to obtain, according to the access request, a target access data block of the access request in the multi-level cache system and target subsidiary information of the target access data block from a subsidiary directory of the multi-level cache system, wherein the subsidiary directory is stored on a shared cache in the multi-level cache system; and a response module, used to respond to the access request according to the target subsidiary information.
  • An embodiment of the fourth aspect of the present disclosure proposes a data storage device for a multi-level cache system, characterized in that the device includes: a first writing module, used to write data to be stored into the multi-level cache system, and obtain post-write information of the data to be stored in the multi-level cache system; a second writing module, used to generate subsidiary information corresponding to the post-write information of the data to be stored, and write the subsidiary information into a subsidiary directory of the multi-level cache system, wherein the subsidiary directory is stored on a shared cache in the multi-level cache system.
  • the fifth aspect of the present disclosure proposes an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor.
  • the processor executes the program, the access method of the multi-level cache system proposed in the first aspect or the data storage method of the multi-level cache system proposed in the second aspect is implemented.
  • the sixth aspect embodiment of the present disclosure proposes a computer-readable storage medium on which a computer program is stored.
  • the program When the program is executed by a processor, it implements the access method of the multi-level cache system proposed in the first aspect embodiment or the data storage method of the multi-level cache system proposed in the second aspect embodiment.
  • a seventh aspect embodiment of the present disclosure proposes a computer program product, including a computer program, which, when executed by a processor, implements the access method of the multi-level cache system proposed in the first aspect embodiment or the data storage method of the multi-level cache system proposed in the second aspect embodiment.
  • An embodiment of the eighth aspect of the present disclosure proposes a computer program, including computer program code.
  • the computer program code runs on a computer, the computer executes the access method of the multi-level cache system proposed in the embodiment of the first aspect or the data storage method of the multi-level cache system proposed in the embodiment of the second aspect.
  • the access method and device of the multi-level cache system of the embodiments of the present disclosure the data storage method and device, the electronic device, the storage medium, the computer program product and the computer program, wherein the access method of the multi-level cache system includes obtaining an access request of the multi-level cache system, and reading the subsidiary directory stored on the shared cache in the multi-level cache system according to the access request to obtain the target access data block corresponding to the access request in the multi-level cache system and the target subsidiary information corresponding to the target access data block.
  • the access request is responded to according to the target subsidiary information.
  • the data storage method of the multi-level cache system includes obtaining post-write information of the data to be stored in the multi-level cache system, generating the subsidiary information corresponding to the data to be stored according to the post-write information, and writing it into the subsidiary directory of the shared cache for sharing in the multi-level cache system.
  • the auxiliary information corresponding to the post-write information of the data to be stored in the multi-level cache system is generated, and written into the auxiliary directory of the shared cache in the multi-level cache system, so that by reading the auxiliary directory in the tag field of the shared cache, the post-write information of the data to be stored in the multi-level cache system can be obtained, the method for obtaining the post-write information of the data to be stored is simplified, the efficiency of obtaining the post-write information of the data to be stored in the multi-level cache system is improved, the resources for directory maintenance in the multi-level cache system are saved, the directory in the multi-level cache system is expandable, and the performance of the multi-level cache system is optimized.
  • the auxiliary directory exists on the shared cache of the multi-level cache system, and the effective management of the data blocks stored in the multi-level cache system is realized.
  • the target auxiliary information corresponding to the target access data block corresponding to the access request is obtained by reading the auxiliary directory, and the access request is responded to according to the target auxiliary information, which simplifies the method for obtaining the response information corresponding to the access request, thereby reducing the load degree caused by responding to the access request on the multi-level cache system, improving the stability of the performance of the multi-level cache system, and further reducing the access delay of the access request, optimizing the access method of the multi-level cache system, improving the access efficiency of the multi-level cache system, and saving the resources of the multi-level cache system.
  • FIG1 is a schematic flow chart of a method for accessing a multi-level cache system according to an embodiment of the present disclosure
  • FIG2 is a schematic flow chart of a method for accessing a multi-level cache system according to another embodiment of the present disclosure
  • FIG3 is a schematic diagram of a multi-level cache system according to an embodiment of the present disclosure.
  • FIG4 is a schematic flow chart of a data storage method of a multi-level cache system according to an embodiment of the present disclosure
  • FIG5 is a schematic flow chart of a data storage method of a multi-level cache system according to another embodiment of the present disclosure.
  • FIG6 is a schematic diagram of auxiliary information of a multi-level cache system according to an embodiment of the present disclosure.
  • FIG7 is a schematic flow chart of a data storage method of a multi-level cache system according to another embodiment of the present disclosure.
  • FIG8 is a schematic flow chart of a data storage method of a multi-level cache system according to another embodiment of the present disclosure.
  • FIG9 is a schematic diagram of an attached directory according to an embodiment of the present disclosure.
  • FIG10 is a schematic diagram of an attached directory according to another embodiment of the present disclosure.
  • FIG11 is a schematic flow chart of a method for accessing a multi-level cache system according to another embodiment of the present disclosure.
  • FIG12 is a schematic flow chart of a method for accessing a multi-level cache system according to another embodiment of the present disclosure.
  • FIG13 is a schematic diagram of the structure of an access device of a multi-level cache system according to an embodiment of the present disclosure
  • FIG14 is a schematic diagram of the structure of a data storage device of a multi-level cache system according to an embodiment of the present disclosure
  • FIG. 15 is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure.
  • FIG1 is a flow chart of a method for accessing a multi-level cache system according to an embodiment of the present disclosure. As shown in FIG1 , the method includes: S101 - S103 .
  • the data stored in the multi-level cache system can be obtained by initiating a corresponding request to the multi-level cache system.
  • a request corresponding to reading data stored in the multi-level cache system may be determined as an access request to the multi-level cache system.
  • the multi-level cache system is configured with a corresponding functional unit for receiving and reading the access requests it receives, and the access requests sent to the multi-level cache system can be obtained by reading the information received in the functional unit.
  • S102 obtain the target access data block of the access request in the multi-level cache system and the target subsidiary information of the target access data block from the subsidiary directory of the multi-level cache system, wherein the subsidiary directory is stored on the shared cache in the multi-level cache system.
  • a corresponding area may be configured on the shared cache in the multi-level cache system for storing the corresponding subsidiary directory of the multi-level cache system.
  • the subsidiary directory may be used to store storage information corresponding to data blocks stored in the multi-level cache system, thereby enabling access to corresponding data blocks in the multi-level cache system through the subsidiary directory.
  • the specific information carried in the access request may be read, and the subsidiary directory stored in the shared cache of the multi-level cache system may be read according to the read information.
  • an access request may carry identification information corresponding to a data block that needs to be read.
  • the identification information has corresponding identification information in a subsidiary directory of a shared cache of a multi-level cache.
  • the information in the subsidiary directory corresponding to the matched identification information is determined to be the relevant information required for the access request.
  • the subsidiary directory stores storage information corresponding to the data blocks stored in the multi-level cache system.
  • the relevant information of the corresponding data block that the access request needs to access and read is obtained according to the subsidiary directory.
  • the data block that needs to be accessed and read can be determined as the target access data block of the access request in the multi-level cache system.
  • the corresponding storage information stored in the subsidiary directory of the target access data block may be determined as the target subsidiary information of the target access data block in the subsidiary directory.
  • subsidiary information associated with an access request can be obtained from a subsidiary directory according to the access request, wherein the subsidiary information is target subsidiary information of a target access data block of the access request in a multi-level cache system stored in the subsidiary directory.
  • the target subsidiary information includes storage information corresponding to the target access data block stored in the multi-level cache system. Therefore, the access request can be responded to according to the target subsidiary information.
  • the data stored in the target access data block corresponding to the access request may be provided to the initiator of the access request according to the storage path of the target access data block indicated in the target auxiliary information.
  • return information corresponding to the normal reading can be generated according to the target auxiliary information, and the received access request can be responded to based on the return information.
  • the reason why the access request cannot normally access can be determined based on the target attached information, and corresponding response information is generated to respond to the received access request.
  • the access method of the multi-level cache system proposed in the embodiment of the present disclosure obtains the access request of the multi-level cache system, and reads the subsidiary directory stored on the shared cache in the multi-level cache system according to the access request, so as to obtain the target access data block corresponding to the access request in the multi-level cache system and the target subsidiary information corresponding to the target access data block.
  • the access request is responded to according to the target subsidiary information.
  • the effective management of the data blocks stored in the multi-level cache system is realized through the subsidiary directory on the shared cache of the multi-level cache system, the target subsidiary information corresponding to the target access data block corresponding to the access request is obtained by reading the subsidiary directory, and the access request is responded to according to the target subsidiary information, which simplifies the method for obtaining the response information corresponding to the access request, thereby reducing the load degree caused by responding to the access request on the multi-level cache system, improving the stability of the performance of the multi-level cache system, and further reducing the access delay of the access request, optimizing the access method of the multi-level cache system, improving the access efficiency of the multi-level cache system, and saving the resources of the multi-level cache system.
  • Figure 2 is a flow chart of an access method for a multi-level cache system according to another embodiment of the present disclosure. As shown in Figure 2, the method includes: S201-S202.
  • the access status of the access request in the multi-level cache system may be determined from the target subsidiary information corresponding to the target access data block stored in the target subsidiary information.
  • the target attachment information may be obtained based on an attachment directory in a multi-level cache system, wherein the attachment directory is stored in a tag field on a shared cache in the multi-level cache system.
  • the target attachment information corresponding to the target access data block of the access request in the multi-level cache system can be obtained from the attachment directory stored in the tag field on the shared cache in the multi-level cache system, thereby determining the access status of the access request in the multi-level cache system.
  • an abnormal storage state may occur, causing the access request to be unable to access and read it normally.
  • the storage state corresponding to the target access data block can be obtained based on the target subsidiary information of the target access data block in the subsidiary directory, thereby determining the access state corresponding to the access request.
  • the multi-level cache system may include a shared cache and a private cache, wherein the shared cache is a multi-level cache system.
  • the L1 cache is the upper level cache of the L2 cache
  • the L2 cache is the upper level cache of the L3 cache
  • the L3 cache is the shared cache in the multi-level cache system shown in Figure 3
  • the L1 cache and the L2 cache are private caches in the multi-level cache system shown in Figure 3.
  • the L2 cache is set as the first private cache in the multi-level cache system shown in FIG. 3
  • the L1 cache is set as the second private cache in the multi-level cache system shown in FIG. 3 .
  • each multi-core processor may include at least one first private cache and/or at least one second private cache.
  • the access request sent by the first private cache to the second private cache can be obtained by the access request receiving and reading unit set on the second private cache.
  • a first private cache in a multi-level cache system may send an access request to a second private cache, wherein, in response to the access status of the access request sent by the first private cache to the second private cache in the multi-level cache system being access invalidation, the first private cache sends an invalidation processing request to the shared cache in the multi-level cache system.
  • the multi-core processor can obtain relevant information about data stored in the multi-level cache system by accessing the subsidiary directory of the shared cache.
  • an access request can be initiated to the subsidiary directory of the shared cache in the multi-level cache system.
  • the shared cache can read the subsidiary information in its subsidiary directory, so as to obtain the distribution of the target access data block that the access request needs to access in the multi-level cache system and related information of the corresponding status.
  • the first private cache can continue to initiate access requests to its next-level cache, the second private cache, and the second private cache can provide relevant responses and data transmissions to the first private cache, so that the first private cache can satisfy the access requests initiated by the second private cache.
  • a scenario in which the first private cache cannot satisfy and correctly respond to an access request initiated by the second private cache may be determined as an access failure of the first private cache to the access request sent by the second private cache.
  • the request that the first private cache continues to initiate to the shared cache in this scenario is determined as a corresponding invalidation processing request.
  • an abnormality occurs in the status of a related data block in the first private cache corresponding to the access request sent by the second private cache, making it impossible for the first private cache to correctly respond to the access request sent by the second private cache, and it is determined that the access request currently sent by the second private cache to the first private cache has failed.
  • the first private cache can continue to send corresponding invalidation processing requests to its next-level shared cache.
  • the first private cache can implement the access request initiated by the second private cache.
  • the set controller can be used to maintain the subsidiary directory in the tag field of the shared cache used for sharing in the multi-level cache system.
  • the shared cache initiates a request for the first private cache, the returned response, and the coherent access request of the next level cache and/or memory corresponding to the shared cache, as well as the related operations of the shared cache, are all implemented by the set subsidiary directory controller.
  • auxiliary information corresponding to a target access data block of an access request in a multi-level cache system is determined as target auxiliary information.
  • the shared cache after the shared cache receives an invalidation processing request sent by the first private cache, it can obtain from the invalidation processing request the data block that the access request sent by the second private cache to the first private cache needs to access, wherein the data block can be determined as the target access data block corresponding to the access request in the multi-level cache system.
  • the shared cache needs to obtain relevant post-write information such as the distribution and storage status of the target access data block in the multi-level cache system.
  • the corresponding subsidiary information may be determined from the subsidiary directory of the shared cache according to the relevant information of the target access data block, and the corresponding subsidiary information may be determined as the target subsidiary information.
  • a relevant query can be performed on a backup bit in a subsidiary directory of a shared cache based on identification information corresponding to the backup processor core, and subsidiary information on the backup bit that contains identification information corresponding to the backup processor core can be determined as target subsidiary information corresponding to the target access data block.
  • the corresponding target subsidiary information can be determined from the subsidiary directory through the subsidiary information corresponding to the target access data block in the information domain of the data storage array.
  • the supplementary information on the supplementary identification bit of the target supplementary information is obtained, and the access status of the access request is obtained based on the supplementary information on the supplementary identification bit.
  • the subsidiary information with the subsidiary identifier on the target subsidiary information may be read, and the storage state of the target access data block in the multi-level cache system may be determined according to the content of the read subsidiary information.
  • the target access data block corresponding to the access request is currently in a normal storage state in the multi-level cache system and can be accessed and read normally by the access request, thereby determining that the access state of the current access request is normal.
  • the storage status of the target access data block corresponding to the access request in the multi-level cache system is abnormal, and then it is determined that the target access data block cannot be normally accessed and read by the access request, and the access status of the current access request is determined to be abnormal.
  • S202 The shared cache responds to the access request in the access state.
  • the shared cache may respond to the received access request according to the determined access status of the access request in the multi-level cache system.
  • the corresponding data in the target access data block can be returned to the initiator of the access request based on the information required by the access request, thereby responding to the access request in the normal access status.
  • exception information corresponding to the abnormal access status of the access request can be obtained from the target auxiliary information, and the obtained exception information can be returned to the initiator of the access request, thereby achieving a response to the access request in the abnormal access status.
  • an access request with an abnormal access status may generate a corresponding invalidation processing request
  • the shared cache may respond to the access request in the abnormal access status by responding to the invalidation processing request corresponding to the access request with the abnormal access status.
  • the shared cache responds to the invalidation processing request according to the target attachment information.
  • the relevant information of the target access data block can be determined from the identification information on the subsidiary identification bit of the target subsidiary information.
  • the invalidation processing request initiated by the first private cache is responded to according to the acquired relevant information.
  • the second private cache H2 sends an access request to the first private cache H1, and the storage status of the target access data block that the access request needs to access in the first private cache H1 is abnormal, resulting in the second private cache H2 being unable to make a read call on it.
  • the access request initiated by the first private cache H1 to the second private cache H2 fails.
  • the first private cache H1 sends an invalidation processing request to the shared cache H3.
  • the shared cache H3 determines the target subsidiary information of the target access data block in the subsidiary directory, it obtains the backup processor core to which the backup data block of the target access data block belongs, and then obtains the backup data block corresponding to the target access data block from the first private cache on the backup processor core, and generates corresponding response information with its related information and returns it to the first private cache H1.
  • the first private cache H1 responds to the second private cache H2 that initiated the access request based on the response information returned by the shared cache H3 to the invalidation processing request.
  • the multi-level cache on the multi-core processor proposed in the embodiment of the present disclosure may include a shared cache, a first private cache and a second private cache, wherein the shared cache is the shared cache of the multi-core processor to which the multi-level cache system belongs, the first private cache and the second private cache are the private caches of the multi-core processor, and each processor core in the multi-core processor includes at least one first private cache and/or at least one second private cache.
  • the access method of the multi-level cache system proposed in the embodiment of the present disclosure is to access the target attached information of the target access data block corresponding to the access request according to the target attached information of the target access data block corresponding to the access request.
  • the shared cache obtains the access status of the access request, and responds to the access request according to the access status of the access request.
  • the first private cache can initiate an invalidation processing request to the shared cache, and the shared cache determines the corresponding target subsidiary information in the subsidiary directory according to the target access data block corresponding to the access request, and generates a relevant response to the invalidation processing request according to the identification information in the target subsidiary information, and returns it to the first private cache that initiated the invalidation processing request.
  • auxiliary directory on the shared cache of the multi-level cache system, which realizes the effective management of the data blocks stored in the multi-level cache system, obtains the target auxiliary information corresponding to the target access data block corresponding to the access request by reading the auxiliary directory, and responds to the access request according to the target auxiliary information, which simplifies the method of obtaining the response information corresponding to the access request.
  • the invalidation processing request sent by the first private cache to the shared cache enables the shared cache to respond to the invalidation processing request through the auxiliary directory maintained in its tag domain, thereby enabling the first private cache to respond to the second private cache, and realizing exception processing in abnormal access scenarios, thereby reducing the load degree caused by responding to access requests on the multi-level cache system, improving the stability of the performance of the multi-level cache system, and thereby reducing the abnormal probability of abnormal situations such as access delays in access requests, optimizing the access method of the multi-level cache system, and improving the access efficiency of the multi-level cache system.
  • FIG4 is a flow chart of a data storage method of a multi-level cache system according to an embodiment of the present disclosure. As shown in FIG4 , the method includes: S401 - S402 .
  • each level may include at least one cache system, wherein relevant information after data in the previous level cache is written can be written into the tag field of the set level cache, so that the set level cache can record and maintain the information after the data in the previous level cache is written.
  • an auxiliary directory with an independent structure can be set in the tag field of the set-level cache, and based on the structural setting of the auxiliary directory, the auxiliary information corresponding to the relevant information of the data stored in the previous level cache in the tag field of the set-level cache is generated.
  • the subsidiary information is written into a subsidiary directory in the tag field of the set level cache, and is maintained as a sparse directory in the tag field of the set level cache as relevant post-write information of data in the previous level cache.
  • the L2 cache is set as the upper-level cache of the L3 cache.
  • Corresponding subsidiary information can be generated based on relevant post-write information of the data in the L2 cache, and written into the tag field of the L3 cache as a sparse directory maintained in the L3 tag field for relevant post-write information of the data in the L2 cache.
  • the post-write information may include relevant information such as the write address, storage status, and parameters related to the occupied storage space of the data to be stored in the multi-level cache system.
  • a subsidiary directory with an independent structure is provided in the tag field of the setting level cache, wherein the subsidiary directory is composed of subsidiary information corresponding to different data.
  • the subsidiary information constituting the subsidiary directory has a set format, and therefore, the relevant information in the written information can be integrated according to the set format to generate the subsidiary information corresponding to the data to be stored.
  • the auxiliary information there are different types of data bits in the auxiliary information. According to the type of data to be filled in each data bit, the corresponding storage data can be obtained from the written information and filled in the corresponding data bit.
  • the storage data corresponding to the storage location of the data to be stored can be obtained from the written information of the data to be stored and filled in the data bit of the storage location type.
  • the storage data corresponding to the storage occupied space of the data to be stored can be obtained from the written information of the data to be stored and filled in the data bit of the storage location type.
  • supplementary information corresponding to the data to be stored is generated according to the filling of the storage data on different types of data bits.
  • a multi-level cache system on a multi-core processor may include a shared cache and a private cache, wherein the private cache
  • the memory is a private cache system for each processor core.
  • a corresponding subsidiary directory can be set in the tag field of the shared cache, and the subsidiary directory can be stored on the shared cache in the multi-level cache system.
  • the shared cache in the multi-level cache system can be determined as the shared cache.
  • the L3 cache is the shared cache used for sharing in the multi-level cache system shown in FIG. 3 .
  • the subsidiary information corresponding to the data to be stored can be written into the subsidiary directory of the shared cache as a sparse directory of the data to be stored in the tag field of the shared cache.
  • the post-write information related to the data to be stored can be recorded and maintained.
  • the subsidiary information corresponding to the data to be stored may be written into the subsidiary directory in the tag field of the L3 cache as a sparse directory maintained in the tag field of the L3 cache for the data to be stored.
  • the data storage method of the multi-level cache system proposed in the embodiment of the present disclosure obtains the post-write information of the data to be stored in the multi-level cache system, generates the subsidiary information corresponding to the data to be stored according to the post-write information, and writes it into the subsidiary directory of the shared cache used for sharing in the multi-level cache system.
  • the subsidiary information corresponding to the post-write information of the data to be stored in the multi-level cache system is generated, and written into the subsidiary directory of the shared cache in the multi-level cache system, so that the post-write information of the data to be stored in the multi-level cache system can be obtained by reading the subsidiary directory in the tag field of the shared cache, which simplifies the method for obtaining the post-write information of the data to be stored, improves the efficiency of obtaining the post-write information of the data to be stored in the multi-level cache system, saves the resources for directory maintenance in the multi-level cache system, realizes the scalability of the directory in the multi-level cache system, and optimizes the performance of the multi-level cache system.
  • Figure 5 is a flow chart of a data storage method of a multi-level cache system in another embodiment of the present disclosure. As shown in Figure 5, the method includes: S501-S502.
  • the multi-level cache system of a multi-core processor includes a shared cache, a first private cache, and a second private cache.
  • the shared cache is the shared cache in the multi-core processor to which the multi-level cache system belongs, and the first private cache and the second private cache are the private caches of the multi-core processor.
  • the subsidiary directory is stored in a shared cache, and each processor core in the multi-core processor includes at least one first private cache and/or at least one second private cache.
  • the subsidiary directory is stored in a tag field on a shared cache in a multi-level cache system.
  • the multi-core processor includes N processor cores.
  • the private cache system on each of the N processor cores can be determined as the private cache in the multi-level cache system on the multi-core processor, and the cache system shared by the N processor cores can be determined as the shared cache in the multi-level cache system on the multi-core processor.
  • the shared cache stores the subsidiary directory of the multi-level cache system on the multi-core processor.
  • the subsidiary directories of the multi-level cache system on the multiple processors may be stored in a tag field on a shared cache in the multi-level cache.
  • the L3 cache is a shared cache used for sharing in the multi-level cache system shown in FIG. 3
  • the L2 cache and the L3 cache are private caches of the processor core.
  • the subsidiary directory of the multi-level cache shown in FIG. 3 may be stored in a tag field on the L3 cache.
  • the multi-level cache system includes a first private cache, wherein the first private cache is a shared cache of some processor cores in a multi-core processor to which the multi-level cache system belongs.
  • the first private cache may be a cache system shared by a set number of processor cores in a multi-core processor, wherein the set number is smaller than the corresponding number of all processor cores in the multi-core processor.
  • the multi-core processor includes N processor cores, and the cache system shared by the M processor cores in the multi-core processor can be determined as a partial shared cache in the multi-level cache system on the multi-core processor, where M is less than N.
  • the first private cache L2 may be a shared cache of some processor cores in the multi-core processor shown in FIG. 3 .
  • the initial subsidiary information corresponding to the subsidiary directory of the shared cache can be obtained, and the subsidiary directory on the initial subsidiary information can be obtained by The corresponding identification information is filled in the attribute identification bit to generate the corresponding auxiliary information.
  • the auxiliary identification bit of the initial auxiliary information of the shared cache includes a corresponding auxiliary identification bit for indicating the information related to the shared cache.
  • the corresponding auxiliary identification bit for indicating the information related to the shared cache may include:
  • the write address bit is used to indicate the write address of the data block storing the data to be stored.
  • the address valid bit is used to indicate whether the write address of the storage data block is valid.
  • the first valid bit is used to indicate whether the first data block stored in the shared cache is valid, wherein the first data block is a data block storing data to be stored in the shared cache.
  • the first status bit is used to indicate whether the data to be stored has been written in the shared cache.
  • the data domain row number bit is used to indicate the storage row number of the first data block in the data domain of the data storage array of the shared cache.
  • This part may be used to indicate a corresponding subsidiary identification bit of the shared cache related information, and may be determined as the first subsidiary identification bit in the initial subsidiary information.
  • the set flag on the first valid bit indicates that the first data block in the shared cache is valid
  • the set flag on the first status bit used to indicate whether the data to be stored has been written to the shared cache is valid.
  • the set flag on the first state bit may include identification information 0 and identification information 1, wherein, in response to the identification information corresponding to the set flag on the first state bit being 0, it is determined that the data to be stored has not been written in the shared cache, and the data to be stored in this scenario is identified as clean data that has not been written.
  • first data block storing dirty data may be replaced and updated.
  • the replaced first data block storing dirty data is written back to the next level cache or memory of the shared cache.
  • the first private cache can send a set write-back request to the shared cache.
  • the first private cache can send corresponding information about whether the data to be stored has been written in the first private cache to the shared cache.
  • the shared cache can modify the set flag on the first status bit based on the information sent by the first private cache.
  • the shared cache in response to the first private cache sending corresponding information that the data to be stored has been written in the first private cache to the shared cache, the shared cache updates the set flag on its corresponding first status bit to flag information 1 based on the received information.
  • the shared cache in response to the first private cache sending corresponding information that the data to be stored has not been written to the first private cache to the shared cache, the shared cache updates the set flag on its corresponding first status bit to flag information 0 based on the received information.
  • the auxiliary identification bit of the initial auxiliary information of the shared cache further includes a corresponding auxiliary identification bit for indicating the first private cache related information.
  • the corresponding auxiliary identification bit for indicating the first private cache related information may include:
  • the second valid bit is used to indicate whether the second data block stored in the first private cache is valid, wherein the second data block is a data block storing data to be stored in the first private cache.
  • the second state bit is used to indicate a second data state of the second data block in all first private caches of the multi-core processor, wherein the second data state is an exclusive state (EXC) or a shared state (SHD).
  • EXC exclusive state
  • SHD shared state
  • the backup bit is used to indicate a backup processor core storing a backup data block of the second data block in a multi-core processor.
  • the first owner bit is used to indicate whether there is an owner processor core of the second data block in the multi-core processor.
  • the second owner bit is used to indicate the owner processor core of the second data block in the multi-core processor.
  • This part may be used to indicate a corresponding subsidiary identification bit of the first private cache related information, and may be determined as the second subsidiary identification bit in the initial subsidiary information.
  • the first subsidiary identification bit of the shared cache and the second subsidiary identification bit of the first private cache are combined according to a setting order in the subsidiary directory to generate a corresponding complete subsidiary identification bit in the subsidiary directory of the shared cache.
  • corresponding identification information in the post-write information of the data to be stored is obtained according to the subsidiary identification bit set on the initial subsidiary information in the subsidiary directory of the shared cache.
  • the acquired identification information is marked on the corresponding subsidiary identification bit, thereby generating subsidiary information corresponding to the data to be stored.
  • the cache where the data to be stored is stored may be determined as the target cache of the data to be stored, and different subsidiary information of the data to be stored in different target caches may be generated according to different target caches.
  • a target cache in a multi-level cache system in which data is to be stored is determined.
  • the data to be stored may be stored only in a shared cache.
  • the shared cache is the target cache for storing the data to be stored.
  • the data to be stored may be stored only in the first private cache.
  • the first private cache is the target cache for storing the data to be stored.
  • the data to be stored may be stored in a shared cache and a first private cache at the same time.
  • both the shared cache and the first private cache are target caches for storing the data to be stored.
  • target identification information corresponding to the initial subsidiary information of the shared cache is obtained, and in response to generating data to be stored according to the target identification information, the target subsidiary information is written into the subsidiary directory.
  • first identification information corresponding to the initial subsidiary information can be obtained, and the first identification information can be marked on the subsidiary identification bit, so as to generate the first subsidiary information written into the subsidiary directory of the shared cache when the data to be stored is stored in the shared cache.
  • the identification information required on the subsidiary identification bit of the initial subsidiary information obtained from the post-write information in this scenario is determined as the first identification information.
  • the first identification information obtained from the post-writing information may include:
  • the first write address in the shared cache of the first data block corresponding to the data to be stored in the shared cache is marked on the write address bit.
  • the first write address is valid.
  • the status of the first data block is valid.
  • the first status bit indicates whether the data to be stored has been written in the shared cache.
  • the storage row number of the first data block in the data domain of the data storage array of the shared cache is marked on the data domain row number bit.
  • the first owner bit is marked invalid.
  • the first identification information on the subsidiary identification bit used to indicate the first private cache related information in the initial subsidiary information in this scenario is all invalid indication information.
  • the data to be stored can be stored only in the first private cache
  • second identification information of the initial subsidiary information is obtained, and in response to marking the second identification information onto the subsidiary identification bit, the data to be stored is generated to be stored in the first private cache, and second subsidiary information is written into the subsidiary directory of the shared cache.
  • the identification information required on the subsidiary identification bit of the initial subsidiary information obtained from the post-write information in this scenario is determined as the second identification information.
  • the second identification information obtained from the post-writing information may include:
  • the data to be stored is marked on the write address bit and the corresponding second data block is stored in the first private cache at the second write address in the first private cache.
  • the second write address is valid.
  • the mark on the first valid bit is invalid.
  • the first state bit is in an invalid state.
  • the mark on the row number position of the data field is invalid.
  • the status of the second data block is valid.
  • the second data state of the second data block marked on the second state bit is an exclusive state (EXC) or a shared state (SHD).
  • the backup processor core marked on the backup bit stores a backup data block of the second data block in the multi-core processor.
  • the first owner bit is marked to determine whether there is an owner processor core of the second data block in the multi-core processor.
  • the processor core marked in the second owner bit is the owner of the second data block in the multi-core processor.
  • the second identification information on the subsidiary identification bit used to indicate the shared cache related information in the initial subsidiary information in this scenario is all invalid indication information.
  • the data to be stored in both the shared cache and the first private cache, in response to the data to be stored being written into the shared cache and the first private cache, the third identification information of the initial subsidiary information is obtained, and in response to marking the third identification information onto the subsidiary identification bit, the data to be stored is generated and stored in the shared cache and the first private cache, and the third subsidiary information is written into the subsidiary directory of the shared cache.
  • the identification information required on the subsidiary identification bit of the initial subsidiary information obtained from the post-write information in this scenario is determined as the third identification information.
  • the third identification information obtained from the post-writing information may include:
  • the third write address of the first data block in the shared cache and/or the fourth write address of the second data block in the first private cache are marked on the write address bit.
  • the status of the first data block is valid.
  • the first status bit indicates whether the data to be stored has been written in the shared cache.
  • the storage row number of the first data block in the data domain of the data storage array of the shared cache is marked on the data domain row number bit.
  • the status of the second data block is valid.
  • the second data state of the second data block marked on the second state bit is an exclusive state (EXC) or a shared state (SHD).
  • the backup processor core marked on the backup bit stores a backup data block of the second data block in the multi-core processor.
  • the first owner bit is marked to determine whether there is an owner processor core of the second data block in the multi-core processor.
  • the processor core marked in the second owner bit is the owner of the second data block in the multi-core processor.
  • the shared cache and the first private cache there is a set association relationship between the shared cache and the first private cache, wherein, in response to the shared cache and the first private cache being a non-inclusive relationship (exclusive), the data to be stored can be stored only in the first private cache; in response to the shared cache and the first private cache being an inclusive relationship (inclusive), the data to be stored can be stored in both the shared cache and the first private cache; in response to the shared cache and the first private cache being a non-inclusive relationship (non-inclusive), the data to be stored can be stored in the shared cache and/or the first private cache.
  • the first subsidiary information may be written into a subsidiary directory of the shared cache as a sparse directory maintained in the tag field of the shared cache when the data to be stored is stored in the shared cache.
  • the second subsidiary information can be written into the subsidiary directory of the shared cache as a sparse directory maintained in the tag field of the shared cache when the data to be stored is stored in the first private cache.
  • the third subsidiary information can be written into the subsidiary directory of the shared cache as a sparse directory maintained in the tag field of the shared cache when the data to be stored is stored in both the shared cache and the first private cache.
  • a multi-level cache system on a multi-core processor is set as shown in FIG3 , wherein the multi-core processor includes 128 processor cores, each cache line has 512 bits, and a physical address of 40 bits.
  • the data A to be stored is assumed to be stored in a shared cache and a first private cache, wherein the physical write address (paddr) of the first data block A1 stored in the shared cache is paddr0: 0x802d7950 (corresponding to binary: 0000 0000 1000 0000 0010 1101 0111 1001 0101 0000), and the first valid bit of the first data block A1 in the supplementary information is marked as valid, and the first status bit is marked as the data status that has been written.
  • the physical write address (paddr) of the first data block A1 stored in the shared cache is paddr0: 0x802d7950 (corresponding to binary: 0000 0000 1000 0000 0010 1101 0111 1001 0101 0000)
  • the first valid bit of the first data block A1 in the supplementary information is marked as valid
  • the first status bit is marked as the data status that has been written.
  • the second status bit of the second data block A2 stored in the first private cache in the auxiliary information is marked as an exclusive state (EXC)
  • the processor core storing the second data block A2 is processor core No. 127 (7’b1111111)
  • the owner processor core of the second data block A2 stored in the data A to be stored in the first private cache is processor core No. 127.
  • the first data block B1 of the data B to be stored is only stored in the shared cache, and its physical write address is paddr1: 0xf75dde08 (corresponding to binary: 0000 0000 0000 0111 0101 1101 1101 1110 0000 1000), where:
  • the data to be stored A and the data to be stored B are stored in a multi-level cache system, and the corresponding auxiliary information can be understood in conjunction with FIG. 6 .
  • valid indicates valid
  • inv indicates invalid
  • EXC indicates exclusive state
  • SHD indicates shared state
  • 1 on the first state bit indicates that data has been written
  • 0 indicates that data has not been written
  • 1 on the first owner bit indicates that an owner processor core exists
  • 0 indicates that an owner processor core does not exist.
  • the data storage method of the multi-level cache system proposed in the embodiment of the present disclosure obtains the initial subsidiary information in the subsidiary directory of the shared cache, and obtains the corresponding identification information from the post-write information of the data to be stored according to the subsidiary identification bit of the initial subsidiary information.
  • the identification information is marked on the corresponding subsidiary identification bit, thereby generating the subsidiary information corresponding to the data to be stored.
  • the scalability of the directory in the multi-level cache system is achieved by setting the subsidiary identification bit, and the identification information corresponding to the post-write information of the data to be stored is obtained according to the subsidiary identification bit, and then the corresponding subsidiary information is generated, so that the subsidiary information can be written into the subsidiary directory in the tag field of the shared cache, thereby realizing the maintenance and recording of the post-write information of the data to be stored in the subsidiary directory of the shared cache, saving the resources for directory maintenance in the multi-level cache system, and optimizing the performance of the multi-level cache system.
  • Figure 7 is a flow chart of a data storage method of a multi-level cache system in another embodiment of the present disclosure. As shown in Figure 7, the method includes: S701-S702.
  • auxiliary directory In some embodiments, during the process of writing the auxiliary information into the auxiliary directory of the shared cache, there is a possibility that the auxiliary directory is filled.
  • the set processing method can be obtained, and according to the obtained processing method, a corresponding row for writing the subsidiary information can be vacated in the subsidiary directory.
  • the processing method in this scenario may be determined as the first replacement strategy.
  • the first replacement strategy may include a random replacement strategy, a least recently used replacement strategy, a least frequently used replacement strategy, and a first-in-first-out replacement strategy.
  • S702 determine the first replacement information in the subsidiary directory, delete the first replacement information and write the subsidiary information into the corresponding row of the first replacement information, and simultaneously delete the data block corresponding to the first replacement information.
  • the label that needs to be replaced can be obtained from the subsidiary directory and determined as the first replacement information.
  • a tag in response to the first replacement strategy being a random replacement strategy, may be randomly selected as the first replacement information.
  • the tag with the lowest frequency of use within a set time range may be used as the first replacement information.
  • the row where the first replacement information is located in the subsidiary directory is determined, and the subsidiary information corresponding to the data to be stored is written into the row, and the related information of the first replacement information is deleted.
  • the subsidiary directory is used to maintain the relevant post-write information of the data in the multi-level cache system. Therefore, after the first replacement information is replaced and deleted, the storage data corresponding to the first replacement information needs to be replaced and deleted accordingly.
  • the first valid bit on the first replacement information needs to be marked as valid.
  • the data block corresponding to the first replacement information can be deleted.
  • the storage location of the corresponding data block can be determined through the identification information on the row number position of the data field of the first replacement information, and then the data block at the location can be deleted.
  • the second valid bit on the second replacement information needs to be marked as valid, and the processor core where the first private cache to which the data block belongs is located is one of the backup processor cores indicated on the backup bit of the second replacement information.
  • the data block corresponding to the first replacement information can be deleted.
  • the Index and Block offset of the data block corresponding to the data to be stored obtained from the supplementary information corresponding to the data to be stored in the first private cache can be used as the low-order address of the data block, and the address indicated by the write address bit of the first replacement information can be used as the high-order address of the data block, thereby determining the storage position of the data block corresponding to the first replacement information in the first private cache.
  • the data storage method of the multi-level cache system proposed in the embodiment of the present disclosure obtains the first replacement strategy of the subsidiary directory in response to the absence of a corresponding row for writing subsidiary information in the subsidiary directory of the shared cache, and determines the first replacement information to be replaced from the subsidiary directory according to the first replacement strategy.
  • the subsidiary information is written to the row where the first replacement information is located in the subsidiary directory, and the first replacement information is deleted. Accordingly, the data block corresponding to the first replacement information in the multi-level cache system is determined, and it is deleted from the corresponding storage location.
  • exception handling is implemented for the scenario where the subsidiary directory is full, and data cleaning in the multi-level cache system is implemented by maintaining the subsidiary directory, thereby optimizing the performance of the multi-level cache system.
  • Figure 8 is a flow chart of a data storage method of a multi-level cache system in another embodiment of the present disclosure. As shown in Figure 8, the method includes: S801-S804.
  • a relevant processing method corresponding to the data storage array of the shared cache can be obtained, and a corresponding location for storage of the first data block can be vacated according to the obtained processing method.
  • the processing method obtained in this scenario can be determined as the second replacement strategy.
  • the second replacement strategy can include a random replacement strategy, a least recently used replacement strategy, a least frequently used replacement strategy, and a first-in-first-out replacement strategy.
  • the corresponding position in the data domain that is vacated for storage of the first data block can be vacated accordingly, and the storage position corresponding to the supplementary information path number and the supplementary information row number corresponding to the corresponding position in the data domain in the information domain can be vacated, and when the first data block is stored in the data domain, the supplementary information row number and the supplementary information path number of the supplementary information corresponding to the first data block in the supplementary directory can be written into the corresponding position in the information domain.
  • S802 determine a second replacement data block in the data domain, store the first data block to a second replacement position to which the second replacement data block belongs, and delete the second replacement data block at the second replacement position.
  • a data block that can be replaced can be obtained from the data storage array of the shared cache and determined as the second replacement data block.
  • a storage location to which the second data block belongs in the shared cache is determined and determined as a second replacement location vacated for the first data block in the shared cache.
  • the first data block may be stored in the second replacement position, and the second replacement data block may be deleted from the second replacement position.
  • S803 Determine second replacement information corresponding to the second replacement data block in the subsidiary directory.
  • the data blocks stored in the shared cache have corresponding subsidiary information in the subsidiary directory.
  • the subsidiary information corresponding to the second replacement data block in the subsidiary directory needs to be deleted.
  • the replacement subsidiary information row number and the replacement subsidiary information path number of the second replacement information corresponding to the second replacement data block are obtained from the information field of the data storage array.
  • a data block when a data block is stored in the data domain of the data storage array of the shared cache, corresponding record information exists in the information domain, wherein relevant information of the tag corresponding to the data block in the subsidiary directory can be stored in the information domain.
  • the subsidiary directory of the shared cache may be a multi-way group directory as shown in FIG. 9 . Therefore, the subsidiary information in the subsidiary directory has corresponding subsidiary information way numbers and subsidiary information row numbers.
  • the subsidiary information path number of subsidiary information group 1 is 0, the subsidiary information path number of subsidiary information group 2 is 1, the subsidiary information path number of subsidiary information group 3 is 2, and so on.
  • the supplementary information A in the supplementary information group 1 is in the first row of the supplementary information group 1, and the supplementary information row number of the supplementary information A in the supplementary information group 1 is 0, the supplementary information B is in the third row of the supplementary information group 2, and the supplementary information row number of the supplementary information B is 2, the supplementary information C is in the second row of the supplementary information group 3, and the supplementary information row number of the supplementary information C is 1, and so on.
  • the supplementary information row number of the supplementary information A in the supplementary directory shown in Figure 9 is 0, and the supplementary information path number is 0, the supplementary information row number of the supplementary information B in the supplementary directory shown in Figure 9 is 2, and the supplementary information path number is 1, and the supplementary information row number of the supplementary information C in the supplementary directory shown in Figure 9 is 1, and the supplementary information path number is 3.
  • the path number and row number of the subsidiary information can be used as the record information corresponding to the data block and stored in the information field of the data storage array. As shown in FIG10 , different data blocks are stored in different rows of the data storage array, and the corresponding rows in the information field can record the subsidiary information corresponding to the data block in the subsidiary directory. Line number and attached information route number.
  • the subsidiary information path number and the subsidiary information row number of the subsidiary information corresponding to the second replacement data block can be obtained from the record information of the second replacement data block in the information domain of the data storage array, and determined as the replacement subsidiary information path number and the replacement subsidiary information row number.
  • a query is performed in the subsidiary directory to determine the label corresponding to the second replacement data block and determine it as the second replacement information.
  • the second replacement information after the second replacement information is determined, it can be deleted, and the corresponding row after the deletion is used as the corresponding row for writing the supplementary information corresponding to the first data block.
  • the subsidiary information corresponding to the first data block can be stored in the corresponding row vacated after the second replacement information is deleted from the subsidiary directory.
  • the subsidiary information C is set as the second replacement information. After determining that the subsidiary information C is the second replacement information, the subsidiary information C can be deleted from the row where it is located, and the corresponding row obtained after the deletion is used as the corresponding row where the subsidiary information corresponding to the first data block is written.
  • the data storage method of the multi-level cache system proposed in the embodiment of the present disclosure is that when there is no corresponding position available for storing the first data block in the shared cache, the second replacement strategy corresponding to the shared cache is obtained, and the corresponding second replacement data block is determined from the data domain of the shared cache according to the second replacement strategy.
  • the second replacement position where the second replacement data block is stored in the shared cache is obtained, the second replacement data block at the second replacement position is deleted, and the first data block of the data to be stored is written. Accordingly, the second replacement information corresponding to the second replacement data block in the subsidiary directory is obtained and deleted.
  • the exception handling of the scenario where there is no corresponding position available for storage in the data domain of the shared cache is realized, and while the data in the shared cache is maintained and managed, the synchronization of the subsidiary directory is realized, the maintenance and management method of the subsidiary directory is optimized, and the performance of the multi-level cache system is optimized.
  • Figure 11 is a flow chart of the access method of the multi-level cache system of another embodiment of the present disclosure. As shown in Figure 11, the method includes: S1101-S1103.
  • S1101 In response to an access status of an access request sent by a first private cache to a second private cache in a multi-level cache system being access invalid, the first private cache sends an invalidation processing request to a shared cache in the multi-level cache system.
  • the access status of the access request sent by the first private cache to the second private cache may be in an access failure state, wherein, in response to the target attached information indication, the access request sent by the first private cache to the second private cache does not hit in the first private cache, and the access status of the access request is determined to be an access failure.
  • the request type of the access request sent by the first private cache to the second private cache can be determined based on the identification information on the subsidiary identification bit in the target subsidiary information, and then the access status of the access request sent by the first private cache to the second private cache can be determined.
  • the access request initiated by the second private cache to the first private cache may include a read access request or a write access request.
  • the target access data block corresponding to the read access request does not exist in the first private cache that receives the read access request, or the corresponding target access data block is in an invalid state (INV) in the first private cache that receives the read access request, it can be determined that the read access request has not hit in the first private cache.
  • ISV invalid state
  • a read access request initiated by the second private cache to the first private cache is read invalidated in the first private cache, wherein, in response to the access request being a read access request and the read access request not hitting in the first private cache, it is determined that the first private cache read invalidates the read access request, the first private cache generates a read invalidation processing request corresponding to the read access request, and sends it as a first read invalidation processing request (ReqRead) to the shared cache.
  • ReqRead first read invalidation processing request
  • a write access request in a scenario where a write access request is initiated by the second private cache to the first private cache, in response to the target access data block corresponding to the write access request not existing in the first private cache that receives the write access request, or the corresponding target access data block in the first private cache that receives the write access request is in an invalid state (INV), or the corresponding target access data block in the first private cache that receives the write access request is in a shared state (SHD), it can be determined that the write access request does not hit in the first private cache.
  • ISV invalid state
  • SHD shared state
  • a write access request initiated by the second private cache to the first private cache is write-failed in the first private cache, wherein, in response to the access request being a write access request and the write access request not hitting in the first private cache, it is determined that the first private cache write-failed the write access request, the first private cache generates a write-failure processing request corresponding to the write access request, and sends it to the shared cache as a first write-failure processing request (ReqWrite).
  • the data to be stored may be stored in a shared cache and a first private cache at the same time.
  • the data in the shared cache needs to be replaced accordingly.
  • the shared cache After the shared cache receives the replacement request sent by the first private cache, in response to the replacement data block corresponding to the replacement request stored in the shared cache, the shared cache replaces the replacement data block corresponding to the replacement request, and generates a corresponding response and sends it to the processor core to which the corresponding first private cache belongs.
  • replacement processing can also be performed on the corresponding data stored in the next-level storage system of the shared cache.
  • the replacement data block corresponding to the replacement request in response to the absence of a replacement data block corresponding to the replacement request in the shared cache, is determined in the next-level storage system of the shared cache.
  • the next-level storage system performs replacement processing on the replacement data block corresponding to the replacement request, and generates a corresponding response and sends it to the processor core to which the corresponding first private cache belongs.
  • the first private cache that receives the corresponding response is the first private cache that has a data block that needs to be replaced and sends a replacement request to the shared cache.
  • the target subsidiary information of the target accessed data block in the subsidiary directory of the shared cache can be determined according to the relevant information of the target accessed data block.
  • target subsidiary information corresponding to the target access data block may be determined from the subsidiary directory according to relevant information of the processor core to which the first private cache belongs.
  • target subsidiary information corresponding to the target access data block in the subsidiary directory is determined according to identification information on the backup bit in the subsidiary directory.
  • identification information of the processor core to which the first private cache storing the target access data block belongs can be obtained and compared with identification information on the backup bit of the subsidiary directory. Based on the comparison result, corresponding subsidiary information is determined from the subsidiary directory and used as the target subsidiary information corresponding to the target access data block in the subsidiary directory.
  • target subsidiary information corresponding to the target access data block in the subsidiary directory is determined based on identification information on a corresponding owner bit in the subsidiary directory.
  • identification information of the processor core to which the first private cache storing the target access data block belongs can be obtained and compared with the identification information on the corresponding owner bit in the subsidiary directory. Based on the comparison result, the corresponding subsidiary information is determined from the subsidiary directory and used as the target subsidiary information corresponding to the target access data block in the subsidiary directory.
  • the shared cache responds to the invalidation processing request according to the target attachment information.
  • the shared cache may obtain relevant status information of the target access data block from the target attachment information, and respond to the invalidation processing request sent by the first private cache according to the relevant status information.
  • the shared cache can determine the target state of the target access data block based on the identification information on the relevant subsidiary identification bit in the target subsidiary information.
  • the shared cache can obtain the identification information on the valid bit and the target owner bit of the data block to be stored in the target subsidiary information to determine the target state of the target access data block.
  • the target state of the target access data block is determined to be valid and dirty (VALID-DIRTY).
  • the target owner bit identifying that the data block to be stored has an owner processor core, it can be determined that the data block to be stored in this scenario is a data block in the dirty state, and the target state of the target access data block can be marked as valid and dirty.
  • the shared cache responds to the invalidation request based on the target state.
  • the shared cache in response to the target state being valid and dirty (VALID-DIRTY), the shared cache generates a write-back request corresponding to the first read invalidation processing request, and sends it as a first write-back request (ReqWtbk) to the first private cache on the owner processor core corresponding to the target access data block.
  • the first private cache after the first private cache receives the first write back request, in response to identifying that a backup data block corresponding to the target access data block is stored in the second private cache, the first private cache generates a corresponding write back request and sends it to the second private cache as a third write back request (ReqWtbk request).
  • the second private cache adjusts the state of the backup data block stored in itself to the shared (SHD) state according to the third write-back request, and writes the adjusted backup data block back to the first private cache.
  • the second private cache After the second private cache completes the status adjustment of the backup data block and writes it back to the first private cache, it can mark the processor core where the first private cache, to which the target access data block with the adjusted status belongs, is located as the owner processor core of the target access data block adjusted to the shared state, and update it in the subsidiary directory of the shared cache.
  • the first private cache adjusts the status of its own stored target access data block to a shared status, and generates a corresponding write-back response, which is sent to the shared cache as a first write-back response (RespWtbk).
  • the shared cache in response to the target state being valid and dirty (VALID-DIRTY), the shared cache generates a write-back request corresponding to the first write invalidation processing request, and sends it as a first invalidation and write-back request (ReqINVWtbk) to the first private cache on the owner processor core corresponding to the target access data block.
  • the first private cache in response to identifying that a backup data block corresponding to the target access data block is stored in the second private cache, the first private cache generates a corresponding invalidate and write back request and sends it to the second private cache as a second invalidate and write back request (ReqINVWtbk).
  • the second private cache After receiving the second invalidation and write-back request, the second private cache adjusts the backup data block to an invalid state according to the second invalidation and write-back request, and writes the adjusted backup data block back to the first private cache.
  • the first private cache adjusts the target access data block to an invalid state and generates a corresponding invalidation and write-back response, which is sent to the shared cache as a first invalidation and write-back response (RespINVWtbk).
  • the target state of the target access data block is determined to be valid and clean (VALID-CLEAN).
  • the target owner bit indicating that the data block to be stored does not have an owner processor core, it can be determined that the data block to be stored in this scenario is a data block in a clean state, and the target state of the target access data block can be marked as valid and clean.
  • the shared cache responds to the invalidation request based on the target state.
  • the shared cache in response to the target state being valid and clean (VALID-CLEAN), the shared cache generates a write-back request corresponding to the first read invalidation processing request, and sends it as a second write-back request (ReqWtbkFwd) to the first private cache on any backup processor core corresponding to the target access data block.
  • the first private cache that receives the second write-back request may send the data in the target access data block to the shared cache.
  • the shared cache in response to the target state being valid and clean (VALID-CLEAN), the shared cache generates an invalidation request corresponding to the first write invalidation processing request, and sends it as a first invalidation request (ReqINV) to the first private caches on all backup processor cores corresponding to the target access data block.
  • ReqINV first invalidation request
  • the first private cache after receiving the first invalidation request, identifies whether a backup data block of the target access data block is stored in its corresponding second private cache, wherein, in response to identifying that the backup data block of the target access data block is stored in the second private cache, the first private cache generates a corresponding invalidation request and sends it to the second private cache as a second invalidation request (ReqINV).
  • the second private cache After the second private cache receives the second invalidation request, the second private cache adjusts the backup data block to an invalid state according to the second invalidation request. state, and writes the adjusted backup data block back to the first private cache.
  • the first private cache adjusts the target access data block to an invalid state and generates a corresponding invalidation response, which is sent to the shared cache as a first invalidation response (RespINV).
  • the shared cache may also respond to the invalidation processing request received from the first private cache according to the relevant information indicated by the target attachment information corresponding to the target access data block.
  • the first read invalidation processing request in response to the shared cache receiving the first read invalidation processing request sent by the first private cache, the first read invalidation processing request may be responded to according to the relevant information indicated by the target subsidiary information.
  • the shared cache in response to the target attachment information indicating that the target access data block does not exist in the first private cache, after obtaining the data corresponding to the target access data block, the shared cache generates a corresponding read invalidation response (RespRead) and sends it to the first private cache that issued the first read invalidation processing request.
  • RespRead read invalidation response
  • the shared cache in response to the target attachment information indicating that the target access data block in the first private cache is in a dirty state, after the shared cache receives the first write-back response, it generates a corresponding read invalidation response (RespRead) and sends it to the first private cache that issued the first read invalidation processing request.
  • RespRead read invalidation response
  • the first write-invalidation processing request in response to the shared cache receiving the first write-invalidation processing request sent by the first private cache, the first write-invalidation processing request may be responded to according to the relevant information indicated by the target subsidiary information.
  • the shared cache in response to the target attachment information indicating that the target access data block does not exist in the first private cache, after obtaining the data corresponding to the target access data block, the shared cache generates a corresponding write invalidation response and sends it to the first private cache that issued the first write invalidation processing request.
  • the shared cache in response to the target attachment information indicating that the target access data block in the first private cache is valid and clean, after the shared cache receives the first invalidation response, it generates a corresponding write invalidation response and sends it to the first private cache that issued the first write invalidation processing request.
  • the shared cache in response to the target attachment information indicating that the target access data block in the first private cache is valid and clean, after the shared cache receives the first invalidation and write-back response, it generates a corresponding write-failure response and sends it to the first private cache that issued the first write-failure processing request.
  • the access method of the multi-level cache system proposed in the embodiment of the present disclosure is that in response to the access request initiated by the second private cache in the multi-level cache system to the first private cache, the access is invalid in the first private cache, and the first private cache can initiate an invalidation processing request to the shared cache.
  • the shared cache determines the corresponding target subsidiary information in the subsidiary directory according to the target access data block corresponding to the access request, and generates a relevant response to the invalidation processing request according to the identification information in the target subsidiary information, and returns it to the first private cache that initiated the invalidation processing request.
  • the access in response to the access request of the second private cache to the first private cache, the access is invalid, and the invalidation processing request sent by the first private cache to the shared cache enables the shared cache to respond to the invalidation processing request through the subsidiary directory maintained in its tag domain, thereby enabling the first private cache to respond to the second private cache, realizing exception processing in abnormal access scenarios, improving the stability of the multi-level cache system, and obtaining the post-write information of the target access data block on multiple processor cores through access to the subsidiary directory, optimizing the access method of the multi-level cache system, improving access efficiency, and optimizing access results.
  • Figure 12 is a flow chart of an access method of a multi-level cache system according to another embodiment of the present disclosure. As shown in Figure 12, the method includes: S1201-S1202.
  • identification information of the subsidiary information in the subsidiary directory in the tag field of the shared cache may not match the actual post-write information in the multi-level cache system.
  • the target access data block that the access request needs to access is indicated by the target subsidiary information corresponding to the subsidiary directory, and the target access data block does not exist in the first private cache of the multi-level cache system. It can be understood that there is a difference between the information in the subsidiary directory in the current shared cache and the post-write information of the data in the multi-level cache system. Therefore, the information in the subsidiary directory needs to be updated.
  • the replacement policy corresponding to the subsidiary directory of the shared cache may be obtained, and the relevant information of the subsidiary directory may be updated according to the corresponding replacement policy.
  • the corresponding tag corresponding data block in the first private cache is valid and In the clean state, in this scenario, it can be understood that the data block is a clean data block in the multi-level cache system. Therefore, if the data block has a corresponding owner processor core, the shared cache generates a corresponding invalidation request and uses it as the third invalidation request, and sends the third invalidation request to the first private cache on the owner processor core corresponding to the data block.
  • the state of the corresponding data block stored in the first private cache on the owner processor core is adjusted to invalid to ensure that the data block is in a clean state in the multi-level cache system.
  • a data block corresponding to a corresponding tag in the first private cache is valid and dirty.
  • the data block is a dirty data block in a multi-level cache system.
  • the backup data stored in the first private cache on the non-owner processor core corresponding to the data block needs to be invalidated, wherein the shared cache can generate a corresponding invalidation request and send it as a fourth invalidation request to the first private cache on the non-owner processor core corresponding to the data block.
  • the state of a corresponding data block stored in a first private cache on a non-owner processor core is adjusted to invalid, so as to ensure that the data block is in a dirty state in the multi-level cache system.
  • a data block corresponding to a corresponding tag in the first private cache is in a valid and dirty state.
  • the data block is a data block having an owner processor core in a multi-level cache system.
  • the shared cache can also generate a corresponding invalidate and write back request, and send it as a third invalidate and write back request to the first private cache on the owner processor core corresponding to the data block corresponding to the tag, or to the first private cache on the backup processor core that exclusively owns the data block corresponding to the tag.
  • the shared cache in response to the shared cache storing a backup data block corresponding to the data block corresponding to the tag, and the identification information of the updated auxiliary information does not match the post-write information of the data block corresponding to the tag in the first private cache, the shared cache needs to perform corresponding replacement processing on the related data stored in itself, wherein the shared cache can replace the backup data blocks stored in the data domain in its own data storage array.
  • the access method of the multi-level cache system proposed in the embodiment of the present disclosure responds to the indication in the identification information of the target subsidiary information corresponding to the target access data block that the relevant information of the corresponding target access data block does not exist in the first private cache, and it is necessary to update the subsidiary directory of the shared cache, obtain the updated subsidiary directory, and update the information of the first private cache according to the updated subsidiary information in the updated subsidiary directory.
  • the stability of the multi-level cache system is improved, the access method of the multi-level cache system is optimized, the access efficiency is improved, and the access results are optimized.
  • an embodiment of the present disclosure also proposes an access device for the multi-level cache system. Since the access device for the multi-level cache system proposed in the embodiment of the present disclosure corresponds to the access methods for the multi-level cache system proposed in the above-mentioned embodiments, the implementation methods of the access methods for the multi-level cache system are also applicable to the access device for the multi-level cache system proposed in the embodiment of the present disclosure, and will not be described in detail in the following embodiments.
  • FIG. 13 is a schematic diagram of the structure of an access device of a multi-level cache system according to an embodiment of the present disclosure.
  • the access device 1300 of the multi-level cache system includes an acquisition module 131, an access module 132, and a response module 133, wherein:
  • An acquisition module 131 is used to acquire an access request of a multi-level cache system
  • the access module 132 is used to obtain, according to the access request, a target access data block of the access request in the multi-level cache system and target attachment information of the target access data block from an attachment directory of the multi-level cache system, wherein the attachment directory is stored in a shared cache in the multi-level cache system;
  • the response module 133 is used to respond to the access request according to the target attached information.
  • the response module 133 is further used to: determine the access status of the access request according to the target attached information; and the shared cache responds to the access request in the access status.
  • the subsidiary directory is stored in a tag field on a shared cache in a multi-level cache system.
  • the response module 133 is further used to: obtain an access request sent by the first private cache to the second private cache in the multi-level cache system, wherein the first private cache and the second private cache are private caches of a multi-core processor, and each processor core in the multi-core processor includes at least one first private cache and/or at least one second private cache; determine, in the subsidiary directory of the shared cache, subsidiary information corresponding to a target access data block of the access request in the multi-level cache system as target subsidiary information; obtain subsidiary information on the subsidiary identification bit of the target subsidiary information, and obtain the access status of the access request based on the subsidiary information on the subsidiary identification bit.
  • the response module 133 is further configured to: in response to the target auxiliary information indication, the first private cache responds to the second private cache The access request sent by the storage does not hit in the first private cache, and the access status of the access request is determined to be access failure.
  • the response module 133 is also used for: in response to the access status of an access request sent by a first private cache to a second private cache in a multi-level cache system being access invalid, the first private cache sends an invalidation processing request to a shared cache in the multi-level cache system; and the shared cache responds to the invalidation processing request based on the target attached information.
  • the response module 133 is further used for: in response to an access request being a read access request and the read access request not hitting the first private cache, determining that the first private cache has read-failed the read access request, the first private cache generating a first read-failure processing request corresponding to the read access request, and sending it to the shared cache; in response to an access request being a write access request and the write access request not hitting the first private cache, determining that the first private cache has write-failed the write access request, the first private cache generating a first write-failure processing request corresponding to the write access request, and sending it to the shared cache.
  • the response module 133 is further used for: in response to the target subsidiary information indicating that the target access data block does not exist in the first private cache, after obtaining the data corresponding to the target access data block, the shared cache generates a corresponding read invalidation response, and sends it to the first private cache that issued the first read invalidation processing request; or, in response to the target subsidiary information indicating that the target access data block in the first private cache is in a dirty state, after receiving the first write back response, the shared cache generates a corresponding read invalidation response, and sends it to the first private cache that issued the first read invalidation processing request.
  • the response module 133 is further used for: in response to the target subsidiary information indicating that the target access data block does not exist in the first private cache, after obtaining the data corresponding to the target access data block, the shared cache generates a corresponding write-invalidation response, and sends it to the first private cache that issued the first write-invalidation processing request; or, in response to the target subsidiary information indicating that the target access data block in the first private cache is valid and clean, after the shared cache receives the first invalidation response, it generates a corresponding write-invalidation response, and sends it to the first private cache that issued the first write-invalidation processing request; or, in response to the target subsidiary information indicating that the target access data block in the first private cache is valid and clean, after the shared cache receives the first invalidation response, it generates a corresponding write-invalidation response, and sends it to the first private cache that issued the first write-invalidation processing request.
  • the response module 133 is further configured to: in response to a data block in the first private cache being replaced, the first private cache sends a replacement request to the shared cache.
  • the response module 133 is also used for: in response to the shared cache storing a replacement data block corresponding to the replacement request, the shared cache performs replacement processing on the replacement data block corresponding to the replacement request, and generates a corresponding response and sends it to the processor core to which the corresponding first private cache belongs; in response to the shared cache not having the replacement data block corresponding to the replacement request, in the next-level storage system of the shared cache, determining the replacement data block corresponding to the replacement request, the next-level storage system performs replacement processing on the replacement data block corresponding to the replacement request, and generates a corresponding response and sends it to the processor core to which the corresponding first private cache belongs.
  • the access module 132 is further used to: in response to the processor core to which the first private cache belongs being the backup processor core of the target access data block, determine the target subsidiary information corresponding to the target access data block in the subsidiary directory according to the identification information on the backup bit in the subsidiary directory; in response to the processor core to which the first private cache belongs being the owner processor core of the target access data block, determine the target subsidiary information corresponding to the target access data block in the subsidiary directory according to the identification information on the corresponding owner bit in the subsidiary directory.
  • the response module 133 is also used for: the shared cache obtains identification information on the valid bit of the data block to be stored and the target owner bit in the target subsidiary information, and determines the target state of the target access data block; the shared cache responds to the invalidation processing request according to the target state.
  • the response module 133 is further used to: in response to the valid bit of the data block to be stored being marked as valid, and the target owner bit being marked as the existence of an owner processor core state of the data block to be stored, determine that the target state of the target access data block is valid and dirty; in response to the valid bit of the data block to be stored being marked as valid, and the target owner bit being marked as the existence of an owner processor core state of the data block to be stored, determine that the target state of the target access data block is valid and clean.
  • the response module 133 is also used for: in response to the target state being valid and dirty, the shared cache generates a first write-back request corresponding to the first read invalidation processing request, and sends it to the first private cache on the owner processor core corresponding to the target access data block; in response to the target state being valid and clean, the shared cache generates a second write-back request corresponding to the first read invalidation processing request, and sends it to the first private cache on any backup processor core corresponding to the target access data block.
  • the response module 133 is further used to: in response to identifying that the backup data block corresponding to the target access data block is stored in the second private cache, the first private cache generates a third write-back request and sends it to the second private cache; according to the third write-back request, the second private cache adjusts the backup data block to a shared state, and writes the adjusted backup data block back to the first private cache; the first private cache adjusts the target access data block to the shared state, and writes the adjusted backup data block back to the first private cache; The tag accesses the data block to a shared state.
  • the response module 133 is further used to: mark the processor core where the first private cache to which the target access data block whose state is adjusted belongs is located as the owner processor core of the target access data block adjusted to the shared state, and update it in the subsidiary directory of the shared cache.
  • the response module 133 is further configured to: the first private cache sends the data in the target access data block to the shared cache.
  • the response module 133 is also used for: in response to the target state being valid and dirty, the shared cache generates a first invalidation and write-back request corresponding to the first write invalidation processing request, and sends it to the first private cache on the owner processor core corresponding to the target access data block; in response to the target state being valid and clean, the shared cache generates a first invalidation request corresponding to the first write invalidation processing request, and sends it to the first private cache on all backup processor cores corresponding to the target access data block.
  • the response module 133 is also used for: in response to identifying that the backup data block corresponding to the target access data block is stored in the second private cache, the first private cache generates a second invalidation and write-back request and sends it to the second private cache; according to the second invalidation and write-back request, the second private cache adjusts the backup data block to an invalid state, and writes the adjusted backup data block back to the first private cache; the first private cache adjusts the target access data block to an invalid state, and generates a first invalidation and write-back response and sends it to the shared cache.
  • the response module 133 is further used for: in response to identifying that a backup data block of the target access data block is stored in the second private cache, the first private cache generates a second invalidation request and sends it to the second private cache; according to the second invalidation request, the second private cache adjusts the backup data block to an invalid state, and writes the adjusted backup data block back to the first private cache; the first private cache adjusts the target access data block to an invalid state, and generates a first invalidation response and sends it to the shared cache.
  • the response module 133 is further configured to: the first private cache on the owner processor core sends the data in the target access data block to the shared cache.
  • the response module 133 is also used to: in response to the target subsidiary information indicating that the target access data block does not exist in the first private cache of the multi-level cache system, obtain the replacement strategy of the subsidiary directory of the shared cache, and update the subsidiary directory of the shared cache according to the replacement strategy; and update the first private cache according to the updated subsidiary information in the updated subsidiary directory.
  • the response module 133 is further used for: in response to an indication of updating the subsidiary information, the data block corresponding to the subsidiary information in the first private cache is valid and in a clean state, the shared cache generates a third invalidation request, and sends the third invalidation request to the first private cache on the owner processor core corresponding to the data block corresponding to the subsidiary information; in response to an indication of updating the subsidiary information, the data block corresponding to the subsidiary information in the first private cache is valid and in a dirty state, the shared cache generates a fourth invalidation request, and sends the fourth invalidation request to the first private cache on the non-owner processor core corresponding to the data block corresponding to the subsidiary information.
  • the response module 133 is also used for: in response to an indication of updating the subsidiary information, the data block corresponding to the subsidiary information in the first private cache is valid and dirty, the shared cache generates a third invalidation and write-back request, and sends the third invalidation and write-back request to the first private cache on the owner processor core corresponding to the data block corresponding to the subsidiary information, or, sends it to the first private cache on the backup processor core that exclusively owns the data block corresponding to the subsidiary information.
  • the response module 133 is also used for: in response to the shared cache storing a backup data block corresponding to the data block corresponding to the subsidiary information, and the identification information of the updated subsidiary information does not match the post-write information of the data block corresponding to the subsidiary information in the first private cache, the shared cache replaces the backup data block stored in the data domain in its own data storage array.
  • the access device of the multi-level cache system proposed in the embodiment of the present disclosure obtains the access request of the multi-level cache system, and reads the subsidiary directory stored on the shared cache in the multi-level cache system according to the access request, so as to obtain the target access data block corresponding to the access request in the multi-level cache system and the target subsidiary information corresponding to the target access data block.
  • the access request is responded to according to the target subsidiary information.
  • a subsidiary directory on the shared cache of the multi-level cache system which realizes the effective management of the data blocks stored in the multi-level cache system, obtains the target subsidiary information corresponding to the target access data block corresponding to the access request by reading the subsidiary directory, and responds to the access request according to the target subsidiary information, which simplifies the method for obtaining the response information corresponding to the access request, thereby reducing the load degree caused by responding to the access request on the multi-level cache system, improving the stability of the performance of the multi-level cache system, thereby reducing the access delay of the access request, optimizing the access method of the multi-level cache system, improving the access efficiency of the multi-level cache system, and saving the resources of the multi-level cache system.
  • an embodiment of the present disclosure further proposes a data storage device of the multi-level cache system.
  • the data storage method for the multi-level cache system proposed in the example corresponds to the data storage method for the multi-level cache system, so the implementation method of the above-mentioned data storage method for the multi-level cache system is also applicable to the data storage device for the multi-level cache system proposed in the embodiment of the present disclosure, and will not be described in detail in the following embodiments.
  • FIG14 is a schematic diagram of the structure of an access device of a multi-level cache system according to an embodiment of the present disclosure.
  • a data storage device 1400 of a multi-level cache system includes a first writing module 141 and a second writing module 142, wherein:
  • a first writing module 141 is used to write the data to be stored into the multi-level cache system and obtain the post-writing information of the data to be stored in the multi-level cache system;
  • the second writing module 142 is used to generate subsidiary information corresponding to the written information of the data to be stored, and write the subsidiary information into a subsidiary directory of the multi-level cache system, wherein the subsidiary directory is stored in a shared cache in the multi-level cache system.
  • a multi-level cache system includes a shared cache, a first private cache, and a second private cache.
  • the shared cache is a shared cache in a multi-core processor to which the multi-level cache system belongs, and the first private cache and the second private cache are private caches of the multi-core processor; wherein each processor core in the multi-core processor includes at least one first private cache and/or at least one second private cache.
  • the subsidiary directory is stored in a tag field on a shared cache in a multi-level cache system.
  • the multi-level cache system includes a first private cache, wherein the first private cache is a shared cache of some processor cores in a multi-core processor to which the multi-level cache system belongs.
  • the second writing module 142 is also used to: obtain the subsidiary identification bit in the initial subsidiary information of the shared cache; obtain the identification information of the data to be stored in the subsidiary identification bit from the written information, and mark the identification information to the corresponding subsidiary identification bit to generate the subsidiary information of the data to be stored.
  • the second write module 142 is further used for: writing an address bit, used to indicate the write address of a data block storing data to be stored; an address valid bit, used to indicate whether the write address of the stored data block is valid; a first valid bit, used to indicate whether a first data block stored in a shared cache is valid, wherein the first data block is a data block storing data to be stored in the shared cache; a first status bit, used to indicate whether the data to be stored has been written in the shared cache; and a data domain row number bit, used to indicate the storage row number of the first data block in the data domain of the data storage array of the shared cache.
  • the second write module 142 is also used for: a second valid bit, used to indicate whether the second data block stored in the first private cache is valid, wherein the second data block is a data block storing data to be stored in the first private cache; a second status bit, used to indicate the second data status of the second data block in all first private caches of the multi-core processor, wherein the second data status is an exclusive status (EXC) or a shared status (SHD); a backup bit, used to indicate a backup processor core in the multi-core processor that stores a backup data block of the second data block; a first owner bit, used to indicate whether there is an owner processor core of the second data block in the multi-core processor; and a second owner bit, used to indicate the owner processor core of the second data block in the multi-core processor.
  • EXC exclusive status
  • SHD shared status
  • the second writing module 142 is also used to: determine a target cache in a multi-level cache system, into which the data to be stored is written; obtain target identification information corresponding to the initial subsidiary information of the shared cache according to the target cache; and write the target subsidiary information in the subsidiary directory in response to generating the data to be stored in the target cache according to the target identification information.
  • the second writing module 142 is further used to: in response to the data to be stored being stored in the shared cache, obtain the first identification information corresponding to the initial subsidiary information.
  • the second writing module 142 is further used to: in response to marking the first identification information to the subsidiary identification bit to generate the data to be stored in the shared cache, write the first subsidiary information in the subsidiary directory of the shared cache.
  • the second writing module 142 is further used to: in response to the data to be stored being written into the first private cache, obtain the second identification information of the initial subsidiary information.
  • the second writing module 142 is further used to: in response to marking the second identification information to the subsidiary identification bit, generate the data to be stored and store it in the first private cache, and write the second subsidiary information in the subsidiary directory of the shared cache.
  • the second writing module 142 is further used to: in response to the data to be stored being written into the shared cache and the first private cache, obtain the third identification information of the initial subsidiary information.
  • the second writing module 142 is further used to: in response to marking the third identification information to the subsidiary identification bit to generate data to be stored in the shared cache and the first private cache, write the third subsidiary information in the subsidiary directory of the shared cache.
  • the second writing module 142 is also used to: in response to the data to be stored being stored in the shared cache, obtain the subsidiary information path number and the subsidiary information row number in the subsidiary directory; write the subsidiary information path number and the subsidiary information row number into the information field of the data storage array of the shared cache.
  • the second writing module 142 is also used to: in response to the absence of a corresponding row in the subsidiary directory for writing the subsidiary information corresponding to the data to be stored, obtain a first replacement strategy for the subsidiary directory; determine the first replacement information in the subsidiary directory according to the first replacement strategy, delete the first replacement information and write the subsidiary information into the corresponding row of the first replacement information, and synchronously delete the data block corresponding to the first replacement information.
  • the second writing module 142 is further used to: obtain a second replacement strategy of the shared cache in response to the fact that there is no corresponding location for storing the first data block of data to be stored in the data domain of the data storage array of the shared cache; determine the second replacement data block in the data domain according to the second replacement strategy, store the first data block to the second replacement location to which the second replacement data block belongs, and delete the second replacement data block at the second replacement location; determine the second replacement information corresponding to the second replacement data block in the subsidiary directory; determine the corresponding row in the subsidiary directory where the second replacement information is deleted, and write the subsidiary information corresponding to the first data block into the corresponding row deleted.
  • the second writing module 142 is also used to: obtain the replacement subsidiary information row number and the replacement subsidiary information path number of the second replacement information corresponding to the second replacement data block from the information domain of the data storage array; and determine the second replacement information from the subsidiary directory of the shared cache according to the replacement subsidiary information row number and the replacement subsidiary information path number.
  • the data storage device of the multi-level cache system proposed in the embodiment of the present disclosure obtains the post-write information of the data to be stored in the multi-level cache system, generates the subsidiary information corresponding to the data to be stored according to the post-write information, and writes it into the subsidiary directory of the shared cache used for sharing in the multi-level cache system.
  • the subsidiary information corresponding to the post-write information of the data to be stored in the multi-level cache system is generated, and written into the subsidiary directory of the shared cache in the multi-level cache system, so that the post-write information of the data to be stored in the multi-level cache system can be obtained by reading the subsidiary directory in the tag field of the shared cache, which simplifies the method for obtaining the post-write information of the data to be stored, improves the efficiency of obtaining the post-write information of the data to be stored in the multi-level cache system, saves the resources for directory maintenance in the multi-level cache system, realizes the scalability of the directory in the multi-level cache system, and optimizes the performance of the multi-level cache system.
  • the embodiments of the present disclosure also propose an electronic device 1500, as shown in Figure 15, the electronic device 1500 may specifically include: a memory 1501, a processor 1502, and a computer program stored in the memory 1501 and executable on the processor 1502.
  • the processor 1502 executes the program, it implements the data storage method of the multi-level cache system or the access method of the multi-level cache system as shown in the above embodiments.
  • the embodiments of the present disclosure also propose a computer-readable storage medium on which a computer program is stored.
  • the program is executed by a processor to implement a data storage method of a multi-level cache system or an access method of a multi-level cache system as shown in the above embodiments.
  • the embodiments of the present disclosure also propose a computer program product, including a computer program, which, when executed by a processor, implements the data storage method of the multi-level cache system or the access method of the multi-level cache system as shown in the above embodiments.
  • the embodiments of the present disclosure also propose a computer program, including computer program code.
  • the computer program code runs on a computer, the computer executes the data storage method of the multi-level cache system or the access method of the multi-level cache system as shown in the above embodiments.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more, unless otherwise clearly and specifically defined.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

L'invention concerne un procédé d'accès pour un système de mémoire cache multiniveau. Le procédé d'accès pour un système de mémoire cache multiniveau comprend les étapes consistant à : acquérir une demande d'accès d'un système de mémoire cache multiniveau ; lire un répertoire affilié du système de mémoire cache multiniveau selon la demande d'accès, le répertoire affilié étant stocké dans une mémoire cache partagée dans le système de mémoire cache multiniveau ; selon le répertoire affilié, acquérir un bloc de données d'accès cible de la demande d'accès dans le système de mémoire cache multiniveau et des informations affiliées cibles du bloc de données d'accès cible ; et répondre à la demande d'accès selon les informations affiliées cibles. L'invention concerne en outre un appareil d'accès, et un procédé et un appareil de stockage de données pour un système de mémoire cache multiniveau, ainsi qu'un dispositif électronique, un support de stockage, un produit de programme informatique et un programme informatique.
PCT/CN2023/104895 2022-09-28 2023-06-30 Procédé et appareil d'accès et procédé et appareil de stockage de données pour système de mémoire cache multiniveau WO2024066613A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211190657.XA CN115328820B (zh) 2022-09-28 2022-09-28 多级缓存系统的访问方法、数据存储方法及装置
CN202211190657.X 2022-09-28

Publications (1)

Publication Number Publication Date
WO2024066613A1 true WO2024066613A1 (fr) 2024-04-04

Family

ID=83913860

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/104895 WO2024066613A1 (fr) 2022-09-28 2023-06-30 Procédé et appareil d'accès et procédé et appareil de stockage de données pour système de mémoire cache multiniveau

Country Status (2)

Country Link
CN (1) CN115328820B (fr)
WO (1) WO2024066613A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115328820B (zh) * 2022-09-28 2022-12-20 北京微核芯科技有限公司 多级缓存系统的访问方法、数据存储方法及装置
CN117093511B (zh) * 2023-09-04 2024-05-10 海光云芯集成电路设计(上海)有限公司 访存控制方法、访存控制装置、芯片及电子设备
CN117472802B (zh) * 2023-12-28 2024-03-29 北京微核芯科技有限公司 高速缓存访问方法、处理器、电子设备及存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180181490A1 (en) * 2016-12-27 2018-06-28 Eta Scale Ab System and method for self-invalidation, self-downgrade cachecoherence protocols
CN112416615A (zh) * 2020-11-05 2021-02-26 珠海格力电器股份有限公司 多核处理器及其缓存一致性的实现方法、装置和存储介质
CN113342709A (zh) * 2021-06-04 2021-09-03 海光信息技术股份有限公司 在多处理器系统中访问数据的方法和多处理器系统
CN114036084A (zh) * 2021-11-17 2022-02-11 海光信息技术股份有限公司 一种数据访问方法、共享缓存、芯片系统和电子设备
CN115328820A (zh) * 2022-09-28 2022-11-11 北京微核芯科技有限公司 多级缓存系统的访问方法、数据存储方法及装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8271898B1 (en) * 2009-06-04 2012-09-18 Mellmo Inc. Predictive scrolling
CN103955435B (zh) * 2014-04-09 2017-01-11 上海理工大学 一种融合多级缓存目录建立访问方法
CN104317736B (zh) * 2014-09-28 2017-09-01 曙光信息产业股份有限公司 一种分布式文件系统多级缓存实现方法
CN105677580B (zh) * 2015-12-30 2019-04-12 杭州华为数字技术有限公司 访问缓存的方法和装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180181490A1 (en) * 2016-12-27 2018-06-28 Eta Scale Ab System and method for self-invalidation, self-downgrade cachecoherence protocols
CN112416615A (zh) * 2020-11-05 2021-02-26 珠海格力电器股份有限公司 多核处理器及其缓存一致性的实现方法、装置和存储介质
CN113342709A (zh) * 2021-06-04 2021-09-03 海光信息技术股份有限公司 在多处理器系统中访问数据的方法和多处理器系统
CN114036084A (zh) * 2021-11-17 2022-02-11 海光信息技术股份有限公司 一种数据访问方法、共享缓存、芯片系统和电子设备
CN115328820A (zh) * 2022-09-28 2022-11-11 北京微核芯科技有限公司 多级缓存系统的访问方法、数据存储方法及装置

Also Published As

Publication number Publication date
CN115328820A (zh) 2022-11-11
CN115328820B (zh) 2022-12-20

Similar Documents

Publication Publication Date Title
WO2024066613A1 (fr) Procédé et appareil d'accès et procédé et appareil de stockage de données pour système de mémoire cache multiniveau
KR102193689B1 (ko) 예측에 기초하여 효율적으로 캐시 라인을 관리하는 시스템 및 방법
US8307149B2 (en) Nonvolatile memory device including a logical-to-physical logig-to-physical address conversion table, a temporary block and a temporary table
KR100389867B1 (ko) 플래시 메모리 관리방법
US7761655B2 (en) Storage system and method of preventing deterioration of write performance in storage system
US6901483B2 (en) Prioritizing and locking removed and subsequently reloaded cache lines
US8745334B2 (en) Sectored cache replacement algorithm for reducing memory writebacks
US8291175B2 (en) Processor-bus attached flash main-memory module
CN110321301B (zh) 一种数据处理的方法及装置
CN106201335B (zh) 存储系统
JP2017151982A (ja) データストレージサブシステムにおけるキャッシングのための方法およびシステム
WO2013123855A1 (fr) Procédé de commande de lecture-écriture pour mémoire et mémoire et serveur correspondants
JP3866447B2 (ja) マルチプロセッサ・ノードデータ処理システムに使用するディレクトリエントリ割当てシステム及び方法
KR101779174B1 (ko) 저널링 파일시스템의 데이터 폐기 방법 및 이를 구현하기 위한 메모리 관리 장치
CN107341114B (zh) 一种目录管理的方法、节点控制器和系统
US8977816B2 (en) Cache and disk management method, and a controller using the method
CN111488125A (zh) 一种基于Ceph集群的Cache Tier缓存优化方法
KR20110046118A (ko) 적응적 로깅 장치 및 방법
CN111443874B (zh) 基于内容感知的固态盘内存缓存管理方法、设备及固态盘
US6298419B1 (en) Protocol for software distributed shared memory with memory scaling
CN110968266B (zh) 一种基于热度的存储管理方法及系统
KR102220468B1 (ko) 트랜잭션 지원을 가진 선점형 캐시 후기록
CN116755625A (zh) 一种数据处理方法、装置、设备及可读存储介质
CN113656396A (zh) 非统一内存访问架构下的持久性内存索引构建方法
US7979638B2 (en) Method and system for accessing data using an asymmetric cache device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23869861

Country of ref document: EP

Kind code of ref document: A1