WO2024066451A1

WO2024066451A1 - Semiconductor structure and formation method therefor

Info

Publication number: WO2024066451A1
Application number: PCT/CN2023/098374
Authority: WO
Inventors: 杨蒙蒙; 唐怡
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-09-30
Filing date: 2023-06-05
Publication date: 2024-04-04
Also published as: CN117881177A

Abstract

Provided in the embodiments of the present disclosure are a semiconductor structure and a formation method therefor. The method comprises: providing a plurality of first staircase structures, which are arranged at intervals in a first direction and have different sizes in a third direction; etching the first staircase structures multiple times in a second direction, so as to form, in each first staircase structure, a plurality of second staircase structures sequentially stacked in the third direction, wherein, in the first staircase structure, the sizes of the second staircase structures in the first direction sequentially decrease in the third direction from bottom to top.

Description

Semiconductor structure and method of forming the same

CROSS-REFERENCE TO RELATED APPLICATIONS

This disclosure is based on the Chinese patent application with application number 202211215462.6, application date September 30, 2022, and invention name “Semiconductor structure and method for forming the same”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this disclosure as a reference.

Technical Field

The embodiments of the present disclosure relate to, but are not limited to, a semiconductor structure and a method for forming the same.

Background technique

At present, staircase structures are usually used to assist in realizing the stacking structure of three-dimensional semiconductor devices to improve the integration of semiconductor devices. However, for stacked three-dimensional semiconductor devices, both the bit line (BL) staircase structure and the word line (WL) staircase structure face a large coupling problem.

Summary of the invention

Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method comprising:

Providing an active area and a first step area and a second step area respectively located on both sides of the active area along a first direction; the first step area and the second step area include a plurality of first step structures arranged at intervals along the first direction, and any two of the first step structures have different sizes in a third direction;

Etching the plurality of first step structures multiple times along the second direction to form a plurality of second step structures sequentially stacked along the third direction in each of the first step structures; from bottom to top along the third direction, the sizes of the second step structures in the first step structures in the first direction are sequentially reduced;

The first direction intersects with the second direction and is parallel to the plane where the active region is located, and the third direction is perpendicular to the plane where the active region is located.

In some embodiments, providing an active region and a first step region and a second step region respectively located on both sides of the active region along a first direction includes:

Providing a stacked structure; the stacked structure comprises the first step region and the second step region respectively located at both sides of the active region along the first direction; the first step region and the second step region comprise M initial step structures arranged at intervals along the first direction;

The M initial step structures are etched M-1 times along the first direction to form M first step structures; wherein the size of the first step structure in the third direction increases or decreases sequentially; the i-th etching exposes i initial step structures, i=1, 2..., M-1.

In some embodiments, the projection area of the stacked structure along the third direction is comb-tooth shaped; the second step structures located at the connection ends of each first step structure in the first step region are interconnected in the projection area along the third direction and connected to the active area; the second step structures located at the connection ends of each first step structure in the second step region are interconnected in the projection area along the third direction and connected to the active area; the providing of the stacked structure includes:

Providing an initial stacked structure, wherein the initial stacked structure is located on both sides of the active area along the first direction;

forming a protective layer on the surface of the active area;

The initial stacked structure is etched to form the initial step structure and a U-shaped isolation groove located between two adjacent initial step structures and between the initial step structure and the active area.

In some embodiments, before forming the M first step structures, the method further includes:

An isolation structure is formed in the U-shaped isolation groove.

In some embodiments, etching the M initial step structures multiple times along the first direction to form the M first step structures includes:

A first photoresist layer is formed on the surfaces of the M initial step structures, the isolation structure and the protective layer;

Etching the initial step structure and the isolation structure M-1 times through the first photoresist layer to form the M first step structures and the etched isolation structure;

Before the i-th etching, the first photoresist layer used in the (i-1)-th etching process is trimmed along the first direction so that the first photoresist layer in the i-th etching process at least exposes the first i initial step structures in the first step structure.

In some embodiments, etching part of the initial step structure M-1 times through the first photoresist layer to form the M first step structures includes:

The i-th initial step structure in the initial step structures is etched M-i times in sequence along the first direction through the first photoresist layer to form the M first step structures; i=1, 2..., M-1.

In some embodiments, the second step structure is formed by the following steps:

Forming a second photoresist layer having a preset pattern on the surfaces of the M first step structures, the protective layer and the etched isolation structure; the preset pattern includes a plurality of sub-patterns arranged in sequence along a first direction;

Etching part of the first step structure and part of the etched isolation structure N-1 times through the second photoresist layer to form the second step structure and the remaining isolation structure;

Wherein, before the jth etching, the second photoresist layer used in the j-1th etching process is trimmed so that the size of the sub-pattern in the second photoresist layer in the jth etching process in the first direction is larger than the size of the sub-pattern in the second photoresist layer used in the j-1th etching process in the first direction, and the second photoresist layer in the jth etching process exposes at least the first j parts of each first step structure away from the connecting end along the second direction; j=1, 2…, N.

In some embodiments, the first stepped structure includes j parts sequentially arranged from right to left along the second direction, and the first stepped structure is etched N-1 times through the second photoresist layer to form the second stepped structure, including:

The j-th portion away from the connecting end is etched N-j times in sequence along the second direction to form the second step structure.

In some embodiments, after forming the second stepped structure, the method further includes:

The second photoresist layer and the protective layer are removed in sequence.

In some embodiments, after removing the protective layer, the method further comprises:

forming a dielectric layer on surfaces of the second stepped structure, the remaining isolation structure and the active area;

Etching the dielectric layer to form M×N etching holes, wherein each of the etching holes exposes one of the second step structures;

A conductive pillar is formed in the etched hole.

In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure comprising:

A first step region, a second step region, and an active region located between the first step region and the second step region arranged along a first direction;

The first step region and the second step region include a plurality of first step structures sequentially arranged along the first direction, and the first step structures are all connected to the active region; any two of the first step structures have different sizes in the third direction;

Each of the first step structures includes a plurality of second step structures stacked in sequence along the third direction;

Wherein, from bottom to top along the third direction, the size of the second step structure in the first direction decreases in sequence: The first direction is parallel to the plane where the active area is located, and the third direction is perpendicular to the plane where the active area is located.

In some embodiments, each of the first step structures includes N second step structures stacked sequentially along the third direction;

The i-th first step structure along the first direction includes the (i-1)×N+1-th second step structure to the i×N-th second step structure; each of the second step structures has a preset size in the third direction;

The difference in size between the top surface of the i-th first step structure along the first direction and the top surface of the (i-1)-th first step structure along the first direction in the third direction is N times the preset size; wherein i=1, 2…, M.

In some embodiments, the projection area of the first step structure along the third direction is comb-tooth shaped; the second step structures at the connecting ends of each first step structure in the first step area are interconnected along the projection area in the third direction and connected to the active area; the second step structures at the connecting ends of each first step structure in the second step area are interconnected along the projection area in the third direction and connected to the active area.

In some embodiments, the size of the jth second step structure in the second direction from bottom to top along the third direction is the same as or different from the size of the (j+1)th second step structure in the second direction;

The second direction is parallel to the plane where the active region is located, and intersects with the first direction.

In some embodiments, the semiconductor structure further includes an isolation structure;

The isolation structure is located between adjacent first stepped structures and between the first stepped structure and the active region.

In some embodiments, the semiconductor structure further includes a dielectric layer and a conductive pillar;

The dielectric layer is located on the surfaces of the first step structure, the isolation structure and the active area;

The conductive pillar is located in the dielectric layer and on the surface of each of the second stepped structures.

The semiconductor structure and the method for forming the same provided by the embodiments of the present disclosure have a second step structure formed along the third direction whose size in the first direction decreases from bottom to top, thereby making it possible to gradually reduce the effective area between adjacent second step structures along the third direction from bottom to top, thereby reducing the coupling effect between adjacent second step structures along the third direction and improving the performance of the semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

FIG1 is a schematic diagram of a process of forming a semiconductor structure according to an embodiment of the present disclosure;

2a to 2n are schematic diagrams of structures during the formation process of a semiconductor structure provided by an embodiment of the present disclosure.

Detailed ways

The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

In the following description, a large number of details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

In the drawings, the sizes of layers, regions, and elements as well as their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements.

It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and/or parts, these elements, components, regions, layers and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said/the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and/or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and/or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and/or groups. When used herein, the term "and/or" includes any and all combinations of the relevant listed items.

Before introducing the embodiments of the present disclosure, the three directions that may be used in the following embodiments to describe the three-dimensional structure are defined. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis and Z-axis directions. The active area may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, the direction intersecting (e.g., perpendicular) with the top surface and the bottom surface of the active area is defined as the third direction. In the directions of the top surface and the bottom surface of the active area (i.e., the plane where the active area is located), two directions intersecting (e.g., perpendicular to each other) are defined. For example, the direction in which the first step structure is arranged may be defined as the first direction, and the plane direction of the active area may be determined based on the second direction and the first direction. In the embodiments of the present disclosure, the first direction, the second direction and the third direction may be perpendicular to each other, for example, the first direction may be defined as the X-axis direction, the second direction may be defined as the Y-axis direction, and the third direction may be defined as the Z-axis direction. In other embodiments, the first direction, the second direction and the third direction may also be non-perpendicular.

The present disclosure provides a method for forming a semiconductor structure. FIG. 1 is a schematic flow chart of the method for forming a semiconductor structure provided by the present disclosure. FIG. 2a to FIG. 2n are schematic structural diagrams of the semiconductor structure during the formation process provided by the present disclosure. As shown in FIG. 1 and FIG. 2a to FIG. 2n, the method for forming a semiconductor structure includes the following steps:

Step S101, providing an active area 10 and a first step region A and a second step region B respectively located on both sides of the active area 10 along the first direction; the first step region A and the second step region B include a plurality of first step structures 18 arranged at intervals along the first direction, and the sizes of any two first step structures 18 in the third direction are different.

In some embodiments, a memory cell array including a transistor structure and a capacitor structure is formed in the active area 10, and the first step structure 18 located in the first step region A and the second step region B are both connected to the active area 10. The first step structure 18 is used to form a word line step or a bit line step connected to the memory cell array. In the embodiment of the present disclosure, the area size of the first step region A and the second step region B can be equal. In other embodiments, the area of the first step region A and the second step region B can also be different.

In the embodiment of the present disclosure, the number of first step structures 18 in the first step region A and the second step region B is equal. In other embodiments, the number of first step structures 18 in the first step region A and the second step region B may be unequal. It should be noted that the number of first step structures 18 may be determined according to the number of stacked layers of memory cells in the semiconductor structure, and the number of first step structures 18 may be any integer greater than 1, for example, 2, 3 or more.

In some embodiments, along the first direction, the size of the first step structure 18 in the third direction increases or decreases in sequence. In other embodiments, the size of the first step structure 18 in the third direction may also be arranged in any arrangement pattern, for example, along the first direction, the size of the first step structure 18 in the third direction first increases, then decreases, and then increases.

In the embodiment of the present disclosure, the first step structure 18 includes a conductive layer 111 and an insulating layer alternately arranged along the third direction. 112; the material of the conductive layer 111 can be any metal material of cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt) and palladium (Pd), or any semiconductor material of doped polysilicon, doped silicon, indium gallium zinc oxide, etc.; the material of the insulating layer 112 can be silicon oxide or silicon oxynitride. The insulating layer 112 is used to isolate the conductive layer 111 adjacent to each other along the third direction to prevent leakage.

Each conductive layer 111 in the first stepped structure 18 can be connected to a column (or a row) of word line structures 101 (or gate structures) in the active region 10 to form a word line step. Alternatively, each conductive layer 111 in the first stepped structure 18 can be connected to a row (or a column) of bit line structures 102 in the active region 10 to form a bit line step.

In the embodiment of the present disclosure, the first step structure 18 is located in the first step region A and the second step region B on both sides of the active area 10. Therefore, the conductive pillars 21 connected to each first step structure 18 and the wiring connected to the conductive pillars 21 can be respectively arranged on both sides of the active area 10.

In addition, since the sizes of any two adjacent first step structures 18 in the third direction are not equal, the connection heights of any two adjacent groups of conductive pillars 21 in the third direction can be different, thereby reducing the density of the conductive pillars 21 and wiring, and simplifying the conductive pillars 21 and wiring settings of the semiconductor structure.

In step S102, the plurality of first step structures 18 are etched multiple times along the second direction to form a plurality of second step structures 181 stacked sequentially along the third direction in each first step structure 18; along the third direction from bottom to top, the sizes of the second step structures 181 in the first step structures 18 in the first direction are reduced sequentially.

In some embodiments, the first stepped structure 18 includes j parts sequentially arranged from right to left along the second direction, and the first stepped structures 18 are etched multiple times along the second direction, including: etching the j-th part N-j times sequentially from right to left along the second direction to form a second stepped structure 181. Wherein, j=1, 2...N; N is the number of second stepped structures 181 formed in each first stepped structure 18.

For example, when j is equal to 3, the first step structure 18 includes three parts arranged in sequence from right to left along the second direction, the first part from right to left along the second direction is etched twice, and the second part from right to left along the second direction is etched once to form a second step structure 181. Wherein, from bottom to top along the third direction, the size of the third second step structure 181 in the first step structure 18 in the first direction is smaller than the size of the second second step structure 181 in the first direction; the size of the second second step structure 181 in the first step structure 18 in the first direction is smaller than the size of the first second step structure 181 in the first direction.

The method for forming a semiconductor structure provided by the embodiment of the present disclosure is that the size of the formed second step structure 181 in the first direction decreases from bottom to top along the third direction, so that the effective area between adjacent second step structures 181 along the third direction can be gradually reduced from bottom to top, thereby reducing the coupling effect between adjacent second step structures 181 along the third direction, ensuring the stability of the first step structure 18, and improving the performance of the semiconductor structure.

In addition, since the M first step structures 18 are arranged at intervals, the projection area of the entire step structure in the third direction can be reduced, thereby reducing the coupling effect between the step structures, thereby reducing signal crosstalk and improving the performance of the semiconductor structure.

The formation process of the semiconductor structure provided by the embodiment of the present disclosure is described in detail below with reference to FIGS. 2a to 2n.

First, referring to Figures 2a to 2j, step S101 is performed to provide an active area 10 and a first step area A and a second step area B respectively located on both sides of the active area 10 along the first direction; the first step area A and the second step area B include a plurality of first step structures 18 arranged at intervals along the first direction, and the sizes of any two first step structures 18 in the third direction are different.

In some embodiments, step S101 may include the following steps: providing a stacked structure 13; the stacked structure 13 includes a first step region A and a second step region B respectively located on both sides of the active area 10 along the first direction; the first step region A and the second step region B include M initial step structures 14 arranged at intervals along the first direction; the M initial step structures 14 are etched M-1 times along the first direction to form M first step structures 18; wherein the size of the first step structure 18 in the third direction increases or decreases sequentially; the i-th etching exposes i initial step structures 14, i=1, 2…, M-1.

In the embodiment of the present disclosure, the stacked structure 13 can be formed by the following steps:

An initial stacked structure 11 is provided, and the initial stacked structure 11 is located on both sides of the active area 10 along the first direction; A protection layer 12 is formed on the surface of 10; and the initial stacked structure 11 is etched to form an initial step structure 14 and a U-shaped isolation groove 15a located between two adjacent initial step structures 14 and between the initial step structure 14 and the active area 10.

In the embodiment of the present disclosure, the initial stacked structure 11 can be used to form a word line step or a bit line step.

As shown in FIG. 2a , the initial stacked structure 11 is located on both sides of the active region 10 along the X-axis direction and is connected to the word line structure 101 (or gate structure) in the active region 10; the initial stacked structure 11 includes a plurality of steps 110 stacked in sequence in the Z-axis direction, and the step 110 includes an insulating layer 112 and a conductive layer 111 located on the surface of the insulating layer 112. The step 110 has a preset size L1 in the Z-axis direction.

As shown in FIG. 2 b , the initial stacked structure 11 may also be connected to the bit line structure 102 in the active region 10 .

The embodiment of the present disclosure takes the word line step as an example to illustrate the specific process of the semiconductor structure.

In some embodiments, the number of conductive layers 111 and insulating layers 112 (or steps 110) in the initial stacked structure 11 can be set according to the number of memory cells in the semiconductor structure, and the word line structure 101 located in the same layer can lead out its signal through a conductive layer 111. In the embodiment of the present disclosure, the number of word line structures 101 in the active area 10 is 18 as an example for description.

Please continue to refer to FIG. 2a and FIG. 2c. A dielectric material is deposited on the surface of the active area 10 to form a protective layer 12. The initial stacked structure 11 is etched by dry etching technology to form a stacked structure 13. During implementation, a mask layer (not shown) having a preset pattern is formed on the surface of the initial stacked structure 11, wherein the preset pattern exposes a portion of the initial stacked structure 11. The exposed portion of the initial stacked structure 11 is removed by etching through the mask layer to transfer the preset pattern to the initial stacked structure 11 to form the stacked structure 13. The projection area of the stacked structure 13 along the Z-axis direction is comb-shaped.

In the embodiment of the present disclosure, the dielectric material can be any suitable inert material, such as photoresist, hard mask material. The protection layer 12 is used to protect the active area 10 from being etched and damaged during the subsequent process of forming the word line step.

In the embodiment of the present disclosure, the stacked structure 13 includes 6 initial step structures 14 arranged along the X-axis direction and a U-shaped isolation groove 15a located between two adjacent initial step structures 14 and between the initial step structure 14 and the active area 10. The active area 10 divides the stacked structure 13 into a first step region A and a second step region B arranged along the X-axis direction, and the first step region A and the second step region B both include 3 initial step structures 14 arranged at intervals along the X-axis direction, that is, M=6 in the embodiment of the present disclosure.

It should be noted that, in the embodiment of the present disclosure, the number of word line structures 101 in the active area 10 is 18 as an example for explanation, and the total number of initial step structures 14 in the embodiment of the present disclosure is M, therefore, each subsequent initial step structure 14 needs to form N (N is 18/M) small step structures (corresponding to the second step structure 181 formed subsequently) to electrically lead out each layer of word line structure 101. Since M is 6, N is 3.

In the embodiment of the present disclosure, the connection ends c of the three initial step structures 14 located in the first step area A are connected to each other, the connection ends c of the three initial step structures 14 located in the second step area B are connected to each other, and each initial step structure 14 is connected to the active area 10 (i.e., the word line structure 101) through the connection end c.

In some embodiments, after forming the M initial step structures 14 , the method for forming a semiconductor structure further includes: forming an isolation structure 15 in the U-shaped isolation groove 15 a .

As shown in FIG. 2c and FIG. 2d, an isolation material is deposited in the U-shaped isolation groove 15a to form an isolation structure 15. The isolation material can be any insulating material, such as silicon oxide or silicon oxynitride. The isolation structure 15 can isolate adjacent initial step structures 14 to prevent leakage between the step structures.

It should be noted that the isolation structure 15 in the embodiment of the present disclosure is also formed outside the U-shaped isolation groove 15a. The present disclosure only shows the isolation structure 15 located in the U-shaped isolation groove 15a, and does not show the isolation structure 15 outside the U-shaped isolation groove.

In some embodiments, M initial step structures 14 are etched multiple times along a first direction to form M first step structures 18, including: forming a first photoresist layer on the surfaces of the M initial step structures 14, the isolation structure 15 and the protective layer 12; etching the initial step structure 14 and the isolation structure 15 M-1 times through the first photoresist layer to form M first step structures 18 and the etched isolation structure 19; wherein, before the i-th etching, the first photoresist layer used in the i-1-th etching process is trimmed along the first direction so that the first photoresist layer in the i-th etching process at least exposes the first i initial step structures 14 in the first step structure 18.

In the embodiment of the present disclosure, the first step region A and the second step region B each include three initial step structures 14 (ie, M=6). Therefore, a total of five etchings are required to form six first step structures 18 .

First, referring to FIG. 2e and FIG. 2f, the first longitudinal etching process is performed to form a first photoresist layer 17a on the surface of the initial step structure 14, the isolation structure 15 and the protective layer 12. The surfaces of the first photoresist layer 17a located in different regions can be located in the same plane or different planes, and the thickness of the first photoresist layer 17a satisfies multiple longitudinal etching processes. The first photoresist layer 17a exposes the first initial step structure 14 and the first isolation structure 15 along the X-axis direction, and the exposed initial step structure 14, the isolation structure 15 and the barrier layer 16 are etched for the first time to form a first etched structure 14a. Among them, the first etched structure 14a includes the initial step structure 14 after the first etching and the isolation structure 19 after the first etching. Among them, the etching depth of the first longitudinal etching is 3×L1 (i.e., N steps).

Next, referring to FIG. 2g, the second longitudinal etching process is performed. Before the second longitudinal etching, the first photoresist layer 17a used in the first longitudinal etching process is trimmed along the X-axis direction to form a first photoresist layer 17b; so that the first photoresist layer 17b in the second longitudinal etching process exposes the first etching structure 14a, the second initial step structure 14 in the X-axis direction, and the second isolation structure 15; the exposed first etching structure 14a, the initial step structure 14, and the isolation structure 15 are subjected to the second longitudinal etching to form a second etching structure 14b. Among them, the second etching structure 14b includes two initial step structures 14 located after the second etching and two isolation structures 15 after the second etching. In this initial embodiment, the etching depth of the second longitudinal etching is 3×L1 (i.e., N steps).

By analogy, referring to FIG. 2h to FIG. 2j, the third, fourth and fifth longitudinal etching processes are performed in sequence, and the first photoresist layer 17 used in each longitudinal etching process is trimmed along the X-axis direction, so that the first photoresist layer in the i-th longitudinal etching process at least exposes the first i initial step structures 14 and isolation structures 15 in the first step structure 18 along the X-axis direction; for example, the first photoresist layer 17 in the fifth longitudinal etching process (as shown in FIG. 2j) at least exposes the first five initial step structures 14 and the first five isolation structures 15 in the first step structure 18 along the X-axis direction (i.e., the four initial step structures 14 and the four isolation structures 15 after the fourth etching, and the fifth initial step structure 14 and the fifth isolation structure 15 along the X-axis direction). In the disclosed embodiment, the third, fourth and fifth longitudinal etching processes are similar to the first and second longitudinal etching processes described above, and will not be repeated here.

In the embodiment of the present disclosure, the i-th initial step structure 14 in the initial step structure 14 is longitudinally etched 6-i times in sequence along the X-axis direction to form 6 first step structures 18 and the etched isolation structure 19 as shown in Figure 2j; for example, the first initial step structure 14 in the initial step structure 14 is etched 5 times along the X-axis direction; and the fifth initial step structure 14 in the initial step structure 14 is etched once along the X-axis direction.

It should be noted that, in the embodiment of the present disclosure, the etching depth of each longitudinal etching is 3×L1 (i.e., N steps), and the first photoresist layer sequentially exposes the first i initial step structures 14, and the formed first step structures 18 sequentially increase along the X-axis direction. In other embodiments, the first photoresist layer may not sequentially expose the first i initial step structures 14, that is, the order of exposure of the initial step structures 14 may be disordered, as long as the initial step structure 14 exposed in the previous time is exposed in the next time, for example, the initial step structures 14 on both sides of the active area 10 are sequentially exposed, and the formed first step structure 18 first increases and then decreases along the X-axis direction.

The method for forming a semiconductor structure provided by the embodiment of the present disclosure forms M first step structures 18 arranged at intervals along a first direction in a first step region A and a second step region B by etching the initial step structure 14 in the stacked structure 13. Since the M first step structures 18 are arranged at intervals, the projection area of the formed step structure as a whole in the third direction can be reduced, thereby reducing the coupling effect between the step structures, thereby reducing signal crosstalk, and improving the performance of the semiconductor structure.

In some embodiments, after forming the first step structure 18, the method for forming a semiconductor structure further includes: removing the first photoresist layer 17. In the disclosed embodiment, the first photoresist layer 17 can be removed by wet etching (for example, etching with strong acid such as concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc.) or dry etching.

Next, referring to Figures 2k to 2n, step S102 is executed to etch the multiple first step structures 18 multiple times along the second direction to form multiple second step structures 181 stacked in sequence along the third direction in each first step structure 18; from bottom to top along the third direction, the sizes of the second step structures 181 in the first step structures 18 in the first direction are reduced sequentially.

In some embodiments, the second step structure 181 can be formed by the following steps: forming a second photoresist layer having a preset pattern on the surfaces of M first step structures 18, the protective layer 12 and the etched isolation structure 19; the preset pattern includes a plurality of sub-patterns arranged in sequence along a first direction; etching part of the first step structure 18 and part of the etched isolation structure 19 N-1 times through the second photoresist layer to form the second step structure 181 and the remaining isolation structure 191.

Wherein, before the j-th etching, the second photoresist layer used in the j-1-th etching process is trimmed so that the size of the sub-pattern in the second photoresist layer in the j-th etching process in the first direction is larger than the size of the sub-pattern in the second photoresist layer used in the j-1-th etching process in the first direction, and the second photoresist layer in the j-th etching process exposes at least the first j parts of each first step structure 18 away from the connection end c along the second direction; j=1, 2…, N.

Referring to FIG. 2k , the first step structure 18 includes three parts arranged from right to left along the Y-axis direction, namely d, e, and f (as shown in the parts divided by the dotted lines in FIG. 2k ). Therefore, a total of two etchings are required to form three second step structures 181 corresponding to each first step structure 18. In the embodiment of the present disclosure, the three parts located in the first step region A and the second step region B have the same size along the Y-axis direction. For example, the part d located in the first step region A and the part located in the second step region B have the same size along the Y-axis direction, and the part e located in the first step region A and the part located in the second step region B have the same size along the Y-axis direction.

In other embodiments, the size of portion d located in the first step region A and the size of portion d located in the second step region B along the Y-axis direction may also be unequal; the size of portion d located in the first step region A and the size of portion d located in the second step region B along the Y-axis direction may also be unequal, so that the subsequently formed conductive column 21 can be staggered in the X-axis direction.

First, please continue to refer to FIG. 2j and FIG. 2k, and perform the first lateral etching process to form a second photoresist layer 20a with a preset pattern on the surfaces of the six first step structures 18, the protective layer 12, and the partially etched isolation structure 19; the preset pattern includes a plurality of sub-patterns E arranged in sequence along the X-axis direction; the sub-pattern E exposes the first portion d away from the connection end c and the partially etched isolation structure 19; the first portion d exposed by the sub-pattern E and the partially etched isolation structure 19 are subjected to the first lateral etching to form a first sub-step structure 18a and a first sub-isolation structure 19a. The etching depth of the first lateral etching is L1 (i.e., 1 step).

It should be noted that in the embodiment of the present disclosure, the second photoresist layer 20a does not expose the partially etched isolation structure 19 between the active area 10 and the first step structure 18. In other embodiments, the second photoresist layer may also expose the partially etched isolation structure 19 between the active area 10 and the first step structure 18.

Next, referring to FIG. 21 , a second lateral etching process is performed. Before the second lateral etching, the second photoresist layer 20a used in the first lateral etching process is trimmed along the Y-axis direction near the connection end c to form a second photoresist layer 20b having a preset pattern; the preset pattern includes a plurality of sub-patterns F arranged in sequence along the X-axis direction, and the size of the sub-pattern F in the X-axis direction is greater than the size of the sub-pattern E in the X-axis direction; the sub-pattern F exposes the first sub-step structure 18a, the first sub-isolation structure 19a and the second part e; the first sub-step structure 18a, the first sub-isolation structure 19a and the second part e exposed by the sub-pattern F are subjected to a second lateral etching, and the second photoresist layer 20b is removed to form a second step structure 181 and a remaining isolation structure 191. The etching depth of the second lateral etching is L1 (i.e., 1 step).

In the embodiment of the present disclosure, the j-th second step structure 181 from bottom to top along the Z-axis direction of each first step structure 18 in the first step region A is equal to the j-th second step structure 181 from bottom to top along the Z-axis direction of each first step structure 18 in the second step region B. For example, the second second step structure 181 from bottom to top along the Z-axis direction of each first step structure 18 in the first step region A is equal to the second second step structure 181 from bottom to top along the Z-axis direction of each first step structure 18 in the second step region B (that is, the portion e in the first step region A is equal to the portion e in the second step region B).

In other embodiments, the size of the jth second step structure 181 from bottom to top along the Z-axis direction of each first step structure 18 located in the first step area A may be different from the size of the jth second step structure 181 from bottom to top along the Z-axis direction of each first step structure 18 located in the second step area B.

In the embodiment of the present disclosure, from bottom to top along the Z-axis direction, the second step structure 181 in each first step structure 18 The sizes in the X-axis direction decrease sequentially, and the sizes in the Y-axis direction are the same (that is, the sizes of part d, part e and part f in the Y-axis direction are the same).

In other embodiments, from bottom to top along the Z-axis direction, the sizes of the second step structures 181 in each first step structure 18 in the Y-axis direction may be different.

In the embodiment of the present disclosure, along the third direction from bottom to top, the sizes of the second step structures 181 in the first step structure 18 in the first direction are reduced successively, so that the effective area between the second step structures 181 can be gradually reduced along the third direction from bottom to top, thereby reducing the coupling effect between the adjacent second step structures 181 along the third direction and improving the performance of the semiconductor structure.

As shown in FIG. 2 m , after forming the second stepped structure 181 , the method for forming a semiconductor structure further includes: removing the protective layer 12 .

In the disclosed embodiment, the second photoresist layer 20 b and the protective layer 12 may be removed by wet etching (eg, etching with a strong acid such as concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc.) or dry etching technology.

Please continue to refer to Figure 2m. After removing the protective layer 12, the method for forming the semiconductor structure also includes: depositing a dielectric layer material on the surface of the second step structure 181, the remaining isolation structure 191 and the active area 10 to form a dielectric layer 22; etching the dielectric layer 22 to form M×N etching holes (not shown); wherein each etching hole exposes a second step structure 181; and filling the etching hole with a conductive material to form a conductive column 21.

It should be noted that the sizes of the etched holes (conductive pillars 21) in the same column along the X-axis direction are the same, and the sizes of the etched holes (conductive pillars 21) in the same row along the Y-axis direction are different, that is, the sizes of the etched holes (conductive pillars 21) in the same row along the Y-axis direction increase successively.

In other embodiments, the sizes of the etched holes (conductive pillars 21 ) in the same row along the Y-axis direction may also be the same (as shown in FIG. 2 n ).

In the embodiment of the present disclosure, the dielectric layer material may be any insulating material, such as silicon oxide or silicon oxynitride. The conductive material may be any suitable metal material, such as tungsten, cobalt, copper, etc.

In the embodiment of the present disclosure, a step structure is formed in the first step region A and the second step region B on both sides of the active area 10, and the sizes of any two first step structures 18 in the third direction are not equal. Therefore, the connection heights of any two adjacent groups of wiring in the third direction are different, thereby reducing the density of wiring and simplifying the wiring setting of the semiconductor structure.

The presently disclosed embodiment also provides a semiconductor structure, which is formed by the method for forming the semiconductor structure in the above embodiment. Please continue to refer to Figures 2m and 2n. The semiconductor structure includes: a first step region A and a second step region B arranged along the X-axis direction, and an active region 10 located between the first step region A and the second step region B.

In some embodiments, a word line structure 101 , a bit line structure 102 , a gate structure, etc. are formed in the active region 10 , and the first step region A and the second step region B are connected to the active region 10 .

Please continue to refer to Figure 2m and Figure 2n. The first step region A and the second step region B are connected to the word line structure 101 in the active area 10. In other embodiments, the first step region A and the second step region B are connected to the bit line structure 102 in the active area 10 (refer to Figure 2b).

Please continue to refer to FIG. 2m and FIG. 2n , the area of the first step region A and the area of the second step region B may be equal. In other embodiments, the area of the first step region A and the area of the second step region B may also be different.

Please continue to refer to 2m and 2n, the first step region A and the second step region B include M (for example, M is 6) first step structures 18 arranged in sequence along the X-axis direction, and the first step structures 18 are all connected to the active area 10; the sizes of any two first step structures 18 in the Z-axis direction are different. For example, along the X-axis direction, the sizes of the first step structures 18 in the Z-axis direction increase in sequence; in other embodiments, along the X-axis direction, the sizes of the first step structures 18 in the Z-axis direction decrease in sequence, or increase first and then decrease.

In the embodiment of the present disclosure, the first step structure 18 is located in the first step region A and the second step region B on both sides of the active region 10, and the sizes of any two first step structures 18 in the third direction are not equal. Therefore, a group of wirings connected to the first step structure 18 can be arranged on both sides of the active region 10, and the heights of any two groups of wirings connected in the third direction are different, so that the density of the wirings can be reduced, thereby simplifying the wiring arrangement of the semiconductor structure.

In the disclosed embodiment, the first step structure 18 includes steps (not shown) stacked in sequence in the Z-axis direction, and each step includes a conductive layer 111 (not shown) and an insulating layer 112 (not shown) arranged in sequence in the Z-axis direction. The insulating layer 112 is used to isolate the conductive layers 111 adjacent to each other in the third direction to prevent leakage.

In some embodiments, please continue to refer to Figure 2m and Figure 2n, each first step structure 18 includes a plurality of second step structures 181 stacked in sequence along the Z-axis direction; wherein, from bottom to top along the Z-axis direction, the size of the second step structure 181 in the X-axis direction decreases in sequence.

In some embodiments, please continue to refer to Figure 2m and Figure 2n, each first step structure 18 includes N (for example, N is 3) second step structures 181 stacked in sequence along the Z-axis direction; the i-th first step structure 18 along the X-axis direction includes the (i-1)×N+1 (for example, N is 3) second step structures 181 to the i×N (for example, N is 3) second step structures 181; each second step structure 181 has a preset size in the Z-axis direction (that is, the thickness of one step); the difference between the top surface of the i-th first step structure 18 along the X-axis direction and the top surface of the (i-1)th first step structure 18 along the X-axis direction in the Z-axis direction is N times the preset size; wherein, i=1, 2…, M.

In some embodiments, please continue to refer to Figure 2m and Figure 2n, the projection area of the first step structure 18 along the Z-axis direction is a comb-tooth shape; the second step structure 181 of the connecting end c of each first step structure 18 in the first step area A is interconnected along the projection area of the Z-axis direction and connected to the active area 10; the second step structure 181 of the connecting end c of each first step structure 18 in the second step area B is interconnected along the projection area of the Z-axis direction and connected to the active area 10.

In the disclosed embodiment, please continue to refer to FIG. 2m and FIG. 2n. The size of the j-th second step structure 181 in the Y-axis direction from bottom to top along the Z-axis direction is the same as the size of the (j+1)-th second step structure 181 in the Y-axis direction. For example, the size of the second second step structure 181 in the Y-axis direction from bottom to top along the Z-axis direction is the same as the size of the third second step structure 181 in the Y-axis direction (i.e., the size of part d and part e in the above embodiment is the same); in other embodiments, the size of the j-th second step structure 181 in the Y-axis direction from bottom to top along the Z-axis direction may be different from the size of the (j+1)-th second step structure 181 in the Y-axis direction.

In the embodiment of the present disclosure, please continue to refer to FIG. 2m and FIG. 2n. The size of the j-th second step structure 181 located in the first step region A from bottom to top along the Z-axis direction in the Y-axis direction is the same as the size of the j-th second step structure 181 located in the second step region B in the Y-axis direction. For example, the size of the first second step structure 181 located in the first step region A from bottom to top along the Z-axis direction in the Y-axis direction is equal to the size of the first second step structure 181 located in the second step region B in the Y-axis direction (that is, the size of the portion d located in the first step region A and the second step region B in the above embodiment is the same). In other embodiments, the size of the j-th second step structure 181 located in the first step region A from bottom to top along the Z-axis direction in the Y-axis direction may be different from the size of the j-th second step structure 181 located in the second step region B in the Y-axis direction.

In some embodiments, please continue to refer to FIG. 2m and FIG. 2n, the semiconductor structure further includes an isolation structure (corresponding to the remaining isolation structure 191 in the above embodiment); the isolation structure is located between adjacent first step structures 18, and between the first step structure 18 and the active region 10. The isolation structure can isolate adjacent first step structures 18 to prevent leakage between the step structures.

In some embodiments, please continue to refer to Figure 2m and Figure 2n, the semiconductor structure also includes a dielectric layer 22 and a conductive column 21; the dielectric layer 22 is located on the surface of the first step structure 18, the isolation structure and the active area 10; the conductive column 21 is located in the dielectric layer 22 and on the surface of each second step structure 181.

In the disclosed embodiment, the sizes of the conductive pillars 21 in the same row along the Y-axis direction are different, that is, the sizes of the conductive pillars 21 in the same row along the Y-axis direction increase sequentially (as shown in FIG. 2m ), or, the sizes of the conductive pillars 21 in the same column along the X-axis direction are the same, and the sizes of the conductive pillars 21 in the same row along the Y-axis direction are the same (as shown in FIG. 2n ).

The present disclosure provides a semiconductor structure in which the first step region A and the second step region B both include a first step region A and a second step region B. Since the M first step structures 18 are arranged at intervals in the third direction, the projection area of the entire step structure in the third direction can be reduced, thereby reducing the coupling effect between the step structures, thereby reducing signal crosstalk and improving the performance of the semiconductor structure.

In addition, since the first step structure 18 includes N second step structures 181, and the sizes of the second step structures 181 in the first step structure 18 in the first direction are reduced successively from bottom to top along the third direction, the effective area between the second step structures 181 can be gradually reduced from bottom to top along the third direction, thereby reducing the coupling effect between the adjacent second step structures 181 along the third direction and improving the performance of the semiconductor structure.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

The features disclosed in several method or structural embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be based on the protection scope of the claims. The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be based on the protection scope of the claims.

Industrial Applicability

The embodiment of the present disclosure provides a semiconductor structure and a method for forming the same, the method comprising: providing an active region and a first step region and a second step region respectively located on both sides of the active region along a first direction; the first step region and the second step region include a plurality of first step structures arranged at intervals along the first direction, and any two first step structures have different sizes in a third direction; etching the plurality of first step structures multiple times along the second direction to form a plurality of second step structures stacked in sequence along the third direction in each first step structure; and the size of the second step structures in the first step structures decreases in sequence from bottom to top along the third direction. Since the size of the formed second step structures decreases in sequence from bottom to top along the third direction, the effective area between adjacent second step structures can be gradually reduced from bottom to top along the third direction, thereby reducing the coupling effect between adjacent second step structures along the third direction and improving the performance of the semiconductor structure.

Claims

A method for forming a semiconductor structure, the method comprising:

An active region (10) and a first step region (A) and a second step region (B) respectively located on both sides of the active region (10) along a first direction; the first step region (A) and the second step region (B) include a plurality of first step structures (18) arranged at intervals along the first direction, and any two of the first step structures (18) have different sizes in a third direction;

The plurality of first step structures (18) are etched multiple times along the second direction to form a plurality of second step structures (181) stacked in sequence along the third direction in each of the first step structures (18); from bottom to top along the third direction, the sizes of the second step structures (181) in the first step structures (18) in the first direction are reduced in sequence;

The first direction intersects with the second direction and is parallel to the plane where the active area (10) is located, and the third direction is perpendicular to the plane where the active area (10) is located.
The method according to claim 1, wherein providing an active area (10) and a first step area (A) and a second step area (B) respectively located on both sides of the active area (10) along a first direction comprises:

A stacked structure (13) is provided; the stacked structure (13) comprises the first step region (A) and the second step region (B) respectively located on both sides of the active region (10) along the first direction; the first step region (A) and the second step region (B) comprise M initial step structures (14) arranged at intervals along the first direction;

The M initial step structures (14) are etched M-1 times along the first direction to form M first step structures (18); wherein the size of the first step structures (18) in the third direction increases or decreases in sequence; and the i-th etching exposes i initial step structures (14), i=1, 2, ..., M-1.
The method according to claim 2, wherein the projection area of the stacked structure (13) along the third direction is comb-tooth-shaped; the second step structures (181) located at the connection end (c) of each first step structure (18) in the first step area (A) are interconnected in the projection area along the third direction and connected to the active area (10); the second step structures (181) located at the connection end (c) of each first step structure (18) in the second step area (B) are interconnected in the projection area along the third direction and connected to the active area (10); the providing of the stacked structure (13) comprises:

Providing an initial stacked structure (11), wherein the initial stacked structure (11) is located on both sides of the active region (10) along the first direction;

forming a protective layer (12) on the surface of the active area (10);

The initial stacked structure (11) is etched to form the initial step structure (14) and a U-shaped isolation groove (15a) located between two adjacent initial step structures (14) and between the initial step structure (14) and the active area (10).
The method according to claim 3, wherein before forming the M first step structures (18), the method further comprises:

An isolation structure (15) is formed in the U-shaped isolation groove (15a).
The method according to claim 4, wherein etching the M initial step structures (14) multiple times along the first direction to form the M first step structures (18) comprises:

forming a first photoresist layer on the surfaces of the M initial step structures (14), the isolation structure (15) and the protective layer (12);

Etching the initial step structure (14) and the isolation structure (15) M-1 times through the first photoresist layer to form the M first step structures (18) and the etched isolation structure (19);

Before the i-th etching, the first photoresist layer used in the i-1-th etching process is trimmed along the first direction so that the first photoresist layer in the i-th etching process at least exposes the first i initial step structures (14) in the first step structure (18).
The method according to claim 5, wherein the first photoresist layer is used to partially cover the initial step structure (14) performing M-1 etchings to form the M first step structures (18), including:

The i-th initial step structure (14) in the initial step structure (14) is etched M-i times in sequence along the first direction through the first photoresist layer to form the M first step structures (18); i=1, 2..., M-1.
The method according to claim 5 or 6, wherein the second step structure (181) is formed by the following steps:

Forming a second photoresist layer having a preset pattern on the surfaces of the M first step structures (18), the protective layer (12) and the etched isolation structure (19); the preset pattern comprises a plurality of sub-patterns arranged in sequence along a first direction;

Etching part of the first step structure (18) and part of the etched isolation structure (19) N-1 times through the second photoresist layer to form the second step structure (181) and the remaining isolation structure (191);

Before the j-th etching, the second photoresist layer used in the j-1-th etching process is trimmed so that the size of the sub-pattern in the second photoresist layer in the j-th etching process in the first direction is larger than the size of the sub-pattern in the second photoresist layer used in the j-1-th etching process in the first direction, and the second photoresist layer in the j-th etching process exposes at least the first j parts of each first step structure (18) away from the connecting end (c) along the second direction; j=1, 2..., N.
The method according to claim 7, wherein the first stepped structure (18) comprises j parts sequentially arranged from right to left along the second direction, and the first stepped structure (18) is etched N-1 times through the second photoresist layer to form the second stepped structure (181), comprising:

The j-th portion away from the connecting end (c) is etched N-j times in sequence along the second direction to form the second step structure (181).
The method according to claim 7 or 8, wherein after forming the second step structure (181), the method further comprises:

The second photoresist layer and the protective layer (12) are removed in sequence.
The method according to claim 9, wherein after removing the protective layer (12), the method further comprises:

forming a dielectric layer (22) on the surfaces of the second stepped structure (181), the remaining isolation structure (191) and the active region (10);

Etching the dielectric layer (22) to form M×N etching holes, wherein each of the etching holes exposes one of the second step structures (181);

A conductive column (21) is formed in the etched hole.
A semiconductor structure comprises: a first step region (A), a second step region (B) arranged along a first direction, and an active region (10) located between the first step region (A) and the second step region (B);

The first step region (A) and the second step region (B) include a plurality of first step structures (18) arranged in sequence along the first direction, and the first step structures (18) are all connected to the active region (10); any two of the first step structures (18) have different sizes in the third direction;

Each of the first step structures (18) comprises a plurality of second step structures (181) stacked in sequence along the third direction;

Wherein, along the third direction from bottom to top, the size of the second step structure (181) in the first direction decreases successively; the first direction is parallel to the plane where the active area (10) is located, and the third direction is perpendicular to the plane where the active area (10) is located.
The semiconductor structure according to claim 11, wherein each of the first stepped structures (18) comprises N second stepped structures (181) stacked sequentially along the third direction;

The i-th first step structure (18) along the first direction includes the (i-1)×N+1-th second step structure (181) to the i×N-th second step structure (181); each of the second step structures (181) has a preset size in the third direction;

The difference in size between the top surface of the i-th first step structure (18) along the first direction and the top surface of the (i-1)-th first step structure (18) along the first direction in the third direction is N times the preset size; wherein i=1, 2..., M.
The semiconductor structure according to claim 11 or 12, wherein the projection area of the first step structure (18) along the third direction is comb-shaped; the connection area of each first step structure (18) in the first step area (A) is The second step structures (181) of the end portions (c) are interconnected along a projection area in the third direction and are connected to the active region (10); the second step structures (181) of the connection end portions (c) of each first step structure (18) in the second step region (B) are interconnected along a projection area in the third direction and are connected to the active region (10).
The semiconductor structure according to any one of claims 11 to 13, wherein the size of the j-th second step structure (181) in the second direction from bottom to top along the third direction is the same as or different from the size of the (j+1)-th second step structure (181) in the second direction;

The second direction is parallel to the plane where the active region (10) is located, and intersects with the first direction.
The semiconductor structure according to any one of claims 11 to 14, wherein the semiconductor structure further comprises an isolation structure;

The isolation structure is located between adjacent first step structures (18) and between the first step structure (18) and the active region (10).
The semiconductor structure according to claim 15, wherein the semiconductor structure further comprises a dielectric layer (22) and a conductive pillar (21);

The dielectric layer (22) is located on the surfaces of the first step structure (18), the isolation structure and the active area (10);

The conductive column (21) is located in the dielectric layer (22) and on the surface of each of the second step structures (181).