WO2024065889A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2024065889A1
WO2024065889A1 PCT/CN2022/125424 CN2022125424W WO2024065889A1 WO 2024065889 A1 WO2024065889 A1 WO 2024065889A1 CN 2022125424 W CN2022125424 W CN 2022125424W WO 2024065889 A1 WO2024065889 A1 WO 2024065889A1
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layer
electrical connection
away
forming
substrate
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English (en)
French (fr)
Inventor
郑玉宏
王晓光
徐汉东
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same.
  • Magnetic Random Access Memory is a new type of solid-state non-volatile memory with high-speed reading and writing characteristics, which is formed by the characteristics of magnetic tunnel junction (MTJ).
  • MRAM relies on magnetic field polarization rather than charge to store data.
  • the magnetic field direction of the free layer in MTJ can be changed, while the magnetic field direction of the reference layer in MTJ remains unchanged.
  • MTJ presents a low resistance state; when the magnetic field directions of the free layer and the reference layer are opposite, MTJ presents a high resistance state.
  • By detecting the resistance of MTJ it can be determined whether the stored data is "0" or "1".
  • the changing trend of the magnetic field direction of the free layer in the MTJ is not easy to control, that is, the angle of change of the magnetic field direction of the free layer relative to the magnetic field direction of the reference layer is not easy to control, and thus it is not easy to control the resistance value of the MTJ.
  • the MTJ is a multi-layer structure. In order to achieve the control of the MTJ by the charge flow, there are requirements for the thickness of each film layer, which is not conducive to reducing the layout space of the MTJ in the MRAM.
  • the disclosed embodiments provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the layout direction of each film layer in a magnetic tunnel junction to increase the space for the change of the spin magnetic moment direction of the free layer, thereby facilitating improving the electrical performance of the magnetic tunnel junction.
  • an embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate and a magnetic tunnel junction located on the substrate; wherein, the direction in which the substrate points to the magnetic tunnel junction is a first direction, and along a direction perpendicular to the first direction, the magnetic tunnel junction comprises a reference layer, a tunneling layer, a free layer and a covering layer arranged in sequence, the reference layer, the tunneling layer, the free layer and the covering layer all extend along the first direction, the magnetic moment direction of the reference layer is the first direction, and the spin magnetic moment direction of the free layer changes in a plane parallel to the first direction; a first data line, which is in contact with the covering layer, is configured to control the spin magnetic moment direction of the free layer through the covering layer.
  • the reference layer is a strip structure
  • the tunneling layer surrounds the sidewall of the strip structure extending along the first direction
  • the free layer surrounds the sidewall of the tunneling layer away from the reference layer
  • the covering layer at least surrounds the sidewall of the free layer away from the tunneling layer.
  • the first data line is at least located on the top surface of the covering layer away from the substrate, and there is a gap between the first data line and the reference layer;
  • the semiconductor structure also includes: a first isolation layer, located between the first data line and the reference layer, and the covering layer also surrounds the side wall of the first isolation layer extending along the first direction; an electrical connection block, which is in contact and connected with a side of the reference layer away from the first isolation layer; a second isolation layer, located between the electrical connection block and the free layer, and between the electrical connection block and the covering layer.
  • the semiconductor structure further includes: a transistor located in the substrate and an electrical connection block contacting and connected to a source or a drain of the transistor, and the reference layer is electrically connected to the electrical connection block.
  • one of the source and the drain of the transistor is in contact with the electrical connection block
  • the semiconductor structure also includes: a second data line, which is in contact with the other of the source and the drain of the transistor; and a third data line, which is opposite to the channel region of the transistor and is configured to control the transistor to be in an on state or an off state.
  • the semiconductor structure also includes: an electrical connection column extending along the first direction, which is in contact with the electrical connection block, the reference layer is located on at least a portion of the side wall of the electrical connection column extending along the first direction, and the orthographic projection of the electrical connection column on the substrate covers the orthographic projection of the electrical connection block on the substrate.
  • the reference layer is a ring structure
  • the tunneling layer surrounds the outer side wall of the ring structure extending along the first direction
  • the free layer surrounds the side wall of the tunneling layer away from the reference layer
  • the covering layer at least surrounds the side wall of the free layer away from the tunneling layer.
  • the first data line is at least located on the top surface of the covering layer away from the substrate, and there is a gap between the first data line and the reference layer and the electrical connection column;
  • the semiconductor structure also includes: a first isolation layer, located between the first data line and the reference layer, and between the first data line and the electrical connection column, and the covering layer also surrounds the side wall of the first isolation layer extending along the first direction.
  • the first data line further covers a sidewall of the capping layer away from the free layer.
  • the reference layer is a strip structure
  • the tunneling layer covers the sidewall of the reference layer away from the electrical connection column
  • the free layer covers the sidewall of the tunneling layer away from the reference layer
  • the covering layer covers the sidewall of the free layer away from the tunneling layer.
  • the electrical connection column in a direction from the reference layer to the free layer, includes a first electrical connection column, a dielectric layer, and a second electrical connection column arranged in sequence, one reference layer covers the side wall of the first electrical connection column away from the dielectric layer, another reference layer covers the side wall of the second electrical connection column away from the dielectric layer, and one transistor corresponds to the two magnetic tunnel junctions.
  • the first data line covers a sidewall of the capping layer away from the free layer.
  • the reference layer, the tunneling layer, the free layer, and the covering layer are arranged in a second direction
  • the first data line extends along a third direction
  • the first direction, the second direction, and the third direction intersect each other
  • the first data line corresponds to a plurality of the magnetic tunnel junctions arranged at intervals along the third direction.
  • the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a magnetic tunnel junction on the substrate, wherein a direction in which the substrate points to the magnetic tunnel junction is a first direction, and along a direction perpendicular to the first direction, the magnetic tunnel junction comprises a reference layer, a tunneling layer, a free layer and a covering layer arranged in sequence, the reference layer, the tunneling layer, the free layer and the covering layer all extend along the first direction, the magnetic moment direction of the reference layer is the first direction, and the spin magnetic moment direction of the free layer changes in a plane parallel to the first direction; forming a first data line in contact with the covering layer, the first data line being configured to control the spin magnetic moment direction of the free layer through the covering layer.
  • the step of providing the substrate includes: forming a transistor and an electrical connection block connected to the source or drain of the transistor in the substrate; the step of forming the magnetic tunnel junction includes: forming the reference layer of the strip structure, the reference layer corresponding to the electrical connection block one by one; forming a second isolation layer, the second isolation layer and the reference layer jointly cover the top surface of the electrical connection block away from the transistor; forming a tunneling layer, the tunneling layer surrounds the side wall of the strip structure extending along the first direction; forming a free layer, the free layer surrounds the side wall of the tunneling layer away from the reference layer; forming a covering layer, the covering layer at least surrounds the side wall of the free layer away from the tunneling layer.
  • the step of providing the substrate includes: forming a transistor and an electrical connection block that is in contact with the source or drain of the transistor in the substrate; after forming the electrical connection block and before forming the magnetic tunnel junction, it also includes: forming an electrical connection column on the top surface of the electrical connection block away from the transistor, the electrical connection column extending along the first direction, the electrical connection column corresponding to the electrical connection block one by one, and the orthographic projection of the electrical connection column on the substrate covers the orthographic projection of the electrical connection block on the substrate.
  • the step of forming the magnetic tunnel junction includes: forming the reference layer surrounding the side wall of the electrical connection column extending along the first direction; forming the tunneling layer surrounding the side wall of the reference layer away from the electrical connection column; forming the free layer surrounding the side wall of the tunneling layer away from the reference layer; forming the covering layer at least surrounding the side wall of the free layer away from the tunneling layer.
  • the free layer and before forming the covering layer also includes: forming a first isolation layer, wherein the first isolation layer covers the top surface away from the substrate formed by the reference layer, the tunneling layer and the free layer, and the covering layer also surrounds the side wall of the first isolation layer extending along the first direction.
  • the step of forming the first data line includes: forming the first data line covering the top surface away from the substrate formed by the first isolation layer and the covering layer; or, forming the first data line covering the top surface away from the substrate formed by the first isolation layer and the covering layer, and covering the side wall of the covering layer away from the electrical connection column.
  • the electrical connection column has two opposite side walls
  • the step of forming the magnetic tunnel junction includes: forming the reference layer covering one of the two side walls; forming the tunneling layer covering the side of the reference layer away from the electrical connection column; forming the free layer covering the side of the tunneling layer away from the reference layer; forming the covering layer covering the side of the free layer away from the tunneling layer; the step of forming the first data line includes: forming the first data line covering the side of the covering layer away from the free layer.
  • the step of forming the electrical connection column includes: forming a first electrical connection column, a dielectric layer, and a second electrical connection column arranged in sequence on a top surface of the electrical connection block away from the transistor in a direction from the reference layer to the free layer.
  • the step of forming the magnetic tunnel junction includes: forming a reference layer on the side wall of the first electrical connection column away from the dielectric layer, and forming another reference layer on the side wall of the second electrical connection column away from the dielectric layer; forming the tunneling layer on the side of each reference layer away from the dielectric layer; forming the free layer on the side of each tunneling layer away from the reference layer; and forming the covering layer on the side of each free layer away from the tunneling layer.
  • the direction in which the substrate points to the magnetic tunnel junction is the first direction
  • the reference layer, tunnel layer, free layer and cover layer in the magnetic tunnel junction are arranged in sequence along a direction perpendicular to the first direction, that is, arranged in sequence along a direction parallel to the substrate surface, so as to provide a new layout mode of each film layer in the magnetic tunnel junction.
  • the reference layer, tunnel layer, free layer and cover layer all extend along the first direction, so that the change trend of the magnetic field direction of the free layer in the magnetic tunnel junction is easy to control, wherein the magnetic moment direction of the reference layer is the first direction, and the spin magnetic moment direction of the free layer changes in a plane parallel to the first direction, so that the angle of change of the magnetic field direction of the free layer relative to the magnetic field direction of the reference layer is easy to control, and it is beneficial to increase the space for the change of the spin magnetic moment direction of the free layer extending along the first direction, and it is beneficial to ensure that the thickness of the free layer in the direction perpendicular to the first direction is relatively thin, so as to reduce the layout area of the free layer on the substrate surface.
  • the magnetic tunnel junction also includes a covering layer that is in contact with the free layer.
  • the covering layer is beneficial to increase the angle of change of the spin magnetic moment direction of the free layer, so that when a smaller charge flow is provided to the free layer, the resistance value of the magnetic tunnel junction can change significantly, thereby increasing the resistance difference before and after the reversal of the magnetic tunnel junction and improving the electrical performance of the magnetic tunnel junction.
  • FIG1 is a schematic diagram of a partial cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG2 is a schematic diagram of a partial top view of the structure shown in FIG1 ;
  • FIG3 is a schematic diagram of a partial three-dimensional structure of a magnetic tunnel junction in the structure shown in FIG1 ;
  • FIGS. 4 and 5 are two other partial cross-sectional structural schematic diagrams of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG6 is a partial top view of the structure shown in FIG4 or FIG5;
  • FIG7 is a schematic diagram of another partial cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of a partial top view of the structure shown in FIG7 ;
  • FIG9 is a schematic diagram of another partial cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG10 is a schematic diagram of a partial top view of the structure shown in FIG9 ;
  • 11 to 15 are schematic structural diagrams corresponding to the steps of a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure.
  • the direction in which the substrate points to the MTJ is the first direction
  • the reference layer, tunnel layer and free layer in the MTJ are arranged in sequence along the first direction, that is, along the direction perpendicular to the substrate surface, the reference layer, tunnel layer and free layer are stacked in sequence on the substrate to form an MTJ.
  • the magnetic moment direction of the reference layer is parallel to the substrate surface, that is, perpendicular to the first direction, and the spin magnetic moment direction of the free layer is flipped in a plane parallel to the substrate surface to change the resistance value of the MTJ.
  • the spin magnetic moment direction of the free layer is flipped in a plane parallel to the substrate surface, an eddy current effect is likely to occur in the MTJ, causing the MTJ to heat up, reducing the performance of the MTJ, and causing electrical interference to the MTJ.
  • the magnetic moment direction of the reference layer is perpendicular to the substrate surface, that is, the first direction
  • the spin magnetic moment direction of the free layer is flipped in a plane perpendicular to the substrate surface.
  • the flipping space of the spin magnetic moment direction of the free layer is affected by the thickness of the free layer in the first direction, which can easily lead to incomplete flipping of the spin magnetic moment direction of the free layer.
  • it is necessary to increase the thickness of the free layer in the first direction which makes the overall thickness of the MTJ in the first direction too large, which is not conducive to reducing the layout space of the MTJ in the MRAM.
  • the present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the direction in which the substrate points to the magnetic tunnel junction is a first direction, and the reference layer, tunnel layer, free layer and cover layer in the magnetic tunnel junction are arranged in sequence along a direction perpendicular to the first direction, that is, arranged in sequence along a direction parallel to the substrate surface, so as to provide a new layout mode of each film layer in the magnetic tunnel junction.
  • the reference layer, tunnel layer, free layer and cover layer all extend along the first direction, so that the change trend of the magnetic field direction of the free layer in the magnetic tunnel junction is easy to control, wherein the magnetic moment direction of the reference layer is the first direction, and the spin magnetic moment direction of the free layer changes in a plane parallel to the first direction, so that the angle of change of the magnetic field direction of the free layer relative to the magnetic field direction of the reference layer is easy to control, and it is beneficial to increase the space for the change of the spin magnetic moment direction of the free layer extending along the first direction, and it is beneficial to ensure that the thickness of the free layer in the direction perpendicular to the first direction is relatively thin, so as to reduce the layout area of the free layer on the substrate surface.
  • the magnetic tunnel junction also includes a covering layer that is in contact with the free layer.
  • the covering layer is beneficial to increase the angle of change of the spin magnetic moment direction of the free layer, so that when a smaller charge flow is provided to the free layer, the resistance value of the magnetic tunnel junction can change significantly, thereby increasing the resistance difference before and after the reversal of the magnetic tunnel junction and improving the electrical performance of the magnetic tunnel junction.
  • FIG. 1 is a schematic diagram of a partial cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of a partial top-view structure of the structure shown in Figure 1
  • Figure 3 is a schematic diagram of a partial three-dimensional structure of a magnetic tunnel junction in the structure shown in Figure 1
  • Figures 4 and 5 are two other partial cross-sectional structural schematic diagrams of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 6 is a schematic diagram of a partial top-view structure of the structure shown in Figure 4 or Figure 5
  • Figure 7 is another partial cross-sectional structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 8 is a schematic diagram of a partial top-view structure of the structure shown in Figure 7
  • Figure 9 is another partial cross-sectional structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 10 is
  • the semiconductor structure includes: a substrate 100 and a magnetic tunnel junction 101 located on the substrate 100 ; wherein the direction from the substrate 100 to the magnetic tunnel junction 101 is a first direction X, and along a direction perpendicular to the first direction X, the magnetic tunnel junction 101 includes a reference layer 111, a tunnel layer 121, a free layer 131 and a cover layer 141 arranged in sequence, the reference layer 111, the tunnel layer 121, the free layer 131 and the cover layer 141 all extend along the first direction X, the magnetic moment direction of the reference layer 111 is the first direction X, and the spin magnetic moment direction of the free layer 131 changes in a plane parallel to the first direction X; a first data line 102 is in contact with the cover layer 141 and is configured to control the spin magnetic moment direction of the free layer 131 through the cover layer 141.
  • the reference layer 111, the tunneling layer 121, the free layer 131 and the cover layer 141 are arranged in sequence along a direction perpendicular to the first direction X, so as to provide a new layout mode of each film layer in the magnetic tunnel junction 101.
  • the reference layer 111, the tunneling layer 121, the free layer 131 and the cover layer 141 all extend along the first direction X, wherein the magnetic moment direction of the reference layer 111 is the first direction X, and the spin magnetic moment direction of the free layer 131 changes in a plane parallel to the first direction X, which is conducive to increasing the space for the spin magnetic moment direction change of the free layer 131 extending along the first direction X, so as to improve the resistance difference before and after the reversal of the magnetic tunnel junction 101, improve the electrical performance of the magnetic tunnel junction 101, and help to ensure that the thickness of the free layer 131 in the direction perpendicular to the first direction X is relatively thin, so as to reduce the layout area of the free layer 131 on the surface of the substrate 100.
  • the magnetic tunnel junction 101 also includes a covering layer 141 that is in contact with the free layer 131.
  • the covering layer 141 is beneficial to increasing the angle of change of the spin magnetic moment direction of the free layer 131, so that when a smaller charge flow is provided to the free layer 131, the resistance value of the magnetic tunnel junction 101 can change significantly, thereby improving the electrical performance of the magnetic tunnel junction 101.
  • the direction of the magnetic moment of the reference layer 111 is the first direction X, that is, the direction perpendicular to the surface of the substrate 100, and the direction of the spin magnetic moment of the free layer 131 changes in a plane parallel to the first direction X, which is beneficial to avoid eddy current effects in the magnetic tunnel junction 101, and to avoid overheating of the magnetic tunnel junction 101, so as to avoid degradation of the electrical performance of the magnetic tunnel junction 101 and degradation of the electrical performance.
  • the material of the reference layer 111 and the material of the free layer 131 both include at least one of cobalt iron boron, cobalt, or nickel iron, and the material of the tunneling layer 121 may be magnesium oxide.
  • the semiconductor structure may also include: a transistor 110 located in the substrate 100 and an electrical connection block 120 contacting and connected to the source or drain of the transistor 110, and the reference layer 111 and the electrical connection block 120 are electrically connected.
  • the transistor 110 is used to conduct a current path for performing a write operation or a read operation on the magnetic tunnel junction 101.
  • the electrical connection between the reference layer 111 and the electrical connection block 120 includes the following two situations: the reference layer 111 and the electrical connection block 120 are directly contacted and connected, or the reference layer 111 and the electrical connection block 120 are electrically connected through a conductive structure, and the above two situations will be described in detail later.
  • one of the source and the drain of the transistor 110 is in contact with the electrical connection block 120, and the semiconductor structure may also include: a second data line 130, which is in contact with the other of the source and the drain of the transistor 110; a third data line 140, which is directly opposite to the channel region of the transistor 110 and is configured to control the transistor 110 to be in an on state or an off state.
  • the second data line 130 may be a selection control line
  • the third data line 140 may be a word line.
  • the source of the transistor 110 is in contact with the electrical connection block 120, and the drain of the transistor 110 is in contact with the second data line 130; in another example, the drain of the transistor 110 is in contact with the electrical connection block 120, and the source of the transistor 110 is in contact with the second data line 130.
  • the reference layer 111 is directly contacted and connected with the electrical connection block 120, the orthographic projection of the reference layer 111 on the substrate 100 is located in the orthographic projection of the electrical connection block 120 on the substrate 100, the reference layer 111 is a strip structure, the tunneling layer 121 surrounds the side wall of the strip structure extending along the first direction X, the free layer 131 surrounds the side wall of the tunneling layer 121 away from the reference layer 111, and the covering layer 141 at least surrounds the side wall of the free layer 131 away from the tunneling layer 121.
  • the orthographic projection of the reference layer 111 on the substrate 100 is the first projection
  • the orthographic projection of the electrical connection block 120 on the substrate 100 is the second projection
  • the area of the first projection may be less than or equal to the area of the second projection.
  • the reference layer 111, the tunneling layer 121, the free layer 131 and the covering layer 141 can all be thin film layers extending along the first direction X. While ensuring that there is a large space for the spin magnetic moment direction of the free layer 131 to flip, it is beneficial to reduce the layout area of the magnetic tunnel junction 101 on the surface of the substrate 100, thereby helping to reduce the overall size of the magnetic tunnel junction 101, so as to improve the integration density of the magnetic tunnel junction 101 in the semiconductor structure.
  • FIG2 only illustrates a schematic diagram of a partial top view of the semiconductor structure
  • FIG3 only illustrates a schematic diagram of a partial three-dimensional structure of a single magnetic tunnel junction 101.
  • FIG3 takes the reference layer 111 as a cylinder, and the tunneling layer 121, the free layer 131 and the cover layer 141 as an example of a circular ring structure that sequentially surrounds the reference layer 111.
  • the reference layer 111 may also be other strip structures extending along the first direction X, such as a square column, and at least one of the tunneling layer 121, the free layer 131 and the cover layer 141 may also be other ring structures, such as a square ring.
  • the first data line 102 is at least located on the top surface of the covering layer 141 away from the substrate 100, and there is a gap between the first data line 102 and the reference layer 111;
  • the semiconductor structure also includes: a first isolation layer 103, located between the first data line 102 and the reference layer 111, and the covering layer 141 also surrounds the side wall of the first isolation layer 103 extending along the first direction X;
  • the electrical connection block 120 is in contact with and connected to a side of the reference layer 111 away from the first isolation layer 103;
  • the second isolation layer 113 is located between the electrical connection block 120 and the free layer 131, and between the electrical connection block 120 and the covering layer 141.
  • the first isolation layer 103 is located on the top surface of the reference layer 111, the tunneling layer 121 and the free layer 131, which is far away from the substrate 100, as an example, so as to achieve electrical insulation between the first data line 102 and the reference layer 111, and to simplify the preparation method of the first isolation layer 103.
  • FIG1 takes the example of the first data line 102 being located on the top surface formed by the first isolation layer 103 and the covering layer 141 away from the substrate 100.
  • the first data line 102 is located on the top surface of the covering layer 141 away from the substrate 100 to achieve electrical connection between the first data line 102 and the covering layer 141.
  • the second isolation layer 113 is located between the bottom surface of the tunneling layer 121, the free layer 131 and the cover layer 141 close to the substrate 100 and the substrate 100 as an example, so as to achieve electrical insulation between the free layer 131 and the cover layer 141 and the electrical connection block 120, and it is helpful to simplify the preparation method of the second isolation layer 113.
  • FIG1 takes the example that the covering layer 141 also surrounds the side wall of the first isolation layer 103 extending along the first direction X.
  • the covering layer 141 may only surround the side wall of the free layer 131 away from the tunneling layer 121, and the first data line 102 may surround the side wall of the first isolation layer 103 extending along the first direction X to achieve contact connection between the covering layer 141 and the first data line 102.
  • the material of the first isolation layer 103 and the material of the second isolation layer 113 can be at least one of insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.
  • the semiconductor structure may further include: an electrical connection column 105 extending along the first direction X, contacting and connecting with the electrical connection block 120, a reference layer 111 located on at least a portion of the sidewall of the electrical connection column 105 extending along the first direction X, and an orthographic projection of the electrical connection column 105 on the substrate 100 covering an orthographic projection of the electrical connection block 120 on the substrate 100. It is understandable that the reference layer 111 and the electrical connection block 120 are electrically connected via the electrical connection column 105.
  • the structure of the magnetic tunnel junction 101 when the semiconductor structure includes the electrical connection pillar 105 is described in detail below.
  • the reference layer 111 can be a ring-shaped structure
  • the tunneling layer 121 surrounds the outer side wall of the ring-shaped structure extending along the first direction X
  • the free layer 131 surrounds the side wall of the tunneling layer 121 away from the reference layer 111
  • the covering layer 141 at least surrounds the side wall of the free layer 131 away from the tunneling layer 121.
  • the reference layer 111, the tunneling layer 121, the free layer 131 and the covering layer 141 can all be annular thin film layers extending along the first direction X. While ensuring that there is a large space for the spin magnetic moment direction of the free layer 131 to flip, it is beneficial to reduce the layout area of the magnetic tunnel junction 101 on the surface of the substrate 100, thereby helping to reduce the overall size of the magnetic tunnel junction 101, so as to improve the integration density of the magnetic tunnel junction 101 in the semiconductor structure.
  • FIG6 only illustrates a partial schematic diagram of a top view of the semiconductor structure, and FIG6 may be a schematic diagram of a top view of the semiconductor structure in FIG4 or FIG5 excluding the first isolation layer 103 and the first data line 102.
  • FIG6 takes the reference layer 111, the tunneling layer 121, the free layer 131 and the cover layer 141 as an example of a square ring structure that sequentially surrounds the electrical connection column 105.
  • at least one of the reference layer 111, the tunneling layer 121, the free layer 131 and the cover layer 141 may also be other ring structures extending along the first direction X, such as a circular ring.
  • the first data line 102 is at least located on the top surface of the covering layer 141 away from the substrate 100, and there is a gap between the first data line 102 and the reference layer 111 and the electrical connection column 105;
  • the semiconductor structure also includes: a first isolation layer 103, located between the first data line 102 and the reference layer 111, and between the first data line 102 and the electrical connection column 105, and the covering layer 141 also surrounds the side wall of the first isolation layer 103 extending along the first direction X.
  • the first isolation layer 103 is located on the top surface of the electrical connection column 105, the reference layer 111, the tunneling layer 121 and the free layer 131, which are formed together and are far away from the substrate 100, as an example, so as to achieve electrical insulation between the first data line 102 and the reference layer 111, and between the first data line 102 and the electrical connection column 105, and to simplify the preparation method of the first isolation layer 103.
  • the first isolation layer 103 is located between the first data line 102 and the reference layer 111, and between the first data line 102 and the electrical connection column 105, so as to achieve electrical insulation between the first data line 102 and the reference layer 111 and the electrical connection column 105.
  • the example in which the covering layer 141 also surrounds the side wall of the first isolation layer 103 extending along the first direction X is taken as an example.
  • the covering layer 141 can only surround the side wall of the free layer 131 away from the tunneling layer 121, and the first data line 102 can surround the side wall of the first isolation layer 103 extending along the first direction X to achieve contact connection between the covering layer 141 and the first data line 102.
  • the first data line 102 is at least located on the top surface of the cover layer 141 away from the substrate 100 and includes at least the following two embodiments:
  • the first data line 102 is located on a top surface formed by the first isolation layer 103 and the cover layer 141 and away from the substrate 100 .
  • the first data line 102 is located on a top surface of the cover layer 141 away from the substrate 100 , and the first data line 102 also covers a sidewall of the cover layer 141 away from the free layer 131 .
  • the first data line 102 is located on the top surface of the first isolation layer 103 and the covering layer 141, which is away from the substrate 100.
  • the first data line 102 is located on the top surface of the covering layer 141 away from the substrate 100 to achieve electrical connection between the first data line 102 and the covering layer 141.
  • the material of the first isolation layer 103 may be at least one of insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.
  • the reference layer 111 can be a strip structure
  • the tunneling layer 121 covers the side wall of the reference layer 111 away from the electrical connection column 105
  • the free layer 131 covers the side wall of the tunneling layer 121 away from the reference layer 111
  • the covering layer 141 covers the side wall of the free layer 131 away from the tunneling layer 121.
  • the following describes in detail two embodiments of the semiconductor structure including the electrical connection pillar 105 and the reference layer 111 being a strip structure.
  • the electrical connection column 105 has a first side and a second side relative to each other, the reference layer 111 is located on the first side or the second side of the electrical connection column 105, and one magnetic tunnel junction 101 corresponds to one electrical connection column 105, so that one transistor 110 corresponds to one magnetic tunnel junction 101.
  • the electrical connection column 105 includes a first electrical connection column 115, a dielectric layer 125, and a second electrical connection column 135 arranged in sequence, a reference layer 111 covers the side wall of the first electrical connection column 115 away from the dielectric layer 125, another reference layer 111 covers the side wall of the second electrical connection column 135 away from the dielectric layer 125, and a transistor 110 corresponds to two magnetic tunnel junctions 101.
  • the dielectric layer 125 is used to achieve electrical insulation between the first electrical connection pillar 115 and the second electrical connection pillar 135 , and the two magnetic tunnel junctions 101 correspond to the same electrical connection pillar 105 , so that one transistor 110 corresponds to two magnetic tunnel junctions 101 .
  • the first data line 102 covers the side wall of the cover layer 141 away from the free layer 131 .
  • the arrangement direction of the reference layer 111, the tunneling layer 121, the free layer 131 and the cover layer 141 is the second direction Y
  • the first data line 102 extends along the third direction Z
  • the first direction X, the second direction Y and the third direction Z intersect each other
  • the first data line 102 corresponds to a plurality of magnetic tunnel junctions 101 arranged at intervals along the third direction Z.
  • the first data line 102 can be a bit line, and the bit line is electrically connected to the free layer 131 through the cover layer 141 to control the flipping of the spin magnetic moment direction in the free layer 131, and one bit line can control a plurality of magnetic tunnel junctions 101 arranged at intervals along the third direction Z.
  • two magnetic tunnel junctions 101 are arranged at intervals along the second direction Y, and two magnetic tunnel junctions 101 are arranged at intervals along the third direction Z.
  • the number may be 1, 3 or 8
  • a second isolation layer 113 and a magnetic tunnel junction 101 in Figure 2 is an example.
  • multiple magnetic tunnel junctions 101 can share a second isolation layer 113, or a second isolation layer 113 extends along the second direction Y and corresponds to a plurality of magnetic tunnel junctions 101 arranged at intervals along the second direction Y, or a second isolation layer 113 extends along the third direction Z and corresponds to a plurality of magnetic tunnel junctions 101 arranged at intervals along the third direction Z.
  • an embodiment of the present disclosure provides a new layout method of each film layer in the magnetic tunnel junction 101.
  • the magnetic moment direction of the reference layer 111 is perpendicular to the surface of the substrate 100, that is, the first direction X
  • the spin magnetic moment direction of the free layer 131 changes in a plane parallel to the first direction X, which is conducive to increasing the space for the spin magnetic moment direction change of the free layer 131 extending along the first direction X, so as to improve the electrical performance of the magnetic tunnel junction 101, and is conducive to ensuring that the thickness of the free layer 131 in the direction perpendicular to the first direction X is relatively thin, so as to reduce the layout area of the free layer 131 on the surface of the substrate 100, and is conducive to avoiding the eddy current effect in the magnetic tunnel junction 101, so as to avoid overheating of the magnetic tunnel junction 101, thereby avoiding the degradation of the electrical performance of the magnetic tunnel junction 101.
  • the covering layer 141 is beneficial to increasing the angle of change of the spin magnetic moment direction of the free layer 131, so that when a smaller charge flow is provided to the free layer 131, the resistance value of the magnetic tunnel junction 101 can change significantly, thereby being beneficial to improving the electrical performance of the magnetic tunnel junction.
  • FIG. 11 to 15 are schematic structural diagrams corresponding to each step of the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure. It should be noted that the parts that are the same or corresponding to the aforementioned embodiments are not repeated here. In addition, Figures 11 to 15 are schematic structural diagrams of local semiconductor structures.
  • a method for manufacturing a semiconductor structure includes: providing a substrate 100; forming a magnetic tunnel junction 101 on the substrate 100, wherein a direction in which the substrate 100 points to the magnetic tunnel junction 101 is a first direction X, and along a direction perpendicular to the first direction X, the magnetic tunnel junction 101 includes a reference layer 111, a tunnel layer 121, a free layer 131 and a cover layer 141 arranged in sequence, the reference layer 111, the tunnel layer 121, the free layer 131 and the cover layer 141 all extend along the first direction X, the magnetic moment direction of the reference layer 111 is the first direction X, and the spin magnetic moment direction of the free layer 131 changes within a plane parallel to the first direction X; forming a first data line 102 in contact with the cover layer 141, and the first data line 102 is configured to control the spin magnetic moment direction of the free layer 131 through the cover layer 141.
  • Providing the substrate 100 includes at least the following two embodiments:
  • providing the substrate 100 comprises the following steps:
  • a transistor 110 and an electrical connection block 120 contact-connected to a source or drain of the transistor 110 are formed in a substrate 100 .
  • Forming the magnetic tunnel junction 101 includes the following steps:
  • a reference layer 111 of a strip structure is formed, and the reference layer 111 corresponds to the electrical connection block 120 one by one.
  • a second isolation layer 113 is formed, and the second isolation layer 113 and the reference layer 111 together cover the top surface of the electrical connection block 120 away from the transistor 110 .
  • the second isolation layer 113 may be formed in at least two embodiments:
  • an initial second isolation layer 123 is formed, and the initial second isolation layer 123 and the reference layer 111 jointly cover the surface of the substrate 100; referring to FIG. 13 , the initial second isolation layer 123 is patterned to form a second isolation layer 113.
  • FIG. 13 is only an example of patterning the initial second isolation layer 123. In practical applications, there is no restriction on the second isolation layer 113 formed after the initial second isolation layer 123 is patterned. It is only necessary that the second isolation layer 113 is located between each electrical connection block 120 and each free layer 131 and between each electrical connection block 120 and each covering layer 141.
  • the formed second isolation layer 113 and the reference layer 111 jointly cover the surface of the substrate 100 , which can be understood as not performing a patterning process on the initial second isolation layer 123 .
  • a tunneling layer 121 is formed, and the tunneling layer 121 surrounds the sidewalls of the strip structure extending along the first direction X; and a free layer 131 is formed, and the free layer 131 surrounds the sidewalls of the tunneling layer 121 away from the reference layer 111 .
  • a capping layer 141 is formed, and the capping layer 141 at least surrounds a sidewall of the free layer 131 away from the tunneling layer 121 .
  • the process further includes: forming a first isolation layer 103 .
  • the method for forming the first isolation layer 103 will be described in detail later.
  • providing the substrate 100 includes the following steps:
  • a transistor 110 and an electrical connection block 120 contact-connected to a source or drain of the transistor 110 are formed in a substrate 100 .
  • the manufacturing method may further include: forming an electrical connection column 105 on the top surface of the electrical connection block 120 away from the transistor 110, the electrical connection column 105 extending along the first direction X, the electrical connection column 105 corresponding to the electrical connection block 120 one by one, and the orthographic projection of the electrical connection column 105 on the substrate 100 covers the orthographic projection of the electrical connection block 120 on the substrate 100.
  • a method for forming an electrical connection column 105 includes: forming an initial electrical connection column 145 extending along a direction perpendicular to the first direction X, such as a third direction Z, on a surface of a substrate 100, and imaging the initial electrical connection column 145 to form an electrical connection column 105 corresponding one-to-one to an electrical connection block 120 (refer to FIG. 14 ).
  • one electrical connection pillar 105 may correspond to one magnetic tunnel junction 101 , and a method for forming the magnetic tunnel junction 101 includes at least the following two embodiments:
  • the steps of forming the magnetic tunnel junction 101 include: forming a reference layer 111 surrounding the side walls of the electrical connection column 105 extending along the first direction X; forming a tunneling layer 121 surrounding the side walls of the reference layer 111 away from the electrical connection column 105; forming a free layer 131 surrounding the side walls of the tunneling layer 121 away from the reference layer 111; and forming a covering layer 141 at least surrounding the side walls of the free layer 131 away from the tunneling layer 121.
  • the steps of forming the magnetic tunnel junction 101 include: along a direction perpendicular to the first direction X, the electrical connection column 105 has a first side and a second side relative to each other, and a reference layer 111 with a strip structure is formed on the first side or the second side of the electrical connection column 105; a tunneling layer 121 is formed to cover the side wall of the reference layer 111 away from the electrical connection column 105, and a free layer 131 is formed to cover the side wall of the tunneling layer 121 away from the reference layer 111; and a covering layer 141 is formed to cover the side wall of the free layer 131 away from the tunneling layer 121.
  • the manufacturing method may further include: forming a first isolation layer 103, wherein the first isolation layer 103 covers a top surface away from the substrate 100 formed by the reference layer 111, the tunneling layer 121 and the free layer 131, and the covering layer 141 also surrounds the side wall of the first isolation layer 103 extending along the first direction X.
  • the step of forming the first data line 102 may include: referring to FIG. 1 or FIG. 4 , forming the first data line 102 covering the top surface away from the substrate 100 formed by the first isolation layer 103 and the covering layer 141; or, referring to FIG. 5 , forming the first data line 102 covering the top surface away from the substrate 100 formed by the first isolation layer 103 and the covering layer 141, and covering the side wall of the covering layer 141 away from the electrical connection column 105.
  • the same electrical connection column 105 can correspond to two magnetic tunnel junctions 101.
  • the electrical connection column 105 has two opposite side walls along the direction perpendicular to the first direction X.
  • the steps of forming the magnetic tunnel junction 101 include: forming a reference layer 111 covering one of the two side walls; forming a tunneling layer 121 covering the side of the reference layer 111 away from the electrical connection column 105; forming a free layer 131 covering the side of the tunneling layer 121 away from the reference layer 111; forming a covering layer 141 covering the side of the free layer 131 away from the tunneling layer 121; the steps of forming the first data line 102 include: forming the first data line 102 covering the side of the covering layer 141 away from the free layer 131.
  • the step of forming the electrical connection pillar 105 includes: forming a first electrical connection pillar 115, a dielectric layer 125, and a second electrical connection pillar 135 arranged in sequence on the top surface of the electrical connection block 120 away from the transistor 110 in a direction from the reference layer 111 to the free layer 131. It should be noted that another embodiment of the present disclosure does not limit the specific method of how to form the first electrical connection pillar 115, the dielectric layer 125, and the second electrical connection pillar 135.
  • the steps of forming the magnetic tunnel junction 101 include: forming a reference layer 111 on the side wall of the first electrical connection column 115 away from the dielectric layer 125, and forming another reference layer 111 on the side wall of the second electrical connection column 135 away from the dielectric layer 125; forming a tunneling layer 121 on a side of each reference layer 111 away from the dielectric layer 125; forming a free layer 131 on a side of each tunneling layer 121 away from the reference layer 111; and forming a covering layer 141 on a side of each free layer 131 away from the tunneling layer 121.
  • the formed first data line 102 may also extend along the third direction Z, that is, a first data line 102 corresponds to a plurality of magnetic tunnel junctions 101 arranged at intervals along the third direction Z.
  • the reference layer 111, the tunneling layer 121, the free layer 131 and the cover layer 141 to be formed all extend along the first direction X, which is conducive to simplifying the process steps of forming the magnetic tunnel junction 101 and reducing the process difficulty of forming the magnetic tunnel junction 101.
  • the thicknesses of the reference layer 111, the tunneling layer 121, the free layer 131 and the cover layer 141 are all easy to control and adjust.
  • the spin magnetic moment direction of the free layer 131 changes in a plane parallel to the first direction X, which is conducive to increasing the space for the spin magnetic moment direction of the free layer 131 extending along the first direction X to change, so as to improve the electrical performance of the magnetic tunnel junction 101, and is conducive to ensuring that the thickness of the free layer 131 in the direction perpendicular to the first direction X is relatively thin, so as to reduce the layout area of the free layer 131 on the surface of the substrate 100, and is conducive to avoiding the eddy current effect in the magnetic tunnel junction 101, so as to avoid overheating of the magnetic tunnel junction 101, thereby avoiding the degradation of the electrical performance of the magnetic tunnel junction 101 and the degradation of the electrical performance.
  • the cover layer 141 is conducive to increasing the angle of the spin magnetic moment direction change of the free layer 131, so that when a small charge flow is provided to the free layer 131, the resistance value of the magnetic tunnel junction 101 can change significantly, thereby facilitating the improvement of the electrical performance of the magnetic tunnel junction.

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Abstract

本公开实施例涉及半导体技术领域，提供一种半导体结构及其制造方法，半导体结构包括：基底以及位于基底上的磁性隧道结；其中，基底指向磁性隧道结的方向为第一方向，沿垂直于第一方向的方向上，磁性隧道结包括依次排列的参考层、隧穿层、自由层和覆盖层，参考层、隧穿层、自由层和覆盖层均沿第一方向延伸，参考层的磁矩方向为第一方向，自由层的自旋磁矩方向在平行于第一方向的平面内变化；第一数据线，与覆盖层接触连接，被配置为，通过覆盖层控制自由层的自旋磁矩方向。本公开实施例至少有利于改善磁性隧道结中各膜层的布局方向，以增加自由层的自旋磁矩方向变化的空间，从而有利于提高磁性隧道结的电学性能。

Description

半导体结构及其制造方法
交叉引用
本申请要求于2022年09月28日递交的名称为“半导体结构及其制造方法”、申请号为202211193068.7的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本公开实施例涉及半导体技术领域，特别涉及一种半导体结构及其制造方法。
背景技术
磁性随机存储器(MRAM，Magnetic Random Access Memory)是一种新型固态非易失性记忆体，具有高速读写的特性，利用磁性隧道结(MTJ，Magnetic Tunnel Junction)的特性形成。其中，MRAM靠磁场极化而非电荷以存储数据，MTJ中自由层的磁场方向可以改变，MTJ中参考层的磁场方向不变，当自由层与参考层的磁场方向相同时，MTJ呈现低电阻状态；当自由层与参考层的磁场方向相反时，MTJ呈现高电阻状态，则通过检测MTJ电阻的高低，即可判断所存数据是“0”还是“1”。
然而，MTJ中自由层的磁场方向的改变趋势不易控制，即自由层的磁场方向相对于参考层的磁场方向转变的角度不易控制，从而不易控制MTJ的电阻值。此外，MTJ为多膜层结构，为实现利用电荷流对MTJ进行调控，对各膜层的厚度有要求，不利于降低MTJ在MRAM中的布局空间。
发明内容
本公开实施例提供一种半导体结构及其制造方法，至少有利于改善磁性隧道结中各膜层的布局方向，以增加自由层的自旋磁矩方向变化的空间，从而有利于提高磁性隧道结的电学性能。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：基底以及位于所述基底上的磁性隧道结；其中，所述基底指向所述磁性隧道结的方向为第一方向，沿垂直于所述第一方向的方向上，所述磁性隧道结包括依次排列的参考层、隧穿层、自由层和覆盖层，所述参考层、所述隧穿层、所述自由层和所述覆盖层均沿所述第一方向延伸，所述参考层的磁矩方向为所述第一方向，所述自由层的自旋磁矩方向在平行于所述第一方向的平面内变化；第一数据线，与所述覆盖层接触连接，被配置为，通过所述覆盖层控制所述自由层的自旋磁矩方向。
在一些实施例中，所述参考层为条状结构，所述隧穿层环绕所述条状结构沿所述第一方向延伸的侧壁，所述自由层环绕所述隧穿层远离所述参考层的侧壁，所述覆盖层至少环绕所述自由层远离所述隧穿层的侧壁。
在一些实施例中，所述第一数据线至少位于所述覆盖层远离所述基底的顶面，所述第一数据线与所述参考层之间具有间隔；所述半导体结构还包括：第一隔离层，位于所述第一数据线与所述参考层之间，所述覆盖层还环绕所述第一隔离层沿所述第一方向延伸的侧壁；电连接块，与所述参考层远离所述第一隔离层的一侧接触连接；第二隔离层，位于所述电连接块和所述自由层之间，且位于所述电连接块和所述覆盖层之间。
在一些实施例中，所述半导体结构还包括：位于所述基底中的晶体管以及与所述晶体管的源极或漏极接触连接的电连接块，所述参考层和所述电连接块电连接。
在一些实施例中，所述晶体管的源极和漏极中的一者与所述电连接块接触连接，所述半导体结构还包括：第二数据线，与所述晶体管的源极和漏极中的另一者接触连接；第三数 据线，与所述晶体管的沟道区正对，被配置为，控制所述晶体管处于导通状态或关断状态。
在一些实施例中，所述半导体结构还包括：沿所述第一方向延伸的电连接柱，与所述电连接块接触连接，所述参考层位于所述电连接柱沿所述第一方向上延伸的至少部分侧壁，所述电连接柱在所述基底上的正投影覆盖所述电连接块在所述基底上的正投影。
在一些实施例中，所述参考层为环状结构，所述隧穿层环绕所述环状结构沿所述第一方向延伸的外侧壁，所述自由层环绕所述隧穿层远离所述参考层的侧壁，所述覆盖层至少环绕所述自由层远离所述隧穿层的侧壁。
在一些实施例中，所述第一数据线至少位于所述覆盖层远离所述基底的顶面，所述第一数据线与所述参考层和所述电连接柱之间具有间隔；所述半导体结构还包括：第一隔离层，位于所述第一数据线与所述参考层之间，以及位于所述第一数据线与所述电连接柱之间，所述覆盖层还环绕所述第一隔离层沿所述第一方向延伸的侧壁。
在一些实施例中，所述第一数据线还覆盖所述覆盖层远离所述自由层的侧壁。
在一些实施例中，所述参考层为条状结构，所述隧穿层覆盖所述参考层远离所述电连接柱的侧壁，所述自由层覆盖所述隧穿层远离所述参考层的侧壁，所述覆盖层覆盖所述自由层远离所述隧穿层的侧壁。
在一些实施例中，沿所述参考层指向所述自由层的方向上，所述电连接柱包括依次排列的第一电连接柱、介质层和第二电连接柱，一所述参考层覆盖所述第一电连接柱远离所述介质层的侧壁，另一所述参考层覆盖所述第二电连接柱远离所述介质层的侧壁，一所述晶体管与两个所述磁性隧道结对应。
在一些实施例中，所述第一数据线覆盖所述覆盖层远离所述自由层的侧壁。
在一些实施例中，所述参考层、所述隧穿层、所述自由层和所述覆盖层的排列方向第二方向，所述第一数据线沿第三方向延伸，所述第一方向、所述第二方向和所述第三方向两两相交，所述第一数据线与沿所述第三方向间隔排布的多个所述磁性隧道结对应。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制造方法，包括：提供基底；在所述基底上形成磁性隧道结，其中，所述基底指向所述磁性隧道结的方向为第一方向，沿垂直于所述第一方向的方向上，所述磁性隧道结包括依次排列的参考层、隧穿层、自由层和覆盖层，所述参考层、所述隧穿层、所述自由层和所述覆盖层均沿所述第一方向延伸，所述参考层的磁矩方向为所述第一方向，所述自由层的自旋磁矩方向在平行于所述第一方向的平面内变化；形成与所述覆盖层接触连接的第一数据线，所述第一数据线被配置为，通过所述覆盖层控制所述自由层的自旋磁矩方向。
在一些实施例中，提供所述基底的步骤包括：在所述基底中形成晶体管以及与所述晶体管的源极或漏极接触连接的电连接块；形成所述磁性隧道结的步骤包括：形成条状结构的所述参考层，所述参考层与所述电连接块一一对应；形成第二隔离层，所述第二隔离层和所述参考层共同覆盖所述电连接块远离所述晶体管的顶面；形成隧穿层，所述隧穿层环绕所述条状结构沿所述第一方向延伸的侧壁；形成自由层，所述自由层环绕所述隧穿层远离所述参考层的侧壁；形成覆盖层，所述覆盖层至少环绕所述自由层远离所述隧穿层的侧壁。
在一些实施例中，提供所述基底的步骤包括：在所述基底中形成晶体管以及与所述晶体管的源极或漏极接触连接的电连接块；在形成所述电连接块之后，在形成所述磁性隧道结之前，还包括：在所述电连接块远离所述晶体管的顶面形成电连接柱，所述电连接柱沿所述第一方向延伸，所述电连接柱与所述电连接块一一对应，且所述电连接柱在所述基底上的正投影覆盖所述电连接块在所述基底上的正投影。
在一些实施例中，形成所述磁性隧道结的步骤包括：形成环绕所述电连接柱沿所述第 一方向延伸的侧壁的所述参考层；形成环绕所述参考层远离所述电连接柱的侧壁的所述隧穿层；形成环绕所述隧穿层远离所述参考层的侧壁的所述自由层；形成至少环绕所述自由层远离所述隧穿层的侧壁的所述覆盖层。
在一些实施例中，在形成所述自由层之后，在形成所述覆盖层之前，还包括：形成第一隔离层，所述第一隔离层覆盖所述参考层、所述隧穿层和所述自由层共同构成的远离所述基底的顶面，所述覆盖层还环绕所述第一隔离层沿所述第一方向延伸的侧壁。
在一些实施例中，形成所述第一数据线的步骤包括：形成覆盖所述第一隔离层和所述覆盖层共同构成的远离所述基底的顶面的所述第一数据线；或者，形成覆盖所述第一隔离层和所述覆盖层共同构成的远离所述基底的顶面，且覆盖所述覆盖层远离所述电连接柱的侧壁的所述第一数据线。
在一些实施例中，沿垂直于所述第一方向的方向上，所述电连接柱具有相对的两个侧壁，形成所述磁性隧道结的步骤包括：形成覆盖所述两个侧壁中的一者的所述参考层；形成覆盖所述参考层远离所述电连接柱的一侧的所述隧穿层；形成覆盖所述隧穿层远离所述参考层的一侧的所述自由层；形成覆盖所述自由层远离所述隧穿层的一侧的所述覆盖层；形成所述第一数据线的步骤包括：形成覆盖所述覆盖层远离所述自由层的一侧的所述第一数据线。
在一些实施例中，形成所述电连接柱的步骤包括：沿所述参考层指向所述自由层的方向上，在所述电连接块远离所述晶体管的顶面形成依次排列的第一电连接柱、介质层和第二电连接柱。
在一些实施例中，形成所述磁性隧道结的步骤包括：在所述第一电连接柱远离所述介质层的侧壁形成一所述参考层，在所述第二电连接柱远离所述介质层的侧壁形成另一所述参考层；在每一所述参考层远离所述介质层的一侧形成所述隧穿层；在每一所述隧穿层远离所述参考层的一侧形成所述自由层；在每一所述自由层远离所述隧穿层的一侧形成所述覆盖层。
本公开实施例提供的技术方案至少具有以下优点：
基底指向磁性隧道结的方向为第一方向，磁性隧道结中的参考层、隧穿层、自由层和覆盖层沿垂直于第一方向的方向依次排列，即沿平行于基底表面的方向依次排列，以提供一种新的磁性隧道结中各膜层的布局方式。而且，参考层、隧穿层、自由层和覆盖层均沿第一方向延伸，使得磁性隧道结中自由层的磁场方向的改变趋势易于控制，其中，参考层的磁矩方向为第一方向，自由层的自旋磁矩方向在平行于第一方向的平面内变化，使得自由层的磁场方向相对于参考层的磁场方向转变的角度易于控制，而且，有利于增大沿第一方向延伸的自由层的自旋磁矩方向变化的空间，以及有利于保证自由层在垂直于第一方向的方向上的厚度较薄，以降低自由层在基底表面的布局面积。此外，磁性隧道结中还包括与自由层接触连接的覆盖层，在提供给自由层的电荷流的大小一定时，覆盖层有利于增大自由层的自旋磁矩方向转变的角度，使得在给自由层提供较小的电荷流的情形下，磁性隧道结的电阻值可以发生较大的改变，以提高磁性隧道结反转前后的电阻差异，提升磁性隧道结的电学性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的半导体结构的一种局部剖视结构示意图；
图2为图1所示结构的一种局部俯视结构示意图；
图3为图1所示结构中磁性隧道结的一种局部立体结构示意图；
图4和图5为本公开一实施例提供的半导体结构的另外两种局部剖视结构示意图；
图6为图4或图5所示结构的一种局部俯视结构示意图；
图7为本公开一实施例提供的半导体结构的又一种局部剖视结构示意图；
图8为图7所示结构的一种局部俯视结构示意图；
图9为本公开一实施例提供的半导体结构的再一种局部剖视结构示意图；
图10为图9所示结构的一种局部俯视结构示意图；
图11至图15为本公开另一实施例提供的半导体结构的制造方法各步骤对应的结构示意图。
具体实施方式
经分析发现，将基底指向MTJ的方向为第一方向，MTJ中参考层、隧穿层和自由层依次沿第一方向排列，即沿垂直于基底表面的方向上，在基底上依次堆叠参考层、隧穿层和自由层，以形成MTJ。
在一些情况中，参考层的磁矩方向平行于基底表面，即垂直于第一方向，自由层的自旋磁矩方向在平行于基底表面的平面中翻转，以改变MTJ的电阻值。然而，在自由层的自旋磁矩方向在平行于基底表面的平面中翻转的情况下，MTJ中易出现涡流效应，使得MTJ发热，降低MTJ的性能，且对MTJ造成电干扰。
在另一些情况中，参考层的磁矩方向垂直于基底表面，即第一方向，自由层的自旋磁矩方向在垂直于基底表面的平面中翻转，如此，自由层的自旋磁矩方向的翻转空间受到自由层在第一方向上的厚度的影响，容易导致自由层的自旋磁矩方向翻转不完全，为增加自由层的自旋磁矩方向的翻转空间，需要增大自由层在第一方向上的厚度，从而使得MTJ整体在第一方向上的厚度过大，不利于降低MTJ在MRAM中的布局空间。
本公开实施提供一种半导体结构及其制造方法，基底指向磁性隧道结的方向为第一方向，磁性隧道结中的参考层、隧穿层、自由层和覆盖层沿垂直于第一方向的方向依次排列，即沿平行于基底表面的方向依次排列，以提供一种新的磁性隧道结中各膜层的布局方式。而且，参考层、隧穿层、自由层和覆盖层均沿第一方向延伸，使得磁性隧道结中自由层的磁场方向的改变趋势易于控制，其中，参考层的磁矩方向为第一方向，自由层的自旋磁矩方向在平行于第一方向的平面内变化，使得自由层的磁场方向相对于参考层的磁场方向转变的角度易于控制，而且，有利于增大沿第一方向延伸的自由层的自旋磁矩方向变化的空间，以及有利于保证自由层在垂直于第一方向的方向上的厚度较薄，以降低自由层在基底表面的布局面积。此外，磁性隧道结中还包括与自由层接触连接的覆盖层，在提供给自由层的电荷流的大小一定时，覆盖层有利于增大自由层的自旋磁矩方向转变的角度，使得在给自由层提供较小的电荷流的情形下，磁性隧道结的电阻值可以发生较大的改变，以提高磁性隧道结反转前后的电阻差异，提升磁性隧道结的电学性能。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
本公开一实施例提供一种半导体结构，以下将结合附图对本公开一实施例提供的半导体结构进行详细说明。图1为本公开一实施例提供的半导体结构的一种局部剖视结构示意图；图2为图1所示结构的一种局部俯视结构示意图；图3为图1所示结构中磁性隧道结的一种局部立体结构示意图；图4和图5为本公开一实施例提供的半导体结构的另外两种局部剖视 结构示意图；图6为图4或图5所示结构的一种局部俯视结构示意图；图7为本公开一实施例提供的半导体结构的又一种局部剖视结构示意图；图8为图7所示结构的一种局部俯视结构示意图；图9为本公开一实施例提供的半导体结构的再一种局部剖视结构示意图；图10为图9所示结构的一种局部俯视结构示意图。
参考图1至图10，半导体结构包括：基底100以及位于基底100上的磁性隧道结101；其中，基底100指向磁性隧道结101的方向为第一方向X，沿垂直于第一方向X的方向上，磁性隧道结101包括依次排列的参考层111、隧穿层121、自由层131和覆盖层141，参考层111、隧穿层121、自由层131和覆盖层141均沿第一方向X延伸，参考层111的磁矩方向为第一方向X，自由层131的自旋磁矩方向在平行于第一方向X的平面内变化；第一数据线102，与覆盖层141接触连接，被配置为，通过覆盖层141控制自由层131的自旋磁矩方向。
可以理解的是，参考层111、隧穿层121、自由层131和覆盖层141沿垂直于第一方向X的方向依次排列，以提供一种新的磁性隧道结101中各膜层的布局方式。而且，参考层111、隧穿层121、自由层131和覆盖层141均沿第一方向X延伸，其中，参考层111的磁矩方向为第一方向X，自由层131的自旋磁矩方向在平行于第一方向X的平面内变化，有利于增大沿第一方向X延伸的自由层131的自旋磁矩方向变化的空间，以提高磁性隧道结101反转前后的电阻差异，提升磁性隧道结101的电学性能，以及有利于保证自由层131在垂直于第一方向X的方向上的厚度较薄，以降低自由层131在基底100表面的布局面积。此外，磁性隧道结101中还包括与自由层131接触连接的覆盖层141，在提供给自由层131的电荷流的大小一定时，覆盖层141有利于增大自由层131的自旋磁矩方向转变的角度，使得在给自由层131提供较小的电荷流的情形下，磁性隧道结101的电阻值可以发生较大的改变，以提高磁性隧道结101的电学性能。
而且，参考层111的磁矩方向为第一方向X，即垂直于基底100表面的方向，自由层131的自旋磁矩方向在平行于第一方向X的平面内变化，有利于避免在磁性隧道结101中发生涡流效应，有利于避免磁性隧道结101过热，以避免磁性隧道结101的电学性能下降以及电学性能降低。
以下将结合附图对本公开实施例进行更为详细的说明。
在一些实施例中，参考层111的材料和自由层131的材料均包括钴铁硼、钴或镍铁中的至少一种，隧穿层121的材料可以为氧化镁。
在一些实施例中，参考图1、图4、图5、图7和图9，半导体结构还可以包括：位于基底100中的晶体管110以及与晶体管110的源极或漏极接触连接的电连接块120，参考层111和电连接块120电连接。
可以理解的是，晶体管110用于导通对磁性隧道结101进行写操作或读操作的电流路径。参考层111和电连接块120电连接包括以下两种情形：参考层111和电连接块120直接接触连接，或者，参考层111和电连接块120之间通过导电结构实现电连接，后续会对上述两种情形进行详细描述。
在一些实施例中，继续参考图1、图4、图5、图7和图9，晶体管110的源极和漏极中的一者与电连接块120接触连接，半导体结构还可以包括：第二数据线130，与晶体管110的源极和漏极中的另一者接触连接；第三数据线140，与晶体管110的沟道区正对，被配置为，控制晶体管110处于导通状态或关断状态。
可以理解的是，第二数据线130可以为选择控制线，第三数据线140可以为字线。在一个例子中，晶体管110的源极与电连接块120接触连接，晶体管110的漏极与第二数据线130接触连接；在另一个例子中，晶体管110的漏极与电连接块120接触连接，晶体管110的源极与第二数据线130接触连接。
以下对参考层111和电连接块120之间实现电连接的具体方式进行详细说明。
在一些实施例中，参考图1至图3，参考层111和电连接块120直接接触连接，参考层111在基底100上的正投影位于电连接块120在基底100上的正投影中，参考层111为条状结构，隧穿层121环绕条状结构沿第一方向X延伸的侧壁，自由层131环绕隧穿层121远离参考层111的侧壁，覆盖层141至少环绕自由层131远离隧穿层121的侧壁。
其中，参考层111在基底100上的正投影为第一投影，电连接块120在基底100上的正投影为第二投影，第一投影的面积可以小于或等于第二投影的面积。
可以理解的是，参考层111、隧穿层121、自由层131和覆盖层141均可以为沿第一方向X上延伸的薄膜层，在保证自由层131的自旋磁矩方向翻转的空间较大的同时，有利于降低磁性隧道结101在基底100表面的布局面积，从而有利于降低磁性隧道结101整体的尺寸，以提高磁性隧道结101在半导体结构中的集成密度。
需要说明的是，图2中仅示意出半导体结构的局部俯视结构示意图，图3中仅示意出单个磁性隧道结101的局部立体结构示意图。此外，图3中以参考层111为圆柱，隧穿层121、自由层131和覆盖层141为依次环绕参考层111的圆环状结构为示例，在实际应用中，参考层111也可以为沿第一方向X延伸的其它条状结构，例如方形柱，隧穿层121、自由层131和覆盖层141中的至少一者也可以为其他环状结构，例如方形环。
在一些实施例中，继续参考图1至图3，第一数据线102至少位于覆盖层141远离基底100的顶面，第一数据线102与参考层111之间具有间隔；半导体结构还包括：第一隔离层103，位于第一数据线102与参考层111之间，覆盖层141还环绕第一隔离层103沿第一方向X延伸的侧壁；电连接块120，与参考层111远离第一隔离层103的一侧接触连接；第二隔离层113，位于电连接块120和自由层131之间，且位于电连接块120和覆盖层141之间。
需要说明的是，图1中以第一隔离层103位于参考层111、隧穿层121和自由层131共同构成的远离基底100的顶面为示例，如此，以实现第一数据线102与参考层111之间的电绝缘，以及有利于简化第一隔离层103的制备方法。在实际应用中，对隧穿层121远离基底100的顶面和自由层131远离基底100的顶面是否具有第一隔离层103不做限制，只需满足第一隔离层103位于第一数据线102与参考层111之间，以实现第一数据线102与参考层111之间的电绝缘即可。
此外，图1中以第一数据线102位于第一隔离层103和覆盖层141共同构成的远离基底100的顶面为示例，在实际应用中，对第一隔离层103远离基底100的顶面是否具有第一数据线102不做限制，只需满足第一数据线102位于覆盖层141远离基底100的顶面，以实现第一数据线102和覆盖层141之间的电连接即可。
此外，图1中以第二隔离层113位于隧穿层121、自由层131和覆盖层141共同构成的靠近基底100的底面与基底100之间为示例，如此，以实现自由层131和覆盖层141两者与电连接块120之间的电绝缘，以及有利于简化第二隔离层113的制备方法。在实际应用中，对隧穿层121靠近基底100的底面与基底100之间是否具有第二隔离层113不做限制，只需满足第二隔离层113位于电连接块120与自由层131之间以及位于电连接块120与覆盖层141之间，以实现自由层131和覆盖层141两者与电连接块120之间的电绝缘即可。
此外，图1中以覆盖层141还环绕第一隔离层103沿第一方向X延伸的侧壁为示例，在实际应用中，覆盖层141可以仅环绕自由层131远离隧穿层121的侧壁，第一数据线102可以环绕第一隔离层103沿第一方向X延伸的侧壁，以实现覆盖层141和第一数据线102之间的接触连接。
在一些实施例中，第一隔离层103的材料和第二隔离层113的材料均可以为氧化硅、 氮化硅或者氮氧化硅等绝缘材料中的至少一种。
在另一些实施例中，参考图4至图10，半导体结构还可以包括：沿第一方向延X伸的电连接柱105，与电连接块120接触连接，参考层111位于电连接柱105沿第一方向X上延伸的至少部分侧壁，电连接柱105在基底100上的正投影覆盖电连接块120在基底100上的正投影。可以理解的是，参考层111和电连接块120之间通过电连接柱105实现电连接。
以下对半导体结构中包括电连接柱105时，磁性隧道结101的构造进行详细说明。
在一些实施例中，参考图4至图6，参考层111可以为环状结构，隧穿层121环绕环状结构沿第一方向X延伸的外侧壁，自由层131环绕隧穿层121远离参考层111的侧壁，覆盖层141至少环绕自由层131远离隧穿层121的侧壁。
可以理解的是，参考层111、隧穿层121、自由层131和覆盖层141均可以为沿第一方向X上延伸的环状薄膜层，在保证自由层131的自旋磁矩方向翻转的空间较大的同时，有利于降低磁性隧道结101在基底100表面的布局面积，从而有利于降低磁性隧道结101整体的尺寸，以提高磁性隧道结101在半导体结构中的集成密度。
需要说明的是，图6中仅示意出半导体结构的局部俯视结构示意图，图6可以为图4或图5中半导体结构不包括第一隔离层103和第一数据线102的俯视结构示意图。此外，图6中以参考层111、隧穿层121、自由层131和覆盖层141为依次环绕电连接柱105的方形环状结构为示例，在实际应用中，参考层111、隧穿层121、自由层131和覆盖层141中的至少一者也可以为沿第一方向X延伸的其它环状结构，例如圆形环。
在一些实施例中，第一数据线102至少位于覆盖层141远离基底100的顶面，第一数据线102与参考层111和电连接柱105之间具有间隔；半导体结构还包括：第一隔离层103，位于第一数据线102与参考层111之间，以及位于第一数据线102与电连接柱105之间，覆盖层141还环绕第一隔离层103沿第一方向X延伸的侧壁。
需要说明的是，图4和图5中以第一隔离层103位于电连接柱105、参考层111、隧穿层121和自由层131共同构成的远离基底100的顶面为示例，如此，以实现第一数据线102与参考层111之间的电绝缘，以及第一数据线102与电连接柱105之间的电绝缘，以及有利于简化第一隔离层103的制备方法。在实际应用中，对隧穿层121远离基底100的顶面和自由层131远离基底100的顶面是否具有第一隔离层103不做限制，只需满足第一隔离层103位于第一数据线102与参考层111之间，以及位于第一数据线102与电连接柱105之间，以实现第一数据线102与参考层111和电连接柱105之间的电绝缘即可。
此外，图4和图5中以覆盖层141还环绕第一隔离层103沿第一方向X延伸的侧壁为示例，在实际应用中，覆盖层141可以仅环绕自由层131远离隧穿层121的侧壁，第一数据线102可以环绕第一隔离层103沿第一方向X延伸的侧壁，以实现覆盖层141和第一数据线102之间的接触连接。
第一数据线102至少位于覆盖层141远离基底100的顶面至少包括以下两种实施例：
在一些实施例中，参考图4，第一数据线102位于第一隔离层103和覆盖层141共同构成的远离基底100的顶面。
在另一些实施例中，参考图5，第一数据线102在位于覆盖层141远离基底100的顶面的同时，第一数据线102还覆盖覆盖层141远离自由层131的侧壁。
需要说明的是，图4和图5中均以第一数据线102位于第一隔离层103和覆盖层141共同构成的远离基底100的顶面为示例，在实际应用中，对第一隔离层103远离基底100的顶面是否具有第一数据线102不做限制，只需满足第一数据线102位于覆盖层141远离基底100的顶面，以实现第一数据线102和覆盖层141之间的电连接即可。
在一些实施例中，第一隔离层103的材料可以为氧化硅、氮化硅或者氮氧化硅等绝缘材料中的至少一种。
在另一些实施例中，参考图7至图10，参考层111可以为条状结构，隧穿层121覆盖参考层111远离电连接柱105的侧壁，自由层131覆盖隧穿层121远离参考层111的侧壁，覆盖层141覆盖自由层131远离隧穿层121的侧壁。
以下通过两种实施例对半导体结构包括电连接柱105时，参考层111为条状结构进行详细说明。
在一些实施例中，参考图7和图8，沿垂直于第一方向X的方向上，电连接柱105具有相对的第一侧和第二侧，参考层111位于电连接柱105的第一侧或第二侧，一个磁性隧道结101与一个电连接柱105对应，使得一个晶体管110与一个磁性隧道结101对应。
在另一些实施例中，参考图9和图10，沿参考层111指向自由层131的方向上，电连接柱105包括依次排列的第一电连接柱115、介质层125和第二电连接柱135，一参考层111覆盖第一电连接柱115远离介质层125的侧壁，另一参考层111覆盖第二电连接柱135远离介质层125的侧壁，一晶体管110与两个磁性隧道结101对应。
可以理解的是，介质层125用于实现第一电连接柱115和第二电连接柱135之间的电绝缘，两个磁性隧道结101与同一电连接柱105对应，使得一个晶体管110与两个磁性隧道结101对应。
在上述两种实施例中，参考老图7和图9，第一数据线102覆盖覆盖层141远离自由层131的侧壁。
上述各种实施例中，参考图1至图10，参考层111、隧穿层121、自由层131和覆盖层141的排列方向第二方向Y，第一数据线102沿第三方向Z延伸，第一方向X、第二方向Y和第三方向Z两两相交，第一数据线102与沿第三方向Z间隔排布的多个磁性隧道结101对应。可以理解的是，第一数据线102可以为位线，位线通过覆盖层141实现与自由层131的电连接，以控制自由层131中自旋磁矩方向的翻转，一条位线可以控制沿第三方向Z间隔排布的多个磁性隧道结101。
需要说明的是，图1、图2和图4至图10中均以沿第二方向Y上间隔排布有2个磁性隧道结101，沿第三方向Z上间隔排布有2个磁性隧道结101为示例。在实际应用中，对沿第二方向Y上间隔排布的磁性隧道结101的数量不做限制，例如数量可以为1个、3个或8个等，而且对沿第三方向Z上间隔排布的磁性隧道结101的数量也不做限制，例如数量可以为1个、4个或7个等。
此外，图2中一第二隔离层113与一磁性隧道结101对应为示例，在实际应用中，多个磁性隧道结101可以共用一第二隔离层113，或者，一第二隔离层113沿第二方向Y延伸，与沿第二方向Y上间隔排布的多个磁性隧道结101对应，或者，一第二隔离层113沿第三方向Z延伸，与沿第三方向Z上间隔排布的多个磁性隧道结101对应。
综上所述，本公开一实施例提供一种新的磁性隧道结101中各膜层的布局方式。而且，参考层111的磁矩方向垂直于基底100表面，即第一方向X，自由层131的自旋磁矩方向在平行于第一方向X的平面内变化，有利于增大沿第一方向X延伸的自由层131的自旋磁矩方向变化的空间，以提高磁性隧道结101的电学性能，以及有利于保证自由层131在垂直于第一方向X的方向上的厚度较薄，以降低自由层131在基底100表面的布局面积，而且，有利于避免在磁性隧道结101中发生涡流效应，以避免磁性隧道结101过热，从而避免磁性隧道结101的电学性能下降。此外，在提供给自由层131的电荷流的大小一定时，覆盖层141有利于增大自由层131的自旋磁矩方向转变的角度，使得在给自由层131提供较小的电荷流的情形下，磁性隧道结101的电阻值可以发生较大的改变，从而有利于提高磁性隧道结的电学 性能。
本公开另一实施例还提供一种半导体结构的制造方法，用于制造本公开一实施例提供的半导体结构，以下将结合图1至图15对本公开另一实施例提供的半导体结构的制造方法进行详细说明。图11至图15为本公开另一实施例提供的半导体结构的制造方法各步骤对应的结构示意图。需要说明的是，与前述实施例相同或相应的部分在此不再赘述，此外，图11至图15均为半导体结构的局部结构示意图。
参考图1至图15，半导体结构的制造方法包括：提供基底100；在基底100上形成磁性隧道结101，其中，基底100指向磁性隧道结101的方向为第一方向X，沿垂直于第一方向X的方向上，磁性隧道结101包括依次排列的参考层111、隧穿层121、自由层131和覆盖层141，参考层111、隧穿层121、自由层131和覆盖层141均沿第一方向X延伸，参考层111的磁矩方向为第一方向X，自由层131的自旋磁矩方向在平行于第一方向X的平面内变化；形成与覆盖层141接触连接的第一数据线102，第一数据线102被配置为，通过覆盖层141控制自由层131的自旋磁矩方向。
以下结构附图对半导体结构的制造方法进行详细说明。
提供基底100至少包括以下两种实施例：
在一些实施例中，提供基底100包括如下步骤：
参考图11，在基底100中形成晶体管110以及与晶体管110的源极或漏极接触连接的电连接块120。
形成磁性隧道结101包括如下步骤：
继续参考图11，形成条状结构的参考层111，参考层111与电连接块120一一对应。
参考图12和图13，形成第二隔离层113，第二隔离层113和参考层111共同覆盖电连接块120远离晶体管110的顶面。
形成第二隔离层113至少包括以下两种实施例：
在一些实施例中，参考图12，形成初始第二隔离层123，初始第二隔离层123和参考层111共同覆盖基底100的表面；参考图13，对初始第二隔离层123进行图形化处理，以形成第二隔离层113，需要说明的是，图13仅为对初始第二隔离层123进行图形化处理的一种示例，实际应用中，对初始第二隔离层123被图形化处理后形成的第二隔离层113不做限制，只需满足第二隔离层113位于每一电连接块120与每一自由层131之间以及位于每一电连接块120与每一覆盖层141之间即可。
在另一些实施例中，形成的第二隔离层113和参考层111共同覆盖基底100的表面，可以理解为不对初始第二隔离层123进行图形化处理。
参考图13，形成隧穿层121，隧穿层121环绕条状结构沿第一方向X延伸的侧壁；形成自由层131，自由层131环绕隧穿层121远离参考层111的侧壁。
参考图1，形成覆盖层141，覆盖层141至少环绕自由层131远离隧穿层121的侧壁。
在一些实施例中，参考图1，在形成自由层131之后，在形成覆盖层141之前，还包括：形成第一隔离层103，后续对第一隔离层103的形成方法进行详细说明。
在另一些实施例中，提供基底100包括如下步骤：
参考图14，在基底100中形成晶体管110以及与晶体管110的源极或漏极接触连接的电连接块120。
参考图14、图15和图4，在形成电连接块120之后，在形成磁性隧道结101之前， 制造方法还可以包括：在电连接块120远离晶体管110的顶面形成电连接柱105，电连接柱105沿第一方向X延伸，电连接柱105与电连接块120一一对应，且电连接柱105在基底100上的正投影覆盖电连接块120在基底100上的正投影。
在一些实施例中，参考图15，形成电连接柱105的方法包括：在基底100的表面形成沿垂直于第一方向X的方向，例如第三方向Z延伸的初始电连接柱145，对初始电连接柱145进行图像化处理，以形成于电连接块120(参考图14)一一对应的电连接柱105。
在一些实施例中，一个电连接柱105可以与一个磁性隧道结101对应，形成磁性隧道结101的方法至少包括以下两种实施例：
在一些实施例中，参考图4和图5，形成磁性隧道结101的步骤包括：形成环绕电连接柱105沿第一方向X延伸的侧壁的参考层111；形成环绕参考层111远离电连接柱105的侧壁的隧穿层121；形成环绕隧穿层121远离参考层111的侧壁的自由层131；形成至少环绕自由层131远离隧穿层121的侧壁的覆盖层141。
在另一些实施例中，参考图7和图8，形成磁性隧道结101的步骤包括：沿垂直于第一方向X的方向上，电连接柱105具有相对的第一侧和第二侧，在电连接柱105的第一侧或第二侧形成条状结构的参考层111；形成覆盖参考层111远离电连接柱105的侧壁的隧穿层121，形成覆盖隧穿层121远离参考层111的侧壁的自由层131；形成覆盖自由层131远离隧穿层121的侧壁的覆盖层141。
在上述各种实施例中，参考图1、图4或图5，在形成自由层131之后，在形成覆盖层141之前，制造方法还可以包括：形成第一隔离层103，第一隔离层103覆盖参考层111、隧穿层121和自由层131共同构成的远离基底100的顶面，覆盖层141还环绕第一隔离层103沿第一方向X延伸的侧壁。
在上述各种实施例中，形成第一数据线102的步骤可以包括：参考图1或图4，形成覆盖第一隔离层103和覆盖层141共同构成的远离基底100的顶面的第一数据线102；或者，参考图5，形成覆盖第一隔离层103和覆盖层141共同构成的远离基底100的顶面，且覆盖覆盖层141远离电连接柱105的侧壁的第一数据线102。
在一些实施例中，同一电连接柱105可以与两个磁性隧道结101对应，参考图9和图10，沿垂直于第一方向X的方向上，电连接柱105具有相对的两个侧壁，形成磁性隧道结101的步骤包括：形成覆盖两个侧壁中的一者的参考层111；形成覆盖参考层111远离电连接柱105的一侧的隧穿层121；形成覆盖隧穿层121远离参考层111的一侧的自由层131；形成覆盖自由层131远离隧穿层121的一侧的覆盖层141；形成第一数据线102的步骤包括：形成覆盖覆盖层141远离自由层131的一侧的第一数据线102。
在一些实施例中，继续参考图9和图10，形成电连接柱105的步骤包括：沿参考层111指向自由层131的方向上，在电连接块120远离晶体管110的顶面形成依次排列的第一电连接柱115、介质层125和第二电连接柱135。需要说明的是，本公开另一实施例对如何形成第一电连接柱115、介质层125和第二电连接柱135的具体方法不做限制。
在一些实施例中，继续参考图9和图10，形成磁性隧道结101的步骤包括：在第一电连接柱115远离介质层125的侧壁形成一参考层111，在第二电连接柱135远离介质层125的侧壁形成另一参考层111；在每一参考层111远离介质层125的一侧形成隧穿层121；在每一隧穿层121远离参考层111的一侧形成自由层131；在每一自由层131远离隧穿层121的一侧形成覆盖层141。
在上述各种实施例中，形成的第一数据线102还可以沿第三方向Z延伸，即一第一数据线102与沿第三方向Z间隔排布的多个磁性隧道结101对应。
综上所述，本公开另一实施例提供的制造方法中，需要形成的参考层111、隧穿层121、 自由层131和覆盖层141均沿第一方向X延伸，有利于简化形成磁性隧道结101的工艺步骤，以及降低形成磁性隧道结101的工艺难度。而且，沿垂直于第一方向X的方向上，参考层111、隧穿层121、自由层131和覆盖层141四者的厚度均易于控制和调整。此外，本公开另一实施例提供的制造方法形成的半导体结构中，自由层131的自旋磁矩方向在平行于第一方向X的平面内变化，有利于增大沿第一方向X延伸的自由层131的自旋磁矩方向变化的空间，以提高磁性隧道结101的电学性能，以及有利于保证自由层131在垂直于第一方向X的方向上的厚度较薄，以降低自由层131在基底100表面的布局面积，而且，有利于避免在磁性隧道结101中发生涡流效应，以避免磁性隧道结101过热，从而避免磁性隧道结101的电学性能下降以及电学性能降低。此外，在提供给自由层131的电荷流的大小一定时，覆盖层141有利于增大自由层131的自旋磁矩方向转变的角度，使得在给自由层131提供较小的电荷流的情形下，磁性隧道结101的电阻值可以发生较大的改变，从而有利于提高磁性隧道结的电学性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各种改动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (22)

  1. 一种种半导体结构，包括：
    基底以及位于所述基底上的磁性隧道结；
    其中，所述基底指向所述磁性隧道结的方向为第一方向，沿垂直于所述第一方向的方向上，所述磁性隧道结包括依次排列的参考层、隧穿层、自由层和覆盖层，所述参考层、所述隧穿层、所述自由层和所述覆盖层均沿所述第一方向延伸，所述参考层的磁矩方向为所述第一方向，所述自由层的自旋磁矩方向在平行于所述第一方向的平面内变化；
    第一数据线，与所述覆盖层接触连接，被配置为，通过所述覆盖层控制所述自由层的自旋磁矩方向。
  2. 如权利要求1所述的半导体结构，其中，所述参考层为条状结构，所述隧穿层环绕所述条状结构沿所述第一方向延伸的侧壁，所述自由层环绕所述隧穿层远离所述参考层的侧壁，所述覆盖层至少环绕所述自由层远离所述隧穿层的侧壁。
  3. 如权利要求2所述的半导体结构，其中，所述第一数据线至少位于所述覆盖层远离所述基底的顶面，所述第一数据线与所述参考层之间具有间隔；所述半导体结构还包括：
    第一隔离层，位于所述第一数据线与所述参考层之间，所述覆盖层还环绕所述第一隔离层沿所述第一方向延伸的侧壁；
    电连接块，与所述参考层远离所述第一隔离层的一侧接触连接；
    第二隔离层，位于所述电连接块和所述自由层之间，且位于所述电连接块和所述覆盖层之间。
  4. 如权利要求1所述的半导体结构，还包括：
    位于所述基底中的晶体管以及与所述晶体管的源极或漏极接触连接的电连接块，所述参考层和所述电连接块电连接。
  5. 如权利要求4所述的半导体结构，其中，所述晶体管的源极和漏极中的一者与所述电连接块接触连接，所述半导体结构还包括：
    第二数据线，与所述晶体管的源极和漏极中的另一者接触连接；
    第三数据线，与所述晶体管的沟道区正对，被配置为，控制所述晶体管处于导通状态或关断状态。
  6. 如权利要求4所述的半导体结构，还包括：沿所述第一方向延伸的电连接柱，与所述电连接块接触连接，所述参考层位于所述电连接柱沿所述第一方向上延伸的至少部分侧壁，所述电连接柱在所述基底上的正投影覆盖所述电连接块在所述基底上的正投影。
  7. 如权利要求6所述的半导体结构，其中，所述参考层为环状结构，所述隧穿层环绕所述环状结构沿所述第一方向延伸的外侧壁，所述自由层环绕所述隧穿层远离所述参考层的侧壁，所述覆盖层至少环绕所述自由层远离所述隧穿层的侧壁。
  8. 如权利要求7所述的半导体结构，其中，所述第一数据线至少位于所述覆盖层远离所述基底的顶面，所述第一数据线与所述参考层和所述电连接柱之间具有间隔；所述半导体结构还包括：
    第一隔离层，位于所述第一数据线与所述参考层之间，以及位于所述第一数据线与所述电连接柱之间，所述覆盖层还环绕所述第一隔离层沿所述第一方向延伸的侧壁。
  9. 如权利要求8所述的半导体结构，其中，所述第一数据线还覆盖所述覆盖层远离所述自 由层的侧壁。
  10. 如权利要求6所述的半导体结构，其中，所述参考层为条状结构，所述隧穿层覆盖所述参考层远离所述电连接柱的侧壁，所述自由层覆盖所述隧穿层远离所述参考层的侧壁，所述覆盖层覆盖所述自由层远离所述隧穿层的侧壁。
  11. 如权利要求10所述的半导体结构，其中，沿所述参考层指向所述自由层的方向上，所述电连接柱包括依次排列的第一电连接柱、介质层和第二电连接柱，一所述参考层覆盖所述第一电连接柱远离所述介质层的侧壁，另一所述参考层覆盖所述第二电连接柱远离所述介质层的侧壁，一所述晶体管与两个所述磁性隧道结对应。
  12. 如权利要求10或11所述的半导体结构，其中，所述第一数据线覆盖所述覆盖层远离所述自由层的侧壁。
  13. 如权利要求2或6所述的半导体结构，其中，所述参考层、所述隧穿层、所述自由层和所述覆盖层的排列方向第二方向，所述第一数据线沿第三方向延伸，所述第一方向、所述第二方向和所述第三方向两两相交，所述第一数据线与沿所述第三方向间隔排布的多个所述磁性隧道结对应。
  14. 一种半导体结构的制造方法，包括：
    提供基底；
    在所述基底上形成磁性隧道结，其中，所述基底指向所述磁性隧道结的方向为第一方向，沿垂直于所述第一方向的方向上，所述磁性隧道结包括依次排列的参考层、隧穿层、自由层和覆盖层，所述参考层、所述隧穿层、所述自由层和所述覆盖层均沿所述第一方向延伸，所述参考层的磁矩方向为所述第一方向，所述自由层的自旋磁矩方向在平行于所述第一方向的平面内变化；
    形成与所述覆盖层接触连接的第一数据线，所述第一数据线被配置为，通过所述覆盖层控制所述自由层的自旋磁矩方向。
  15. 如权利要求14所述的制造方法，其中，提供所述基底的步骤包括：
    在所述基底中形成晶体管以及与所述晶体管的源极或漏极接触连接的电连接块；
    形成所述磁性隧道结的步骤包括：
    形成条状结构的所述参考层，所述参考层与所述电连接块一一对应；
    形成第二隔离层，所述第二隔离层和所述参考层共同覆盖所述电连接块远离所述晶体管的顶面；
    形成隧穿层，所述隧穿层环绕所述条状结构沿所述第一方向延伸的侧壁；
    形成自由层，所述自由层环绕所述隧穿层远离所述参考层的侧壁；
    形成覆盖层，所述覆盖层至少环绕所述自由层远离所述隧穿层的侧壁。
  16. 如权利要求14所述的制造方法，其中，提供所述基底的步骤包括：
    在所述基底中形成晶体管以及与所述晶体管的源极或漏极接触连接的电连接块；
    在形成所述电连接块之后，在形成所述磁性隧道结之前，还包括：
    在所述电连接块远离所述晶体管的顶面形成电连接柱，所述电连接柱沿所述第一方向延伸，所述电连接柱与所述电连接块一一对应，且所述电连接柱在所述基底上的正投影覆盖所述电连接块在所述基底上的正投影。
  17. 如权利要求16所述的制造方法，其中，形成所述磁性隧道结的步骤包括：
    形成环绕所述电连接柱沿所述第一方向延伸的侧壁的所述参考层；
    形成环绕所述参考层远离所述电连接柱的侧壁的所述隧穿层；
    形成环绕所述隧穿层远离所述参考层的侧壁的所述自由层；
    形成至少环绕所述自由层远离所述隧穿层的侧壁的所述覆盖层。
  18. 如权利要求15或17所述的制造方法，其中，在形成所述自由层之后，在形成所述覆盖层之前，还包括：
    形成第一隔离层，所述第一隔离层覆盖所述参考层、所述隧穿层和所述自由层共同构成的远离所述基底的顶面，所述覆盖层还环绕所述第一隔离层沿所述第一方向延伸的侧壁。
  19. 如权利要求18所述的制造方法，其中，形成所述第一数据线的步骤包括：
    形成覆盖所述第一隔离层和所述覆盖层共同构成的远离所述基底的顶面的所述第一数据线；或者，形成覆盖所述第一隔离层和所述覆盖层共同构成的远离所述基底的顶面，且覆盖所述覆盖层远离所述电连接柱的侧壁的所述第一数据线。
  20. 如权利要求16所述的制造方法，其中，沿垂直于所述第一方向的方向上，所述电连接柱具有相对的两个侧壁，形成所述磁性隧道结的步骤包括：
    形成覆盖所述两个侧壁中的一者的所述参考层；
    形成覆盖所述参考层远离所述电连接柱的一侧的所述隧穿层；
    形成覆盖所述隧穿层远离所述参考层的一侧的所述自由层；
    形成覆盖所述自由层远离所述隧穿层的一侧的所述覆盖层；
    形成所述第一数据线的步骤包括：
    形成覆盖所述覆盖层远离所述自由层的一侧的所述第一数据线。
  21. 如权利要求16所述的制造方法，其中，形成所述电连接柱的步骤包括：
    沿所述参考层指向所述自由层的方向上，在所述电连接块远离所述晶体管的顶面形成依次排列的第一电连接柱、介质层和第二电连接柱。
  22. 如权利要求21所述的制造方法，其中，形成所述磁性隧道结的步骤包括：
    在所述第一电连接柱远离所述介质层的侧壁形成一所述参考层，在所述第二电连接柱远离所述介质层的侧壁形成另一所述参考层；
    在每一所述参考层远离所述介质层的一侧形成所述隧穿层；
    在每一所述隧穿层远离所述参考层的一侧形成所述自由层；
    在每一所述自由层远离所述隧穿层的一侧形成所述覆盖层。
PCT/CN2022/125424 2022-09-28 2022-10-14 半导体结构及其制造方法 Ceased WO2024065889A1 (zh)

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