WO2024065405A1

WO2024065405A1 - Charge pump circuit and half-bridge driver circuit

Info

Publication number: WO2024065405A1
Application number: PCT/CN2022/122650
Authority: WO
Inventors: 张晓亮
Original assignee: 舍弗勒技术股份两合公司; 张晓亮
Priority date: 2022-09-29
Filing date: 2022-09-29
Publication date: 2024-04-04

Abstract

The present application provides a charge pump circuit and a half-bridge driver circuit. The charge pump circuit comprises: an input voltage switch circuit which is connected to an input voltage and a charge pump control signal and outputs the input voltage under the control of the charge pump control signal; a regulation voltage generation circuit which is connected to the input voltage and outputs a regulation voltage; a regulation voltage loading control circuit which is connected to both the regulation voltage generation circuit and the charge pump control signal and loads the regulation voltage under the control of the charge pump control signal; and a charging circuit which is connected to all of the input voltage switch circuit, the regulation voltage generation circuit, and the regulation voltage loading control circuit and outputs an output voltage, wherein the output voltage = the input voltage + the regulation voltage. According to the charge pump circuit and the half-bridge driver circuit of the present application, the charge pump circuit is formed by discrete components, the structure is simple, and the cost is low; moreover, parameters can be adjusted according to actual needs, and peripheral applications are flexible and convenient.

Description

Charge pump circuit and half-bridge drive circuit

Technical Field

The present application relates to the field of circuit technology, and in particular to a charge pump circuit and a half-bridge drive circuit.

Background technique

The high side of the power driver adopts the NMOS technology solution, which is usually used in the controller of the drive motor (for example, EPS, MCU, i-Booster electronic brake assist system) and the high side anti-backflow design of the power driver. NMOS has the characteristics of extremely large gate impedance, extremely small drain-source on-resistance and large drain on-current. The conduction condition of NMOS must meet the gate-source voltage difference greater than its gate-source conduction threshold voltage V _GS(th) , and the voltage provided by the charge pump at the gate meets the conduction condition.

At present, the control chip of the power drive often integrates a charge pump, and the output voltage of the charge pump is always greater than the power supply voltage, which is usually constant. The use of a control chip with an integrated boost pump (referred to as an integrated chip) can have the advantages of simple overall circuit and high integration. However, the general parameter characteristics of the integrated chip cannot be adjusted at will, so it brings restrictions to the peripheral application. For example, the integrated chip has a limit on the power supply voltage. When the power supply voltage is greater than the absolute maximum value it can withstand, this is not allowed. Therefore, a charge pump circuit composed of discrete components is needed.

Summary of the invention

Based on the above-mentioned background technical defects, the purpose of this application is to provide a charge pump circuit and a half-bridge drive circuit, which are composed of discrete components, can flexibly adjust parameters, and are convenient for peripheral applications.

In order to achieve the above object, the present application provides a charge pump circuit, which includes:

An input voltage switch circuit is connected to the input voltage and the charge pump control signal, and outputs the input voltage under the control of the charge pump control signal;

A regulating voltage generating circuit, connected to the input voltage and outputting a regulating voltage;

A regulating voltage loading control circuit is connected to both the regulating voltage generating circuit and the charge pump control signal, and loads the regulating voltage under the control of the charge pump control signal;

The charging circuit is connected to the input voltage switch circuit, the regulating voltage generating circuit, and the regulating voltage loading control circuit, has an output terminal as the output of the charge pump circuit, and outputs an output voltage, wherein the output voltage = the input voltage + the regulating voltage.

In one embodiment, the input voltage switch circuit includes a second triode, a third triode, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, the base of the second triode is connected to the charge pump control signal via the seventh resistor, the base of the second triode is also connected to the emitter of the second triode via the sixth resistor, the emitter of the second triode is grounded, the collector of the second triode is connected to the base of the third triode via the fifth resistor, the base of the third triode is connected to the emitter of the third triode via the eighth resistor, the emitter of the third triode is connected to the input voltage, the collector of the third triode outputs the input voltage, the second triode is an NPN triode, and the third triode is a PNP triode; or,

The input voltage switch circuit includes a second MOS tube and a third MOS tube, the gate of the second MOS tube is connected to the charge pump control signal, the source of the second MOS tube is grounded, the drain of the second MOS tube is the gate of the third MOS tube, the source of the third MOS tube is connected to the input voltage, the drain of the third MOS tube outputs the input voltage, the second MOS tube is NMOS, and the third MOS tube is PMOS.

In one embodiment, the regulating voltage generating circuit includes a fourth transistor, a third Zener diode, and a ninth resistor, the collector of the fourth transistor is connected to the input voltage, the collector of the fourth transistor is also connected to the base of the fourth transistor via the ninth resistor, the base of the fourth transistor is also grounded via the third Zener diode, and the emitter of the fourth transistor outputs the regulating voltage.

In one embodiment, the regulating voltage generating circuit further includes a second bypass capacitor, and the emitter of the fourth transistor is grounded via the second bypass capacitor.

In one embodiment, the regulating voltage generating circuit also includes a fourth anti-backflow diode, the positive electrode of the fourth anti-backflow diode is connected to the emitter of the fourth transistor, and the negative electrode of the fourth anti-backflow diode is connected to the charging circuit; the regulating voltage generating circuit also includes a fourth current limiting resistor, the first end of the fourth current limiting resistor is connected to the negative electrode of the fourth anti-backflow diode, and the second end of the fourth current limiting resistor is connected to the charging circuit.

In one embodiment, the regulating voltage generating circuit further includes a voltage regulating resistor, and the voltage regulating resistor is connected between the third Zener diode and the base of the fourth transistor.

In one embodiment, the regulating voltage loading control circuit includes a first transistor, a second resistor, and a third resistor, the base of the first transistor is connected to the charge pump control signal via the third resistor, the base of the first transistor is also connected to the emitter of the first transistor via the second resistor, the emitter of the first transistor is grounded, and the collector of the first transistor is connected to the regulating voltage generating circuit and the charging circuit; or,

The regulating voltage loading control circuit includes a first MOS tube, a gate of the first MOS tube is connected to the charge pump control signal, a source of the first MOS tube is grounded, a drain of the first MOS tube is connected to the regulating voltage generating circuit and the charging circuit, and the first MOS tube is an NMOS.

In one embodiment, the charging circuit includes a first capacitor, a first end of the first capacitor is connected to the input voltage switching circuit and serves as the output end of the charging circuit to output the output voltage, and a second end of the first capacitor is connected to the regulating voltage generating circuit and the regulating voltage loading control circuit.

In one embodiment, the charging circuit further includes a first anti-backflow diode and a second anti-backflow diode, the first end of the first capacitor is connected to the cathode of the first anti-backflow diode, the anode of the first anti-backflow diode is connected to the input voltage switch circuit, the first end of the first capacitor is also connected to the anode of the second anti-backflow diode, and the cathode of the second anti-backflow diode serves as the output end of the charging circuit to output the output voltage;

The charging circuit also includes a first current limiting resistor, the cathode of the second anti-backflow diode is connected to the first end of the first current limiting resistor, and the second end of the first current limiting resistor serves as the output end of the charging circuit to output the output voltage.

The present application also provides a half-bridge drive circuit, which includes: a charge pump circuit and a switch tube, wherein the output end of the charge pump circuit is connected to the gate of the switch tube, the drain of the switch tube is connected to the input voltage, the source of the switch tube is connected to the driven load, the switch tube is NMOS, the half-bridge drive circuit is a high-side drive circuit, and the charge pump circuit is the charge pump circuit described above.

The charge pump circuit and half-bridge drive circuit described in the present application use discrete components to form the charge pump circuit, which has a simple structure and low cost. Moreover, the parameters can be adjusted according to actual needs, and the peripheral application is flexible and convenient.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are for explanation purposes only and are not intended to limit the scope of the present application in any way. In addition, the shapes and proportional dimensions of the components in the drawings are only for illustration purposes and are used to help understand the present application. They do not specifically limit the shapes and proportional dimensions of the components of the present application. Under the guidance of the present application, those skilled in the art can select various possible shapes and proportional dimensions to implement the present application according to specific circumstances. In the drawings:

FIG1 is a schematic diagram of the structure of a half-bridge driving circuit provided in the second embodiment of the present application, wherein the solid line frame is a schematic diagram of the structure of a charge pump circuit provided in the first embodiment of the present application;

FIG2 is a schematic diagram of a simulation effect of a charge pump circuit provided in the first embodiment of the present application;

FIG. 3 is another schematic diagram of simulation effects of a charge pump circuit provided in the first embodiment of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

Referring to FIG. 1 , a first embodiment of the present application provides a charge pump circuit 1, which includes:

An input voltage switch circuit 11 is connected to an input voltage Vbat and a charge pump control signal Vctrl, and outputs the input voltage Vbat under the control of the charge pump control signal Vctrl;

A regulating voltage generating circuit 12 is connected to the input voltage Vbat and outputs a regulating voltage Vb;

A regulating voltage loading control circuit 13 is connected to the regulating voltage generating circuit 12 and the charge pump control signal Vctrl, and loads the regulating voltage Vb under the control of the charge pump control signal Vctrl;

The charging circuit 14 is connected to the input voltage switch circuit 11, the regulating voltage generating circuit 12, and the regulating voltage loading control circuit 13, has an output end serving as the output of the charge pump circuit, and outputs an output voltage Vcp, wherein the output voltage Vcp=the input voltage Vbat+the regulating voltage Vb.

In one embodiment, the input voltage switch circuit 11 includes a second transistor Q2, a third transistor Q3, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The base of the second transistor Q2 is connected to the charge pump control signal Vctrl via the seventh resistor R7, and the charge pump control signal is a PWM signal. The base of the second transistor Q2 is also connected to the emitter of the second transistor Q2 via the sixth resistor R6. The emitter of the second transistor Q2 is grounded. The collector of the second transistor Q2 is connected to the base of the third transistor Q3 via the fifth resistor R5. The base of the third transistor Q3 is connected to the emitter of the third transistor Q3 via the eighth resistor R8. The emitter of the third transistor Q3 is connected to the input voltage Vbat. The collector of the third transistor Q3 outputs the input voltage Vbat. The second transistor is an NPN transistor, and the third transistor is a PNP transistor. Thus, when the charge pump control signal Vctrl is at a high level, the second transistor Q2 is turned on, the third transistor Q3 is also turned on, and the collector voltage of the third transistor Q3 is nearly the input voltage Vbat (the on-voltage of the third transistor Q3 is very small relative to the input voltage Vbat and can be ignored), and the input voltage Vbat is output; when the charge pump control signal Vctrl is at a low level, the second transistor Q2 is turned off, the third transistor Q3 is also turned off, and the collector of the third transistor Q3 has no voltage output. Therefore, in essence, the input voltage switch circuit 11 outputs the input voltage Vbat at intervals under the control of the charge pump control signal Vctrl.

Of course, the input voltage switch circuit 11 may also use a MOS tube instead of a triode. In one embodiment (not shown), the input voltage switch circuit 11 includes a second MOS tube and a third MOS tube, the gate of the second MOS tube is connected to the charge pump control signal, the source of the second MOS tube is grounded, the drain of the second MOS tube is the gate of the third MOS tube, the source of the third MOS tube is connected to the input voltage, the drain of the third MOS tube outputs the input voltage, the second MOS tube is an NMOS, and the third MOS tube is a PMOS. In this way, when the charge pump control signal is at a high level, the second MOS tube is turned on, the third MOS tube is also turned on, the drain voltage of the third MOS tube is the input voltage, and the input voltage is output; when the charge pump control signal is at a low level, the second MOS tube is turned off, the third MOS tube is also turned off, and the drain of the third MOS tube has no voltage output. In this way, the input voltage is also output at intervals under the control of the charge pump control signal. Generally speaking, the solution using triodes is relatively cheaper, and the solution using MOS tubes is relatively more expensive.

In one embodiment, the regulating voltage generating circuit 12 includes a fourth transistor Q4, a third Zener diode D3, and a ninth resistor R9, the collector of the fourth transistor Q4 is connected to the input voltage Vbat, the collector of the fourth transistor Q4 is also connected to the base of the fourth transistor Q4 via the ninth resistor R9, the base of the fourth transistor Q4 is also grounded via the third Zener diode D3, and the emitter of the fourth transistor Q4 outputs the regulating voltage Vb. In this way, the third Zener diode D3 clamps the base voltage of the fourth transistor Q4, the fourth transistor Q4 is in an amplified state, and the emitter voltage of the fourth transistor Q4 is Vzener-Vbe, which is the regulating voltage Vb, wherein Vzener is the nominal voltage of the third Zener diode D3, and Vbe is the base-emitter conduction voltage of the fourth transistor Q4.

In one embodiment, the regulating voltage generating circuit 12 further includes a second bypass capacitor C2, and the emitter of the fourth transistor Q4 is grounded via the second bypass capacitor C2. The second bypass capacitor C2 can filter out possible spike pulses.

In one embodiment, the regulating voltage generating circuit 12 also includes a fourth anti-backflow diode D4, the positive electrode of the fourth anti-backflow diode D4 is connected to the emitter of the fourth transistor Q4, and the negative electrode of the fourth anti-backflow diode D4 is connected to the charging circuit 14. The fourth anti-backflow diode D4 can prevent the current from flowing in reverse from the charging circuit 14 to the fourth transistor Q4 (regulating voltage generating circuit 12).

In one embodiment, the regulating voltage generating circuit 12 also includes a fourth current limiting resistor R4, a first end of the fourth current limiting resistor R4 is connected to the cathode of the fourth anti-backflow diode D4, and a second end of the fourth current limiting resistor is connected to the charging circuit 14. The fourth current limiting resistor R4 can limit the current when the regulating voltage Vb flows from the regulating voltage generating circuit 12 to the charging circuit 14, thereby ensuring circuit safety.

In one embodiment, the regulating voltage loading control circuit 13 includes a first transistor Q1, a second resistor R2, and a third resistor R3. The base of the first transistor Q1 is connected to the charge pump control signal Vctrl via the third resistor R3. The base of the first transistor Q1 is also connected to the emitter of the first transistor Q1 via the second resistor R2. The emitter of the first transistor Q1 is grounded. The collector of the first transistor Q1 is connected to the regulating voltage generating circuit 12 and the charging circuit 14. In this way, when the charge pump control signal Vctrl is at a high level, the first transistor Q1 is turned on, and the regulating voltage Vb output by the regulating voltage generating circuit 12 flows to the ground via the first transistor Q1, and is not loaded to the charging circuit 14; when the charge pump control signal Vctrl is at a low level, the first transistor Q1 is turned off, and the collector voltage of the first transistor is the regulating voltage Vb, that is, the regulating voltage Vb is loaded to the charging circuit 14. Therefore, in essence, the regulated voltage loading control circuit 13 loads the regulated voltage Vb to the charging circuit 14 at intervals under the control of the charge pump control signal Vctrl.

Correspondingly, the regulating voltage loading control circuit 13 may also use a MOS tube instead of a triode. In one embodiment (not shown), the regulating voltage loading control circuit includes a first MOS tube, the gate of the first MOS tube is connected to the charge pump control signal, the source of the first MOS tube is grounded, the drain of the first MOS tube is connected to the regulating voltage generating circuit and the charging circuit, and the first MOS tube is an NMOS. In this way, when the charge pump control signal is at a high level, the first MOS tube is turned on, and the regulating voltage output by the regulating voltage generating circuit flows to the ground through the first MOS tube, and is not loaded to the charging circuit; when the charge pump control signal is at a low level, the first MOS tube is turned off, and the drain voltage of the first MOS tube is the regulating voltage, that is, the regulating voltage is loaded to the charging circuit. In this way, the intermittent loading of the regulating voltage under the control of the charge pump control signal is also realized. Similarly, in general, the solution using triodes is relatively cheaper, and the solution using MOS tubes is relatively more expensive.

In one embodiment, the charging circuit 14 includes a first capacitor C1, a first end of the first capacitor C1 is connected to the input voltage switch circuit 11 and serves as the output end of the charging circuit 14 to output the output voltage Vcp, and a second end of the first capacitor C1 is connected to the regulating voltage generating circuit 12 and the regulating voltage loading control circuit 13. Combined with the above, when the charge pump control signal Vctrl is at a high level, the input voltage switch circuit 11 outputs the input voltage Vbat to the first end of the first capacitor C1, and the regulating voltage Vb output by the regulating voltage generating circuit 12 flows to the ground via the regulating voltage loading control circuit 13 (the first transistor Q1), that is, the second end of the first capacitor C1 is also the ground, so the voltage difference across the first capacitor C1 is Vbat; when the charge pump control signal Vctrl is at a low level, the regulating voltage Vzener-Vbe output by the regulating voltage generating circuit 12 is loaded on the second end of the first capacitor C1, and based on the characteristic that the voltage difference across the capacitor cannot suddenly change, the voltage at the first end of the first capacitor C1 becomes Vbat+Vzener-Vbe, and is output, which is the output voltage Vcp of the charge pump circuit, which is equal to the input voltage Vbat+regulating voltage Vb. Obviously, the output voltage Vcp is greater than the input voltage Vbat, which meets the circuit requirements of the charge pump circuit.

In one embodiment, the charging circuit 14 further includes a first anti-backflow diode D1 and a second anti-backflow diode D2, the first end of the first capacitor C1 is connected to the cathode of the first anti-backflow diode D1, the anode of the first anti-backflow diode D1 is connected to the input voltage switch circuit 11, the first end of the first capacitor C1 is also connected to the anode of the second anti-backflow diode D2, and the cathode of the second anti-backflow diode D2 serves as the output end of the charging circuit 14 to output the output voltage Vcp. The first anti-backflow diode D1 and the second anti-backflow diode D2 can also prevent the current from flowing in the circuit in the reverse direction, for example, the first anti-backflow diode D1 prevents the current from flowing from the first end of the first capacitor C1 toward the input voltage switch circuit 11 (the third transistor Q3) and then toward the input voltage Vbat, and the second anti-backflow diode D2 prevents the current from flowing from the output voltage Vcp (the cathode of the second anti-backflow diode D2) toward the first end of the first capacitor C1. Of course, correspondingly, when the regulating voltage generating circuit 12 also includes a fourth anti-backflow diode D4, the output voltage Vcp will become Vbat+Vzener-Vbe-Vd1-Vd2-Vd4, wherein Vd1 is the nominal voltage of the first anti-backflow diode D1, Vd2 is the nominal voltage of the second anti-backflow diode D2, and Vd4 is the nominal voltage of the fourth anti-backflow diode D4. Generally speaking, the first anti-backflow diode D1, the second anti-backflow diode D2, and the fourth anti-backflow diode D4 can be selected from the same model, and have the same nominal voltage Vd, so that the output voltage Vcp can be simplified to Vbat+Vzener-Vbe-3*Vd, and the nominal voltage Vzener of the third Zener diode D3 can be significantly greater than the base-emitter conduction voltage Vbe of the fourth transistor Q4 and the nominal voltage Vd of the anti-backflow diode (including the first anti-backflow diode D1, the second anti-backflow diode D2, and the fourth anti-backflow diode D4), so the output voltage Vcp=Vbat+Vzener-Vbe-3*Vd is still greater than the input voltage Vbat. Of course, the input voltage Vbat, the nominal voltage of the third Zener diode D3, the fourth transistor Q4, and the anti-backflow diode (including the first anti-backflow diode D1, the second anti-backflow diode D2, and the fourth anti-backflow diode D4) can all be selected according to actual needs. Appropriate models provide the required parameter characteristics to meet different usage requirements. Moreover, the fourth anti-backflow diode D4 and the fourth current limiting resistor R4 can also be set in the charging circuit 14, and the front and rear positions can also be adjusted. This adjustment can be easily thought of by technical personnel in this field under the guidance of the application.

Furthermore, the regulating voltage generating circuit 12 also includes a regulating resistor (not shown), which is connected between the third Zener diode D3 and the base of the fourth transistor Q4. Correspondingly, the ninth resistor R9 is connected to the connection point between the regulating resistor and the base of the fourth transistor Q4, so that the size of the regulating voltage Vb can be adjusted, and then the size of the output voltage Vcp can be adjusted.

In one embodiment, the charging circuit 14 further includes a first current limiting resistor R1, the cathode of the second anti-backflow diode D2 is connected to the first end of the first current limiting resistor R1, and the second end of the first current limiting resistor R1 serves as the output end of the charging circuit 14 to output the output voltage Vcp. The first current limiting resistor R1 can limit the current outputted by the output voltage Vcp to ensure circuit safety.

Please refer to Figure 2, which shows the simulation effect when the input voltage Vbat is 24V, and the charge pump control signal Vctrl is a PWM signal with a frequency of 20kHz and a voltage varying between 0 and 5V; please refer to Figure 3, which shows the simulation effect when the input voltage is 48V, and the charge pump control signal is a PWM signal with a frequency of 20kHz and a voltage varying between 0 and 5V; from these two simulation effects, it can be seen that the charge pump circuit 1 of the present application can realize the function of boosting the voltage based on the input voltage Vbat, and the change in the amplitude of the boost can be achieved by adjusting the component parameters in the charge pump circuit.

The second embodiment of the present application provides a half-bridge drive circuit, which includes: a charge pump circuit 1 and a switch tube M1, wherein the output end of the charge pump circuit 1 is connected to the gate of the switch tube M1, the drain of the switch tube M1 is connected to the input voltage Vbat, the source of the switch tube M1 is connected to the load LoadDrive to be driven, the switch tube is NMOS, the half-bridge drive circuit is a high-side drive circuit, and the charge pump circuit 1 is the charge pump circuit 1 described above.

It should be understood that the above description is for illustration and not for limitation. Many embodiments and many applications beyond the examples provided will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of the present teachings should not be determined with reference to the above description, but rather with reference to the foregoing claims and the full scope of equivalents to which such claims are entitled. For the purpose of comprehensiveness, all articles and references, including disclosures of patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended to be a waiver of the subject matter, nor should it be considered that the applicant has not considered the subject matter to be part of the disclosed application subject matter.

Claims

A charge pump circuit, characterized in that it comprises:

An input voltage switch circuit is connected to the input voltage and the charge pump control signal, and outputs the input voltage under the control of the charge pump control signal;

A regulating voltage generating circuit, connected to the input voltage and outputting a regulating voltage;

A regulating voltage loading control circuit is connected to both the regulating voltage generating circuit and the charge pump control signal, and loads the regulating voltage under the control of the charge pump control signal;

The charging circuit is connected to the input voltage switch circuit, the regulating voltage generating circuit, and the regulating voltage loading control circuit, has an output terminal as the output of the charge pump circuit, and outputs an output voltage, wherein the output voltage = the input voltage + the regulating voltage.
The charge pump circuit according to claim 1 is characterized in that the input voltage switch circuit comprises a second transistor, a third transistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, the base of the second transistor is connected to the charge pump control signal via the seventh resistor, the base of the second transistor is also connected to the emitter of the second transistor via the sixth resistor, the emitter of the second transistor is grounded, the collector of the second transistor is connected to the base of the third transistor via the fifth resistor, the base of the third transistor is connected to the emitter of the third transistor via the eighth resistor, the emitter of the third transistor is connected to the input voltage, the collector of the third transistor outputs the input voltage, the second transistor is an NPN transistor, and the third transistor is a PNP transistor; or,

The input voltage switch circuit includes a second MOS tube and a third MOS tube, the gate of the second MOS tube is connected to the charge pump control signal, the source of the second MOS tube is grounded, the drain of the second MOS tube is the gate of the third MOS tube, the source of the third MOS tube is connected to the input voltage, the drain of the third MOS tube outputs the input voltage, the second MOS tube is NMOS, and the third MOS tube is PMOS.
The charge pump circuit as described in claim 1 is characterized in that the regulating voltage generating circuit includes a fourth transistor, a third Zener diode, and a ninth resistor, the collector of the fourth transistor is connected to the input voltage, the collector of the fourth transistor is also connected to the base of the fourth transistor via the ninth resistor, the base of the fourth transistor is also grounded via the third Zener diode, and the emitter of the fourth transistor outputs the regulating voltage.
The charge pump circuit as claimed in claim 3 is characterized in that the regulating voltage generating circuit further includes a second bypass capacitor, and the emitter of the fourth transistor is grounded via the second bypass capacitor.
The charge pump circuit as described in claim 3 is characterized in that the regulating voltage generating circuit also includes a fourth anti-backflow diode, the positive electrode of the fourth anti-backflow diode is connected to the emitter of the fourth transistor, and the negative electrode of the fourth anti-backflow diode is connected to the charging circuit; the regulating voltage generating circuit also includes a fourth current limiting resistor, the first end of the fourth current limiting resistor is connected to the negative electrode of the fourth anti-backflow diode, and the second end of the fourth current limiting resistor is connected to the charging circuit.
The charge pump circuit according to claim 3 is characterized in that the regulating voltage generating circuit further includes a voltage regulating resistor, and the voltage regulating resistor is connected between the third Zener diode and the base of the fourth transistor.
The charge pump circuit according to claim 1, characterized in that the regulating voltage loading control circuit comprises a first transistor, a second resistor, and a third resistor, the base of the first transistor is connected to the charge pump control signal via the third resistor, the base of the first transistor is also connected to the emitter of the first transistor via the second resistor, the emitter of the first transistor is grounded, and the collector of the first transistor is connected to the regulating voltage generating circuit and the charging circuit; or,

The regulating voltage loading control circuit includes a first MOS tube, a gate of the first MOS tube is connected to the charge pump control signal, a source of the first MOS tube is grounded, a drain of the first MOS tube is connected to the regulating voltage generating circuit and the charging circuit, and the first MOS tube is an NMOS.
The charge pump circuit according to any one of claims 1 to 7 is characterized in that the charging circuit includes a first capacitor, a first end of the first capacitor is connected to the input voltage switching circuit and serves as the output end of the charging circuit to output the output voltage, and a second end of the first capacitor is connected to the regulating voltage generating circuit and the regulating voltage loading control circuit.
The charge pump circuit according to claim 8, characterized in that the charging circuit further includes a first anti-backflow diode and a second anti-backflow diode, the first end of the first capacitor is connected to the cathode of the first anti-backflow diode, the anode of the first anti-backflow diode is connected to the input voltage switch circuit, the first end of the first capacitor is also connected to the anode of the second anti-backflow diode, and the cathode of the second anti-backflow diode serves as the output end of the charging circuit to output the output voltage;

The charging circuit also includes a first current limiting resistor, the cathode of the second anti-backflow diode is connected to the first end of the first current limiting resistor, and the second end of the first current limiting resistor serves as the output end of the charging circuit to output the output voltage.
A half-bridge drive circuit, characterized in that it comprises: a charge pump circuit and a switch tube, wherein the output end of the charge pump circuit is connected to the gate of the switch tube, the drain of the switch tube is connected to an input voltage, the source of the switch tube is connected to a driven load, the switch tube is an NMOS, the half-bridge drive circuit is a high-side drive circuit, and the charge pump circuit is a charge pump circuit as described in any one of claims 1 to 9.