WO2024062664A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2024062664A1
WO2024062664A1 PCT/JP2023/014749 JP2023014749W WO2024062664A1 WO 2024062664 A1 WO2024062664 A1 WO 2024062664A1 JP 2023014749 W JP2023014749 W JP 2023014749W WO 2024062664 A1 WO2024062664 A1 WO 2024062664A1
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Prior art keywords
trench
layer
semiconductor device
emitter
conductivity type
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PCT/JP2023/014749
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French (fr)
Japanese (ja)
Inventor
谷ツ田　雄司
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株式会社日立パワーデバイス
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Publication of WO2024062664A1 publication Critical patent/WO2024062664A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a semiconductor device.
  • IGBT Insulated Gate Bipolar Transistor
  • a first trench (17) with a width WT1 and a second trench (17) with a width WT2 are formed by dry etching using mask patterns with different opening widths.
  • a structure in which a trench (20) is formed is described.
  • the width of the second trench (20) is wider than that of the first trench (17)
  • by performing dry etching all at once the depth of the second trench (20) is changed to the depth of the first trench (17). ) can be formed deeper.
  • a first gate electrode (19) is formed in the first trench (17), and a second gate electrode (22) is formed in the second trench (20).
  • the second gate electrode (22) is connected to the first gate electrode (19), it is described that it may be connected to the emitter electrode (24) (see paragraph 0032).
  • An N+ type emitter region (16) is formed around the first trench (17), and an N+ type emitter region (16) is formed around the second trench (20). do not have.
  • An N-type carrier accumulation layer (14) for carrier accumulation is formed under the P-type base region (15).
  • Patent Document 1 when the depth of the second trench (20) is deeper than the first trench (17), the electric field intensity distribution when applying a reverse bias of 600V is equal to the depth of the second trench (20). As shown in FIG. 3(b) of Patent Document 1, the electric field is higher near the second trench (20) than near the first trench (17) at the tip (bottom) of the trench.
  • the hole carrier distribution when the intensity distribution becomes high and the turn-off surge voltage of the VCE waveform reaches the maximum during turn-off is as shown in FIG. 5(b) of Patent Document 1, compared to when the depth is the same. , it is stated that the hole carrier density at the top of the trench is higher near the second trench (20) than near the first trench (17) (see paragraphs 0025 to 0026).
  • the second trench (20) does not have an N+ type emitter region (16) above it, and therefore does not form an npnp thyristor, so latch-up does not structurally occur even if the electric field strength near the second trench (20) increases. It is also described that the lowered carrier density of holes near the first trench (17) reduces the base current of the npn transistor, improving breakdown resistance (see paragraph 0027).
  • Patent Document 1 it is difficult to maintain the IE (Injection Enhancement) effect when the IGBT is in the on state due to the effect of having a configuration for discharging holes when the IGBT is off, and the on-state voltage is reduced. It may be insufficient.
  • the IE effect is an effect in which carriers (one of holes and electrons) are accumulated on the surface side of a semiconductor device, thereby promoting injection of the other hole and electron from the emitter side, thereby reducing the on-state voltage. There is a trade-off relationship between the hole evacuation effect and the IE effect of accumulating holes.
  • an N-type carrier accumulation layer (14) for carrier accumulation is formed under a P-type base region (15), and it is thought that this is intended to obtain an IE effect. It will be done.
  • the N-type carrier accumulation layer (14) is provided under the P-type base region (15) as in Patent Document 1, it is difficult for the depletion layer to extend downward from the PN junction boundary when the IGBT is off. Therefore, there is a problem that the withstand voltage margin decreases.
  • the N-type carrier accumulation layer (14) prevents hole discharge, there is also the problem that the effect of hole discharge becomes weak.
  • the problem to be solved by the present invention is to provide a semiconductor device in an IGBT that can reduce the on-state voltage by increasing the IE effect while ensuring breakdown resistance against avalanche by providing a carrier discharge path when off. .
  • a semiconductor device of the present invention includes, for example, a drift layer of a first conductivity type, a collector layer of a second conductivity type provided on a back surface side of the drift layer, and a collector layer of a second conductivity type provided on a back side of the drift layer.
  • an in-trench emitter electrode provided inside the second trench, between a side wall part inside the second trench and the in-trench emitter electrode, and between a bottom part and the in-trench emitter electrode.
  • an insulating film in the trench provided; an emitter layer of a first conductivity type provided on the surface of the body layer and in contact with the first trench and spaced apart from the second trench; and the emitter layer and the body. and an emitter electrode electrically connected to the in-trench emitter electrode, and the first trench and the two body layers are arranged between the two second trenches.
  • the width of the first trench in a longitudinal section is Wg
  • the width of the second trench is We
  • the body layer is sandwiched between the first trench and the second trench. It is characterized in that, when the width of is Wb, Wg ⁇ Wb and We/Wb ⁇ 2.
  • the semiconductor device of the present invention since the emitter layer is not in contact with the side wall portion of the second trench, a carrier discharge path is formed during off-time, and the second trench is formed wide so that the second trench is not in contact with the emitter layer. Since the in-trench emitter electrode is provided inside the trench via the in-trench insulating film, a large amount of carriers can be accumulated under the wide second trench, and the IE effect can be enhanced. Therefore, according to the semiconductor device of the present invention, in the IGBT, it is possible to provide a carrier discharge path during off-time and ensure breakdown resistance against avalanche, while enhancing the IE effect and reducing the on-voltage.
  • FIG. 1 is a vertical cross-sectional view of a semiconductor device of Example 1.
  • FIG. FIG. 3 is a vertical cross-sectional view of a semiconductor device of Example 2.
  • FIG. 3 is a vertical cross-sectional view of a semiconductor device of Example 3.
  • FIG. 13 is a vertical cross-sectional view of a semiconductor device according to a fourth embodiment.
  • FIG. 13 is a vertical cross-sectional view of a semiconductor device according to a fifth embodiment.
  • FIG. 7 is a vertical cross-sectional view of a semiconductor device of Example 6.
  • FIG. 7 is a vertical cross-sectional view of a semiconductor device of Example 7.
  • FIG. 8 is a vertical cross-sectional view of a semiconductor device of Example 8.
  • FIG. 9 is a vertical cross-sectional view of a semiconductor device of Example 9.
  • FIG. 7 is a vertical cross-sectional view of a semiconductor device of Example 10.
  • FIG. 7 is a vertical cross-sectional view of a semiconductor device of Example 11.
  • FIG. 7 is a vertical cross-sectional view of a semiconductor device of Example 12.
  • 13 is a process flow of a method for manufacturing a semiconductor device according to Example 13.
  • FIG. 9 is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 13;
  • FIG. 9 is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 13;
  • FIG. 9 is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 13;
  • FIG. 9 is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 13;
  • FIG. 9 is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 13;
  • FIG. 9 is a vertical cross-sectional view illustrating a
  • FIG. 1 is a vertical cross-sectional view of a semiconductor device according to the first embodiment.
  • the semiconductor device 1 of Example 1 includes a drift layer 2 of a first conductivity type (n type in FIG. 1) and a collector of a second conductivity type (p type in FIG. 1) provided on the back side of the drift layer 2. It has a layer 4 and a collector electrode 5 electrically connected to the collector layer 4. Note that although the semiconductor device 1 also has a buffer layer 3 of the first conductivity type between the drift layer 2 and the collector layer 4, the effect of Example 1 can be obtained regardless of the presence or absence of the buffer layer 3. , may be applied to omitted configurations.
  • the semiconductor device 1 includes a body layer 6 of a second conductivity type provided on the surface side of the drift layer 2, and a first trench 7 and a second trench 8 that penetrate the body layer 6 and reach the drift layer 2. has.
  • the semiconductor device 1 includes a gate electrode 9 provided inside the first trench 7 and a gap between the side wall portion and the gate electrode 9 inside the first trench 7 and between the bottom surface portion and the gate electrode 9. and a gate insulating film 10 provided therebetween.
  • Gate electrode 9 is also called a trench gate.
  • Gate electrode 9 is made of polysilicon, for example. Since a gate potential G is applied to the gate electrode 9, the symbol G is indicated on the gate electrode 9 in FIG.
  • the semiconductor device 1 further includes an in-trench emitter electrode 13 provided inside the second trench 8, an in-trench insulating film 14 provided between the sidewall portion and the in-trench emitter electrode 13 inside the second trench 8 and between the bottom surface and the in-trench emitter electrode 13, an emitter layer 11 of a first conductivity type provided on the surface of the body layer 6, contacting the first trench 7 and spaced apart from the second trench 8, and an emitter electrode 12 electrically connected to the emitter layer 11, the body layer 6, and the in-trench emitter electrode 13.
  • the in-trench emitter electrode 13 is formed of, for example, polysilicon.
  • An emitter potential E is applied to the in-trench emitter electrode 13, so the in-trench emitter electrode 13 is indicated with the symbol E in FIG. 1.
  • the emitter layer 11 and the body layer 6 are connected to the emitter electrode 12 through one contact hole provided in the interlayer insulating film 15, and the trench emitter electrode 13 is connected to the emitter electrode 12 through another contact hole provided in the interlayer insulating
  • the drift layer 2, buffer layer 3, collector layer 4, body layer 6, and emitter layer 11 are made of semiconductor, and each layer is formed in a semiconductor substrate such as a silicon substrate, for example.
  • a semiconductor substrate such as a silicon substrate
  • the present invention is not limited to this.
  • the type may be n-type.
  • the description regarding carriers in the examples may be read by reversing holes and electrons. For example, the statement that holes are discharged through a carrier discharge path may be read as electrons are discharged. In FIG.
  • the impurity concentration of the drift layer 2 is expressed as n- because it is low
  • the impurity concentration of the emitter layer 11 is expressed as n+ because it is high concentration
  • the semiconductor device 1 of Example 1 has a structure in which a first trench 7 and two body layers 6 are arranged between two second trenches 8 as a basic cell configuration 16.
  • the semiconductor device 1 of the first embodiment includes the first trench 7 in which the gate electrode 9 is formed via the gate insulating film 10, and the in-trench emitter via the in-trench insulating film 14 in the first trench 7.
  • the emitter layer 11 has a second trench 8 in which an electrode 13 is formed, and the emitter layer 11 is not in contact with the second trench 8.
  • the emitter layer 11 Since the emitter layer 11 is not in contact with the side wall of the second trench 8, it becomes a carrier discharge path during off-time, and the breakdown resistance against avalanche can be improved compared to the case without this. Specifically, the body layer 6 in contact with the side wall of the second trench 8 becomes a discharge path for holes generated by avalanche, and the holes are discharged to the emitter electrode 12 without being obstructed by the emitter layer 11. can do.
  • the vertical structure of this region is not a parasitic thyristor structure (npnp thyristor structure formed of n+ of emitter layer 11/p of body layer 6/n- of drift layer 2/p of collector layer 4). There is no latch-up and the breakdown resistance is improved.
  • the semiconductor device 1 of Example 1 provides a carrier discharge path during off-time as described above to ensure breakdown resistance against avalanche, while increasing the IE effect, which is in a trade-off relationship, to reduce on-voltage. It has a structure that allows for Specifically, in the semiconductor device 1 of Example 1, the width of the first trench 7 in the longitudinal section is Wg, the width of the second trench 8 is We, and the width of the first trench 7 and the second trench is Letting Wb be the width of the body layer 6 sandwiched between the body layer 6 and the body layer 8, Wg ⁇ Wb and We/Wb ⁇ 2.
  • Wg and Wb are preferably within the commonly used ranges of 0.5 ⁇ m ⁇ Wg ⁇ 1.8 ⁇ m and 0.5 ⁇ m ⁇ Wb ⁇ 1.8 ⁇ m, but are not limited thereto. Furthermore, since it is generally desirable that Wb be greater than or equal to Wg, Wg ⁇ Wb was set.
  • the second trench 8 was wide so that We/Wb ⁇ 2, that is, the width (We) of the second trench 8 was at least twice the width (Wb) of the body layer 6.
  • a rough guideline for the upper limit is We/Wb ⁇ 20, but it is not limited to this.
  • the wide second trench 8 allows a large number of holes, which are carriers from the collector side on the back surface, to be accumulated under the wide second trench 8 when the IGBT is in the on state, thereby enhancing the IE effect, which in turn promotes the injection of electrons from the emitter side on the front surface and reduces the on-voltage.
  • the wide second trench 8 enhances the IE effect and reduces the on-voltage.
  • the accumulated holes are then discharged to the emitter electrode 12 via the body layer 6. Even if the second trench 8 is made wider, the carrier discharge path during the off state is still secured, so the IE effect can be enhanced and the on-voltage can be reduced while securing the breakdown resistance against avalanches.
  • the in-trench emitter electrode 13 functions as a field plate, it has the effect of maintaining a high breakdown voltage even when the second trench 8 is made wide.
  • the in-trench emitter electrode 13 is insulated from the drift layer 2 by the in-trench insulating film 14, the holes accumulated under the second trench 8 penetrate through the in-trench insulating film 14 to the in-trench emitter electrode. 13, and the IE effect can be maintained.
  • trench gates are provided with a narrow part and a wide part, a floating layer of the second conductivity type (floating P layer) is provided in the part with a wide trench gate interval, and the floating layer is There is also a technique to accumulate holes.
  • a floating layer is provided, when the IGBT is turned on, holes transiently flow into the floating layer, the potential of the floating layer rises, and the gate potential of the trench gate adjacent to the floating layer is raised, and the IGBT is turned on.
  • speed acceleration occurs, causing a problem in which the controllability of the time rate of change of the output voltage dV/dt decreases.
  • the semiconductor device 1 of Example 1 such a problem does not occur and dV/dt controllability can be ensured.
  • the semiconductor device 1 of Example 1 also has the effect that the reliability of the insulating film is high.
  • the carrier (hole) discharge path in a high electric field is mainly on the second trench 8 side, so the first trench 7 provided with the gate electrode 9 that performs the switching operation is less susceptible to this effect.
  • the reliability of the gate insulating film 10 is higher than in the case where this is not the case.
  • the second trench 8 is a wide trench, the total number of trenches is reduced compared to a structure with a large number of thin trenches, and the gate electrode 9 or emitter electrode 13 in the trench is connected to the semiconductor substrate.
  • the total area facing the drift layer 2 or body layer 6 decreases, the total area of the insulating films provided in the trench (gate insulating film 10 and in-trench insulating film 14) also decreases. It is considered that the margin for ensuring the reliability of the insulating film is improved compared to the case where a large number of thin trenches are provided.
  • the second trench 8 provided with the in-trench emitter electrode 13 by having the second trench 8 provided with the in-trench emitter electrode 13, the number of first trenches 7 provided with the gate electrode 9 is reduced; There is also the effect that the feedback capacitance, which is the capacitance between the collector and the gate, can be reduced compared to the case of the trench 7 shown in FIG.
  • td is the depth of the first trench 7 in the longitudinal section.
  • the depth of a typical trench is often 3 ⁇ m to 8 ⁇ m, but by making the trench shallower than that, feedback capacitance can be reduced. Note that from the viewpoint of enhancing the IE effect, it is not essential to make the trench shallow, so the trench may have a depth other than the above. Further, in order to manufacture the first trench 7 and the second trench 8 by the same process, it is desirable that the first trench 7 and the second trench 8 have the same depth.
  • the thickness of the gate insulating film 10 at the side wall of the first trench 7 in the longitudinal section is ta
  • the semiconductor device 1 of Example 1 is a semiconductor that can reduce the on-voltage by increasing the IE effect while providing a carrier discharge path during off-state and securing breakdown resistance against avalanche in an IGBT. equipment can be provided. Further, it is possible to realize an IGBT with excellent total balance including dV/dt controllability, reliability of the insulating film, and feedback capacitance.
  • Embodiment 2 and subsequent examples are modifications of Embodiment 1.
  • the differences will be mainly explained, and redundant explanations will be omitted.
  • FIG. 2 is a longitudinal cross-sectional view of the semiconductor device of Example 2.
  • the semiconductor device 1 of Example 2 has an impurity concentration lower than that of the drift layer 2, which is provided between the body layer 6 and the drift layer 2 which are sandwiched between the first trench 7 and the second trench 8.
  • This example differs from Example 1 in that it has a first barrier layer 17 of a high first conductivity type.
  • the first barrier layer 17 acts as a barrier for holes flowing into the emitter side when the IGBT is on, so the hole concentration under the first barrier layer 17 increases, reducing the on-voltage when the IGBT is conductive. It can be further reduced.
  • Example 2 although the breakdown resistance against avalanche is somewhat reduced compared to Example 1 due to the influence of the first barrier layer 17, the reduced breakdown resistance is secured and the IE effect is improved by the wide second trench 8. The same effect as in Example 1 can be obtained in that the on-state voltage can be reduced by increasing the on-voltage.
  • FIG. 3 is a longitudinal cross-sectional view of the semiconductor device of Example 3.
  • the semiconductor device 1 of Example 3 differs from Example 2 in that it includes a second barrier layer 18 of the second conductivity type provided between the first barrier layer 17 and the drift layer 2.
  • the depletion layer extends downward from the PN junction boundary when the IGBT is off. There is a problem in that the breakdown voltage margin when the IGBT is off decreases.
  • Example 3 by providing the second barrier layer 18 of the second conductivity type under the first barrier layer 17, the electric field can be relaxed and the breakdown voltage margin when the IGBT is off can be improved.
  • FIG. 4 is a longitudinal cross-sectional view of the semiconductor device of Example 4.
  • the second trench 8 is divided into a third trench 20 and a fourth trench 21 in a part of the region, and the third trench 20 and the fourth trench 21 are divided into a third trench 20 and a fourth trench 21.
  • An inactive body layer 19 of a second conductivity type on the surface of which a layer of the first conductivity type is not formed is provided in a region sandwiched between the inert body layer 19 and the emitter electrode 12 . This is different from the first embodiment in that the first embodiment is connected to the second embodiment.
  • the semiconductor device 1 of Example 4 has a structure having a vertical cross-sectional area as shown in FIG. 1 and a vertical cross-sectional area as shown in FIG. 4. Therefore, like the second trench 8, the third trench 20 and the fourth trench 21 have an in-trench emitter electrode 13 and an in-trench insulating film 14 at a location other than that shown in FIG. Since the third trench 20 and the fourth trench 21 are connected to the second trench 8 in FIG.
  • the inactive body layer 19 functions as a carrier discharge path, although the IE effect is reduced in the region where the inactive body layer 19 is provided, the margin of breakdown resistance at turn-off can be further improved. Note that the structure of the fourth embodiment can be realized by the same manufacturing process as the first embodiment, only by changing the layout.
  • the width of the inactive body layer 19 in the longitudinal section is Wb', it is desirable that 0.5 ⁇ m ⁇ Wb’ ⁇ 1.8 ⁇ m, but it is not limited thereto.
  • the width of the third trench 20 and the fourth trench 21 is preferably twice or more of Wb like the second trench 8, a sufficient IE effect can be obtained with the second trench 8. If so, the widths of the third trench 20 and the fourth trench 21 may be smaller than twice Wb.
  • Example 4 the breakdown resistance against avalanche is improved compared to Example 1 due to the influence of the inert body layer 19, and although the IE effect is reduced, the breakdown resistance is ensured and the wide second trench 8 (necessary
  • the same effect as in the first embodiment can be obtained in that the IE effect can be enhanced and the on-voltage can be reduced by increasing the width of the third trench 20 and the fourth trench 21 (according to the width of the third trench 20 and the fourth trench 21).
  • FIG. 5 is a vertical cross-sectional view of a semiconductor device according to the fifth embodiment.
  • Example 5 is an example in which the first barrier layer 17 of Example 2 is applied to Example 4. Note that it is desirable that the first barrier layer 17 is not provided under the inactive body layer 19 so as not to impede carrier discharge. Since the first barrier layer 17 can originally be formed selectively, there is no increase in the manufacturing process even if the first barrier layer 17 is not provided under the inactive body layer 19.
  • FIG. 6 is a longitudinal cross-sectional view of the semiconductor device of Example 6.
  • Example 6 is an example in which the second barrier layer 18 of Example 3 is applied to Example 5.
  • FIG. 7 is a longitudinal cross-sectional view of the semiconductor device of Example 7.
  • the emitter layer 11, the body layer 6, and the in-trench emitter electrode 13 are connected to the emitter electrode 12 through one contact hole 22, and the bottom surface of the contact hole 22 is located at the position of the bottom surface of the contact hole 22.
  • This embodiment differs from the first embodiment in that it is deeper than the bottom surface of the emitter layer 11.
  • the width (Wb) of the body layer 6 is preferably 0.25 ⁇ m ⁇ Wb ⁇ 1.8 ⁇ m, but is not limited to this. Further, as the lower limit of Wb has become smaller, it is desirable that the upper limit of We/Wb be We/Wb ⁇ 40, but it is not limited to this.
  • FIG. 8 is a longitudinal cross-sectional view of the semiconductor device of Example 8.
  • Example 8 is an example in which the first barrier layer 17 of Example 2 is applied to Example 7.
  • FIG. 9 is a longitudinal cross-sectional view of the semiconductor device of Example 9.
  • Example 9 is an example in which the second barrier layer 18 of Example 3 is applied to Example 8.
  • FIG. 10 is a longitudinal cross-sectional view of the semiconductor device of Example 10.
  • Example 10 is an example in which the third trench 20, fourth trench 21, and inactive body layer 19 of Example 4 are applied to Example 7.
  • Inactive body layer 19 is connected to emitter electrode 12 through a contact hole formed in the same process as contact hole 22 .
  • Example 10 has a structure having a vertical cross-sectional area as shown in FIG. 7 and a vertical cross-sectional area as shown in FIG. 10.
  • the width of the inactive body layer 19 in the longitudinal section is Wb', it is desirable that 0.25 ⁇ m ⁇ Wb' ⁇ 1.8 ⁇ m, but this is not limited to this.
  • FIG. 11 is a longitudinal cross-sectional view of the semiconductor device of Example 11.
  • Example 11 is an example in which the first barrier layer 17 of Example 2 is applied to Example 10.
  • FIG. 12 is a longitudinal cross-sectional view of the semiconductor device of Example 12.
  • Example 12 is an example in which the second barrier layer 18 of Example 3 is applied to Example 11.
  • Figure 13 shows the process flow of the manufacturing method of the semiconductor device of Example 13.
  • Example 13 is an example for explaining an example of a method for manufacturing the semiconductor device 1 of Examples 1 to 12.
  • the method is basically the same as a general semiconductor device manufacturing method, in which a wafer of a semiconductor substrate is prepared in the wafer preparation step of step S1, and a wafer of a semiconductor substrate is prepared in the step S2 of forming a termination region diffusion layer.
  • a second conductivity type diffusion layer also called a deep P well layer
  • the termination region not shown in FIGS. 1 to 12
  • a trench is formed in the trench formation process of step S3
  • a polysilicon In the electrode forming step, the gate electrode 9 and the in-trench emitter electrode 13 are formed of polysilicon, and in the body layer/emitter layer forming step of step S5, the body layer 6 and the emitter layer 11 are formed.
  • the body layer 6 is formed in step S5, but in the case of a deep trench, the body layer 6 may also be formed in step S2. good.
  • the interlayer insulating film 15 and contact holes are formed, the emitter electrode 12 is formed in the metal electrode forming step of step S7, and the wafer is thinned in the back surface process of step S8.
  • a back surface process including impurity implantation on the back surface is performed, a collector electrode 5 is formed in the back surface electrode forming step of step S9, and a wafer is inspected in the wafer inspection step of step S10 to complete the process.
  • 14A to 14F are longitudinal cross-sectional views illustrating a method for manufacturing a semiconductor device of Example 13.
  • 14A to 14F illustrate a method of forming a wide shallow trench such as the second trench 8 in steps S3 and S4 of FIG. 13, and forming an insulating film and a polysilicon electrode inside the trench. It is a diagram. Note that shallow trenches that are not wide, such as the first trench 7, can also be made at the same time using the same process.
  • a semiconductor substrate 31 such as a silicon substrate
  • an oxide film 32, a silicon nitride film 33, a CVD insulating film 34, and a resist 35 are laminated in order from the bottom to form a laminated film.
  • the trench 36 is etched.
  • the silicon surface within the trench 36 is oxidized to form an in-trench oxide film 37.
  • a film of polysilicon 38 is formed, a resist 35 is applied, and baking is performed.
  • FIG. 14E is an example, and shows a case where the etching rates of the resist 35 and polysilicon 38 are approximately the same, but this is not limiting.
  • the CVD insulating film 34 and silicon nitride film 33 are removed.
  • a wide shallow trench, an in-trench insulating film and a polysilicon electrode provided inside the trench can be formed.

Abstract

Provided is a semiconductor device which has, during an OFF time, a carrier discharge path that is provided in an IGBT, and increases an IE effect while assuring breakdown resistance against avalanches, and is thereby capable of reducing an ON-voltage. This semiconductor device 1 has: a first trench 7 having formed therein a gate electrode 9 with a gate insulating film 10 interposed therebetween; and a second trench 8 having formed therein an in-trench emitter electrode 13 with an in-trench insulating film 14 interposed therebetween, wherein an emitter layer 11 is not in contact with the second trench 8, and, in a vertical cross-section, when Wg is the width of the first trench 7, We is the width of the second trench 8, and Wb is the width of a body layer 6 interposed between the first trench 7 and the second trench 8, WG ≤ Wb and We/Wb ≥ 2.

Description

半導体装置semiconductor equipment
　本発明は、半導体装置に関する。 The present invention relates to a semiconductor device.
　電力変換装置などに用いられる半導体装置の一種として、ＩＧＢＴ（Insulated Gate Bipolar Transistor）がある。 An IGBT (Insulated Gate Bipolar Transistor) is a type of semiconductor device used in power converters and the like.
　スイッチング素子としてＩＧＢＴを用いたパワーモジュールの高電力化・高密度化に対応するため、耐圧を保持しつつ、高い次元で高性能・高信頼を維持可能な半導体装置の実現が求められる。 In order to respond to the increase in power and density of power modules that use IGBTs as switching elements, it is necessary to realize semiconductor devices that can maintain high performance and reliability while maintaining voltage resistance.
　例えば、破壊耐量の向上に関する技術として、特許文献１の図７には、開口幅の異なるマスクパターンを用いたドライエッチングにより、幅がＷＴ１の第１のトレンチ（１７）と幅がＷＴ２の第２のトレンチ（２０）を形成したものが記載されている。ここで、第２のトレンチ（２０）の幅は第１のトレンチ（１７）よりも広いので、一括でドライエッチングすることで、第２のトレンチ（２０）の深さを第１のトレンチ（１７）よりも深く形成することができる。第１のトレンチ（１７）内には第１のゲート電極（１９）が形成されており、第２のトレンチ（２０）内には第２のゲート電極（２２）が形成されている。また、第２のゲート電極（２２）は、第１のゲート電極（１９）に接続されているが、エミッタ電極（２４）に接続してもよいことが記載されている（段落００３２参照）。第１のトレンチ（１７）の周囲には、Ｎ＋型のエミッタ領域（１６）が形成されており、第２のトレンチ（２０）の周囲には、Ｎ＋型のエミッタ領域（１６）が形成されていない。Ｐ型のベース領域（１５）の下には、キャリア蓄積のためのＮ型のキャリア蓄積層（１４）が形成されている。 For example, as a technique for improving breakdown resistance, in FIG. 7 of Patent Document 1, a first trench (17) with a width WT1 and a second trench (17) with a width WT2 are formed by dry etching using mask patterns with different opening widths. A structure in which a trench (20) is formed is described. Here, since the width of the second trench (20) is wider than that of the first trench (17), by performing dry etching all at once, the depth of the second trench (20) is changed to the depth of the first trench (17). ) can be formed deeper. A first gate electrode (19) is formed in the first trench (17), and a second gate electrode (22) is formed in the second trench (20). Further, although the second gate electrode (22) is connected to the first gate electrode (19), it is described that it may be connected to the emitter electrode (24) (see paragraph 0032). An N+ type emitter region (16) is formed around the first trench (17), and an N+ type emitter region (16) is formed around the second trench (20). do not have. An N-type carrier accumulation layer (14) for carrier accumulation is formed under the P-type base region (15).
　特許文献１の技術によれば、第２のトレンチ（２０）の深さが第１のトレンチ（１７）よりも深い場合には、６００Ｖの逆バイアス印加時の電界強度分布は、深さが同じ場合に比べて、特許文献１の図３（ｂ）に示すように、第１のトレンチ（１７）付近よりも第２のトレンチ（２０）付近の方が、トレンチの先端（底）部において電界強度分布が高くなり、また、ターンオフ時にＶＣＥ波形のターンオフサージ電圧が最大となった時のホールキャリア分布は、深さが同じ場合に比べて、特許文献１の図５（ｂ）に示すように、第１のトレンチ（１７）付近よりも第２のトレンチ（２０）付近の方が、トレンチ上部におけるホールのキャリア密度が大きくなることが記載されている（段落００２５～００２６参照）。 According to the technology of Patent Document 1, when the depth of the second trench (20) is deeper than the first trench (17), the electric field intensity distribution when applying a reverse bias of 600V is equal to the depth of the second trench (20). As shown in FIG. 3(b) of Patent Document 1, the electric field is higher near the second trench (20) than near the first trench (17) at the tip (bottom) of the trench. The hole carrier distribution when the intensity distribution becomes high and the turn-off surge voltage of the VCE waveform reaches the maximum during turn-off is as shown in FIG. 5(b) of Patent Document 1, compared to when the depth is the same. , it is stated that the hole carrier density at the top of the trench is higher near the second trench (20) than near the first trench (17) (see paragraphs 0025 to 0026).
　そして、特許文献１の技術によれば、第２のトレンチ（２０）の場合、第１のトレンチ（１７）と異なり、その上部にはＮ＋型のエミッタ領域（１６）が無く、よって、ｎｐｎｐサイリスタが構成されないため、第２のトレンチ（２０）付近の電界強度が高くなっても構造的にラッチアップは起こらない。そして、第１のトレンチ（１７）付近のホールのキャリア密度が下がることでｎｐｎトランジスタのベース電流が下がるため、破壊耐量が向上することが記載されている（段落００２７参照）。 According to the technology of Patent Document 1, unlike the first trench (17), the second trench (20) does not have an N+ type emitter region (16) above it, and therefore does not form an npnp thyristor, so latch-up does not structurally occur even if the electric field strength near the second trench (20) increases. It is also described that the lowered carrier density of holes near the first trench (17) reduces the base current of the npn transistor, improving breakdown resistance (see paragraph 0027).
特開２００８－２１９１８号公報Japanese Patent Application Publication No. 2008-21918
　特許文献１では、第２のトレンチ（２０）の周囲にはＮ＋型のエミッタ領域（１６）が形成されていないので、アバランシェで発生するホールの排出経路となり、アバランシェによる破壊を抑制することができると推測される。 In Patent Document 1, since the N+ type emitter region (16) is not formed around the second trench (20), it serves as a discharge path for holes generated by avalanche, and damage caused by avalanche can be suppressed. It is assumed that.
　しかしながら、特許文献１では、ＩＧＢＴがオフの時のホール排出のための構成を有する影響で、ＩＧＢＴがオン状態の時を考えると、ＩＥ（Injection Enhancement）効果を維持しにくく、オン電圧の低減が不十分である可能性がある。ＩＥ効果とは、半導体装置の表面側にキャリア（ホールおよび電子の一方）を蓄積させ、これによりエミッタ側からのホールおよび電子の他方の注入が促進されオン電圧を低減できる効果である。ホール排出の効果とホールを蓄積するＩＥ効果はトレードオフの関係にある。特許文献１では、Ｐ型のベース領域（１５）の下にキャリア蓄積のためのＮ型のキャリア蓄積層（１４）が形成されており、これによりＩＥ効果を得ることを意図していると考えられる。しかしながら、特許文献１のように、Ｐ型のベース領域（１５）の下にＮ型のキャリア蓄積層（１４）を設けた場合、ＩＧＢＴがオフの時にＰＮ接合境界から空乏層が下に伸びにくくなり、耐圧マージンが低下するという問題がある。また、Ｎ型のキャリア蓄積層（１４）がホールの排出を妨げるため、ホールの排出の効果が弱くなるという問題もある。 However, in Patent Document 1, it is difficult to maintain the IE (Injection Enhancement) effect when the IGBT is in the on state due to the effect of having a configuration for discharging holes when the IGBT is off, and the on-state voltage is reduced. It may be insufficient. The IE effect is an effect in which carriers (one of holes and electrons) are accumulated on the surface side of a semiconductor device, thereby promoting injection of the other hole and electron from the emitter side, thereby reducing the on-state voltage. There is a trade-off relationship between the hole evacuation effect and the IE effect of accumulating holes. In Patent Document 1, an N-type carrier accumulation layer (14) for carrier accumulation is formed under a P-type base region (15), and it is thought that this is intended to obtain an IE effect. It will be done. However, when the N-type carrier accumulation layer (14) is provided under the P-type base region (15) as in Patent Document 1, it is difficult for the depletion layer to extend downward from the PN junction boundary when the IGBT is off. Therefore, there is a problem that the withstand voltage margin decreases. Furthermore, since the N-type carrier accumulation layer (14) prevents hole discharge, there is also the problem that the effect of hole discharge becomes weak.
　本発明が解決しようとする課題は、ＩＧＢＴにおいて、オフ時のキャリア排出経路を設けてアバランシェに対する破壊耐量を確保しつつ、ＩＥ効果を高めてオン電圧の低減ができる半導体装置を提供することである。 The problem to be solved by the present invention is to provide a semiconductor device in an IGBT that can reduce the on-state voltage by increasing the IE effect while ensuring breakdown resistance against avalanche by providing a carrier discharge path when off. .
　上記課題を解決するために、本発明の半導体装置は、例えば、第１導電型のドリフト層と、前記ドリフト層よりも裏面側に設けられた第２導電型のコレクタ層と、前記コレクタ層に電気的に接続されたコレクタ電極と、前記ドリフト層よりも表面側に設けられた第２導電型のボディ層と、ボディ層を貫き前記ドリフト層に達する第１のトレンチおよび第２のトレンチと、前記第１のトレンチの内部に設けられたゲート電極と、前記第１のトレンチの内部の側壁部と前記ゲート電極との間および底面部と前記ゲート電極との間に設けられたゲート絶縁膜と、前記第２のトレンチの内部に設けられたトレンチ内エミッタ電極と、前記第２のトレンチの内部の側壁部と前記トレンチ内エミッタ電極との間および底面部と前記トレンチ内エミッタ電極との間に設けられたトレンチ内絶縁膜と、前記ボディ層の表面に設けられ、前記第１のトレンチに接し、前記第２のトレンチからは離間した第１導電型のエミッタ層と、前記エミッタ層と前記ボディ層と前記トレンチ内エミッタ電極とに電気的に接続されたエミッタ電極と、を有し、２つの前記第２のトレンチの間に前記第１のトレンチと２つの前記ボディ層とが配置された半導体装置において、縦断面における、前記第１のトレンチの幅をＷｇとし、前記第２のトレンチの幅をＷｅとし、前記第１のトレンチと前記第２のトレンチとの間に挟まれた前記ボディ層の幅をＷｂとしたとき、Ｗｇ≦Ｗｂ、かつ、Ｗｅ／Ｗｂ≧２であることを特徴とする。 In order to solve the above problems, a semiconductor device of the present invention includes, for example, a drift layer of a first conductivity type, a collector layer of a second conductivity type provided on a back surface side of the drift layer, and a collector layer of a second conductivity type provided on a back side of the drift layer. an electrically connected collector electrode, a body layer of a second conductivity type provided on the surface side of the drift layer, a first trench and a second trench that penetrate the body layer and reach the drift layer; a gate electrode provided inside the first trench; and a gate insulating film provided between the side wall portion and the gate electrode and between the bottom portion and the gate electrode inside the first trench. , an in-trench emitter electrode provided inside the second trench, between a side wall part inside the second trench and the in-trench emitter electrode, and between a bottom part and the in-trench emitter electrode. an insulating film in the trench provided; an emitter layer of a first conductivity type provided on the surface of the body layer and in contact with the first trench and spaced apart from the second trench; and the emitter layer and the body. and an emitter electrode electrically connected to the in-trench emitter electrode, and the first trench and the two body layers are arranged between the two second trenches. In the device, the width of the first trench in a longitudinal section is Wg, the width of the second trench is We, and the body layer is sandwiched between the first trench and the second trench. It is characterized in that, when the width of is Wb, Wg≦Wb and We/Wb≧2.
　本発明の半導体装置によれば、第２のトレンチの側壁部にはエミッタ層が接していないため、オフ時のキャリア排出経路が形成されるとともに、第２のトレンチが幅広で形成され第２のトレンチの内部にトレンチ内絶縁膜を介してトレンチ内エミッタ電極が設けられているので、幅広の第２のトレンチの下にキャリアを多く蓄積することができ、ＩＥ効果を高めることができる。したがって、本発明の半導体装置によれば、ＩＧＢＴにおいて、オフ時のキャリア排出経路を設けてアバランシェに対する破壊耐量を確保しつつ、ＩＥ効果を高めてオン電圧の低減ができる。 According to the semiconductor device of the present invention, since the emitter layer is not in contact with the side wall portion of the second trench, a carrier discharge path is formed during off-time, and the second trench is formed wide so that the second trench is not in contact with the emitter layer. Since the in-trench emitter electrode is provided inside the trench via the in-trench insulating film, a large amount of carriers can be accumulated under the wide second trench, and the IE effect can be enhanced. Therefore, according to the semiconductor device of the present invention, in the IGBT, it is possible to provide a carrier discharge path during off-time and ensure breakdown resistance against avalanche, while enhancing the IE effect and reducing the on-voltage.
実施例１の半導体装置の縦断面図。1 is a vertical cross-sectional view of a semiconductor device of Example 1. FIG. 実施例２の半導体装置の縦断面図。FIG. 3 is a vertical cross-sectional view of a semiconductor device of Example 2. 実施例３の半導体装置の縦断面図。FIG. 3 is a vertical cross-sectional view of a semiconductor device of Example 3. 実施例４の半導体装置の縦断面図。FIG. 13 is a vertical cross-sectional view of a semiconductor device according to a fourth embodiment. 実施例５の半導体装置の縦断面図。FIG. 13 is a vertical cross-sectional view of a semiconductor device according to a fifth embodiment. 実施例６の半導体装置の縦断面図。FIG. 7 is a vertical cross-sectional view of a semiconductor device of Example 6. 実施例７の半導体装置の縦断面図。FIG. 7 is a vertical cross-sectional view of a semiconductor device of Example 7. 実施例８の半導体装置の縦断面図。FIG. 8 is a vertical cross-sectional view of a semiconductor device of Example 8. 実施例９の半導体装置の縦断面図。FIG. 9 is a vertical cross-sectional view of a semiconductor device of Example 9. 実施例１０の半導体装置の縦断面図。FIG. 7 is a vertical cross-sectional view of a semiconductor device of Example 10. 実施例１１の半導体装置の縦断面図。FIG. 7 is a vertical cross-sectional view of a semiconductor device of Example 11. 実施例１２の半導体装置の縦断面図。FIG. 7 is a vertical cross-sectional view of a semiconductor device of Example 12. 実施例１３の半導体装置の製造方法のプロセスフロー。13 is a process flow of a method for manufacturing a semiconductor device according to Example 13. 実施例１３の半導体装置の製造方法を説明する縦断面図。FIG. 9 is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 13; 実施例１３の半導体装置の製造方法を説明する縦断面図。FIG. 9 is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 13; 実施例１３の半導体装置の製造方法を説明する縦断面図。FIG. 9 is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 13; 実施例１３の半導体装置の製造方法を説明する縦断面図。FIG. 9 is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 13; 実施例１３の半導体装置の製造方法を説明する縦断面図。FIG. 9 is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 13; 実施例１３の半導体装置の製造方法を説明する縦断面図。FIG. 9 is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 13;
　以下、図面を用いて本発明の実施例を説明する。各図、各実施例において、同一または類似の構成要素については同じ符号を付け、重複する説明は省略する。 Embodiments of the present invention will be described below with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and overlapping explanations will be omitted.
　図１は、実施例１の半導体装置の縦断面図である。 FIG. 1 is a vertical cross-sectional view of a semiconductor device according to the first embodiment.
　実施例１の半導体装置１は、第１導電型（図１ではｎ型）のドリフト層２と、ドリフト層２よりも裏面側に設けられた第２導電型（図１ではｐ型）のコレクタ層４と、コレクタ層４に電気的に接続されたコレクタ電極５とを有する。なお、半導体装置１は、ドリフト層２とコレクタ層４との間に第１導電型のバッファ層３も有しているが、バッファ層３の有無に関わらず実施例１の効果は得られるので、省略した構成に適用してもよい。 The semiconductor device 1 of Example 1 includes a drift layer 2 of a first conductivity type (n type in FIG. 1) and a collector of a second conductivity type (p type in FIG. 1) provided on the back side of the drift layer 2. It has a layer 4 and a collector electrode 5 electrically connected to the collector layer 4. Note that although the semiconductor device 1 also has a buffer layer 3 of the first conductivity type between the drift layer 2 and the collector layer 4, the effect of Example 1 can be obtained regardless of the presence or absence of the buffer layer 3. , may be applied to omitted configurations.
　さらに、半導体装置１は、ドリフト層２よりも表面側に設けられた第２導電型のボディ層６と、ボディ層６を貫きドリフト層２に達する第１のトレンチ７および第２のトレンチ８とを有する。 Further, the semiconductor device 1 includes a body layer 6 of a second conductivity type provided on the surface side of the drift layer 2, and a first trench 7 and a second trench 8 that penetrate the body layer 6 and reach the drift layer 2. has.
　ここで、半導体装置１は、第１のトレンチ７の内部に設けられたゲート電極９と、第１のトレンチ７の内部の側壁部とゲート電極９との間および底面部とゲート電極９との間に設けられたゲート絶縁膜１０とを有する。ゲート電極９はトレンチゲートとも呼ばれる。ゲート電極９は、例えばポリシリコンで形成されている。ゲート電極９にはゲート電位Ｇが印加されるので、図１ではゲート電極９にＧの符号を表示している。 Here, the semiconductor device 1 includes a gate electrode 9 provided inside the first trench 7 and a gap between the side wall portion and the gate electrode 9 inside the first trench 7 and between the bottom surface portion and the gate electrode 9. and a gate insulating film 10 provided therebetween. Gate electrode 9 is also called a trench gate. Gate electrode 9 is made of polysilicon, for example. Since a gate potential G is applied to the gate electrode 9, the symbol G is indicated on the gate electrode 9 in FIG.
　さらに、半導体装置１は、第２のトレンチ８の内部に設けられたトレンチ内エミッタ電極１３と、第２のトレンチ８の内部の側壁部とトレンチ内エミッタ電極１３との間および底面部とトレンチ内エミッタ電極１３との間に設けられたトレンチ内絶縁膜１４と、ボディ層６の表面に設けられ、第１のトレンチ７に接し、第２のトレンチ８からは離間した第１導電型のエミッタ層１１と、エミッタ層１１とボディ層６とトレンチ内エミッタ電極１３とに電気的に接続されたエミッタ電極１２とを有する。トレンチ内エミッタ電極１３は、例えばポリシリコンで形成されている。トレンチ内エミッタ電極１３にはエミッタ電位Ｅが印加されるので、図１ではトレンチ内エミッタ電極１３にＥの符号を表示している。エミッタ層１１とボディ層６は、層間絶縁膜１５に設けられた１つのコンタクトホールを介してエミッタ電極１２に接続されており、トレンチ内エミッタ電極１３は、層間絶縁膜１５に設けられた別のコンタクトホールを介してエミッタ電極１２に接続されている。 The semiconductor device 1 further includes an in-trench emitter electrode 13 provided inside the second trench 8, an in-trench insulating film 14 provided between the sidewall portion and the in-trench emitter electrode 13 inside the second trench 8 and between the bottom surface and the in-trench emitter electrode 13, an emitter layer 11 of a first conductivity type provided on the surface of the body layer 6, contacting the first trench 7 and spaced apart from the second trench 8, and an emitter electrode 12 electrically connected to the emitter layer 11, the body layer 6, and the in-trench emitter electrode 13. The in-trench emitter electrode 13 is formed of, for example, polysilicon. An emitter potential E is applied to the in-trench emitter electrode 13, so the in-trench emitter electrode 13 is indicated with the symbol E in FIG. 1. The emitter layer 11 and the body layer 6 are connected to the emitter electrode 12 through one contact hole provided in the interlayer insulating film 15, and the trench emitter electrode 13 is connected to the emitter electrode 12 through another contact hole provided in the interlayer insulating film 15.
　ドリフト層２と、バッファ層３と、コレクタ層４と、ボディ層６と、エミッタ層１１は、半導体で形成されており、例えばシリコン基板などの半導体基板内にそれぞれの層が形成されている。実施例１では、第１導電型がｎ型、第２導電型がｐ型のＩＧＢＴである場合を例として説明しているが、これに限らず、第１導電型がｐ型、第２導電型がｎ型であってもよい。第１導電型がｐ型、第２導電型がｎ型の場合は、実施例中のキャリアに関する記載について、ホールと電子を逆にして読み替えればよい。例えば、キャリア排出経路でホールを排出するとの記載は、電子を排出すると読み替えればよい。
 　図１では、一例として、ドリフト層２の不純物濃度は低濃度であるためｎ－と表記し、エミッタ層１１の不純物濃度は高濃度であるためｎ＋と表記し、バッファ層３はｎ、ボディ層６とコレクタ層４はｐと表記しているが、これに限られず、所望の動作が可能な範囲で不純物濃度は適宜変更が可能である。本実施例以降の実施例における不純物濃度に関する記載についても同様である。 The drift layer 2, buffer layer 3, collector layer 4, body layer 6, and emitter layer 11 are made of semiconductor, and each layer is formed in a semiconductor substrate such as a silicon substrate, for example. In Embodiment 1, the case where the first conductivity type is an n type and the second conductivity type is a p type is described as an example, but the present invention is not limited to this. The type may be n-type. When the first conductivity type is p-type and the second conductivity type is n-type, the description regarding carriers in the examples may be read by reversing holes and electrons. For example, the statement that holes are discharged through a carrier discharge path may be read as electrons are discharged.
In FIG. 1, as an example, the impurity concentration of the drift layer 2 is expressed as n- because it is low, the impurity concentration of the emitter layer 11 is expressed as n+ because it is high concentration, and the impurity concentration of the buffer layer 3 is expressed as n and the body layer. 6 and the collector layer 4 are expressed as p, but the impurity concentration is not limited to this and can be changed as appropriate within a range that allows the desired operation. The same applies to the descriptions regarding impurity concentrations in Examples subsequent to this example.
　実施例１の半導体装置１は、基本セル構成１６として、２つの第２のトレンチ８の間に第１のトレンチ７と２つのボディ層６とが配置された構造となっている。 The semiconductor device 1 of Example 1 has a structure in which a first trench 7 and two body layers 6 are arranged between two second trenches 8 as a basic cell configuration 16.
　すでに説明したとおり、実施例１の半導体装置１は、内部にゲート絶縁膜１０を介してゲート電極９が形成された第１のトレンチ７と、内部にトレンチ内絶縁膜１４を介してトレンチ内エミッタ電極１３が形成された第２のトレンチ８とを有し、エミッタ層１１は第２のトレンチ８には接していない構造となっている。 As already explained, the semiconductor device 1 of the first embodiment includes the first trench 7 in which the gate electrode 9 is formed via the gate insulating film 10, and the in-trench emitter via the in-trench insulating film 14 in the first trench 7. The emitter layer 11 has a second trench 8 in which an electrode 13 is formed, and the emitter layer 11 is not in contact with the second trench 8.
　第２のトレンチ８の側壁部にはエミッタ層１１が接していないため、オフ時のキャリア排出経路となり、これがない場合に比べてアバランシェに対する破壊耐量を向上させることができる。具体的には、第２のトレンチ８の側壁部に接しているボディ層６が、アバランシェで発生するホールの排出経路となり、エミッタ層１１に経路を阻害されることなくエミッタ電極１２にホールを排出することができる。また、この領域の縦方向構造は、寄生サイリスタ構造（エミッタ層１１のｎ＋／ボディ層６のｐ／ドリフト層２のｎ－／コレクタ層４のｐで形成されたｎｐｎｐサイリスタ構造）ではないので、ラッチアップすることがなく、破壊耐量が向上する。 Since the emitter layer 11 is not in contact with the side wall of the second trench 8, it becomes a carrier discharge path during off-time, and the breakdown resistance against avalanche can be improved compared to the case without this. Specifically, the body layer 6 in contact with the side wall of the second trench 8 becomes a discharge path for holes generated by avalanche, and the holes are discharged to the emitter electrode 12 without being obstructed by the emitter layer 11. can do. In addition, the vertical structure of this region is not a parasitic thyristor structure (npnp thyristor structure formed of n+ of emitter layer 11/p of body layer 6/n- of drift layer 2/p of collector layer 4). There is no latch-up and the breakdown resistance is improved.
　さらに、実施例１の半導体装置１は、上記のようにオフ時のキャリア排出経路を設けてアバランシェに対する破壊耐量を確保しつつ、これとトレードオフの関係にあるＩＥ効果を高めてオン電圧の低減ができる構造を有している。具体的には、実施例１の半導体装置１は、縦断面における、第１のトレンチ７の幅をＷｇとし、第２のトレンチ８の幅をＷｅとし、第１のトレンチ７と第２のトレンチ８との間に挟まれたボディ層６の幅をＷｂとしたとき、Ｗｇ≦Ｗｂ、かつ、Ｗｅ／Ｗｂ≧２となっている。 Furthermore, the semiconductor device 1 of Example 1 provides a carrier discharge path during off-time as described above to ensure breakdown resistance against avalanche, while increasing the IE effect, which is in a trade-off relationship, to reduce on-voltage. It has a structure that allows for Specifically, in the semiconductor device 1 of Example 1, the width of the first trench 7 in the longitudinal section is Wg, the width of the second trench 8 is We, and the width of the first trench 7 and the second trench is Letting Wb be the width of the body layer 6 sandwiched between the body layer 6 and the body layer 8, Wg≦Wb and We/Wb≧2.
　ＷｇとＷｂの大きさは、通常用いられる範囲である０．５μｍ≦Ｗｇ≦１．８μｍ、０．５μｍ≦Ｗｂ≦１．８μｍであることが望ましいが、これに限られない。また、Ｗｂは、一般的にＷｇ以上であることが望ましいため、Ｗｇ≦Ｗｂとした。 The sizes of Wg and Wb are preferably within the commonly used ranges of 0.5 μm≦Wg≦1.8 μm and 0.5 μm≦Wb≦1.8 μm, but are not limited thereto. Furthermore, since it is generally desirable that Wb be greater than or equal to Wg, Wg≦Wb was set.
　その上で、Ｗｅ／Ｗｂ≧２、すなわち、第２のトレンチ８の幅（Ｗｅ）がボディ層６の幅（Ｗｂ）の２倍以上である幅広の第２のトレンチ８とした。上限の目安としてはＷｅ／Ｗｂ≦２０であるが、これに限られない。 In addition, the second trench 8 was wide so that We/Wb≧2, that is, the width (We) of the second trench 8 was at least twice the width (Wb) of the body layer 6. A rough guideline for the upper limit is We/Wb≦20, but it is not limited to this.
　実施例１の半導体装置１によれば、幅広の第２のトレンチ８により、ＩＧＢＴがオン状態の時に幅広の第２のトレンチ８の下に裏面のコレクタ側からのキャリアであるホールを多く蓄積することができるのでＩＥ効果を高めることができ、これにより表面のエミッタ側からの電子の注入が促進されオン電圧を低減できる。すなわち、幅広の第２のトレンチ８により、ＩＥ効果を高めてオン電圧の低減ができる。なお、蓄積されたホールは、その後、ボディ層６を経由してエミッタ電極１２に排出される。また、第２のトレンチ８を幅広にした場合でも、オフ時のキャリア排出経路は引き続き確保されているので、アバランシェに対する破壊耐量を確保しつつ、ＩＥ効果を高めてオン電圧の低減ができる。 In the semiconductor device 1 of the first embodiment, the wide second trench 8 allows a large number of holes, which are carriers from the collector side on the back surface, to be accumulated under the wide second trench 8 when the IGBT is in the on state, thereby enhancing the IE effect, which in turn promotes the injection of electrons from the emitter side on the front surface and reduces the on-voltage. In other words, the wide second trench 8 enhances the IE effect and reduces the on-voltage. The accumulated holes are then discharged to the emitter electrode 12 via the body layer 6. Even if the second trench 8 is made wider, the carrier discharge path during the off state is still secured, so the IE effect can be enhanced and the on-voltage can be reduced while securing the breakdown resistance against avalanches.
　さらに、トレンチ内エミッタ電極１３は、フィールドプレートとして働くので、第２のトレンチ８を幅広にした場合でも高耐圧を保持できる効果もある。 Furthermore, since the in-trench emitter electrode 13 functions as a field plate, it has the effect of maintaining a high breakdown voltage even when the second trench 8 is made wide.
　また、トレンチ内エミッタ電極１３は、トレンチ内絶縁膜１４によってドリフト層２から絶縁されているので、第２のトレンチ８の下に蓄積したホールがトレンチ内絶縁膜１４を貫通してトレンチ内エミッタ電極１３に抜けてしまうことがなく、ＩＥ効果を維持することができる。 Further, since the in-trench emitter electrode 13 is insulated from the drift layer 2 by the in-trench insulating film 14, the holes accumulated under the second trench 8 penetrate through the in-trench insulating film 14 to the in-trench emitter electrode. 13, and the IE effect can be maintained.
　ＩＥ効果を高めるための技術としては、トレンチゲートの間隔が狭い部分と広い部分とを設け、トレンチゲートの間隔が広い部分に第２導電型のフローティング層（フローティングＰ層）を設け、フローティング層にホールを蓄積する技術もある。しかしながら、フローティング層を設ける構成の場合、ＩＧＢＴがオン状態になると、フローティング層に過渡的にホールが流れ込み、フローティング層の電位が上昇し、フローティング層に隣接するトレンチゲートのゲート電位が持ち上げられ、ターンオン速度の加速が起こって、出力電圧の時間変化率ｄＶ／ｄｔの制御性が低下する問題が生じる可能性がある。これに対して、実施例１の半導体装置１によれば、そのような問題は発生せず、ｄＶ／ｄｔ制御性を確保できる。 As a technique to enhance the IE effect, trench gates are provided with a narrow part and a wide part, a floating layer of the second conductivity type (floating P layer) is provided in the part with a wide trench gate interval, and the floating layer is There is also a technique to accumulate holes. However, in the case of a structure in which a floating layer is provided, when the IGBT is turned on, holes transiently flow into the floating layer, the potential of the floating layer rises, and the gate potential of the trench gate adjacent to the floating layer is raised, and the IGBT is turned on. There is a possibility that speed acceleration occurs, causing a problem in which the controllability of the time rate of change of the output voltage dV/dt decreases. On the other hand, according to the semiconductor device 1 of Example 1, such a problem does not occur and dV/dt controllability can be ensured.
　実施例１の半導体装置１では、絶縁膜の信頼性が高いという効果もある。例えば、ターンオフ時は、高電界におけるキャリア（ホール）排出経路が主に第２のトレンチ８側となるので、スイッチング動作を行うゲート電極９が設けられた第１のトレンチ７はその影響を受けにくく、そうでない場合に比べゲート絶縁膜１０の信頼性は高くなる。また、第２のトレンチ８が幅広のトレンチとなっているので、細いトレンチが多数設けられているものに比べれば全体のトレンチの数が減り、ゲート電極９またはトレンチ内エミッタ電極１３と半導体基板のドリフト層２またはボディ層６との対向面積の合計（すべてのトレンチの対向面積の合計）が減るので、トレンチ内に設ける絶縁膜（ゲート絶縁膜１０とトレンチ内絶縁膜１４）の面積の合計も減り、細いトレンチが多数設けられているものに比べれば絶縁膜の信頼性確保に対するマージンは向上すると考えられる。 The semiconductor device 1 of Example 1 also has the effect that the reliability of the insulating film is high. For example, during turn-off, the carrier (hole) discharge path in a high electric field is mainly on the second trench 8 side, so the first trench 7 provided with the gate electrode 9 that performs the switching operation is less susceptible to this effect. , the reliability of the gate insulating film 10 is higher than in the case where this is not the case. In addition, since the second trench 8 is a wide trench, the total number of trenches is reduced compared to a structure with a large number of thin trenches, and the gate electrode 9 or emitter electrode 13 in the trench is connected to the semiconductor substrate. Since the total area facing the drift layer 2 or body layer 6 (total area facing all trenches) decreases, the total area of the insulating films provided in the trench (gate insulating film 10 and in-trench insulating film 14) also decreases. It is considered that the margin for ensuring the reliability of the insulating film is improved compared to the case where a large number of thin trenches are provided.
　実施例１の半導体装置１では、トレンチ内エミッタ電極１３が設けられた第２のトレンチ８を有することで、ゲート電極９が設けられた第１のトレンチ７の数が減るので、すべてが第１のトレンチ７の場合に比べて、コレクタ－ゲート間の容量である帰還容量を低減できるという効果もある。 In the semiconductor device 1 of the first embodiment, by having the second trench 8 provided with the in-trench emitter electrode 13, the number of first trenches 7 provided with the gate electrode 9 is reduced; There is also the effect that the feedback capacitance, which is the capacitance between the collector and the gate, can be reduced compared to the case of the trench 7 shown in FIG.
　帰還容量をさらに低減するためには、縦断面における第１のトレンチ７の深さをｔｄとしたとき、１．０μｍ≦ｔｄ≦２．０μｍとすることが望ましい。一般的なトレンチの深さは３μｍ～８μｍであることが多いが、それより浅いトレンチとすることで、帰還容量を低減することができる。なお、ＩＥ効果を高める観点においては浅いトレンチにすることは必須ではないので、上記以外の深さのトレンチにしてもよい。また、第１のトレンチ７と第２のトレンチ８とを同一のプロセスで製造するためには、第１のトレンチ７と第２のトレンチ８の深さを同じにすることが望ましい。 In order to further reduce the feedback capacitance, it is desirable that 1.0 μm≦td≦2.0 μm, where td is the depth of the first trench 7 in the longitudinal section. The depth of a typical trench is often 3 μm to 8 μm, but by making the trench shallower than that, feedback capacitance can be reduced. Note that from the viewpoint of enhancing the IE effect, it is not essential to make the trench shallow, so the trench may have a depth other than the above. Further, in order to manufacture the first trench 7 and the second trench 8 by the same process, it is desirable that the first trench 7 and the second trench 8 have the same depth.
　帰還容量をさらに低減するためには、縦断面における、第１のトレンチ７の側壁部のゲート絶縁膜１０の厚さをｔａとし、第１のトレンチ７の底面部のゲート絶縁膜１０の厚さをｔｂとしたとき、ｔａ＜ｔｂとすることが望ましい。なお、ＩＥ効果を高める観点においてはｔａ＜ｔｂは必須ではないので、ｔａ＝ｔｂとしてもよい。なお、ｔａ＜ｔｂの場合は、ｔａ＝ｔｂの場合よりも製造プロセスが増加するので、必要に応じて採用の可否を決めればよい。また、ゲート絶縁膜１０とトレンチ内絶縁膜１４とを同一のプロセスで製造するためには、トレンチ内絶縁膜１４の厚さをゲート絶縁膜１０の厚さと同じにすることが望ましい。 In order to further reduce the feedback capacitance, the thickness of the gate insulating film 10 at the side wall of the first trench 7 in the longitudinal section is ta, and the thickness of the gate insulating film 10 at the bottom of the first trench 7 is When is tb, it is desirable that ta<tb. Note that from the viewpoint of enhancing the IE effect, ta<tb is not essential, so ta=tb may be used. Note that in the case of ta<tb, the number of manufacturing processes is increased compared to the case of ta=tb, so whether or not to adopt the method may be determined as necessary. Furthermore, in order to manufacture the gate insulating film 10 and the in-trench insulating film 14 in the same process, it is desirable that the in-trench insulating film 14 has the same thickness as the gate insulating film 10 .
　以上説明した構成により、実施例１の半導体装置１によれば、ＩＧＢＴにおいて、オフ時のキャリア排出経路を設けてアバランシェに対する破壊耐量を確保しつつ、ＩＥ効果を高めてオン電圧の低減ができる半導体装置を提供することができる。また、ｄＶ／ｄｔ制御性や、絶縁膜の信頼性や、帰還容量の面も含め、トータルバランスに優れたＩＧＢＴを実現できる。 With the configuration described above, the semiconductor device 1 of Example 1 is a semiconductor that can reduce the on-voltage by increasing the IE effect while providing a carrier discharge path during off-state and securing breakdown resistance against avalanche in an IGBT. equipment can be provided. Further, it is possible to realize an IGBT with excellent total balance including dV/dt controllability, reliability of the insulating film, and feedback capacitance.
　実施例２以降は、実施例１の変形例である。実施例２以降では、相違点を中心に説明し、重複する説明は省略する。 Embodiment 2 and subsequent examples are modifications of Embodiment 1. In the second and subsequent embodiments, the differences will be mainly explained, and redundant explanations will be omitted.
　図２は、実施例２の半導体装置の縦断面図である。 FIG. 2 is a longitudinal cross-sectional view of the semiconductor device of Example 2.
　実施例２の半導体装置１は、第１のトレンチ７と第２のトレンチ８との間に挟まれたボディ層６とドリフト層２との間に設けられた、ドリフト層２よりも不純物濃度が高い第１導電型の第１のバリア層１７を有する点で、実施例１と相違する。 The semiconductor device 1 of Example 2 has an impurity concentration lower than that of the drift layer 2, which is provided between the body layer 6 and the drift layer 2 which are sandwiched between the first trench 7 and the second trench 8. This example differs from Example 1 in that it has a first barrier layer 17 of a high first conductivity type.
　第１のバリア層１７は、ＩＧＢＴがオン状態において、エミッタ側に流れ込むホールにとって障壁（バリア）になるので、第１のバリア層１７の下のホール濃度が増加し、ＩＧＢＴ導通時のオン電圧をさらに低減することができる。 The first barrier layer 17 acts as a barrier for holes flowing into the emitter side when the IGBT is on, so the hole concentration under the first barrier layer 17 increases, reducing the on-voltage when the IGBT is conductive. It can be further reduced.
　実施例２では、第１のバリア層１７の影響で実施例１に比べてアバランシェに対する破壊耐量は多少減少するものの、減少後の破壊耐量は確保しつつ、幅広の第２のトレンチ８によってＩＥ効果を高めてオン電圧の低減ができるという点では実施例１と同じ効果を得られる。 In Example 2, although the breakdown resistance against avalanche is somewhat reduced compared to Example 1 due to the influence of the first barrier layer 17, the reduced breakdown resistance is secured and the IE effect is improved by the wide second trench 8. The same effect as in Example 1 can be obtained in that the on-state voltage can be reduced by increasing the on-voltage.
　図３は、実施例３の半導体装置の縦断面図である。 FIG. 3 is a longitudinal cross-sectional view of the semiconductor device of Example 3.
　実施例３の半導体装置１は、第１のバリア層１７とドリフト層２との間に設けられた第２導電型の第２のバリア層１８を有する点で、実施例２と相違する。 The semiconductor device 1 of Example 3 differs from Example 2 in that it includes a second barrier layer 18 of the second conductivity type provided between the first barrier layer 17 and the drift layer 2.
　実施例２のように第１のバリア層１７を設けた場合、第１のバリア層１７はドリフト層２よりも不純物濃度が高いので、ＩＧＢＴがオフの時にＰＮ接合境界から空乏層が下に伸びにくくなり、ＩＧＢＴオフ時の耐圧マージンが低下するという問題がある。 When the first barrier layer 17 is provided as in Example 2, since the first barrier layer 17 has a higher impurity concentration than the drift layer 2, the depletion layer extends downward from the PN junction boundary when the IGBT is off. There is a problem in that the breakdown voltage margin when the IGBT is off decreases.
　そこで、実施例３では、第１のバリア層１７の下に第２導電型の第２のバリア層１８を設けることで、電界を緩和し、ＩＧＢＴオフ時の耐圧マージンを向上させることができる。 Therefore, in Example 3, by providing the second barrier layer 18 of the second conductivity type under the first barrier layer 17, the electric field can be relaxed and the breakdown voltage margin when the IGBT is off can be improved.
　図４は、実施例４の半導体装置の縦断面図である。 FIG. 4 is a longitudinal cross-sectional view of the semiconductor device of Example 4.
　実施例４の半導体装置１は、第２のトレンチ８が、一部の領域において第３のトレンチ２０と第４のトレンチ２１とに分割されており、第３のトレンチ２０と第４のトレンチ２１との間に挟まれた領域に、第１導電型の層が表面に形成されていない第２導電型の不活性ボディ層１９を有し、不活性ボディ層１９は、エミッタ電極１２と電気的に接続されている点で、実施例１と相違する。 In the semiconductor device 1 of the fourth embodiment, the second trench 8 is divided into a third trench 20 and a fourth trench 21 in a part of the region, and the third trench 20 and the fourth trench 21 are divided into a third trench 20 and a fourth trench 21. An inactive body layer 19 of a second conductivity type on the surface of which a layer of the first conductivity type is not formed is provided in a region sandwiched between the inert body layer 19 and the emitter electrode 12 . This is different from the first embodiment in that the first embodiment is connected to the second embodiment.
　すなわち、実施例４の半導体装置１は、図１のような縦断面の領域と、図４のような縦断面の領域とを有した構造となっている。したがって、第３のトレンチ２０と第４のトレンチ２１の内部には、第２のトレンチ８と同様に、トレンチ内エミッタ電極１３とトレンチ内絶縁膜１４とを有しており、図４以外の場所で図１の第２のトレンチ８とつながっているので、第３のトレンチ２０と第４のトレンチ２１の内部のトレンチ内エミッタ電極１３もエミッタ電位Ｅとなっている。 That is, the semiconductor device 1 of Example 4 has a structure having a vertical cross-sectional area as shown in FIG. 1 and a vertical cross-sectional area as shown in FIG. 4. Therefore, like the second trench 8, the third trench 20 and the fourth trench 21 have an in-trench emitter electrode 13 and an in-trench insulating film 14 at a location other than that shown in FIG. Since the third trench 20 and the fourth trench 21 are connected to the second trench 8 in FIG.
　不活性ボディ層１９は、キャリア排出経路として機能するので、不活性ボディ層１９を設けた領域ではＩＥ効果は減少するものの、ターンオフ時の破壊耐量のマージンをさらに向上させることができる。なお、実施例４の構造は、実施例１の製造プロセスと同じプロセスで、レイアウトの変更のみで実現可能である。 Since the inactive body layer 19 functions as a carrier discharge path, although the IE effect is reduced in the region where the inactive body layer 19 is provided, the margin of breakdown resistance at turn-off can be further improved. Note that the structure of the fourth embodiment can be realized by the same manufacturing process as the first embodiment, only by changing the layout.
　縦断面における不活性ボディ層１９の幅をＷｂ’としたとき、０．５μｍ≦Ｗｂ’≦１．８μｍであることが望ましいが、これに限られない。 When the width of the inactive body layer 19 in the longitudinal section is Wb', it is desirable that 0.5 μm≦Wb’≦1.8 μm, but it is not limited thereto.
　第３のトレンチ２０および第４のトレンチ２１の幅は、第２のトレンチ８と同様にＷｂの２倍以上であることが望ましいが、第２のトレンチ８で十分なＩＥ効果を得られているのであれば、第３のトレンチ２０および第４のトレンチ２１の幅はＷｂの２倍より小さくてもよい。 Although the width of the third trench 20 and the fourth trench 21 is preferably twice or more of Wb like the second trench 8, a sufficient IE effect can be obtained with the second trench 8. If so, the widths of the third trench 20 and the fourth trench 21 may be smaller than twice Wb.
　実施例４では、不活性ボディ層１９の影響で実施例１に比べてアバランシェに対する破壊耐量は向上し、ＩＥ効果は低減するものの、破壊耐量は確保しつつ、幅広の第２のトレンチ８（必要に応じて幅広の第３のトレンチ２０、第４のトレンチ２１も）によってＩＥ効果を高めてオン電圧の低減ができるという点では実施例１と同じ効果を得られる。 In Example 4, the breakdown resistance against avalanche is improved compared to Example 1 due to the influence of the inert body layer 19, and although the IE effect is reduced, the breakdown resistance is ensured and the wide second trench 8 (necessary The same effect as in the first embodiment can be obtained in that the IE effect can be enhanced and the on-voltage can be reduced by increasing the width of the third trench 20 and the fourth trench 21 (according to the width of the third trench 20 and the fourth trench 21).
　図５は、実施例５の半導体装置の縦断面図である。 FIG. 5 is a vertical cross-sectional view of a semiconductor device according to the fifth embodiment.
　実施例５は、実施例４に対して、実施例２の第１のバリア層１７を適用した実施例である。なお、キャリア排出の障害にならないよう、不活性ボディ層１９の下には第１のバリア層１７は設けないことが望ましい。もともと第１のバリア層１７は選択的に形成できるので、不活性ボディ層１９の下に第１のバリア層１７を設けないようにしても製造プロセスの増加はない。 Example 5 is an example in which the first barrier layer 17 of Example 2 is applied to Example 4. Note that it is desirable that the first barrier layer 17 is not provided under the inactive body layer 19 so as not to impede carrier discharge. Since the first barrier layer 17 can originally be formed selectively, there is no increase in the manufacturing process even if the first barrier layer 17 is not provided under the inactive body layer 19.
　図６は、実施例６の半導体装置の縦断面図である。 FIG. 6 is a longitudinal cross-sectional view of the semiconductor device of Example 6.
　実施例６は、実施例５に対して、実施例３の第２のバリア層１８を適用した実施例である。 Example 6 is an example in which the second barrier layer 18 of Example 3 is applied to Example 5.
　図７は、実施例７の半導体装置の縦断面図である。 FIG. 7 is a longitudinal cross-sectional view of the semiconductor device of Example 7.
　実施例７の半導体装置１は、エミッタ層１１とボディ層６とトレンチ内エミッタ電極１３とが、１つのコンタクトホール２２を介してエミッタ電極１２と接続されており、コンタクトホール２２の底面の位置はエミッタ層１１の底面の位置よりも深い点で、実施例１と相違する。 In the semiconductor device 1 of Example 7, the emitter layer 11, the body layer 6, and the in-trench emitter electrode 13 are connected to the emitter electrode 12 through one contact hole 22, and the bottom surface of the contact hole 22 is located at the position of the bottom surface of the contact hole 22. This embodiment differs from the first embodiment in that it is deeper than the bottom surface of the emitter layer 11.
　これにより、ボディ層６の幅（Ｗｂ）を小さくしたシュリンク型の基本セル構成１６とすることができるので、小型化できる、もしくは、同じ半導体基板の中に作り込める基本セルの数を増やすことができる。また、ボディ層６を経由したキャリア排出経路が狭くなるので、実施例１に比べてキャリアを蓄積する効果が高まり、ＩＥ効果を高めることができる。 This allows a shrink-type basic cell structure 16 in which the width (Wb) of the body layer 6 is reduced, making it possible to reduce the size or increase the number of basic cells that can be fabricated in the same semiconductor substrate. can. Further, since the carrier discharge path via the body layer 6 is narrowed, the effect of accumulating carriers is enhanced compared to the first embodiment, and the IE effect can be enhanced.
　なお、ボディ層６の幅（Ｗｂ）は、０．２５μｍ≦Ｗｂ≦１．８μｍであることが望ましいが、これに限られない。また、Ｗｂの下限が小さくなったことに伴い、Ｗｅ／Ｗｂの上限の目安は、Ｗｅ／Ｗｂ≦４０であることが望ましいが、これに限られない。 Note that the width (Wb) of the body layer 6 is preferably 0.25 μm≦Wb≦1.8 μm, but is not limited to this. Further, as the lower limit of Wb has become smaller, it is desirable that the upper limit of We/Wb be We/Wb≦40, but it is not limited to this.
　図８は、実施例８の半導体装置の縦断面図である。 FIG. 8 is a longitudinal cross-sectional view of the semiconductor device of Example 8.
　実施例８は、実施例７に対して、実施例２の第１のバリア層１７を適用した実施例である。 Example 8 is an example in which the first barrier layer 17 of Example 2 is applied to Example 7.
　図９は、実施例９の半導体装置の縦断面図である。 FIG. 9 is a longitudinal cross-sectional view of the semiconductor device of Example 9.
　実施例９は、実施例８に対して、実施例３の第２のバリア層１８を適用した実施例である。 Example 9 is an example in which the second barrier layer 18 of Example 3 is applied to Example 8.
　図１０は、実施例１０の半導体装置の縦断面図である。 FIG. 10 is a longitudinal cross-sectional view of the semiconductor device of Example 10.
　実施例１０は、実施例７に対して、実施例４の第３のトレンチ２０、第４のトレンチ２１、不活性ボディ層１９を適用した実施例である。不活性ボディ層１９は、コンタクトホール２２と同じプロセスで形成されたコンタクトホールを介してエミッタ電極１２と接続されている。 Example 10 is an example in which the third trench 20, fourth trench 21, and inactive body layer 19 of Example 4 are applied to Example 7. Inactive body layer 19 is connected to emitter electrode 12 through a contact hole formed in the same process as contact hole 22 .
　実施例１０は、実施例４と同様に、図７のような縦断面の領域と、図１０のような縦断面の領域とを有した構造となっている。 Similarly to Example 4, Example 10 has a structure having a vertical cross-sectional area as shown in FIG. 7 and a vertical cross-sectional area as shown in FIG. 10.
　なお、縦断面における不活性ボディ層１９の幅をＷｂ’としたとき、０．２５μｍ≦Ｗｂ’≦１．８μｍであることが望ましいが、これに限られない。 When the width of the inactive body layer 19 in the longitudinal section is Wb', it is desirable that 0.25 μm≦Wb'≦1.8 μm, but this is not limited to this.
　図１１は、実施例１１の半導体装置の縦断面図である。 FIG. 11 is a longitudinal cross-sectional view of the semiconductor device of Example 11.
　実施例１１は、実施例１０に対して、実施例２の第１のバリア層１７を適用した実施例である。 Example 11 is an example in which the first barrier layer 17 of Example 2 is applied to Example 10.
　図１２は、実施例１２の半導体装置の縦断面図である。 FIG. 12 is a longitudinal cross-sectional view of the semiconductor device of Example 12.
　実施例１２は、実施例１１に対して、実施例３の第２のバリア層１８を適用した実施例である。 Example 12 is an example in which the second barrier layer 18 of Example 3 is applied to Example 11.
　図１３は、実施例１３の半導体装置の製造方法のプロセスフローである。 Figure 13 shows the process flow of the manufacturing method of the semiconductor device of Example 13.
　実施例１３は、実施例１から実施例１２の半導体装置１の製造方法の一例を説明する実施例である。 Example 13 is an example for explaining an example of a method for manufacturing the semiconductor device 1 of Examples 1 to 12.
　図１３に示すように、基本的には一般的な半導体装置の製造方法と同じであり、ステップＳ１のウェハ準備工程において半導体基板のウェハを準備し、ステップＳ２の終端領域拡散層形成工程において、図１から図１２では図示していない終端領域に第２導電型の拡散層（深いＰウェル層とも呼ばれる）を形成し、ステップＳ３のトレンチ形成工程において、トレンチを形成し、ステップＳ４のポリシリコン電極形成工程において、ポリシリコンでゲート電極９およびトレンチ内エミッタ電極１３を形成し、ステップＳ５のボディ層・エミッタ層形成工程において、ボディ層６とエミッタ層１１を形成する。 As shown in FIG. 13, the method is basically the same as a general semiconductor device manufacturing method, in which a wafer of a semiconductor substrate is prepared in the wafer preparation step of step S1, and a wafer of a semiconductor substrate is prepared in the step S2 of forming a termination region diffusion layer. A second conductivity type diffusion layer (also called a deep P well layer) is formed in the termination region (not shown in FIGS. 1 to 12), a trench is formed in the trench formation process of step S3, and a polysilicon In the electrode forming step, the gate electrode 9 and the in-trench emitter electrode 13 are formed of polysilicon, and in the body layer/emitter layer forming step of step S5, the body layer 6 and the emitter layer 11 are formed.
　なお、ここでは浅いトレンチを想定しているので、ステップＳ５においてボディ層６を形成しているが、深いトレンチの場合には、ステップＳ２においてボディ層６も一緒に形成するように変更してもよい。 Note that since a shallow trench is assumed here, the body layer 6 is formed in step S5, but in the case of a deep trench, the body layer 6 may also be formed in step S2. good.
　ステップＳ６の絶縁膜形成・コンタクト開口工程において、層間絶縁膜１５とコンタクトホールを形成し、ステップＳ７のメタル電極形成工程において、エミッタ電極１２を形成し、ステップＳ８の裏面プロセス工程において、薄ウェハ化や裏面の不純物注入を含む裏面プロセスを行い、ステップＳ９の裏面電極形成工程において、コレクタ電極５を形成し、ステップＳ１０のウェハ検査工程においてウェハ検査を行って完成となる。 In the insulating film formation/contact opening step of step S6, the interlayer insulating film 15 and contact holes are formed, the emitter electrode 12 is formed in the metal electrode forming step of step S7, and the wafer is thinned in the back surface process of step S8. A back surface process including impurity implantation on the back surface is performed, a collector electrode 5 is formed in the back surface electrode forming step of step S9, and a wafer is inspected in the wafer inspection step of step S10 to complete the process.
　図１４Ａから図１４Ｆは、実施例１３の半導体装置の製造方法を説明する縦断面図である。図１４Ａから図１４Ｆは、図１３のステップＳ３およびステップＳ４において、第２のトレンチ８のような幅広の浅いトレンチを形成し、内部にトレンチ内絶縁膜とポリシリコン電極を形成する方法を説明する図である。なお、第１のトレンチ７のような幅広ではない浅いトレンチも同じプロセスで同時に作ることができる。 14A to 14F are longitudinal cross-sectional views illustrating a method for manufacturing a semiconductor device of Example 13. 14A to 14F illustrate a method of forming a wide shallow trench such as the second trench 8 in steps S3 and S4 of FIG. 13, and forming an insulating film and a polysilicon electrode inside the trench. It is a diagram. Note that shallow trenches that are not wide, such as the first trench 7, can also be made at the same time using the same process.
　はじめに、図１４Ａに示すように、例えばシリコン基板などの半導体基板３１の上に、下から順に酸化膜３２、シリコン窒化膜３３、ＣＶＤ絶縁膜３４、レジスト３５を積層して積層膜を形成する。 First, as shown in FIG. 14A, on a semiconductor substrate 31 such as a silicon substrate, an oxide film 32, a silicon nitride film 33, a CVD insulating film 34, and a resist 35 are laminated in order from the bottom to form a laminated film.
　次に、図１４Ｂに示すように、パターニングと積層膜のエッチングを行ったのち、トレンチ３６のエッチングを行う。 Next, as shown in FIG. 14B, after patterning and etching the laminated film, the trench 36 is etched.
　次に、図１４Ｃに示すように、レジスト３５を除去した後、トレンチ３６内のシリコン表面を酸化してトレンチ内酸化膜３７を形成する。 Next, as shown in FIG. 14C, after removing the resist 35, the silicon surface within the trench 36 is oxidized to form an in-trench oxide film 37.
　次に、図１４Ｄに示すように、ポリシリコン３８の膜の形成と、レジスト３５の塗布およびベークを行う。 Next, as shown in FIG. 14D, a film of polysilicon 38 is formed, a resist 35 is applied, and baking is performed.
　次に、図１４Ｅに示すように、レジスト３５とポリシリコン３８の全面エッチバックを行う。なお、図１４Ｅは一例であり、レジスト３５とポリシリコン３８のエッチングレートがほぼ同一である場合を示しているが、これに限られない。 Next, as shown in FIG. 14E, the resist 35 and polysilicon 38 are etched back over the entire surface. Note that FIG. 14E is an example, and shows a case where the etching rates of the resist 35 and polysilicon 38 are approximately the same, but this is not limiting.
　最後に、図１４Ｆに示すように、ＣＶＤ絶縁膜３４とシリコン窒化膜３３を除去する。これによって、幅広の浅いトレンチと、トレンチ内部に設けられたトレンチ内絶縁膜およびポリシリコン電極を形成することができる。 Finally, as shown in FIG. 14F, the CVD insulating film 34 and silicon nitride film 33 are removed. As a result, a wide shallow trench, an in-trench insulating film and a polysilicon electrode provided inside the trench can be formed.
　以上、本発明の実施例を説明したが、本発明は実施例に記載された構成に限定されず、本発明の技術的思想の範囲内で種々の変更が可能である。また、各実施例で説明した構成の一部または全部を組み合わせて適用してもよい。 Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various changes can be made within the scope of the technical idea of the present invention. Further, some or all of the configurations described in each embodiment may be combined and applied.
　１…半導体装置、２…ドリフト層、３…バッファ層、４…コレクタ層、５…コレクタ電極、６…ボディ層、７…第１のトレンチ、８…第２のトレンチ、９…ゲート電極、１０…ゲート絶縁膜、１１…エミッタ層、１２…エミッタ電極、１３…トレンチ内エミッタ電極、１４…トレンチ内絶縁膜、１５…層間絶縁膜、１６…基本セル構成、１７…第１のバリア層、１８…第２のバリア層、１９…不活性ボディ層、２０…第３のトレンチ、２１…第４のトレンチ、２２…コンタクトホール、３１…半導体基板、３２…酸化膜、３３…シリコン窒化膜、３４…ＣＶＤ絶縁膜、３５…レジスト、３６…トレンチ、３７…トレンチ内酸化膜、３８…ポリシリコン DESCRIPTION OF SYMBOLS 1... Semiconductor device, 2... Drift layer, 3... Buffer layer, 4... Collector layer, 5... Collector electrode, 6... Body layer, 7... First trench, 8... Second trench, 9... Gate electrode, 10 ... Gate insulating film, 11... Emitter layer, 12... Emitter electrode, 13... Emitter electrode in trench, 14... Insulating film in trench, 15... Interlayer insulating film, 16... Basic cell configuration, 17... First barrier layer, 18 ...Second barrier layer, 19...Inactive body layer, 20...Third trench, 21...Fourth trench, 22...Contact hole, 31...Semiconductor substrate, 32...Oxide film, 33...Silicon nitride film, 34 ...CVD insulating film, 35...resist, 36...trench, 37...oxide film in trench, 38...polysilicon

Claims (15)

  1. 　第１導電型のドリフト層と、
    　前記ドリフト層よりも裏面側に設けられた第２導電型のコレクタ層と、
    　前記コレクタ層に電気的に接続されたコレクタ電極と、
    　前記ドリフト層よりも表面側に設けられた第２導電型のボディ層と、
    　ボディ層を貫き前記ドリフト層に達する第１のトレンチおよび第２のトレンチと、
    　前記第１のトレンチの内部に設けられたゲート電極と、
    　前記第１のトレンチの内部の側壁部と前記ゲート電極との間および底面部と前記ゲート電極との間に設けられたゲート絶縁膜と、
    　前記第２のトレンチの内部に設けられたトレンチ内エミッタ電極と、
    　前記第２のトレンチの内部の側壁部と前記トレンチ内エミッタ電極との間および底面部と前記トレンチ内エミッタ電極との間に設けられたトレンチ内絶縁膜と、
    　前記ボディ層の表面に設けられ、前記第１のトレンチに接し、前記第２のトレンチからは離間した第１導電型のエミッタ層と、
    　前記エミッタ層と前記ボディ層と前記トレンチ内エミッタ電極とに電気的に接続されたエミッタ電極と、を有し、
    　２つの前記第２のトレンチの間に前記第１のトレンチと２つの前記ボディ層とが配置された半導体装置において、
    　縦断面における、前記第１のトレンチの幅をＷｇとし、前記第２のトレンチの幅をＷｅとし、前記第１のトレンチと前記第２のトレンチとの間に挟まれた前記ボディ層の幅をＷｂとしたとき、Ｗｇ≦Ｗｂ、かつ、Ｗｅ／Ｗｂ≧２であることを特徴とする半導体装置。     a first conductivity type drift layer;
    a collector layer of a second conductivity type provided on the back side of the drift layer;
    a collector electrode electrically connected to the collector layer;
    a body layer of a second conductivity type provided on the surface side of the drift layer;
    a first trench and a second trench that penetrate the body layer and reach the drift layer;
    a gate electrode provided inside the first trench;
    a gate insulating film provided between a side wall part inside the first trench and the gate electrode and between a bottom part and the gate electrode;
    an in-trench emitter electrode provided inside the second trench;
    an in-trench insulating film provided between an inner side wall part of the second trench and the in-trench emitter electrode and between a bottom part and the in-trench emitter electrode;
    an emitter layer of a first conductivity type provided on the surface of the body layer, in contact with the first trench, and spaced apart from the second trench;
    an emitter electrode electrically connected to the emitter layer, the body layer, and the in-trench emitter electrode;
    In a semiconductor device in which the first trench and the two body layers are arranged between the two second trenches,
    In the longitudinal section, the width of the first trench is Wg, the width of the second trench is We, and the width of the body layer sandwiched between the first trench and the second trench is A semiconductor device characterized in that, where Wb, Wg≦Wb and We/Wb≧2.
  2. 　請求項１において、
    　０．５μｍ≦Ｗｇ≦１．８μｍであることを特徴とする半導体装置。     In claim 1,
    A semiconductor device characterized in that 0.5 μm≦Wg≦1.8 μm.
  3. 　請求項１において、
    　縦断面における前記第１のトレンチの深さをｔｄとしたとき、１．０μｍ≦ｔｄ≦２．０μｍであることを特徴とする半導体装置。     In claim 1,
    A semiconductor device characterized in that, where td is a depth of the first trench in a longitudinal section, 1.0 μm≦td≦2.0 μm.
  4. 　請求項１において、
    　縦断面における、前記第１のトレンチの前記側壁部の前記ゲート絶縁膜の厚さをｔａとし、前記第１のトレンチの前記底面部の前記ゲート絶縁膜の厚さをｔｂとしたとき、ｔａ＜ｔｂであることを特徴とする半導体装置。     In claim 1,
    When the thickness of the gate insulating film on the side wall part of the first trench in the longitudinal section is ta, and the thickness of the gate insulating film on the bottom part of the first trench is tb, ta< A semiconductor device characterized by being tb.
  5. 　請求項１において、
    　０．５μｍ≦Ｗｂ≦１．８μｍであることを特徴とする半導体装置。     In claim 1,
    A semiconductor device characterized in that 0.5 μm≦Wb≦1.8 μm.
  6. 　請求項１において、
    　Ｗｅ／Ｗｂ≦２０であることを特徴とする半導体装置。     In claim 1,
    A semiconductor device characterized in that We/Wb≦20.
  7. 　請求項１において、
    　前記第１のトレンチと前記第２のトレンチとの間に挟まれた前記ボディ層と前記ドリフト層との間に設けられた、前記ドリフト層よりも不純物濃度が高い第１導電型の第１のバリア層を有することを特徴とする半導体装置。     In claim 1,
    a first barrier layer of a first conductivity type having an impurity concentration higher than that of the drift layer, the first barrier layer being provided between the body layer sandwiched between the first trench and the second trench and the drift layer.
  8. 　請求項７において、
    　前記第１のバリア層と前記ドリフト層との間に設けられた第２導電型の第２のバリア層を有することを特徴とする半導体装置。     In claim 7,
    A semiconductor device comprising a second barrier layer of a second conductivity type provided between the first barrier layer and the drift layer.
  9. 　請求項１において、
    　前記第２のトレンチは、一部の領域において第３のトレンチと第４のトレンチとに分割されており、
    　前記第３のトレンチと前記第４のトレンチとの間に挟まれた領域に、第１導電型の層が表面に形成されていない第２導電型の不活性ボディ層を有し、
    　前記不活性ボディ層は、前記エミッタ電極と電気的に接続されていることを特徴とする半導体装置。     In claim 1,
    The second trench is divided into a third trench and a fourth trench in some regions,
    In a region sandwiched between the third trench and the fourth trench, an inactive body layer of a second conductivity type on the surface of which a layer of the first conductivity type is not formed;
    A semiconductor device, wherein the inactive body layer is electrically connected to the emitter electrode.
  10. 　請求項９において、
    　縦断面における前記不活性ボディ層の幅をＷｂ’としたとき、０．５μｍ≦Ｗｂ’≦１．８μｍであることを特徴とする半導体装置。     In claim 9,
    A semiconductor device characterized in that, where Wb' is a width of the inactive body layer in a longitudinal section, 0.5 μm≦Wb′≦1.8 μm.
  11. 　請求項１において、
    　前記エミッタ層と前記ボディ層と前記トレンチ内エミッタ電極とが、１つのコンタクトホールを介して前記エミッタ電極と接続されており、
    　前記コンタクトホールの底面の位置は前記エミッタ層の底面の位置よりも深いことを特徴とする半導体装置。     In claim 1,
    The emitter layer, the body layer, and the in-trench emitter electrode are connected to the emitter electrode through one contact hole,
    A semiconductor device, wherein the bottom of the contact hole is deeper than the bottom of the emitter layer.
  12. 　請求項１１において、
    　０．２５μｍ≦Ｗｂ≦１．８μｍであることを特徴とする半導体装置。     In claim 11,
    A semiconductor device characterized in that 0.25 μm≦Wb≦1.8 μm.
  13. 　請求項１１において、
    　Ｗｅ／Ｗｂ≦４０であることを特徴とする半導体装置。     In claim 11,
    A semiconductor device characterized in that We/Wb≦40.
  14. 　請求項１１において、
    　前記第２のトレンチは、一部の領域において第３のトレンチと第４のトレンチとに分割されており、
    　前記第３のトレンチと前記第４のトレンチとの間に挟まれた領域に、第１導電型の層が表面に形成されていない第２導電型の不活性ボディ層を有し、
    　前記不活性ボディ層は、前記エミッタ電極と電気的に接続されていることを特徴とする半導体装置。     In claim 11,
    The second trench is divided into a third trench and a fourth trench in some regions,
    In a region sandwiched between the third trench and the fourth trench, an inactive body layer of a second conductivity type on the surface of which a layer of the first conductivity type is not formed;
    A semiconductor device, wherein the inactive body layer is electrically connected to the emitter electrode.
  15. 　請求項１４において、
    　縦断面における前記不活性ボディ層の幅をＷｂ’としたとき、０．２５μｍ≦Ｗｂ’≦１．８μｍであることを特徴とする半導体装置。     In claim 14,
    A semiconductor device characterized in that, where Wb' is a width of the inactive body layer in a longitudinal section, 0.25 μm≦Wb′≦1.8 μm.
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