WO2024060329A1

WO2024060329A1 - Semiconductor package structure and manufacturing method therefor

Info

Publication number: WO2024060329A1
Application number: PCT/CN2022/124198
Authority: WO
Inventors: 季宏凯
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-09-22
Filing date: 2022-10-09
Publication date: 2024-03-28
Also published as: CN117810185A

Abstract

A semiconductor package structure and a manufacturing method therefor. The semiconductor package structure (100) comprises: a first substrate (1); a processor module (4) and a chip stack structure (5) which are both arranged on a first flat surface of the first substrate (1), the chip stack structure (5) comprising: a first semiconductor chip (51) connected to the first substrate (1), and a second semiconductor chip stack structure (52) located on the first semiconductor chip (51) and comprising a plurality of second semiconductor chips (521) successively stacked in a first direction, the first direction being parallel to the first flat surface of the first substrate (1); a second substrate (2) arranged in a second direction and electrically connected to the second semiconductor chip stack structure (52), a first end in the second direction being provided with a first connection apparatus (21), and the second direction being perpendicular to the first flat surface of the first substrate (1); and a third substrate (3) connected to a second flat surface of the first substrate (1), a first end in the second direction being provided with a second connection apparatus (31), and the first connection apparatus (21) and the second connection apparatus (31) being both used for flexible connection. An integrated replaceable data processing system can be formed.

Description

Semiconductor packaging structure and preparation method thereof

cross reference

This disclosure claims priority to the Chinese patent application with application number 202211160972.8 and titled "Semiconductor Package Structure and Preparation Method Therefor" filed on September 22, 2022. The entire content of this Chinese patent application is incorporated herein by reference.

Technical field

The present disclosure relates to the technical field of integrated circuit manufacturing, and specifically, to a semiconductor packaging structure and a preparation method thereof.

Background technique

As the most important component of electronic equipment hardware, the data processing system formed by DRAM (Dynamic Random Access Memory) and processor (CPU or GPU) is usually the most expensive component in an electronic equipment hardware. .

In conventional technology, the processor and DRAM are fixedly soldered on the motherboard, and because the processor and DRAM have a large number of lead-out signals, the processor and DRAM are usually packaged in BGA (Ball Grid Array) or FBGA (Fine-pitch Ball Grid Array) packages, and the pins used to connect to the motherboard pads are arranged in an array at the bottom of the package. When performing repairs or reconfigurations, it is usually difficult to remove the factory welding or re-solder them manually, which directly leads to high equipment maintenance costs. Once there is a problem with the processor or DRAM, the entire electronic device has little repair value, and may even lead to the entire electronic device being discarded.

It should be noted that the information disclosed in the above background section is only used to enhance understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those of ordinary skill in the art.

Contents of the invention

The purpose of this disclosure is to provide a semiconductor packaging structure and a preparation method thereof for forming a removable connected integrated data processing system.

According to a first aspect of the present disclosure, a semiconductor packaging structure is provided, including: a first substrate; a processor module disposed on a first plane of the first substrate and connected to the first substrate; and a chip stack structure disposed The first plane of the first substrate is connected to the first substrate, wherein the chip stack structure includes: a first semiconductor chip connected to the first substrate; a second semiconductor chip stack structure located on the first plane of the first substrate. The first semiconductor chip includes a plurality of second semiconductor chips stacked sequentially along a first direction, the first direction being parallel to the first plane of the first substrate; the second substrate is arranged along the second direction, and The second semiconductor chip stack structure is electrically connected, and a first connection device is provided at the first end along the second direction, which is perpendicular to the first plane of the first substrate; the third substrate is connected The second plane of the first substrate is provided with a second connecting device along the first end in the second direction. The second plane of the first substrate is parallel to and opposite to the first plane of the first substrate.

In an exemplary embodiment of the present disclosure, the first connection device includes a plurality of gold fingers, and the second connection device includes a plurality of pins distributed in a grid array.

In an exemplary embodiment of the present disclosure, the first connection device and the second connection device are horizontal in the first direction.

In an exemplary embodiment of the present disclosure, the gold finger includes a first gold finger and a second gold finger, the first gold finger is used to connect a ground line on the second substrate, and the second gold finger The gold finger is used to connect the power line on the second substrate.

In an exemplary embodiment of the present disclosure, at least one first gold finger is spaced between two adjacent second gold fingers.

In an exemplary embodiment of the present disclosure, the second substrate is electrically connected to the second semiconductor chip stack structure through a first conductive bump, and the first conductive bump includes a first sub-conductive bump and The second sub-conductive bump, the first sub-conductive bump is electrically connected to the ground line on the second substrate, and the second sub-conductive bump is electrically connected to the power line on the second substrate.

In an exemplary embodiment of the present disclosure, at least one first sub-conductive bump is spaced between two adjacent second sub-conductive bumps, and the first sub-conductive bump surrounds the second sub-conductive bump. Conductive bumps.

In an exemplary embodiment of the present disclosure, a second substrate gap is provided between at least two gold fingers.

In an exemplary embodiment of the present disclosure, the second semiconductor chip stack structure includes a preset number of sub-stack structures, the sub-stack structures are arranged around the processor module, and the second substrate is in the sub-stack structure. Set separately on one side relative to the processor module.

In an exemplary embodiment of the present disclosure, the sub-stack structure includes: a plurality of second semiconductor chips stacked in sequence along the first direction, each of the second semiconductor chips being provided with a plurality of through silicon vias, the through silicon vias penetrating the second semiconductor chip along the first direction, and the positions of the through silicon vias of two adjacent second semiconductor chips corresponding to each other; a plurality of second conductive bumps located between two adjacent second semiconductor chips and correspondingly connected to the through silicon vias; a plurality of first conductive bumps arranged on a first side of the sub-stack structure along the first direction and correspondingly connected to the through silicon vias; wherein the plurality of sub-stack structures are arranged in parallel along the first direction, and the through silicon via of one sub-stack structure on the first side of the first direction is used to connect the first conductive bump of another sub-stack structure.

In an exemplary embodiment of the present disclosure, the first semiconductor chip is connected to the first substrate via stacked structure connection bumps to achieve signal connection, and the first substrate is connected to the third substrate via substrate connection bumps to achieve signal connection.

In an exemplary embodiment of the present disclosure, the first semiconductor chip includes a logic chip, and the second semiconductor chip stack structure includes a DRAM chip.

In an exemplary embodiment of the present disclosure, the first semiconductor chip and the second semiconductor chip stack structure communicate through wireless communication.

In an exemplary embodiment of the present disclosure, it further includes: a packaging compound structure located on the third substrate for wrapping the first substrate, the second substrate, the processor module, the Chip stack structure.

According to a second aspect of the present disclosure, a method for preparing a semiconductor packaging structure is provided, which is used to prepare the semiconductor packaging structure as described in any one of the above, including: forming a first semiconductor chip, a processor module, a first substrate, a second substrate The substrate and the third substrate; forming a second semiconductor chip stack structure, the second semiconductor chip stack structure including a plurality of second semiconductor chips stacked in sequence; disposing the second semiconductor chip stack structure on the first semiconductor chip to form a chip stack structure; dispose the chip stack structure and the processor module on the first substrate; dispose the first substrate on the third substrate; dispose the second substrate Signal connection is made with the second semiconductor chip stack structure.

In an exemplary embodiment of the present disclosure, forming the second semiconductor chip stack structure includes: forming a plurality of sub-stack structures, each of the sub-stack structures including second semiconductor chips sequentially stacked along a first direction and a configuration A plurality of first conductive bumps on the first side of the first direction; connecting the plurality of sub-stack structures through the plurality of first conductive bumps, and connecting the first conductive bumps located in the first direction. The first conductive bumps of the sub-stack structure on one side serve as the first conductive bumps connecting the second semiconductor chip stack structure to the second substrate.

In an exemplary embodiment of the present disclosure, forming a plurality of sub-stack structures includes: forming a plurality of through silicon vias penetrating the second semiconductor chip along the first direction; Second conductive bumps are provided between the chips, and the second conductive bumps are correspondingly connected to the through silicon holes; a plurality of the second semiconductor chips are connected through hybrid bonding, and one of the second semiconductor chips located on the edge is The plurality of first conductive bumps are formed on the surface of the two semiconductor chips, and the first conductive bumps are correspondingly connected to the through silicon vias.

In embodiments of the present disclosure, the semiconductor stack structure and the processor module are disposed on the first substrate, and the first substrate for movable connection is respectively disposed on the second substrate connected to the semiconductor stack structure and the third substrate connected to the first substrate. The connection device and the second connection device can realize the movable connection between the combination of the semiconductor stack structure and the processor module and the mainboard of the electronic device, thereby realizing an integrated data processing system that can be completely removed and replaced as a whole.

It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and do not limit the present disclosure.

Description of the drawings

The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

FIG. 1 is a schematic structural diagram of a semiconductor packaging structure in an exemplary embodiment of the present disclosure.

FIG. 2 is a schematic diagram of a semiconductor packaging structure in another embodiment of the present disclosure.

FIG. 3 is a schematic diagram of a chip stack structure in an embodiment of the present disclosure.

FIG. 4 is a schematic diagram of a second substrate and a first conductive bump in an embodiment of the present disclosure.

FIG. 5 is a side view of the first sub-conductive bump and the second sub-conductive bump along the first direction in an embodiment of the present disclosure.

Figure 6 is a schematic diagram of the structure of an encapsulating compound in one embodiment of the present disclosure.

Figure 7 is a schematic diagram of a filling layer in one embodiment of the present disclosure.

FIG. 8 is a flow chart of a method for manufacturing a semiconductor packaging structure in one embodiment of the present disclosure.

9A to 9E are process schematic diagrams of step S2 in an embodiment of the present disclosure.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art. The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.

In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and/or processor devices and/or microcontroller devices.

Example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of a semiconductor package structure in an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , a semiconductor packaging structure 100 may include:

first substrate 1;

The processor module 4 is arranged on the first plane of the first substrate 1 and is connected to the first substrate 1;

The chip stack structure 5 is arranged on the first plane of the first substrate 1 and is connected to the first substrate 1. The chip stack structure 5 includes:

The first semiconductor chip 51 is connected to the first substrate 1;

The second semiconductor chip stack structure 52 is located on the first semiconductor chip 51 and includes a plurality of second semiconductor chips 521 sequentially stacked along a first direction, and the first direction is parallel to the first plane of the first substrate 1;

The second substrate 2 is arranged along the second direction and connected to the second semiconductor chip stack structure 52. A first connection device 21 is arranged at the first end along the second direction. The second direction is perpendicular to the first plane of the first substrate 1. ;

The third substrate 3 is connected to the second plane of the first substrate 1 and is provided with a second connecting device 31 at the first end along the second direction. The second plane of the first substrate 1 is parallel to the first plane of the first substrate 1 and relatively.

In the embodiment of the present disclosure, the first connection device 21 and the second connection device 31 are horizontal in the first direction and are removably connected to the motherboard (not shown) of the electronic device, so that the entire semiconductor package structure 100 can be An integral part capable of removable connection to the motherboard.

The second semiconductor chip stack structure 52 is formed with a plurality of first conductive bumps 10 on one side along the first direction, and the second substrate 2 is connected to the second semiconductor chip stack structure 52 through the first conductive bumps 10 .

In an embodiment, the first substrate 1 may be a printed circuit board (PCB) or a redistribution substrate (Inter Poser). The first substrate 1 may include a first substrate (not shown) and a first upper insulating dielectric layer (not shown) and a first lower insulating dielectric layer (not shown) respectively located on the upper surface and lower surface of the first substrate. ). The first substrate may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate, etc., It can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked structure, such as Si/SiGe, etc., and can also be other epitaxial structures, such as SGOI (silicon germanium on insulator), etc. The first upper insulating dielectric layer and the first lower insulating dielectric layer may be solder resist layers. For example, the material of the first upper insulating dielectric layer and the first lower insulating dielectric layer may be green paint. In the embodiment of the present disclosure, the surface corresponding to the first upper insulating dielectric layer is called the first plane of the first substrate 1 (the upper surface in FIG. 1 ), and the surface corresponding to the first lower insulating dielectric layer is called the first plane. The second plane of the substrate 1 (lower surface in Figure 1).

The processor module 4 and the chip stack structure 5 are disposed on the first plane of the first substrate 1 , and the first substrate 1 is used to provide a wired communication channel between the processor 4 and the chip stack structure 5 .

Referring to FIG. 2 , in the embodiment of the present disclosure, the number of processor modules 4 provided on the first substrate 1 may be one or more, and the number of chip stack structures 5 may be one or more. Multiple. When there are multiple chip stack structures 5 , they can be arranged around one or more processor modules 4 to facilitate connection to the second substrate 2 .

In the embodiment shown in FIG2 , the number of the processor module 4 is 1. It is arranged at the center of the first substrate 1. According to the size of the first substrate 1 and the size of the chip stacking structure 5, two, four or more chip stacking structures 5 may be arranged on the first substrate 1 to surround the processor module 4. FIG2 may be regarded as a cross-sectional view in the first direction, and the specific number of the chip stacking structures 5 is not limited thereto.

Continuing to refer to FIG. 1 , a substrate connection bump 11 is formed on the second plane of the first substrate 1 . The substrate connection bump 11 can electrically connect the first substrate 1 to the third substrate 3 . The third substrate 3 is used to pass through the third substrate 1 . The second connection structure 31 is connected to the motherboard of the electronic device. Therefore, while the first substrate 1 provides a signal path for the processor module 4 and the chip stack structure 5, it can also receive at least one of the data to be processed, the power signal and the ground signal from the mainboard from the third substrate 3, or The control commands and data signals issued by the processor module 4 are provided to the third substrate 3 and thus to the main board.

The substrate connection bumps 11 include conductive material. In the embodiment of the present disclosure, the substrate connection bumps 11 are solder balls. It can be understood that the shape of the substrate connection bumps provided in the embodiment of the present disclosure is only a lower and feasible specific shape in the embodiment of the present disclosure. The embodiments do not limit the present disclosure, and the substrate connection bumps may also have other shapes and structures. The number, spacing, and location of the substrate connection bumps are not limited to any specific arrangement and may be modified in various ways.

The processor module 4 disposed on the first plane of the first substrate 1 is, for example, a CPU or a GPU, and has an independent package. The processor module 4 is connected to the first plane of the first substrate 1 through processor connection bumps 41 .

The chip stack structure 5 also disposed on the first plane of the first substrate 1 includes a first chip 51 and a second semiconductor chip stack structure 52. In one embodiment, a chip for communicating with the second semiconductor chip 51 is formed on one side of the first semiconductor chip 51. A stacked structure connected to the substrate 1 is connected to the bumps 53 . The first semiconductor chip 51 and the first substrate 1 are electrically connected through the stacked structure connecting bumps 53 . The first substrate 1 supplies power to the first semiconductor chip 51 and performs signal exchange through wires.

The materials of the processor connection bump 41 and the stacked structure connection bump 53 may include, for example, at least one of aluminum, copper, nickel, tungsten, platinum, and gold.

In one embodiment, when the first chip 51 in the chip stack structure 5 is disposed on the first substrate 1 , as shown in FIG. 1 , the process is simple, and there is a gap between the first semiconductor chip 51 and the first substrate 1 The gap can increase the heat dissipation effect of the first semiconductor chip 51 . At this time, the stacked structure connecting bump 53 and the processor connecting bump 41 are horizontal in the first direction.

In another embodiment, the stacked structure connecting bumps 53 may also be disposed in grooves (not shown) on the first substrate 1 to improve structural stability and reduce the packaging height of the semiconductor packaging structure. In addition, the first chip 51 in the chip stack structure 5 can also be partially disposed in the groove to achieve the effect of the chip stack structure 5 being partially embedded in the first substrate 1, further improving structural stability and reducing the packaging height of the semiconductor packaging structure. . At this time, the stacked structure connecting bump 53 is lower than the processor connecting bump 41 in the first direction.

In yet another embodiment, both the chip stack structure 5 and the processor module 4 may have corresponding grooves (not shown) on the first substrate 1 , and the stack structure connecting bumps 53 and the processor connecting bumps 41 are both provided in the corresponding grooves to improve structural stability and reduce the packaging height of the semiconductor packaging structure. In addition, the chip stack structure 5 and the processor module 4 can also be partially disposed in corresponding grooves to achieve the effect that the chip stack structure 5 and the processor module 4 are both partially embedded in the first substrate 1, further improving structural stability and reducing the number of semiconductors. The package height of the package structure. In this case, the stacked structure connecting bump 53 and the processor connecting bump 41 are still horizontal in the first direction.

Regardless of the relative positional relationship, the stacked structure connecting bumps 53 and the processor connecting bumps 41 realize signal transmission through the first substrate 1 . In addition, the stacked structure connecting bump 53 and the processor connecting bump 41 can also be connected to the substrate connecting bump 11 through leads (not shown) in the first substrate 1 , so that the first semiconductor chip 51 and the processor module 4 Information can be exchanged with the third substrate 3 and the main board through the substrate connection bumps 11 .

In an exemplary embodiment of the present disclosure, the first semiconductor chip 51 is, for example, a logic chip (Logic Die, also called a basic chip), and the second semiconductor chip stack structure 52 includes a DRAM chip (also called a core chip).

The second semiconductor chip stack structure 52 is, for example, HBM (High Bandwidth Memory). HBM technology is the main representative product in the development of DRAM from traditional 2D to three-dimensional 3D, opening up the road to three-dimensional DRAM. It mainly stacks chips through Through Silicon Via (TSV) technology to increase throughput and overcome bandwidth limitations within a single package. Several DRAM dies are stacked vertically, and the dies are connected using TVS technology. From a technical perspective, HBM makes full use of space and reduces area, which is in line with the development trend of miniaturization and integration in the semiconductor industry. It also breaks through the bottlenecks of memory capacity and bandwidth and is regarded as a new generation DRAM solution.

In 3D IC product packaging, DRAM chips are generally stacked on logic chips (Logic die) in a parallel stacking (P-Stack) manner. As the integration requirements increase, the number of DRAM chip stacking layers increases, and the technical difficulties also increase. For example, the communication distance between the DRAM chips stacked on the upper layer and the logic chips (Logic die) on the bottom layer is getting longer and longer, and the communication delay between DRAM chips and logic chips on different layers will vary due to the different distances; the TSV through holes used for communication will increase proportionally, sacrificing the wafer area.

In the embodiment of the present disclosure, wireless communication between the first semiconductor chip 51 and the second semiconductor chip stack structure 52 can be configured. For example, a wireless coil (not shown) is provided in each DRAM in the second semiconductor chip stack structure 52 . (shown in the figure), correspondingly, corresponding wireless coils are provided at the above-mentioned coil corresponding positions on the first semiconductor chip 51. Wireless communication between the first semiconductor chip 51 and the second semiconductor chip stack structure 52 can effectively solve the communication difficulties caused by the increase in the number of stacked layers of the second semiconductor chip 521 and reduce the TSV (for transmission). signal) to reduce the process difficulty.

In addition, in the embodiment of the present disclosure, a plurality of second semiconductor chips 521 in the second semiconductor chip stack structure 52 are vertically stacked (V-Stacked) on the first semiconductor chip 51 in parallel. In this way, the first semiconductor chip 51 and the The two semiconductor chips 521 can communicate wirelessly, which effectively solves the communication problems caused by the increase in the number of stacked layers of the second semiconductor chips when multiple second semiconductor chips are sequentially stacked in parallel (P-Stack) on the first semiconductor chip. difficulty. That is, by setting the stacking direction of the second semiconductor chip stack structure 52 perpendicular to the surface of the first semiconductor chip 51, each second semiconductor chip 521 can have the same communication distance with the first semiconductor chip 51, thereby overcoming the problem of multi-layer stacking. resulting in communication delays.

FIG. 3 is a schematic diagram of a chip stacking structure in an embodiment of the present disclosure.

Referring to FIG. 3 , in one embodiment, the second semiconductor chip stack structure 52 may include a preset number of sub-stack structures 520 , each sub-stack structure 520 including:

A plurality of second semiconductor chips 521 are stacked sequentially along the first direction. Each second semiconductor chip 521 is provided with a plurality of through silicon vias 522. The through silicon vias 522 penetrate the second semiconductor chip 521 along the first direction, and are adjacent to each other. The positions of the through silicon vias 522 of the two second semiconductor chips 521 correspond one to one;

A plurality of second conductive bumps 20 are located between two adjacent second semiconductor chips 521 and are correspondingly connected to the through silicon vias 522;

A plurality of first conductive bumps 10 are arranged on the first side of the sub-stack structure 520 along the first direction, and are connected correspondingly to the through silicon holes 522; wherein, the plurality of sub-stack structures 520 are arranged side by side along the first direction, and one sub-stack structure 520 is arranged side by side along the first direction. 520 The through silicon via 521 on the first side in the first direction is used to connect the first conductive bump 10 of another sub-stack structure 520 .

The position of the second conductive bump 20 corresponds to the position of the first conductive bump 10, and is used to transmit the power signal and ground signal obtained by the first conductive bump 10 from the second substrate 2 to each third through the through silicon via 522. on the second semiconductor chip 521.

In the sub-stacked structure 520, each second semiconductor chip 521 can be obtained by a hybrid bonding method (for example, both are pressed and welded). In this way, the stacked chip structure can be used as a whole to improve the mechanical strength of the vertically placed stacked structure. At the same time, Reduce the stress on the chip. The number of stacks of second semiconductor chips 521 in each sub-stacked structure 520 may be multiple, and the numbers are equal. In the embodiment of the present disclosure, as shown in FIG. 3 , the number of stacks of the second semiconductor chips 521 in the sub-stack structure 520 is five.

In one embodiment, a dielectric layer 523 may also be provided between two adjacent second semiconductor chips 521 to insulate and isolate the two adjacent second semiconductor chips 521 and wrap and isolate the second conductive bump 20. The possibility of coupling between adjacent second conductive bumps 20 is reduced. The material of the dielectric layer 523 includes oxide. In a specific embodiment, the material of the dielectric layer 523 is SiO2.

In addition, in order to increase the thickness of the second semiconductor chip stack structure and thereby enhance its mechanical strength, there is no need to thin the outermost chip during the through-silicon via processing process.

Continuing to refer to FIG. 3 , in one embodiment, the chip stack structure 5 further includes an adhesive film layer 54 . The adhesive film layer 54 is located between the first semiconductor chip 51 and the second semiconductor chip stack structure 52 and is used to bond the first semiconductor chip 51 and the second semiconductor chip stack structure 52 to enhance the adhesion between them. , thereby improving the firmness of the semiconductor packaging structure. At the same time, the adhesion film layer 54 can adjust the distance between the second semiconductor chip stack structure 52 and the first semiconductor chip 51 , that is, to prevent the angle between the second substrate 2 and the first conductive bump 10 to cause additional stress, causing the second The first conductive bump 10 on the semiconductor chip stack structure 52 is damaged. The adhesive film layer 54 is realized by a die-hardening adhesive film, for example.

The second substrate 2 is connected to the second semiconductor chip stack structure 52 through the first conductive bumps 10 . The material and structure of the second substrate 2 can be the same as the first substrate 1 .

In one embodiment, the second substrate 2 functions, for example, as a power substrate for providing power voltage and grounding to the first semiconductor chip 51 and the second semiconductor chip 52 .

Referring to Figure 4, the second substrate 2 is provided with a first connection device 21, a ground wire 22 and a power wire 23. The first connection device 21 and the first conductive bump 10 are both used to connect the ground wire 22 and the power wire 23. A connection device 21 is used to supply power to the chip stack structure 5 through the ground wire 22, the power wire 23, and the first conductive bump 10.

In one embodiment, the first conductive bump 10 includes a first sub-conductive bump 101 and a second sub-conductive bump 102. The first sub-conductive bump 101 is electrically connected to the ground line 22 on the second substrate 2. The two sub-conductive bumps 10 are electrically connected to the power line 23 on the second substrate 2 .

As shown in FIG. 5 , at least one first sub-conductive bump 101 is spaced between two adjacent second sub-conductive bumps 102 , and the first sub-conductive bump 101 surrounds the second sub-conductive bump 102 . P (Power) in FIG. 3 is the second sub-conductive bump 102, and G (Ground) is the first sub-conductive bump 101. Since the first sub-conductive bump 101 is connected to the ground signal and the second sub-conductive bump 102 is connected to the power signal, the first sub-conductive bump 101 completely surrounds the second sub-conductive bump 102 to reduce different errors. Crosstalk between power signals and enhanced power shielding.

Referring to FIGS. 4 and 5 , the ground signal of the second semiconductor chip stack structure 52 is led out from the first sub-conductive bump 101 to the ground line 22 , and the power signal of the second semiconductor chip stack structure 52 is led out from the second sub-conductive bump 102 to the power line 23, the ground line 22 and the power line 23 are electrically connected to the motherboard (not shown) through the first connection device 21, whereby the motherboard passes through the first connection device 21, the ground line 22, the power line 23, the first conductive Bump 10 supplies power to second semiconductor chip stack 52 .

Continuing to refer to FIG. 4 , in one embodiment, the first connection device 21 includes a plurality of golden fingers 211 . The gold finger 211 may include a first gold finger and a second gold finger. The first gold finger is used to connect the ground wire 22 on the second substrate 2 , and the second gold finger is used to connect the power line 23 on the second substrate.

The surface of the gold finger is gold-plated, which can protect the edge of the circuit board from wear and tear. Gold fingers are made of hard gold and chemical nickel gold (ENIG). The common thickness of gold plating ranges from 3um to 50um to provide longer durability of the power supply substrate and effectively extend its service life. Long-term uninterrupted operation, air pollution, humidity and temperature changes, dust pollution, chemical corrosion, and other potential hazards and external interference will affect the reliability of the second semiconductor chip stack structure 52 (HBM module), which adopts a gold-finger thick gold-plated interface. The plugging and unplugging usage times of the second semiconductor chip stack structure 52 (HBM module) can be increased.

In the embodiment of the present disclosure, at least one first gold finger is spaced between two adjacent second gold fingers to ensure better shielding between the power supply and the ground.

In addition, a second substrate notch 212 , that is, a fool-proof opening, is provided between at least two gold fingers to ensure the correct installation direction of the second substrate 2 and prevent reverse insertion, which may burn the second semiconductor chip stack structure 52 .

The second substrate notch 212 can be disposed at a left position or a right position in the second substrate 2 to play an obvious position identification role. In the embodiment shown in FIG. 4 , the number of the second substrate notches 212 is one. In other embodiments of the present disclosure, the number of the second substrate notches 212 may also be multiple. When the number of the second substrate notches 212 can be multiple, the position arrangement between the plurality of second substrate notches 212 also needs to play an obvious role in position identification, so that each second substrate notch 212 is in the second substrate 2 The relative positions on the first side and the second side in the first direction are different. In addition, the height and width of the second substrate notch 212 can be determined according to the number and width of the golden fingers 211 , or can also be determined according to the height of the second substrate 2 , which is not specifically limited in this disclosure.

Although in the embodiment shown in FIG. 4 , for convenience of display, the largest surface of the second substrate 2 extends along the first direction, and the plurality of golden fingers 211 of the first connection device 21 are arranged in the first direction, in another aspect of the present disclosure, In one embodiment, the largest surface of the second substrate 2 may also extend along a third direction perpendicular to the first direction and the second direction (that is, perpendicular to the current view), and the plurality of golden fingers 211 of the first connection device 21 may extend along the third direction. The third direction is arranged to save the width of the semiconductor packaging structure 100 in the first direction and the volume of the entire semiconductor packaging structure 100 .

It should be noted that when the first connection device 21 includes multiple golden fingers 211 , corresponding golden finger sockets can be provided on the motherboard to complete the pluggable connection between the motherboard and the semiconductor packaging structure 100 .

Corresponding to the first connection device 21, a second connection device 31 is provided on the third substrate 3 to complete the pluggable connection between the motherboard and the semiconductor packaging structure 100. The third substrate 3 is used to provide a signal or power connection between the first substrate 1 and the motherboard, and to provide a second connection device 31 for the semiconductor packaging structure 100 . The material and structure of the third substrate 3 are the same as those of the first substrate 1 and will not be described again here.

Continuing to refer to FIG. 1 , in one embodiment of the present disclosure, the second connection device 31 may be, for example, a plurality of pins 311 distributed in a grid array, that is, a pluggable PGA (Pin Grid Array Package). array) package. Correspondingly, a pin socket opposite to the position of the pins can also be provided on the motherboard to fix the pins and achieve signal transmission.

In an exemplary embodiment of the present disclosure, the semiconductor packaging structure 100 further includes a packaging compound structure 6 located on the third substrate 3 for wrapping the first substrate 1, the second substrate 2, the processor module 4, and the chip stack. Structure 5.

Referring to FIG. 6 , in one embodiment, the packaging compound structure 6 is located on the third substrate 3 ; the packaging compound structure 6 at least wraps the first substrate 1 , the second substrate 2 , the processor module 4 and the chip stack structure 5 . Encapsulating compound structure 6 includes a silicon-containing compound. The silicon-containing compound may be spin-on glass (SOG), silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials.

By forming the packaging compound structure 6, and the material of the packaging compound structure 6 includes a silicon-containing compound, the warping problem of the second semiconductor chip stack structure 52 can be reduced, and the semiconductor packaging structure 100 can be packaged as a whole, improving the overall structure. strength.

Referring to FIG. 7 , in some embodiments of the present disclosure, the semiconductor packaging structure 100 may further include a filling layer 7 . Filling layer 7 can be set at any one or more of the following locations:

1. The filling layer 7 is located between the second semiconductor chip stack structure 52 and the second substrate 2;

2. The filling layer 7 is located between the first semiconductor chip 51 and the first substrate 1;

3. The filling layer 7 is located between the first substrate 1 and the third substrate 3;

4. The filling layer 7 is located between the second substrate 2 and the chip stack structure 5, the first substrate 1, and the third substrate 3.

For the three-dimensionally stacked second semiconductor chip stacking structure 52, since the thickness along the first direction is relatively thin, the second semiconductor chip stacking structure 52 has a high warpage. When it is erected on the first semiconductor chip 51, it will be difficult to weld the second semiconductor chip stacking structure 52 and the second substrate 2 due to the high warpage. Therefore, a filling layer 7 is provided between the second semiconductor chip stacking structure 52 and the second substrate 2, between the first substrate 1 and the first semiconductor chip 51, between the second substrate 2 and the first substrate 1, between the second substrate 2 and the third substrate 3, and between the first substrate 1 and the third substrate 3, which can effectively reduce the impact caused by the mismatch of the overall temperature expansion characteristics between the chip and the substrate or the external force, and increase the reliability of the semiconductor packaging structure.

In one embodiment, the material of the filling layer 7 includes epoxy resin. The epoxy resin can be applied to the edge of the chip by the capillary action principle to allow it to penetrate into the bottom of the chip or substrate, and then heated to be cured. Since the epoxy resin can effectively improve the mechanical strength of the solder joint, it can improve the service life of the chip.

In one embodiment, the Young's modulus of the filling layer 7 is greater than the Young's modulus of the encapsulating compound structure 6 . Young's modulus is a physical quantity that can describe the ability of a solid material to resist deformation. The greater the Young's modulus, the greater the ability to resist deformation. When the Young's modulus is too low, it will be difficult to maintain the rigidity of the packaging structure, and deformation will easily occur. Problems such as warping or breakage. Therefore, in the embodiment of the present disclosure, by forming the filling layer 7, and the Young's modulus of the filling layer 7 is greater than the Young's modulus of the packaging compound structure 6, the filling layer 7 can have sufficient strength to support the entire packaging structure, so that the packaging The structure is not prone to problems such as deformation, warping or damage.

Referring to FIG. 8 , a method 800 for preparing a semiconductor packaging structure as any one of the above may include:

Step S1, forming a first semiconductor chip, a processor module, a first substrate, a second substrate, and a third substrate;

Step S2: Form a second semiconductor chip stack structure. The second semiconductor chip stack structure includes a plurality of second semiconductor chips stacked in sequence;

Step S3, disposing the second semiconductor chip stack structure on the first semiconductor chip to form a chip stack structure;

Step S4, arrange the chip stack structure and the processor module on the first substrate;

Step S5, place the first substrate on the third substrate;

Step S6: Signal connection is made between the second substrate and the second semiconductor chip stack structure.

In step S1, the first semiconductor chip, the processor module, the first substrate, the second substrate, and the third substrate can all be in the form of any of the embodiments shown in Figures 1 to 7. Before forming the overall packaging structure, the first semiconductor chip, the processor module, the first substrate, the second substrate, and the third substrate can be prepared in advance. The embodiments of the present disclosure do not impose special restrictions on the substrate manufacturing and chip manufacturing processes.

The first substrate, the second substrate, and the third substrate may each be a printed circuit board (PCB) or a redistribution substrate. Wherein, the first substrate may include a first base (not shown) and a first upper insulating dielectric layer and a first lower insulating dielectric layer (not shown) respectively located on the upper surface and lower surface of the first base. The first substrate may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate, etc., It can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked structure, such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator), etc. The first upper insulating dielectric layer and the first lower insulating dielectric layer may be solder resist layers. For example, the material of the first upper insulating dielectric layer and the first lower insulating dielectric layer may be green paint. In the embodiment of the present disclosure, the surface corresponding to the first upper insulating dielectric layer is called the first plane of the first substrate (the upper surface in FIG. 1 ), and the surface corresponding to the first lower insulating dielectric layer is called the first substrate. The second plane (lower surface in Figure 1).

The second substrate, the third substrate and the first substrate have the same layer structure and material, which will not be described again.

In one embodiment, the first semiconductor chip is, for example, a logic chip.

The processor module has an independent package, and the package form is, for example, a cube with six rectangular sides.

In one embodiment of the present disclosure, in step S2, a plurality of first conductive bumps may also be formed on one side of the second semiconductor chip stack structure along the stacking direction, so that in step S6, the first conductive bumps are The two substrates are signally connected to the second semiconductor chip stack structure.

In an exemplary embodiment of the present disclosure, step S2 may include:

Step S21, forming multiple sub-stack structures, each sub-stack structure including second semiconductor chips sequentially stacked along the first direction and a plurality of first conductive bumps disposed on the first side of the first direction;

Step S22: Connect the plurality of sub-stack structures through a plurality of first conductive bumps, and use the first conductive bumps of the sub-stack structures located on the first side of the first direction as the second semiconductor chip stack structure and the second substrate. Connect the first conductive bump.

9A to 9E are process schematic diagrams of step S2 in an embodiment of the present disclosure. 9A to 9D correspond to step S21, and FIG. 9E corresponds to step S22.

In FIG. 9A , a plurality of through silicon vias 522 penetrating the second semiconductor chip 521 are formed along the first direction.

In FIG. 9B , a second conductive bump 20 is provided between two adjacent second semiconductor chips 521 , and the plurality of second semiconductor chips 521 are connected through hybrid bonding. The second conductive bump 20 and the through silicon via 522 Corresponding connection. The number of stacks of second semiconductor chips 521 in one sub-stacked structure 520 may be multiple. In the embodiment of the present disclosure, the number of stacks of second semiconductor chips 521 in a sub-stack structure 520 is five.

In FIG. 9C , step S21 may further include: forming a dielectric layer 523 between two adjacent second semiconductor chips 521 . By providing the dielectric layer 523, two adjacent second semiconductor chips 521 can be insulated and isolated, and the second conductive bumps 20 can be located within the dielectric layer 523, thereby reducing the possibility of coupling between adjacent second conductive bumps 20. . The material of the dielectric layer 523 includes oxide. In a specific embodiment, the material of the dielectric layer 523 includes SiO2.

In FIG. 9D , a plurality of first conductive bumps 10 are formed on the surface of a second semiconductor chip 521 located at the edge, and the first conductive bumps 10 are correspondingly connected to the through silicon holes 522 . "Edge" may refer to the upper surface in Figure 9D or the lower surface.

In addition, in order to increase the thickness of the sub-stack structure 520 and thereby enhance its mechanical strength, there is no need to thin the outermost chip during the through-silicon via processing process.

In FIG. 9E , a plurality of sub-stack structures 520 can be connected through a plurality of first conductive bumps 10 , and the first conductive bumps 10 of the sub-stack structures 520 located on the first side in the first direction serve as the second semiconductor chip. The stacked structure 52 is connected to the first conductive bumps of the second substrate 2 .

In another embodiment of the present disclosure, a stack body including a plurality of sub-stack structures 520 may also be directly manufactured, and the stack body may be cut to form a plurality of sub-stack structures 520 .

In one embodiment, the second semiconductor chip 521 includes a DRAM chip, and the second semiconductor chip stack structure 52 includes an HBM.

Referring to the chip stack structure 5 shown in FIG. 3, in one embodiment, in step S3, the stack structure connecting bumps 53 can be formed on the first plane of the first semiconductor chip 51, and then the second semiconductor chip stack structure 52 is formed along the first plane. The surface perpendicular to the stacking direction is connected to the surface of the first semiconductor chip 51 .

For example, an adhesive film layer 54 can be formed on the first semiconductor chip 51, and the second semiconductor chip stacking structure 52 is arranged on the first semiconductor chip 51 through the adhesive film layer 54. The adhesive film layer 54 can bond the first semiconductor chip 51 and the second semiconductor chip stacking structure 52, enhance the adhesion between them, and thus improve the firmness of the semiconductor packaging structure. At the same time, the adhesive film can adjust the distance between the second semiconductor chip stacking structure 52 and the first semiconductor chip 51, that is, prevent the second substrate 2 from being combined with the first conductive bump 10 at an angle, causing additional stress, so that the first conductive bump 10 on the second semiconductor chip stacking structure 52 is damaged. The adhesive film layer 54 is realized, for example, by a die-bonding adhesive film.

If the stacking direction is perpendicular to the plane of the first semiconductor chip 51 , the second semiconductor chip stack structure 52 is rotated 90 degrees and then connected to the first semiconductor chip 51 . If the stacking direction is a direction parallel to the plane of the first semiconductor chip 51, there is no need to rotate the second semiconductor chip stack structure 52.

In one embodiment, the first semiconductor chip 51 and the second semiconductor chip stack structure 52 can communicate wirelessly. For example, a wireless coil (not shown) is provided in each DRAM in the second semiconductor chip stack structure 52. ), correspondingly, corresponding wireless coils are provided at the above-mentioned coil corresponding positions on the first semiconductor chip 51 .

Wireless communication between the first semiconductor chip 51 and the second semiconductor chip stacking structure 52 can effectively solve the communication difficulties caused by the increase in the number of stacking layers of the second semiconductor chip. By connecting the second semiconductor chip stacking structure 52 along the surface perpendicular to the stacking direction with the surface of the first semiconductor chip 51, each second semiconductor chip 521 can have an equal communication distance with the first semiconductor chip 51, further reducing the communication delay caused by the increase in the number of stacking layers.

In step S4, the processor module, the chip stack structure and the first substrate are connected.

Referring to Figure 1, first, processor connection bumps 41 can be formed on the processor module 4 (this step can also be done in step S1), and stacked structure connection bumps 53 can be formed on the first semiconductor chip 51 (this step can also be done in step S1). (done in step S3), then the processor module 4 and the chip stack structure 5 can be disposed on the first substrate 1 through the processor connection bumps 41 and the stack structure connection bumps 53 respectively. The connection method is, for example, welding. Then, the second plane of the first substrate 1 and the third substrate 3 can be connected by welding.

In one embodiment, the first chip 51 in the chip stack structure 5 may be disposed on the first substrate 1 , as shown in FIG. 1 . This process is simple, and there is a gap between the first semiconductor chip 51 and the first substrate 1 , which can increase the heat dissipation effect of the first semiconductor chip 51 . At this time, the stacked structure connecting bump 53 and the processor connecting bump 41 are horizontal in the first direction.

In another embodiment, the stacked structure connecting bumps 53 may be disposed in grooves (not shown) on the first substrate 1 to improve structural stability and reduce the packaging height of the semiconductor packaging structure. In addition, the first chip 51 in the chip stack structure 5 can also be partially disposed in the groove to achieve the effect of the chip stack structure 5 being partially embedded in the first substrate 1 , further improving the structural stability and reducing the packaging of the semiconductor packaging structure. high. At this time, the stacked structure connecting bump 53 is lower than the processor connecting bump 41 in the first direction.

In yet another embodiment, both the chip stack structure 5 and the processor module 4 have corresponding grooves (not shown) on the first substrate 1. At this time, the stack structure connecting bumps 53 and the processor connecting bumps can be connected. 41 are arranged in corresponding grooves to improve structural stability and reduce the packaging height of the semiconductor packaging structure. In addition, the chip stack structure 5 and the processor module 4 can also be partially disposed in corresponding grooves to achieve the effect that the chip stack structure 5 and the processor module 4 are both partially embedded in the first substrate 1, further improving structural stability and reducing Package height of semiconductor packaging structures. In this case, the stacked structure connecting bump 53 and the processor connecting bump 41 are still horizontal in the first direction.

Continuing to refer to FIG. 1 , in step S5 , the substrate connection bumps 11 can be first formed on the second plane (lower surface) of the first substrate 1 (this step can also be done in step S1 ), and on the lower surface of the third substrate 3 Set the second connection structure 31 (this step can also be done in step S1), and then electrically connect the first substrate 1 to the third substrate 3 through the substrate connection bumps 11.

The substrate connection bumps 11 include conductive material. In the embodiment of the present disclosure, the substrate connection bumps 11 are solder balls. It can be understood that the shape of the processor connection bumps provided in the embodiment of the present disclosure is only a lower and feasible shape in the embodiment of the present disclosure. The specific implementation does not constitute a limitation on the present disclosure, and the processor connection bumps can also have other shapes and structures. The number, spacing, and location of the processor attachment bumps are not limited to any specific arrangement and may be variously modified.

Finally, since the first connection structure 21 has been set on the second substrate 2 in step S1, in step S6, the second substrate can be adjusted according to the distance between the first conductive bump 10 and the lower surface of the third substrate 3. With a height of 2, the second substrate 2 is connected to the chip stack structure 5 through the first conductive bump 10, so that the first connection structure 21 and the second connection structure 31 on the second substrate 2 are horizontal in the first direction, forming The semiconductor package structure 100 shown in FIG. 1 .

In one embodiment, the first conductive bump 10 includes a first sub-conductive bump 101 and a second sub-conductive bump 102. The first sub-conductive bump 101 is electrically connected to the ground line 22 on the second substrate 2. The two sub-conductive bumps 10 are electrically connected to the power line 23 on the second substrate 2 . For this part of the embodiment, please refer to Figure 5 and will not be described again here.

In some embodiments, the packaging compound structure 6 may also be formed after step S6 , or the filling layer 7 may be formed first and then the packaging compound structure 6 may be formed after step S6 to package the semiconductor packaging structure 100 as a whole.

Referring to FIG. 6 , the packaging compound structure 6 is located on the third substrate 3 and is used to wrap the first substrate 1 , the second substrate 2 , the processor module 4 , and the chip stack structure 5 . Encapsulating compound structure 6 includes a silicon-containing compound. The silicon-containing compound may be spin-on glass (SOG), silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials. By forming the packaging compound structure 6, and the material of the packaging compound structure 6 includes a silicon-containing compound, the warping problem of the second semiconductor chip stack structure 52 can be reduced, and the semiconductor packaging structure 100 can be packaged as a whole, improving the overall structure. strength.

Referring to FIG. 7 , the filling layer 7 may be provided, for example, between the second semiconductor chip stack structure 52 and the second substrate 2 , between the first substrate 1 and the first semiconductor chip 51 , or between the second substrate 2 and the first substrate 1 , a filling layer 7 is provided between the second substrate 2 and the third substrate 3, and between the first substrate 1 and the third substrate 3, which can effectively reduce the thermal expansion caused by the mismatch of the overall temperature expansion characteristics between the chip and the substrate or external force. impact, increasing the reliability of the semiconductor packaging structure. The material of the filling layer 7 includes epoxy resin. The principle of capillary action can be used to apply epoxy resin on the edge of the chip, allowing it to penetrate into the bottom of the chip or substrate, and then heat and cure it (cured). Because epoxy resin can effectively improve the mechanical strength of the solder joint, it can improve the chip's performance. service life.

In summary, the embodiment of the present disclosure, by disposing a semiconductor stacking structure and a processor module on a first substrate, and respectively disposing a first connecting device and a second connecting device for active connection on a second substrate connected to the semiconductor stacking structure and a third substrate connected to the first substrate, can achieve active connection between a combination of the semiconductor stacking structure and the processor module and a mainboard of an electronic device, thereby realizing an integrated data processing system that can be removed and replaced as a whole.

Other embodiments of the disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure that follow the general principles of the disclosure and include common knowledge or customary technical means in the technical field that are not disclosed in the disclosure. . It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Industrial applicability

Claims

A semiconductor packaging structure including:

first substrate;

A processor module, disposed on the first plane of the first substrate and connected to the first substrate;

A chip stack structure is provided on the first plane of the first substrate and connected to the first substrate, wherein the chip stack structure includes:

A first semiconductor chip connected to the first substrate;

A second semiconductor chip stack structure, located on the first semiconductor chip, includes a plurality of second semiconductor chips sequentially stacked along a first direction, the first direction being parallel to the first plane of the first substrate;

The second substrate is arranged along the second direction and is electrically connected to the second semiconductor chip stack structure. A first connection device is arranged at the first end along the second direction. The second direction is perpendicular to the first the first plane of the substrate;

The third substrate is connected to the second plane of the first substrate, and a second connection device is provided at the first end along the second direction. The second plane of the first substrate is connected to the first plane of the first substrate. Planes are parallel and opposite;

Wherein, the first connection device and the second connection device are both used for movable connection.
The semiconductor packaging structure of claim 1, wherein the first connection device includes a plurality of gold fingers, and the second connection device includes a plurality of pins distributed in a grid array.
The semiconductor packaging structure of claim 1 or 2, wherein the first connection device and the second connection device are horizontal in the first direction.
The semiconductor packaging structure of claim 2, wherein the gold finger includes a first gold finger and a second gold finger, the first gold finger is used to connect a ground line on the second substrate, and the third gold finger The two gold fingers are used to connect the power lines on the second substrate.
The semiconductor packaging structure of claim 4, wherein at least one first gold finger is spaced between two adjacent second gold fingers.
The semiconductor packaging structure of claim 4, wherein the second substrate is electrically connected to the second semiconductor chip stack structure through a first conductive bump, the first conductive bump including a first sub-conductive bump. and a second sub-conductive bump, the first sub-conductive bump is electrically connected to the ground line on the second substrate, and the second sub-conductive bump is electrically connected to the power line on the second substrate.
The semiconductor packaging structure of claim 6, wherein at least one first sub-conductive bump is spaced between two adjacent second sub-conductive bumps, and the first sub-conductive bump surrounds the second sub-conductive bump. sub conductive bumps.
The semiconductor packaging structure of claim 2, wherein a second substrate gap is provided between at least two of the gold fingers.
The semiconductor packaging structure of claim 1, wherein the second semiconductor chip stack structure includes a preset number of sub-stack structures, the sub-stack structures are arranged around the processor module, and the second substrate is in the sub-stack structure. The structures are arranged separately with respect to one side of the processor module.
The semiconductor package structure according to claim 9, wherein the sub-stack structure comprises:

A plurality of second semiconductor chips are stacked sequentially along the first direction. Each second semiconductor chip is provided with a plurality of through silicon vias, and the through silicon vias penetrate the second semiconductor chip along the first direction. Semiconductor chips, the positions of through silicon vias of two adjacent second semiconductor chips correspond one to one;

A plurality of second conductive bumps are located between two adjacent second semiconductor chips and are correspondingly connected to the through silicon vias;

A plurality of first conductive bumps are provided on the first side of the sub-stack structure along the first direction, and are correspondingly connected to the through silicon vias;

Wherein, a plurality of the sub-stack structures are arranged side by side along the first direction, and the through silicon via of one of the sub-stack structures on the first side of the first direction is used to connect the through-silicon via of the other sub-stack structure. the first conductive bump.
The semiconductor packaging structure of claim 1, wherein the first semiconductor chip realizes signal connection with the first substrate through a stacked structure connection bump, and the first substrate connects with the third substrate through a substrate connection bump. The substrate implements signal connections.
The semiconductor package structure of claim 1, wherein the first semiconductor chip includes a logic chip, and the second semiconductor chip stack structure includes a DRAM chip.
The semiconductor packaging structure of claim 1, wherein the first semiconductor chip and the second semiconductor chip stack structure communicate through wireless communication.
The semiconductor packaging structure of claim 1, further comprising:

A packaging compound structure is located on the third substrate and used to wrap the first substrate, the second substrate, the processor module, and the chip stack structure.
A method for preparing a semiconductor packaging structure, used to prepare the semiconductor packaging structure according to any one of claims 1-14, including:

Forming a first semiconductor chip, a processor module, a first substrate, a second substrate, and a third substrate;

Forming a second semiconductor chip stack structure, the second semiconductor chip stack structure includes a plurality of second semiconductor chips stacked in sequence;

disposing the second semiconductor chip stack structure on the first semiconductor chip to form a chip stack structure;

disposing the chip stack structure and the processor module on the first substrate;

disposing the first substrate on the third substrate;

The second substrate is signally connected to the second semiconductor chip stack structure.
The preparation method of claim 15, wherein forming the second semiconductor chip stack structure includes:

Forming a plurality of sub-stack structures, each of the sub-stack structures including second semiconductor chips sequentially stacked along a first direction and a plurality of first conductive bumps disposed on a first side in the first direction;

The plurality of sub-stack structures are connected through the plurality of first conductive bumps, and the first conductive bumps of the sub-stack structures located on the first side of the first direction are used as the second semiconductor The chip stack structure is connected to a first conductive bump on the second substrate.
The preparation method of claim 16, wherein forming a plurality of sub-stack structures includes:

forming a plurality of through silicon vias penetrating the second semiconductor chip along the first direction;

A second conductive bump is provided between two adjacent second semiconductor chips, and the second conductive bump is correspondingly connected to the through silicon via;

A plurality of second semiconductor chips are connected through hybrid bonding, and the plurality of first conductive bumps are formed on the surface of one of the second semiconductor chips located at the edge. The first conductive bumps are connected to the Through silicon via corresponding connection.