WO2024055358A1 - 数据处理方法、电子设备及计算机可读存储装置 - Google Patents

数据处理方法、电子设备及计算机可读存储装置 Download PDF

Info

Publication number
WO2024055358A1
WO2024055358A1 PCT/CN2022/121803 CN2022121803W WO2024055358A1 WO 2024055358 A1 WO2024055358 A1 WO 2024055358A1 CN 2022121803 W CN2022121803 W CN 2022121803W WO 2024055358 A1 WO2024055358 A1 WO 2024055358A1
Authority
WO
WIPO (PCT)
Prior art keywords
target
target layer
storage
data
layer
Prior art date
Application number
PCT/CN2022/121803
Other languages
English (en)
French (fr)
Inventor
梁小庆
邓恩华
Original Assignee
深圳市江波龙电子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市江波龙电子股份有限公司 filed Critical 深圳市江波龙电子股份有限公司
Publication of WO2024055358A1 publication Critical patent/WO2024055358A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Definitions

  • the present application relates to the field of storage, and in particular to a data processing method, electronic equipment and computer-readable storage device.
  • a storage medium In the storage device, a storage medium is required to store the saved data.
  • Commonly used storage media include RAM (random access memory), ROM (Read-Only Memory), FLASH, etc.
  • the process of storing erased data is a process of charging and discharging. When writing data, the storage unit is charged to complete the data writing. As the storage time increases, the electrons stored in the storage unit will leak, causing the voltage stored in the storage unit to decrease or even disappear completely, causing the stored data to be incorrect or completely lost.
  • the main purpose of this application is to provide a data processing method, electronic equipment and a computer-readable storage device, which can solve the technical problem of data errors in the storage device caused by power outage due to long storage time.
  • the first technical solution adopted by this application is to provide a data processing method.
  • the method includes: determining the target layer corresponding to the target storage unit; operating the storage unit in the non-target layer to increase the storage voltage of the target storage unit; wherein the operation includes at least one of a read operation, a write operation, and an erase operation. .
  • the second technical solution adopted by this application is to provide an electronic device.
  • the electronic device includes a memory and a processor.
  • the memory is used to store program data.
  • the program data can be executed by the processor to implement the method described in the first technical solution.
  • the third technical solution adopted by this application is to provide a computer-readable storage device.
  • the computer-readable storage device stores program data and can be executed by the processor to implement the method described in the first technical solution.
  • this application can further determine the non-target layer, and perform at least one of a read operation, a write operation, and an erase operation on the storage unit in the non-target layer to affect
  • the target storage unit in the target layer increases the storage voltage of the target storage unit, prolongs the retention time of the storage voltage in the target storage unit, and ensures the accuracy of the data.
  • Figure 1 is a schematic structural diagram of a FLASH memory unit
  • FIG2 is a schematic diagram of the structure of a FLASH storage unit during reading
  • Figure 3 is a schematic diagram of the structure of a FLASH memory unit during writing
  • Figure 4 is a schematic flow chart of the first embodiment of the data processing method of the present application.
  • Figure 5 is a schematic flow chart of the second embodiment of the data processing method of the present application.
  • Figure 6 is a schematic flow chart of the third embodiment of the data processing method of the present application.
  • Figure 7 is a schematic flow chart of the fourth embodiment of the data processing method of the present application.
  • Figure 8 is a schematic flow chart of the fifth embodiment of the data processing method of the present application.
  • Figure 9 is a schematic structural diagram of an embodiment of the electronic device of the present application.
  • Figure 10 is a schematic structural diagram of an embodiment of a computer-readable storage device of the present application.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • Figure 1 is a schematic structural diagram of a FLASH memory unit.
  • a MOS tube consists of two gates.
  • the first door is surrounded by oxide and the second door is connected to the outside.
  • the first gate located in the middle is equivalent to forming an electronic isolation zone, which ensures that the electrons stored in the first gate, that is, the data can be retained for a long time.
  • the process of charging and discharging this isolated part is called writing and erasing.
  • FLASH flash memory includes multiple flash memory blocks, and each flash memory block includes multiple flash memory pages. Each flash memory page corresponds to a word line. When operating on a certain flash memory page, it will affect the storage cells in other flash memory pages.
  • Figure 2 is a schematic structural diagram of a memory unit during reading in FLASH.
  • a positive voltage will be applied to the control pole of the unread, unselected flash memory page, that is, the word line, to ensure that the MOS in the unselected flash memory page
  • the tube is conductive.
  • the flash memory page corresponding to the word line to which a positive voltage is applied is in a weakly programmed state, which will affect the state of the electrons in it.
  • applying a positive voltage to the control electrode of a MOS tube will cause electrons to be sucked into the floating gate, thereby changing the stored voltage.
  • Figure 3 is a schematic structural diagram of a memory unit during writing in FLASH.
  • a positive voltage is applied to the control electrode of the selected flash memory page, that is, the flash memory page to which data is to be written, that is, the word line.
  • the storage unit in the rectangular dotted box in the figure is the storage unit currently being written.
  • the bit line corresponding to the memory cell will be connected to ground, while the bit lines of other memory cells that are not currently written to will be connected to a positive voltage. This will cause other memory cells on the same bit line or word line as the memory cell to be affected.
  • the floating gates of other memory cells will absorb electrons and change their own stored voltage, such as the storage in the circular dotted line in the figure. unit.
  • the charge stored in the floating gate of the flash memory cell may leak after a long period of time. After the leakage, the voltage stored in the flash memory cell will decrease, causing the data stored in it to change.
  • the above operations will affect the memory cells on the unoperated word lines or bit lines, causing their floating gates to absorb new electrons, thereby increasing the stored voltage value. If it is determined that the data in some flash memory units is incorrect due to power outage, the above operations can be performed on the flash memory pages next to the flash memory pages where these flash memory units are located to increase the storage voltage of these flash memory units and ensure the accuracy of the data.
  • Figure 4 is a schematic flow chart of the first embodiment of the data processing method of the present application. It includes the following steps:
  • Each storage block contains several layers of pages, and each layer corresponds to several storage units.
  • the target storage unit is a unit that stores valid data.
  • the target layer is the layer where the target storage unit is located.
  • Valid data is data that users need to maintain data reliability. These data are needed by users for a long time or temporarily, and the accuracy of the data must be ensured when reading.
  • S12 Operate the memory cells in the non-target layer to increase the storage voltage of the target memory cell.
  • the operation includes at least one of a read operation, a write operation, and an erase operation.
  • other layers other than the currently operated non-target layer can be affected to increase the number of electrons stored in the memory cells of other layers, thereby increasing the storage voltage of the memory cells. Therefore, the storage voltage of the target memory cell in the target layer can be increased to ensure data accuracy.
  • the non-target layer is a layer adjacent to the target layer. The above operations are performed on the non-target layer to increase the number of electrons stored in the target memory cells in the target layer, thereby increasing the storage voltage of the target memory cells in the target layer.
  • the non-target layer is a layer that is not adjacent to the target layer.
  • the above operations are performed on a non-target layer to increase the storage voltage of the memory cells in the target layer, it may take more operations to increase the target storage voltage in its target layer than the non-target layer adjacent to the target layer.
  • the target layer may be a single layer, multiple layers, or even multiple non-adjacent layers.
  • the target layer may be the first layer, the first, second, and third layers, or the first and third layers.
  • the target storage units may be all storage units in the target layer, or may be part of the storage units in the target layer.
  • the target storage unit by determining the target storage unit and the target layer, it is further possible to determine the non-target layer, and perform at least one of a read operation, a write operation, and an erase operation on the storage unit in the non-target layer to affect the target layer.
  • the target storage unit increases the storage voltage of the target storage unit, prolongs the retention time of the storage voltage in the target storage unit, and ensures the accuracy of the data.
  • FIG. 5 is a schematic flow chart of a second embodiment of the data processing method of the present application. This method is a further expansion of step S12. It includes the following steps:
  • S21 Determine whether there is a non-target layer in the target storage block corresponding to the target layer.
  • the target storage block corresponding to the target layer is determined, and it is further necessary to determine whether all the layers in the target storage block are target layers. If all are target layers, the storage voltage of the target memory cells in the target layer cannot be affected by operating on non-target layers. If it is determined that there is a non-target layer in the target storage block, step S22 is executed. If there is no non-target layer in the target storage block, step S23 is executed.
  • S22 Execute the step of operating the storage unit in the non-target layer in the target storage block.
  • the above steps can be performed to operate the non-target layer to increase the storage voltage of the memory cells in the target layer.
  • S23 Transfer the data in some storage units in the target storage block to other storage blocks to obtain the non-target layer in the target storage block, and perform the steps of operating the storage units in the non-target layer in the target storage block.
  • part of the data stored in the target storage block can be read and written to other free storage blocks or storage blocks containing invalid data. In this way, this part of the data that has been written to other storage blocks is regarded as valid data in other storage blocks, and in the target storage block, this part of the data is regarded as invalid data. This part of the data can be retained or erased after being copied and written to other memory blocks.
  • the storage layer occupied by these data that does not store valid data can be regarded as a non-target layer. After obtaining the non-target layer, the above steps can be performed to increase the storage voltage of the target memory cell.
  • part of the valid data is transferred to other memory blocks to create a non-target layer for the memory blocks, thereby increasing the storage voltage of the target memory unit when the valid data is erroneous. Maintain data accuracy for valid data.
  • the die corresponding to the target layer is determined, and whether the die contains a non-target layer.
  • the non-target layer is operated to increase the storage voltage of the target memory cell in the target layer.
  • FIG. 6 is a schematic flow chart of a third embodiment of the data processing method of the present application. This method is a further expansion of step S12. It includes the following steps:
  • a timer can be preset for the storage device or the storage blocks therein. This timer is set with a preset time. The preset time is the time value preset by the timer. When the preset time is reached, step S32 is executed. After execution, the timer is cleared and the timer is restarted. If the preset time is not reached, step S33 is executed.
  • the storage unit When the preset time is reached, the storage unit may have lost power.
  • the storage voltage of the target storage unit may be increased through the above operations.
  • Figure 7 is a schematic flow chart of the fourth embodiment of the data processing method of the present application. This method is a further expansion of step S12. It includes the following steps:
  • Error correction programs or algorithms such as ECC
  • ECC Error correction programs or algorithms
  • the error correction program has an upper limit on the number of error correction bits. When the number of erroneous data bits exceeds this upper limit, the error correction program cannot correct the error.
  • the ECC verification capability is 1bit ECC/512Byte. When up to 1bit of erroneous data appears in the 512Byte data, it can be corrected. But when 2-bit or more erroneous data appears in the 512Byte data, it cannot be corrected.
  • S42 Determine whether the number of data errors in the read data is greater than the first preset quantity threshold.
  • the first preset quantity threshold is the upper limit of error correction bits of the set error correction program or algorithm. If it is greater, execute step S43. If it is less than, execute step S44.
  • the error correction program cannot perform error correction.
  • the above steps need to be performed to operate the storage units in the non-target layer to increase the storage voltage of the target storage unit, thereby reducing the number of data error bits and making it reach the correction level of the error correction program or algorithm. Within the error capability.
  • the first preset quantity threshold is not exceeded, which proves that the error correction program or algorithm can still perform error correction processing, and there is no need to perform the above-mentioned operations on non-target layers to save control resources.
  • Figure 8 is a schematic flow chart of the fourth embodiment of the data processing method of the present application. This method is a further extension of the fourth embodiment. It includes the following steps:
  • the storage unit in the non-target layer in the target storage block is operated. After the operation, the target storage unit is continued to be read to obtain the read data. , determine the number of bits of its erroneous data.
  • S52 Determine whether the number of data errors in the read data is greater than the first preset quantity threshold.
  • the first preset quantity threshold is the upper limit of error correction bits of the set error correction program or algorithm. If it is less than, execute step S53. If it is greater, execute step S54.
  • the first preset quantity threshold is not exceeded, which proves that the error correction program or algorithm can still perform error correction processing, and there is no need to perform the above-mentioned operations on non-target layers to save control resources.
  • S54 Operate the storage units in the non-target layer in the target storage block.
  • the above steps need to be performed to operate the storage units in the non-target layer to increase the storage voltage of the target storage unit, thereby reducing the number of data error bits and making it reach the limit of the error correction program or algorithm.
  • a second preset quantity threshold for the number of operations, or set a preset time threshold for the time to perform the operation.
  • the second preset quantity threshold is used as the upper limit of the number of times, and it is determined based on the second preset quantity threshold whether to continue to operate the storage units in the non-target layer in the target storage block.
  • the preset time threshold is an upper limit of time, and it is determined based on the preset time threshold whether to continue operating the storage units in the non-target layer in the target storage block.
  • the step of determining whether to continue operating the memory units in the non-target layer in the target memory block based on the second preset quantity threshold or the preset time threshold can be implemented according to the following steps.
  • S55 Determine whether the number of operations is greater than the second preset quantity threshold, or whether the time for operations is greater than the preset time threshold.
  • the number of times is calculated starting from the first operation on the storage unit in the non-target layer, and it is determined whether it is greater than the second preset number threshold.
  • time timing is started from the first operation on the storage unit in the non-target layer to determine whether it reaches the preset time threshold. If yes, execute step S56. If not, execute step S57.
  • the storage voltage of the target memory cell in the target layer still has not increased to the original level, and the data read out is still wrong.
  • the repair of the data in the target storage unit is given up, and the storage units in the non-target layer in the target storage block are no longer operated.
  • the storage units in the non-target layer can continue to be operated until the number of error bits in the read data is less than the first preset quantity threshold or the number of operations reaches the preset The second quantity threshold or the time for performing the operation exceeds the preset time threshold.
  • Figure 9 is a schematic structural diagram of an embodiment of the electronic device of the present application.
  • the electronic device includes a processor 110 and a memory 120 .
  • the processor 110 controls the operation of the electronic device.
  • the processor 110 may also be called a CPU (Central Processing Unit).
  • the processor 110 may be an integrated circuit chip having signal sequence processing capabilities.
  • the processor 110 may also be a general purpose processor, a digital signal sequence processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or discrete hardware components.
  • DSP digital signal sequence processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
  • Memory 120 stores instructions and data required for processor 110 to operate.
  • the processor 110 is configured to execute instructions to implement the methods provided by any embodiment and possible combinations of the aforementioned data processing methods in this application.
  • FIG. 10 is a schematic structural diagram of an embodiment of a computer-readable storage device according to the present application.
  • One embodiment of the readable storage device of the present application includes a memory 210.
  • the memory 210 stores program data.
  • the program data is executed, the method provided by any embodiment and possible combinations of the data processing method of the present application is implemented.
  • the memory 210 may include a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, a Random Access Memory), a magnetic disk or an optical disk, or other media that can store program instructions, or it may be A server that stores the program instructions. The server can send the stored program instructions to other devices for execution, or it can also run the stored program instructions itself.
  • the present application can further determine the non-target layer, and perform at least one of a read operation, a write operation, and an erase operation on the storage unit in the non-target layer to affect the target layer.
  • Target the target storage unit increase the storage voltage of the target storage unit, extend the retention time of the storage voltage in the target storage unit, and ensure the accuracy of the data.
  • the disclosed methods and devices can be implemented in other ways.
  • the device implementation described above is only illustrative.
  • the division of modules or units is only a logical function division.
  • there may be other division methods for example, multiple units or components may be The combination can either be integrated into another system, or some features can be ignored, or not implemented.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above integrated units can be implemented in the form of hardware or software functional units.
  • the integrated units in the above other embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program code.

Abstract

一种数据处理方法、电子设备及计算机可读存储装置。所述方法包括：确定目标存储单元对应的目标层；对非目标层中的存储单元进行操作，以提高目标存储单元的存储电压；其中，操作包括读操作、写操作、擦除操作中至少一种。通过上述方式，延长数据保存时间，保证数据准确性。

Description

数据处理方法、电子设备及计算机可读存储装置
本申请要求申请号为2022111319918的中国专利申请的优先权，其内容通过引用结合在本申请中。
【技术领域】
本申请涉及存储领域，特别是涉及一种数据处理方法、电子设备及计算机可读存储装置。
【背景技术】
在存储装置中，需要使用存储介质来存储保存数据。常用的存储介质有RAM(random access memory，随机存储器)、ROM(Read-Only Memory，只读存储器)以及FLASH等。在以FLASH作为存储介质的产品中，存储擦除数据的过程是充放电的过程。在写入数据时，对存储单元进行充电以完成数据写入。而随着存储时间的增加，存储单元中存储的电子会发生泄露，造成存储单元存储的电压降低，甚至完全消失，使得存储的数据发生错误或完全丢失。
【发明内容】
本申请主要目的是提供一种数据处理方法、电子设备及计算机可读存储装置，能够解决存储装置中因存储时间过长发生掉电导致数据错误的技术问题。
为解决上述技术问题，本申请采用的第一个技术方案是：提供一种数据处理方法。该方法包括：确定目标存储单元对应的目标层；对非目标层中的存储单元进行操作，以提高目标存储单元的存储电压；其中，操作包括读操作、写操作、擦除操作中至少一种。
为解决上述技术问题，本申请采用的第二个技术方案是：提供一种电子设备。该电子设备包括存储器和处理器，存储器用于存储程序数据，程序数据能够被处理器执行，以实现如第一个技术方案中所述的方法。
为解决上述技术问题，本申请采用的第三个技术方案是：提供一种 计算机可读存储装置。该计算机可读存储装置存储有程序数据，能够被处理器执行，以实现如第一个技术方案中所述的方法。
本申请的有益效果是：本申请通过确定目标存储单元、目标层，进一步能够确定非目标层，对非目标层中的存储单元进行读操作、写操作、擦除操作中的至少一种以影响目标层中目标存储单元，提高目标存储单元的存储电压，延长了目标存储单元中存储电压的保持时间，保证了数据的准确性。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是FLASH一存储单元结构示意图；
图2是读取时FLASH一存储单元结构示意图；
图3是写入时FLASH一存储单元结构示意图；
图4是本申请数据处理方法第一实施例的流程示意图；
图5是本申请数据处理方法第二实施例的流程示意图；
图6是本申请数据处理方法第三实施例的流程示意图；
图7是本申请数据处理方法第四实施例的流程示意图；
图8是本申请数据处理方法第五实施例的流程示意图；
图9是本申请电子设备一实施例的结构示意图；
图10是本申请计算机可读存储装置一实施例的结构示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本 申请保护的范围。
本申请中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
在描述本申请的技术方案之前，先对一些概念进行简单介绍。
参照图1，图1为FLASH一存储单元结构示意图。在图中，一个MOS管由两个门组成。第一个门由氧化物包围，第二个门被连接到外面。而位于中间而定第一个门就相当于构成了一个电子隔离带，这样就保证了存储在第一个门中的电子，即数据能够保留很长时间。对这个隔离起来的部分进行充电和放电的过程就称为写入和擦除。
在FLASH闪存中，包括多个闪存块，而每个闪存块包括多个闪存页。每一闪存页对应一条字线。当对某一闪存页进行操作时，会对其他闪存页中的存储单元产生影响。
参照图2，图2是FLASH中读取时存储单元的结构示意图。在一闪存块中选取一闪存页进行数据读取时，会对不读取、未选中的闪存页其控制极，也就是字线上会施加一个正电压，以保证未选中闪存页中的MOS管是导通的。被施加正电压的字线对应的闪存页就处于一种弱编程的状态，这样会影响到其中电子的状态。而频繁的在一个MOS管的控制极施加正电压，会导致电子被吸进浮栅极，从而改变存储的电压。
参照图3，图3是FLASH中写入时存储单元的结构示意图。在闪存块中选取一闪存页进行数据写入时，选中的闪存页，即要写入数据的闪 存页其控制极，也就是字线会施加一个正电压。继续对闪存页中的存储单元进行写入。图中矩形虚线框中的存储单元为当前进行写入的存储单元。当要对其进行写入时，会将该存储单元对应的位线接地，而其他当前不写入的存储单元其位线会接一正电压。这样就会导致与该存储单元处于同一位线或字线的其他存储单元会受到影响，其他存储单元的浮栅极会吸收电子，改变其自身存储的电压，例如图中圆形虚线中的存储单元。
进行擦除时，其选中闪存页的操作与上述操作类似，在此不再赘述。
闪存单元中浮栅极存储的电荷在经过长期时间后，其可能会发生电荷泄露，泄露后闪存单元存储的电压会降低，使得其存储的数据发生变化。而通过上述操作会对未进行操作的字线或位线上的存储单元产生影响，使得其浮栅极吸收新的电子，从而提高存储的电压值。若判断到某些闪存单元中的数据因掉电出错了，可以对这些闪存单元所处闪存页旁边的闪存页进行上述操作，以提高这些闪存单元的存储电压，保证数据的准确性。
参照图4，图4为本申请数据处理方法第一实施例的流程示意图。其包括以下步骤：
S11：确定目标存储单元对应的目标层。
以flash为存储介质的装置为例，在该存储装置中，存在若干存储块block，每一存储块中包含有若干层page，每一层对应若干个存储单元。目标存储单元为实现存储有有效数据的单元。目标层为目标存储单元所处的层。有效数据为用户需要保持数据可靠性的数据。这些数据为用户长期需要或暂时需要，在读取时要保证其数据的准确性。
S12：对非目标层中的存储单元进行操作，以提高目标存储单元的存储电压。
确定了目标存储单元所处的目标层后，对除该目标层的其他层，即非目标层进行操作。操作包括读操作，写操作、擦除操作中至少一种。通过上述操作即能够对当前操作的非目标层以外的其他层产生影响以提高其他层的存储单元存储的电子数量，从而提高存储单元的存储电 压。因此能够提高目标层中目标存储单元的存储电压，达到保证数据准确性的目的。
在一实施例中，非目标层为与目标层相邻的层。对非目标层进行上述操作以提高目标层中的目标存储单元存储的电子数量，从而提高目标层中目标存储单元的存储电压。
在一实施例中，非目标层为与目标层不相邻的层。对非目标层进行上述操作以提高目标层中的存储单元的存储电压时，其相比于目标层相邻的非目标层可能需要花费更多的操作次数来提高其目标层中目标存储电压。
本实施例中，目标层可以是单独的一层，也可以是多层，甚至是不相邻的多层。例如，目标层可以是第一层，可以是第一、第二、第三层，也可以是第一以及第三层。目标存储单元可以是目标层中所有的存储单元，也可以是目标层中部分的存储单元。
在本实施例中，通过确定目标存储单元、目标层，进一步能够确定非目标层，对非目标层中的存储单元进行读操作、写操作、擦除操作中的至少一种以影响目标层中目标存储单元，提高目标存储单元的存储电压，延长了目标存储单元中存储电压的保持时间，保证了数据的准确性。
参照图5，图5为本申请数据处理方法第二实施例的流程示意图。该方法是对步骤S12的进一步扩展。其包括以下步骤：
S21：判断与目标层对应的目标存储块中是否存在非目标层。
在确定了目标存储单元以及其对应的目标层时，确定了与目标层对应的目标存储块，还需进一步确定该目标存储块中的层是否全部为目标层。若全部为目标层，则无法通过对非目标层进行操作以影响目标层中目标存储单元的存储电压。若判断到目标存储块中存在非目标层，执行步骤S22。若目标存储块中不存在非目标层，执行步骤S23。
S22：执行对目标存储块中非目标层中的存储单元进行操作的步骤。
若存在非目标层，可以执行上述步骤，对非目标层进行操作以提高目标层中存储单元的存储电压。
S23：将目标存储块中的部分存储单元中的数据转移至其他存储块， 以得到目标存储块中的非目标层，执行对目标存储块中非目标层中的存储单元进行操作的步骤。
若目标存储块中不存在非目标层，可以将一部分该目标存储块中存储的数据，读取写入至其他空闲的，或存有无效数据的存储块。这样已经写入其他存储块的这部分数据在其他存储块中作为有效数据，而在目标存储块中，这部分数据就算为无效数据。这部分数据在复制写入至其他存储块后，可以保留也可以擦除。在目标存储块中，这些数据占用的存储层中未存储有效数据的层，即可作为非目标层。得到非目标层后，可执行上述步骤，以提高目标存储单元的存储电压。
通过本实施例，对于全部存储有效数据的存储块，将部分有效数据转移至其他存储块，为存储块创造出非目标层，从而实现在有效数据出错时，能够提高目标存储单元的存储电压，维持有效数据的数据准确性。
在一具体实施例中，还可以是确定目标存储单元以及其对应的目标层时，确定与目标层对应的晶粒die，确定该晶粒中是否包含有非目标层，当不存在非目标层时，将晶粒中部分数据转移至其他晶粒中，以在该晶粒中创造出非目标层，对非目标层进行操作以提高目标层中目标存储单元的存储电压。
参照图6，图6为本申请数据处理方法第三实施例的流程示意图。该方法是对步骤S12的进一步扩展。其包括以下步骤：
S31：判断是否达到预设时间。
由于存储单元的掉电是一定程度时间累积的结果，因此可以为存储装置或其中的存储块预设一计时器。该计时器设置有预设时间。预设时间为该计时器预先设置的时间值。当到达预设时间后，执行步骤S32。执行之后，计时器清空，重新进行计时。若未达到预设时间，执行步骤S33。
S32：对目标存储块中非目标层中的存储单元进行操作。
达到预设时间，存储单元可能发生了掉电，通过上述操作提高目标存储单元的存储电压。
S33：不对目标存储块中非目标层中的存储单元进行操作。
未达到预设时间时，存储单元发生掉电的可能性较小，此时不进行上述操作，节约控制资源。
参照图7，图7为本申请数据处理方法第四实施例的流程示意图。该方法是对步骤S12的进一步扩展。其包括以下步骤：
S41：对目标存储单元进行读取，以得到读取数据。
对目标存储单元进行读取，获取其中保存的数据。存储装置中通常会设置纠错程序或算法，例如ECC。但是纠错程序是有纠错位数上限的，当错误的数据位数超过这个上限值，纠错程序就无法进行纠错。例如ECC校验能力为1bit ECC/512Byte，当512Byte数据中最多出现1bit的错误数据时，其可以进行纠正。但当512Byte数据中出现了2bit或以上的错误数据时，其无法进行纠错。
S42：判断读取数据的数据错误数量是否大于第一预设数量阈值。
判断读取出的数据其错误的位数数量是否大于第一预设数量阈值。第一预设数量阈值为设定的纠错程序或算法的纠错位数上限值。若大于，执行步骤S43。若小于，执行步骤S44。
S43：对目标存储块中非目标层中的存储单元进行操作。
纠错程序无法进行纠错，需要执行上述步骤，对非目标层中的存储单元进行操作，以提高目标存储单元的存储电压，从而减少数据错误位数，使其达到纠错程序或算法的纠错能力之内。
S44：不对目标存储块中非目标层中的存储单元进行操作。
未超过第一预设数量阈值，证明纠错程序或算法还能够进行纠错处理，无需执行上述对非目标层的操作，以节约控制资源。
参照图8，图8为本申请数据处理方法第四实施例的流程示意图。该方法是对第四实施例的进一步扩展。其包括以下步骤：
S51：对目标存储单元进行读取，以得到读取数据。
在对目标存储单元中的数据进行读取，发现出现较多错误数据时，对目标存储块中非目标层中的存储单元进行操作，操作之后继续对目标存储单元进行读取获取到读取数据，确定其错误数据的位数数量。
S52：判断读取数据的数据错误数量是否大于第一预设数量阈值。
判断读取出的数据其错误的位数数量是否大于第一预设数量阈值。第一预设数量阈值为设定的纠错程序或算法的纠错位数上限值。若小于，执行步骤S53。若大于，执行步骤S54。
S53：不对目标存储块中非目标层中的存储单元进行操作。
未超过第一预设数量阈值，证明纠错程序或算法还能够进行纠错处理，无需执行上述对非目标层的操作，以节约控制资源。
S54：对目标存储块中非目标层中的存储单元进行操作。
当纠错程序无法进行纠错，需要执行上述步骤，对非目标层中的存储单元进行操作，以提高目标存储单元的存储电压，从而减少数据错误位数，使其达到纠错程序或算法的纠错能力之内。但在对非目标层中存储单元进行操作的过程中，需要为操作的次数设定一第二预设数量阈值，或者为执行操作的时间设定一预设时间阈值。第二预设数量阈值作为一次数上限，基于第二预设数量阈值判断是否继续对目标存储块中非目标层中的存储单元进行操作。预设时间阈值为一时间上限，基于预设时间阈值判断是否继续对目标存储块中非目标层中的存储单元进行操作。而基于第二预设数量阈值或预设时间阈值判断是否继续对目标存储块中非目标层中的存储单元进行操作的步骤可依照下述步骤进行实施。
S55：判断进行操作的次数是否大于第二预设数量阈值，或进行操作的时间是否大于所述预设时间阈值。
从对非目标层中存储单元进行第一次操作时就开始计算次数，判断其是否大于第二预设数量阈值。或者，从对非目标层中存储单元进行第一次操作时就开始进行时间计时，判断其是否达到了预设时间阈值。若是，执行步骤S56。若否，执行步骤S57。
S56：不对目标存储块中非目标层中的存储单元进行操作。
经过大量对非目标层中存储单元的操作后，目标层中的目标存储单元的存储电压依旧没有提高至原有水平，其读取出的数据依旧出错。为节约资源，放弃对于该目标存储单元中数据的修复，不再对该目标存储块中的非目标层中的存储单元进行操作。
S57：对目标存储块中非目标层中的存储单元进行操作。
未达到第二预设数量阈值或预设时间阈值，可继续对非目标层中的存储单元进行操作，直至读取数据的错误位数小于第一预设数量阈值或进行操作的次数达到预设第二数量阈值或进行操作的时间超过预设时间阈值。
如图9所示，图9为本申请电子设备一实施例的结构示意图。
该电子设备包括处理器110、存储器120。
处理器110控制电子设备的操作，处理器110还可以称为CPU(Central Processing Unit，中央处理单元)。处理器110可能是一种集成电路芯片，具有信号序列的处理能力。处理器110还可以是通用处理器、数字信号序列处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
存储器120存储处理器110工作所需要的指令和数据。
处理器110用于执行指令以实现本申请前述数据处理方法的任一实施例及可能的组合所提供的方法。
如图10所示，图10为本申请计算机可读存储装置一实施例的结构示意图。
本申请可读存储装置一实施例包括存储器210，存储器210存储有程序数据，该程序数据被执行时实现本申请数据处理方法任一实施例及可能的组合所提供的方法。
存储器210可以包括U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等可以存储程序指令的介质，或者也可以为存储有该程序指令的服务器，该服务器可将存储的程序指令发送给其他设备运行，或者也可以自运行该存储的程序指令。
综上所述，本申请通过确定目标存储单元、目标层，进一步能够确定非目标层，对非目标层中的存储单元进行读操作、写操作、擦除操作中的至少一种以影响目标层中目标存储单元，提高目标存储单元的存储 电压，延长了目标存储单元中存储电压的保持时间，保证了数据的准确性。
在本申请所提供的几个实施方式中，应该理解到，所揭露的方法以及设备，可以通过其它的方式实现。例如，以上所描述的设备实施方式仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施方式方案的目的。
另外，在本申请各个实施方式中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
上述其他实施方式中的集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本申请各个实施方式所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

  1. 一种数据处理方法，其特征在于，所述方法包括：
    确定目标存储单元对应的目标层；
    对非目标层中的存储单元进行操作，以提高所述目标存储单元的存储电压；
    其中，所述操作包括读操作、写操作、擦除操作中至少一种。
  2. 根据权利要求1所述的方法，其特征在于，
    所述非目标层为与所述目标层相邻的层。
  3. 根据权利要求1所述的方法，其特征在于，
    所述非目标层为与所述目标层不相邻的层。
  4. 根据权利要求1-3中任一项所述的方法，其特征在于，所述对非目标层进行操作之前进一步包括：
    判断与所述目标层对应的目标存储块中是否存在所述非目标层；
    若是，执行对所述目标存储块中所述非目标层中的存储单元进行操作的步骤；
    若否，将所述目标存储块中的部分所述存储单元中的数据转移至其他存储块，以得到所述目标存储块中的所述非目标层，执行对所述目标存储块中所述非目标层中的存储单元进行操作的步骤。
  5. 根据权利要求4所述的方法，其特征在于，所述对非目标层进行操作之前进一步包括：
    判断是否达到预设时间，所述预设时间为预设计时器预先设置的时间值；
    若是，对所述目标存储块中所述非目标层中的存储单元进行操作；
    若否，不对所述目标存储块中所述非目标层中的存储单元进行操作。
  6. 根据权利要求4中任一项所述的方法，其特征在于，所述对非目标层进行操作之前进一步包括：
    对所述目标存储单元进行读取，以得到读取数据；
    判断所述读取数据的数据错误数量是否大于第一预设数量阈值；
    若是，对所述目标存储块中所述非目标层中的存储单元进行操作；
    若否，不对所述目标存储块中所述非目标层中的存储单元进行操作。
  7. 根据权利要求6所述的方法，其特征在于，对所述目标存储块中所述非目标层中的存储单元进行操作之后进一步包括；
    对所述目标存储单元进行读取，以得到读取数据；
    判断所述读取数据的数据错误数量是否大于所述第一预设数量阈值；
    若是，对所述目标存储块中所述非目标层中的存储单元进行操作，并基于第二预设数量阈值或预设时间阈值判断是否继续对所述目标存储块中所述非目标层中的存储单元进行操作；
    若否，不对所述目标存储块中所述非目标层中的存储单元进行操作。
  8. 根据权利要求7所述的方法，其特征在于，所述基于第二预设数量阈值或预设时间阈值判断是否继续对所述目标存储块中所述非目标层中的存储单元进行操作进一步包括：
    判断进行操作的次数是否大于所述第二预设数量阈值，或进行操作的时间是否大于所述预设时间阈值；
    若是，不对所述目标存储块中所述非目标层中的存储单元进行操作；
    若否，对所述目标存储块中所述非目标层中的存储单元进行操作。
  9. 一种电子设备，其特征在于，包括存储器和处理器，所述存储器用于存储程序数据，所述程序数据能够被所述处理器执行，以实现如权利要求1-8中任一项所述的方法。
  10. 一种计算机可读存储装置，其特征在于，存储有程序数据，能够被处理器执行，以实现如权利要求1-8中任一项所述的方法。
PCT/CN2022/121803 2022-09-16 2022-09-27 数据处理方法、电子设备及计算机可读存储装置 WO2024055358A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211131991.8A CN117724878A (zh) 2022-09-16 2022-09-16 数据处理方法、电子设备及计算机可读存储装置
CN202211131991.8 2022-09-16

Publications (1)

Publication Number Publication Date
WO2024055358A1 true WO2024055358A1 (zh) 2024-03-21

Family

ID=90205772

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/121803 WO2024055358A1 (zh) 2022-09-16 2022-09-27 数据处理方法、电子设备及计算机可读存储装置

Country Status (2)

Country Link
CN (1) CN117724878A (zh)
WO (1) WO2024055358A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140143473A1 (en) * 2012-11-19 2014-05-22 Spansion Llc Data refresh in non-volatile memory
US20200050515A1 (en) * 2018-08-10 2020-02-13 SK Hynix Inc. Memory system and operation method thereof
CN112967747A (zh) * 2021-04-07 2021-06-15 中国科学院微电子研究所 一种三维存储器的纠错方法及装置
CN113157486A (zh) * 2021-05-26 2021-07-23 中国科学院微电子研究所 一种存储器的纠错方法及装置
CN113241107A (zh) * 2021-06-01 2021-08-10 中国科学院微电子研究所 一种减少三维存储器的数据刷新操作的方法及装置
CN114203236A (zh) * 2021-12-10 2022-03-18 北京得瑞领新科技有限公司 Nand闪存的数据读操作电压施加方法及装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140143473A1 (en) * 2012-11-19 2014-05-22 Spansion Llc Data refresh in non-volatile memory
US20200050515A1 (en) * 2018-08-10 2020-02-13 SK Hynix Inc. Memory system and operation method thereof
CN112967747A (zh) * 2021-04-07 2021-06-15 中国科学院微电子研究所 一种三维存储器的纠错方法及装置
CN113157486A (zh) * 2021-05-26 2021-07-23 中国科学院微电子研究所 一种存储器的纠错方法及装置
CN113241107A (zh) * 2021-06-01 2021-08-10 中国科学院微电子研究所 一种减少三维存储器的数据刷新操作的方法及装置
CN114203236A (zh) * 2021-12-10 2022-03-18 北京得瑞领新科技有限公司 Nand闪存的数据读操作电压施加方法及装置

Also Published As

Publication number Publication date
CN117724878A (zh) 2024-03-19

Similar Documents

Publication Publication Date Title
US8036035B2 (en) Erase cycle counter usage in a memory device
US9478298B2 (en) Memory system and method of reading data thereof
US9747045B2 (en) Sub-sector wear leveling in memories
TWI545572B (zh) 記憶胞程式化方法、記憶體控制電路單元與記憶體儲存裝置
WO2009127987A1 (en) Using programming-time information to support error correction
Olson et al. Solid state drives data reliability and lifetime
US20230333932A1 (en) Memory system and operating method thereof
US11656777B2 (en) Memory system and operating method thereof
WO2024055358A1 (zh) 数据处理方法、电子设备及计算机可读存储装置
US11775214B2 (en) Memory system for suspending and resuming execution of command according to lock or unlock request, and operating method thereof
US11604734B2 (en) Memory system for determining whether to control a point of execution time of a command based on valid page counts of target memory blocks and operating method thereof
US11372766B2 (en) Memory system, memory controller, and method of operating memory system
US20220091932A1 (en) Memory system and operating method thereof
US20210389902A1 (en) Memory system, memory controller, and operation method of memory system
CN110908825B (zh) 一种数据读取方法、装置、存储设备及存储介质
US20210272619A1 (en) Data Storage With Improved Read Performance By Avoiding Line Discharge
CN113157486A (zh) 一种存储器的纠错方法及装置
US11461232B2 (en) Memory system and operating method of memory system
US11404137B1 (en) Memory system and operating method of memory system
US11960359B2 (en) Memory system, memory controller and operating method of memory system
Pletka et al. Enabling 3D-TLC NAND Flash in Enterprise Storage Systems
US11636007B2 (en) Memory system and operating method thereof for flushing data in data cache with parity
US11848054B2 (en) Memory device determining precharge time based on a number of times that a program voltage is applied to word line and operating method of memory device
US11507323B2 (en) Memory device and operating method thereof
US11899584B2 (en) System setting operating frequency of random access memory based on cache hit ratio and operating method thereof