WO2024054912A1 - Système et procédés de traitement de données de réseau - Google Patents

Système et procédés de traitement de données de réseau Download PDF

Info

Publication number
WO2024054912A1
WO2024054912A1 PCT/US2023/073642 US2023073642W WO2024054912A1 WO 2024054912 A1 WO2024054912 A1 WO 2024054912A1 US 2023073642 W US2023073642 W US 2023073642W WO 2024054912 A1 WO2024054912 A1 WO 2024054912A1
Authority
WO
WIPO (PCT)
Prior art keywords
timestamp
data frame
information
clock rate
frame
Prior art date
Application number
PCT/US2023/073642
Other languages
English (en)
Inventor
Thomas Joergensen
Original Assignee
Microchip Technology Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/098,228 external-priority patent/US20240089021A1/en
Application filed by Microchip Technology Incorporated filed Critical Microchip Technology Incorporated
Publication of WO2024054912A1 publication Critical patent/WO2024054912A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0673—Clock or time synchronisation among packet nodes using intermediate nodes, e.g. modification of a received timestamp before further transmission to the next packet node, e.g. including internal delay time or residence time into the packet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays

Definitions

  • the present disclosure relates to network data processing, and more particularly to processing of network transactions in a packet-switched communication network.
  • Clock synchronization is important in many network communication applications, such as real-time audio and video transmission.
  • Many such networks use Ethernet as a communication medium.
  • the common timebase may be used, for example, to trigger coordinated measurement actions in a network of sensors, to coordinate actions of controllers in an industrial system, or to synchronize clocks of mobile/cellular radio base stations.
  • the system may include computers and communication devices, such as routers and switches.
  • the IEEE802.1AS protocol also called Generalized Precision Time Protocol (gPTP) is one protocol for accurately transferring time information over Ethernet networks. It is designed to be a software protocol and was initially targeted to Audio- Video Bridging (AVB) networks, but has recently been re-purposed for Time Sensitive Networking (TSN) applications, including low-latency networks and industrial automation.
  • gPTP Generalized Precision Time Protocol
  • frames are forwarded to a local central processing unit (CPU) in the switch that receives the frames and performs frame modifications.
  • CPU central processing unit
  • These software operations in a local CPU significantly increase the time that the data frames are inside the Ethernet switch, called the residence time, since the software processing is much slower than the hardware forwarding.
  • the gPTP protocol also runs a separate software routine that measures the frequency difference between the local timebase in the Ethernet switch and the gPTP grandmaster clock source.
  • the calculation of the frequency difference between the local timebase and the grandmaster clock source is a product of calculations done in all previous gPTP bridges between the grandmaster clock source and respective individual bridges and is impacted by the timestamp accuracy of these systems, so the accuracy of this frequency difference will deteriorate with the number of nodes in a given network.
  • the accuracy of the residence time depends on the accuracy of the measured RateRatio (frequency difference between the local time reference and the grandmaster clock source time reference) and is multiplied by the residence time, so keeping the residence time low is the best way to increase the time transfer accuracy of a gPTP bridge.
  • a solution is needed to reduce the residence time in network data processing.
  • a device comprising an ingress port comprising a timestamp circuit to determine a first timestamp information based on a received data frame and to update the received data frame based on the first timestamp information to create a timestamped data frame, the ingress port to output the timestamped data frame, an output circuit comprising one or more egress ports to receive updated and timestamped data frames and modified and timestamp data frames, wherein the egress ports comprise a timestamp circuit to determine egress timestamp information and to save egress timestamp information to a timestamp memory, the output circuit to output data frame, a frame analyzer to receive the timestamped data frame from the ingress port and forward the timestamped data frame to a processor, the processor comprising a timestamp extractor to extract the first timestamp information from the timestamped data frame and to read egress timestamp information from the timestamp memory, a time calculator with inputs coupled to receive the first timestamp information and egress timestamp information, the time calculator to
  • a system including a plurality of network devices, wherein respective ones of a plurality of network devices are coupled to at least one other of the plurality of network devices, each respective ones of the network devices comprising an ingress port comprising a timestamp circuit to determine a first timestamp information based on a received data frame and to update the received data frame based on the first timestamp information to create a timestamped data frame, the ingress port to output the timestamped data frame, an output circuit comprising one or more egress ports to receive updated and timestamped data frames and modified and timestamp data frames, wherein the egress ports comprise a timestamp circuit to determine egress timestamp information and save egress timestamp information to a timestamp memory, the output circuit to output data frames, a frame analyzer to receive the timestamped data frame from the ingress port and forward the timestamped data frame to a processor, the processor comprising a timestamp extractor to extract the first timestamp information from the timestamped data frame and to read
  • a method comprising receiving a first data frame at an ingress port and generating a first timestamped data frame at the ingress port, transmitting first timestamped data frame to a processor, extracting the first timestamp information from the first data frame, reading a second timestamp information from a timestamp memory, calculating residence times and peer delays based on the first and second timestamp information, extracting clock rate information from the first data frame, calculating updated clock rate information based at least on the extracted clock rate information, generating an updated and timestamped data frame based at least on the updated clock rate information, and transmitting the updated and timestamped data frame on an egress port.
  • FIGURE 1 illustrates one of various examples of a device for network data processing.
  • FIGURE 2 illustrates one of various examples of a sequence of network data transactions.
  • FIGURE 3 illustrates one of various examples of a sequence of network data transactions.
  • FIGURE 4 illustrates a method for network data processing according to one of various examples.
  • FIGURE 1 illustrates one of various examples of a device 100 for receiving and transmitting network data transactions.
  • Device 100 may be comprised of primary device 110 and one or more relay devices 115.
  • Relay device 115 may be a switch or a bridge device according to the gPTP protocol.
  • Primary device 110 may transmit a data frame 111 to one or more relay devices 115, which data frame 111 may be received by a respective relay device 115.
  • Data frame 111 may be transmitted over a single wire or may be transmitted over a bussed connection.
  • Departure timestamp information may be stored in primary device 110, the departure timestamp information reflective of the departure time of the data frame from primary device 110.
  • the data frame may be received at ingress port 120.
  • Ingress port 120 may include timestamp circuit 125. Timestamp circuit 125 may determine arrival timestamp information reflective of the arrival time of the data frame at ingress port 120, the arrival time also referred to as tr. Timestamp circuit 125 may append arrival timestamp information to the received data frame to produce a timestamped data frame 127. Arrival timestamp information may also be termed first timestamp information.
  • the timestamped data frame 127 may be output by ingress port 120 and may be received by frame analyzer 140.
  • Frame analyzer 140 may control processing of data frames in secondary device 115 via control interface 157, the control based at least on information in the received timestamped data frame 127.
  • Frame analyzer 140 may forward the timestamped data frame 127 to rewriter circuit 150.
  • Rewriter circuit 150 may receive the timestamped data frame 127 from frame analyzer 140 and frame analyzer 140 may instruct rewriter circuit 150 to modify predetermined data fields in timestamped data frame 127 for at least one egress port.
  • the example of FIGURE 1 includes three egress ports, but this is not intended to be limiting.
  • frame analyzer 140 may instruct rewriter circuit 150 to modify predetermined data fields in timestamped data frame 127 for egress ports 161, 162 and 163, and rewriter circuit 150 may create a modified and timestamped data frame for respective egress ports 161, 162, and 163.
  • rewriter circuit 150 may modify the Media Access Control (MAC) address information in the received data frame for respective egress ports 161, 162 and 163.
  • MAC Media Access Control
  • Rewriter circuit 150 may modify other data in the received timestamped data frame 127.
  • the rewriter circuit 150 may forward the modified and timestamped data frames 155 to output circuit 160.
  • Output circuit 160 may contain one or more egress ports.
  • output circuit 160 may contain three egress ports 161, 162 and 163.
  • the output circuit 160 may update timestamp memory 170 with egress timestamp information for respective egress ports 161, 162, 163.
  • Egress timestamp information may be reflective of the departure time of the modified and timestamped data frame 155 at the respective egress ports.
  • the example illustrated in FIGURE 1 includes 3 egress ports, 161, 162 and 163, but this is not intended to be limiting.
  • One of various examples may include more egress ports than the number of egress ports illustrated in FIGURE 1 or may include fewer egress ports than the number illustrated in FIGURE 1.
  • Timestamp memory 170 may be a random-access memory, a first-in first-out (FIFO), or another memory component.
  • Frame analyzer 140 may additionally forward the timestamped data frame 127 to processor 130.
  • Processor 130 may receive the timestamped data frame 127 from frame analyzer 140.
  • a timestamp extractor 131 may extract the timestamp information, tr, from timestamped data frame 127.
  • Processor 130 may read the egress timestamps, t s , for egress ports from the egress timestamp memory 170. Respective timestamps may be indicated as tsn, where n is number from 1 to N, for respective ones of the N egress ports in the timestamp memory 170. Egress timestamps may also be termed second timestamp information.
  • a time calculator 132 in processor 130 may calculate the residence time for respective ones of the egress ports, as tsn-tr.
  • the value of tsn may represent the egress port timestamp from timestamp memory 170 as described previously, and the value of tr may represent the extracted timestamp information as described previously.
  • a clock rate extractor 134 in processor 130 may extract clock rate information from the timestamped data frame 127.
  • a clock rate calculator 135 in processor 130 may compute clock rate information based on the extracted clock rate information.
  • Clock rate information computed by the clock rate calculator 135 may include one or more clock rate parameters, including but not limited to RateRatio, Correction Field, peer delay and residence time.
  • a frame generator 136 in processor 130 may update data fields in the timestamped data frame 127 and output an updated and timestamped data frame 133 to output circuit 160. Updated and timestamped data frame 133 may be transmitted on at least one egress port in output circuit 160.
  • the RateRatio between a primary device and a relay device may be defined as the ratio of the frequency of the grandmaster clock source in the primary device to the frequency of the local clock in the relay device.
  • the neighborRateRatio between two networked devices may be defined as the ratio of the frequency of the clock at the second networked device to the frequency of the clock at the first networked device.
  • the neighborRateRatio may represent the drift in a clock as it traverses between networked devices.
  • uRR updated RateRatio
  • the frame generator 136 may generate the updated and timestamped data frame 133 based at least on the new Correction Field value and updated RateRatio.
  • the modified and timestamped data frame 155 received from rewriter circuit 150 may be transmitted at egress port 161 and transmitted over physical link 181.
  • Physical link 181 may be connected to one more network devices.
  • Output circuit 160 may save a timestamp generated at the egress of the modified and timestamped data frame 155 from egress port 161 into timestamp memory 170. Timestamp for egress port 161 may be reflective of the time the modified and timestamped data frame 155 may be transmitted on egress port 161. The timestamp for egress port 161 may be read by processor 130 as disclosed previously.
  • a modified and timestamped data frame 155 may be transmitted at egress port 162 and transmitted over physical link 182.
  • Physical link 182 may be connected to one more network devices.
  • Output circuit 160 may save a timestamp generated at the egress of the modified and timestamped data frame 155 from egress port 162 into timestamp memory 170. Timestamp for egress port 162 may be reflective of the time the modified and timestamped data frame 155 may transmitted on egress port 162. The timestamp for egress port 162 may be read by processor 130 as disclosed previously.
  • a modified and timestamped data frame 155 be transmitted at egress port 163 and transmitted over physical link 183.
  • Physical link 183 may be connected to one more network devices.
  • Output circuit 160 may save a timestamp generated at the egress of the modified and timestamped data frame 155 from egress port 163 into timestamp memory 170.
  • the timestamp for egress port 163 may be reflective of the time the modified and timestamped data frame 155 may be transmitted on egress port 163.
  • the timestamp for egress port 163 may be read by processor 130 as disclosed previously.
  • FIGURE 2 illustrates one of various examples of a sequence of transactions in a network.
  • the sequence of transactions illustrated in FIGURE 2 may be part of a procedure to calculate various delays between network components, including but not limited to peer delay and residence time.
  • Peer delay may be defined as the delay in transmitting a message from one networked device to a second networked device.
  • the sequence of transactions illustrated in FIGURE 2 may be received and transmitted by a device as illustrated in FIGURE 1 or may be received and transmitted by another network device.
  • Transactions transmitted from, and received at, a primary device 201 are illustrated on the left side vertical axis, and transactions transmitted from, and received at, a secondary device 202 are illustrated on the right side vertical axis.
  • the vertical direction may indicate time.
  • Primary device 201 may represent a bridge device, a switch device, or another network device capable to receive and transmit network transactions.
  • Secondary device 202 may represent a bridge device, a switch device, or another network device capable to receive and transmit network transactions.
  • Primary device 201 may send a request frame 215 to secondary device 202.
  • Request frame 215 may be sent by primary device 201 at time 210.
  • Time 210 may also be termed ti.
  • the value of time 210 may be stored as a timestamp in a timestamp storage element in primary device 201, including but not limited to a FIFO or random access memory.
  • Request frame 215 may be received at secondary device 202 at time 220.
  • Time 220 may also be termed t2.
  • the time from time 210 to time 220, illustrated as 231, represents the time for the request frame to traverse the physical network from primary device 201 to secondary device 202.
  • secondary device 202 may process request frame 215 as described in reference to FIGURE 1, and clock rate information may be calculated and data frame fields may be updated.
  • Secondary device 202 may send response frame 216 at time 221. Time 221 may also be termed t3.
  • Response frame 216 may transmit information from secondary device 202 to primary device 201, the information including but not limited to the value of time 220., i.e. t2.
  • Secondary device 202 may store the timestamp generated when response frame 216 is transmitted, i.e. t3, in a timestamp storage element in slave device 202, including but not limited to a FIFO or random access memory.
  • Response frame 216 may be received at primary device
  • Time 212 may also be termed t4.
  • the value of time 212 may be stored as a timestamp in a timestamp storage element in primary device 201, including but not limited to a FIFO or random access memory.
  • the time duration from time 221 to time 212 may represent the time for the response frame to traverse the network from secondary device 202 to primary device 201.
  • Secondary device 202 may send follow-up frame 217 at time 222, which time 222 may be prior to time 212.
  • follow-up frame 217 may transmit information from secondary device
  • Follow-up frame 217 may be received at primary device 201 at time 213.
  • NeighborRateRatio may be computed based on the values of t3 and to in subsequent frames, which may represent the difference in clock rates between primary device 201 and secondary device 202.
  • FIGURE 3 illustrates one of various examples of a sequence of transactions received and transmitted by network devices.
  • the sequence of transactions may be received and transmitted by network devices as described in FIGURE 1.
  • the sequence of transactions may be received and transmitted by network devices not illustrated in FIGURE 1.
  • a device 1 may transmit data to a device 2.
  • Device 2 may transmit data to another node in a network (not shown). Data may be transmitted from device 1 egress port 301 to device 2 ingress port 321 and then output at device 2 egress port 341.
  • Transactions transmitted by device 1 egress port 301 are illustrated along the left side vertical axis
  • transactions received by device 2 ingress port 321 are illustrated along the middle vertical axis
  • transactions transmitted by device 2 egress port 341 are illustrated along the right side vertical axis.
  • the vertical direction may indicate time.
  • Device 1 and device 2 may respectively represent a bridge device, a switch device, or another network device capable to receive and transmit network transactions.
  • Device 1 and device 2 may represent network devices as described in reference to FIGURE 1.
  • device 1 may transmit a sync frame 315 from device 1 egress port 301.
  • Sync frame 315 may be received at device 2 ingress port 321 at time 330.
  • a timestamp circuit in device 2 ingress port 321 may timestamp the arrival time of sync frame 315 at device 2 ingress port 321 as time tr as described in reference to ingress port 120 of FIGURE 1.
  • Internal circuitry in device 2 may forward the timestamped sync frame to a rewriter circuit and the rewriter circuit may modify sync frame information as described in reference to FIGURE 1.
  • a processor in device 2 may calculate the residence time of device 2 and the peer delay between device 1 and device 2 as described previously.
  • a processor in device 2 may calculate the peer delay and neighborRateRatio as described previously.
  • Sync frame 355 may be output at device 2 egress port 341 at time 350, and egress timestamps may be recorded in a timestamp memory, as described in reference to output circuit 160 and timestamp memory 170 of FIGURE 1.
  • device 1 may transmit follow-up frame 316 from device 1 egress port 301.
  • the follow-up frame 316 may be transmitted at the same time sync frame 315 is received at device 2 ingress port 321, but this is not intended to be limiting.
  • follow-up frame 316 may be transmitted by device 1 egress port 301 before or after the arrival of sync frame 315 at device 2 ingress port 321.
  • follow-up frame 316 may include timing information, including but not limited to RateRatio (RR) and Correction Field information.
  • RR RateRatio
  • Correction Field information follow-up frame 316 may be received at device 2 ingress port 321 at time 331.
  • Device 2 may compute an updated RateRatio (uRR) and a new Correction Field (nCF) as described in reference to FIGURE 1.
  • Device 2 may generate a follow-up frame 356 for device 2 egress port 341 which may be transmitted at time 351.
  • the example as described in FIGURE 3 may reduce the residence time as forwarding and processing of data frames is done in hardware.
  • device 2 may output a sync frame 355 at time 350, prior to the arrival of the followup frame 316 at time 331.
  • FIGURE 4 illustrates a method 400 for network data processing in a network device according to one of various examples.
  • a network device may receive a first data frame and generate a first timestamp information.
  • the network device may modify the data frame based on the first timestamp information.
  • the network device may transmit the modified and timestamped data frame to a processor.
  • the processor may read second timestamp information from a timestamp memory.
  • processor may calculate residence times and peer delays based on the first and second timestamp information.
  • processor may extract clock rate information from the modified and timestamped data frame and calculate updated clock rate information.
  • processor may generate an updated and timestamped data frame based on updated clock rate information.
  • network device may transmit updated and timestamped data frame at an egress port.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Un système pour les transactions de données de réseau, le système comprenant un port d'entrée pour recevoir des trames de données et horodater les trames de données reçues, un analyseur de trames pour transmettre les trames de données à un processeur, le processeur pour extraire des informations temporelles des trames de données et mettre à jour les trames de données sur la base des calculs temporels mis à jour et sortir les trames de données mises à jour par le biais d'un ou plusieurs ports d'évacuation. Les trames de données sont horodatées au niveau des ports d'entrée et de sortie, et les horodatages de sortie sont enregistrés dans une mémoire d'horodatage. Le système réduit les retards de réseau globaux en utilisant un matériel dédié et des informations d'horodatage stockées.
PCT/US2023/073642 2022-09-08 2023-09-07 Système et procédés de traitement de données de réseau WO2024054912A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202263404710P 2022-09-08 2022-09-08
US63/404,710 2022-09-08
US18/098,228 US20240089021A1 (en) 2022-09-08 2023-01-18 System and methods for network data processing
US18/098,228 2023-01-18

Publications (1)

Publication Number Publication Date
WO2024054912A1 true WO2024054912A1 (fr) 2024-03-14

Family

ID=88236546

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2023/073642 WO2024054912A1 (fr) 2022-09-08 2023-09-07 Système et procédés de traitement de données de réseau

Country Status (1)

Country Link
WO (1) WO2024054912A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120014377A1 (en) * 2010-03-02 2012-01-19 Thomas Kirkegaard Joergensen Distributed packet-based timestamp engine
EP2595331A2 (fr) * 2011-11-16 2013-05-22 Fujitsu Limited Appareil de communication pour synchronisation de temps
WO2019023515A1 (fr) * 2017-07-26 2019-01-31 Aviat Networks, Inc. Horloge radio transparente distribuée sur un réseau sans fil
CN111800213A (zh) * 2020-06-19 2020-10-20 西安电子科技大学 面向高速tte级联网络1588同步方法、系统、装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120014377A1 (en) * 2010-03-02 2012-01-19 Thomas Kirkegaard Joergensen Distributed packet-based timestamp engine
EP2595331A2 (fr) * 2011-11-16 2013-05-22 Fujitsu Limited Appareil de communication pour synchronisation de temps
WO2019023515A1 (fr) * 2017-07-26 2019-01-31 Aviat Networks, Inc. Horloge radio transparente distribuée sur un réseau sans fil
CN111800213A (zh) * 2020-06-19 2020-10-20 西安电子科技大学 面向高速tte级联网络1588同步方法、系统、装置

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
DANIEL KOHLER ED - ANONYMOUS: "A Practical Implementation of an IEEE1588 supporting Ethernet Switch", INFORMATION SCIENCES AND SYSTEMS, 2007. CISS '07. 41ST ANNUAL CON FERENCE ON, IEEE, 1 October 2007 (2007-10-01), pages 134 - 137, XP031161292, ISBN: 978-1-4244-1063-7 *
DIARRA ABOUBACAR ET AL: "Improved clock synchronization start-up time for Ethernet AVB-based in-vehicle networks", 2015 IEEE 20TH CONFERENCE ON EMERGING TECHNOLOGIES & FACTORY AUTOMATION (ETFA), IEEE, 8 September 2015 (2015-09-08), pages 1 - 8, XP032797336, DOI: 10.1109/ETFA.2015.7301412 *
SCHUNGEL MAXIMILIAN ET AL: "Analysis of Time Synchronization for Converged Wired and Wireless Networks", 2020 25TH IEEE INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES AND FACTORY AUTOMATION (ETFA), IEEE, vol. 1, 8 September 2020 (2020-09-08), pages 198 - 205, XP033835766, DOI: 10.1109/ETFA46521.2020.9212068 *

Similar Documents

Publication Publication Date Title
US9256247B2 (en) Method and apparatus for communicating time information between time aware devices
US10931391B2 (en) One-step time stamping of synchronization packets for networked devices
US20110035511A1 (en) Remote Hardware Timestamp-Based Clock Synchronization
KR102652569B1 (ko) 비용 최적화된 환경들에서 phy 레벨 하드웨어 타임스탬핑 및 시간 동기화의 수행
US8576883B2 (en) Measurement and adjustment of real-time values according to residence time in networking equipment without access to real time
US20100034191A1 (en) Method and system for time synchronization in a sensor network
CN113497803B (zh) 使用商品nic/交换机进行tdma联网的网络元件
JP2006101539A (ja) ネットワーク転送装置
US8949648B2 (en) System and method to overcome wander accumulation to achieve precision clock distribution over large networks
US20210385058A1 (en) Method and apparatus for synchronizing different communication ports
EP3785383A1 (fr) Synchronisation temporelle sur des réseaux de câbles
CN102916758B (zh) 以太网时间同步装置和网络设备
CN104243079A (zh) 一种实时以太网的微秒级时钟同步方法
US20240089021A1 (en) System and methods for network data processing
WO2024054912A1 (fr) Système et procédés de traitement de données de réseau
US9442511B2 (en) Method and a device for maintaining a synchronized local timer using a periodic signal
Moreira et al. IEEE 1588 Transparent Clock architecture for FPGA-based network devices
CN113381832B (zh) 一种基于fpga平台的精确时间同步方法
CN114978396A (zh) 一种精确时间协议透明时钟两步模式的实现方法
WO2020132834A1 (fr) Procédé et dispositif de traitement d'estampillage
WO2024131470A1 (fr) Procédé et dispositif de synchronisation d'horloge, puce, module de puce, système et support de stockage
EP3812716B1 (fr) Dispositif de pesée dynamique
JP2006148774A (ja) 同期装置
Nuka et al. Performance Evaluation of PTP in Switched Ethernet Networks
CN113839730A (zh) 时间同步方法、网络设备及存储介质

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23782708

Country of ref document: EP

Kind code of ref document: A1