WO2024054199A1

WO2024054199A1 - Profile selector

Info

Publication number: WO2024054199A1
Application number: PCT/US2022/042585
Authority: WO
Inventors: Callum Stewart
Original assignee: Siemens Industry Software Inc.
Priority date: 2022-09-05
Filing date: 2022-09-05
Publication date: 2024-03-14

Abstract

An integrated circuit and a method of monitoring behaviour in an integrated circuit are provided. The integrated circuit includes sub-blocks in a system-on-chip (SoC) arrangement, interconnect circuitry configured to transport transactions between the sub-blocks and a monitor configured to observe the behaviour of the integrated circuit. The monitor includes a filter configured to filter data observed by the monitor, at least two registers communicatively coupled to the filter and including a configuration profile for the filter, and a profile selector configured to select one of the registers and implement the configuration profile of the selected register as the active configuration of the filter.

Description

PROFILE SELECTOR

TECHNICAL FIELD

[0001] The present disclosure relates to a system and method for an integrated circuit.

BACKGROUND

[0002] Electronic devices incorporating System-on-Chip (SoC) circuits have become ubiquitous. In particular, SoC circuits are widely used in small consumer electronics devices such as smartphones and tablets and embedded systems such as Internet-of-Things (loT) devices and WiFi routers.

[0003] SoC devices are integrated circuits combining components as blocks on a single substrate or microchip. These components may include one or more processor cores, memory, input/output interfaces, a graphics processing unit (GPU), and secondary storage interfaces. SoC architectures provide numerous benefits including power saving, space saving, lower latency, and cost reduction.

SUMMARY

[0004] It is an object of the disclosure to provide a method for monitoring behaviour in an integrated circuit including sub-blocks in a system-on-chip (SoC) arrangement.

[0005] The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description, and the figures.

[0006] According to a first aspect, an integrated circuit is provided. The integrated circuit includes sub-blocks in a system-on-chip (SoC) arrangement, interconnect circuitry configured to transport transactions between the sub-blocks, and a monitor configured to observe the behaviour of the integrated circuit. The monitor includes a filter configured to filter data observed by the monitor and at least two registers. Each register is communicatively coupled to the filter and includes a configuration profile for the filter. The monitor includes a profile selector configured to select one of the registers and implement the configuration profile of the selected register as the active configuration of the filter.

[0007] The integrated circuit according to the first aspect provides a monitor which can implement configuration profiles in a filter quickly and easily. The profile selector enables selection of a profile for the filter with very low latency.

[0008] According to a second aspect, a method of monitoring behaviour in an integrated circuit between sub-blocks in a system-on-chip (SoC) arrangement is provided. The method includes observing the integrated circuit; selecting, using a profile selector connected between at least two registers and a filter, one of at least two registers, each register including a configuration profile for the filter; and implementing the configuration profile of the selected register as an active configuration of the filter in response to the behaviour of the integrated circuit.

[0009] According to a third aspect, a non-transitory computer readable storage is provided. The non-transitory computer readable storage includes program code that, when executed by a processor, provides instructions to perform the method according to the second aspect.

[0010] In a first implementation form of the integrated circuit, each configuration profile is different.

[0011] The first implementation form enables a single filter to implement different configurations. [0012] In a second implementation form, the profile selector is configured to select one of the registers based on an event on the integrated circuit.

[0013] In a third implementation form, the event is cross-triggered event or a user- triggered event.

[0014] In a fourth implementation form, when the profile selector experiences the event the profile selector is configured to react to, the profile selector selects a different register. [0015] The second, third, and fourth implementation forms enable the monitor to react quickly to events on the integrated circuit or in the wider system.

[0016] In a fifth implementation form, the monitor is configured to observe transactions transported by the interconnect circuitry between the sub-blocks.

[0017] In a sixth implementation form, when implemented at the filter, each individual configuration profile is configured to cause the filter to filter transactions according to the configuration profile.

[0018] The fifth and sixth implementation forms enable filtering of different transactions based on, for example, transaction metadata using a single filter and multiple configuration profiles.

[0019] In a seventh implementation form, the monitor is an embedded logic analyser configured to observe signals obtained from the integrated circuit.

[0020] In an eighth implementation form, the registers are adapted to be runtime configurable.

[0021] In a ninth implementation form, the profile selector is a multiplexer.

[0022] The ninth implementation form provides simple logic for implementing a profile selector in hardware. [0023] These and other aspects of the disclosure are apparent from the embodiment s) described below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0025] Figure 1 shows a schematic diagram of an integrated circuit, according to an example.

[0026] Figure 2 is a schematic diagram of a monitor for an integrated circuit, according to an example.

[0027] Figure 3 is a block diagram of a method for monitoring behaviour in an integrated circuit, according to an example.

[0028] Figure 4 shows a simplified schematic diagram of a computing system, according to an example.

DETAILED DESCRIPTION

[0029] Example embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments can be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

[0030] Accordingly, while embodiments can be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description where appropriate.

[0031] The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and “the” are singular in that they have a single referent, however the use of the singular form in the present document should not preclude the [0032] presence of more than one referent. In other words, elements referred to in the singular can number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and/or groups thereof.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as is customary in the art. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

[0034] Figure 1 is a simplified schematic diagram showing an integrated circuit 100, according to an example. The integrated circuit 100 shown in Figure 1 may be used in conjunction with the other methods and systems described herein.

[0035] The integrated circuit 100 includes sub-blocks 110, 120 in a System on Chip (SoC) arrangement. The sub-blocks 110, 120 are fully integrated into the circuit 100 on a single substrate or microchip. Each of sub-blocks 110, 120 may be a central processing unit (CPU), a memory device, input/output device, secondary storage devices, graphical processing units (GPUs), custom logic or any other type of component suitable for a SoC architecture. In the example shown in Figure 1, the integrated circuit 100 includes two subblocks 110, 120. In other examples, more than two sub-blocks may be provided on the integrated circuit 100. According to examples, the integrated circuit 100 may be a standalone circuit. In other cases, the integrated circuit 100 may form part of a larger system.

[0036] According to examples, the sub-blocks 110, 120 are connected via interconnect circuitry forming a bus 130. The bus 130 is configured to transport transactions between the sub-blocks 110, 120. A transaction may include a data payload and a header. The header may include addressing information which may be used to route the transaction to a destination address. The transaction may also include metadata. For example, the transaction may include a time stamp generated at the transactions source, identifying information which identifies the transaction, and information identifying a transaction type. [0037] In Figure 1, the integrated circuit 100 includes a monitor 140. The monitor 140 is configured to observe the behaviour of the integrated chip 100. In the example shown in Figure 1, the monitor 140 is a bus monitor, which is configured to observe transactions transported on the interconnect circuitry. For example, the monitor may be configured to monitor utilization of the bus 130 by sub-blocks 110, 120. This may include monitoring the latency, size, type, number, or any other attribute associated to transactions which are sent over the bus 130.

[0038] In other examples, the monitor 140 may be a different kind of monitor, configured to monitor other aspect of transactions or the integrated circuit 100. For example, the monitor 140 may be an embedded logic analyser configured to observe signals obtained from the integrated circuit 100.

[0039] Figure 2 is a simplified schematic diagram showing a monitor 200, according to an example. The monitor 200 may be the bus monitor 140 shown in Figure 1. In particular, the monitor 200 may be used in conjunction with the other methods and systems described herein.

[0040] The monitor 200 includes a filter 210. The filter 210 may be configured to filter transactions or signals which are obtained from monitoring the integrated circuit. In the case of a transaction filter, the filter 210 may be parameterizable over a transaction field. For example, the filter 210 may filter transactions based on addresses, transaction identifiers, transaction type or any other metadata associated to the transaction. The filter 210 may implement a condition. For example, in one case the filter 210 may measure bus utilization. In another case, the filter 210 may measure latency of transactions and filter for transactions with a latency above a specific threshold. The filter 210 may be used to capture transactions for a trace.

[0041] The monitor 200 includes memory registers 220, 230, 240. Each of the registers 220, 230, 240 is configured to store a different configuration profile for the filter 210. According to examples described herein, each configuration profile provides a different configuration of the filter 210. For example, a first profile in the register 220, may specify filtering for transactions in a specific address range, a second profile in the register 230 may specify filtering for transactions with a latency above a specific threshold and a third profile in the register 240 may specify filtering for transactions in the specific address range of the first profile and above the specified threshold latency in the second profile. [0042] In certain examples, the monitor 200 may include two registers. In another example, the monitor 200 may include more than three registers. In some examples, the registers 220, 230, 240 are runtime configurable. For example, in some cases, configuration profiles for the registers may be loaded at runtime.

[0043] The filter 210 and registers 220, 230, 240 are communicatively coupled to a profile selector 250. The profile selector 250 is configured to select one of the registers and implement the configuration profile as the active configuration profile of the filter 210. The profile selector 250 may be implemented as a switch or multiplexer in hardware.

[0044] According to certain examples, the profile selector 250 is configured to select one of the registers based on an event on the integrated circuit. For example, the profile selector may be configured to respond to a cross-triggered event on the integrated circuit or wider system by selecting a particular register from one of the registers 220, 230, 240 and implementing the profile at the filter 210. In another example, an event may be a user- triggered event.

[0045] Figure 3 is a block diagram of a method 300 of monitoring behaviour in an integrated circuit including sub-blocks in a System on Chip (SoC) arrangement, according to an example. The method 300 may be implemented in conjunction with the integrated circuit 100 shown in Figure 1.

[0046] At block 310, the method 300 includes observing the integrated circuit. According to certain examples, observing the integrated circuit may include observing transactions transported by interconnect circuitry between the sub-blocks. In other examples, observing the integrated circuit includes observing signals obtained from the integrated circuit. Observing may be performed by a monitor similar to the monitor 200 previously described.

[0047] At block 320, the method includes selecting, using a profile selector connected between at least two registers and a filter, one of at least two registers. In certain examples, each of the registers include a configuration profile for the filter. The filter, profile selector, and registers referred to herein may be the filter 210, profile selector 250, and registers 220, 230, 240. Accordingly, selection of the register may be based on an event on the integrated circuit or wider system, such as a user-triggered or cross-triggered event.

[0048] At block 330, the method includes implementing the configuration profile of the selected register as an active configuration of the filter in response to the behaviour of the integrated circuit.

[0049] The method described herein enable a filter to implement different configuration profiles quickly and easily. The method does not require reconfiguration of a configuration profile which is a slow operation in software. Furthermore, the profile selector enables the monitor to use the filter with a different configuration in a way which is highly reactive to events happening in the integrated circuit with very low latency. This is because the profile selector is implemented with minimal additional logic using, for example, a multiplexer.

[0050] The present disclosure is described with reference to flow charts and/or block diagrams of the method, devices, and systems according to examples of the present disclosure. Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted. Blocks described in relation to one flow chart may be combined with those of another flow chart. In some examples, some blocks of the flow diagrams may not be necessary and/or additional blocks may be added. It shall be understood that each flow and/or block in the flow charts and/or block diagrams, as well as combinations of the flows and/or diagrams in the flow charts and/or block diagrams can be realized by machine readable instructions.

[0051] The machine-readable instructions may, for example, be executed by a general- purpose computer, a special purpose computer, an embedded processor, or processors of other programmable data processing devices to realize the functions described in the description and diagrams. In particular, a processor or processing apparatus may execute the machine-readable instructions. Thus, modules of apparatus may be implemented by a processor executing machine-readable instructions stored in a memory, or a processor operating in accordance with instructions embedded in logic circuitry. The term 'processor' is to be interpreted broadly to include a CPU, processing unit, ASIC, logic unit, or programmable gate set, etc. The methods and modules may all be performed by a single processor or divided amongst several processors.

[0052] Such machine-readable instructions may also be stored in a computer readable storage that can guide the computer or other programmable data processing devices to operate in a specific mode. Figure 4 shows an example 400 of a processor 410 associated with a memory 420. The memory 420 includes computer readable instructions 430 which are executable by the processor 410.

[0053] The instructions 430 cause the processor 410 to observe the integrated circuit, select, using a profile selector connected between at least two registers and a filter, one of at least two registers, each register including a configuration profile for the filter and implement the configuration profile of the selected register as an active configuration of the filter in response to the behaviour of the integrated circuit. [0054] Such machine-readable instructions may also be loaded onto a computer or other programmable data processing devices, so that the computer or other programmable data processing devices perform a series of operations to produce computer-implemented processing, thus the instructions executed on the computer or other programmable devices provide an operation for realizing functions specified by flow(s) in the flow charts and/or block(s) in the block diagrams.

[0055] Further, the teachings herein may be implemented in the form of a computer software product, the computer software product being stored in a storage medium and including a plurality of instructions for making a computer device implement the methods recited in the examples of the present disclosure.

[0056] The present disclosure may be embodied in other specific apparatus and/or methods. The described embodiments are to be considered in all respects as illustrative and not restrictive. In particular, the scope of the disclosure is indicated by the appended claims rather than by the description and figures herein. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims

1. An integrated circuit, comprising: sub-blocks in a system-on-chip (SoC) arrangement; interconnect circuitry configured to transport transactions between the sub-blocks; and a monitor configured to observe the behaviour of the integrated circuit, the monitor comprising: a filter configured to filter data observed by the monitor; at least two registers, each register communicatively coupled to the filter and comprising a configuration profile for the filter; and a profile selector configured to select a register of the at least two registers and implement the configuration profile of the selected register as the active configuration of the filter.

2. The integrated circuit of claim 1, wherein each configuration profile is different.

3. The integrated circuit as claimed in 1 or 2, wherein the profile selector is configured to select the register of the at least two registers based on an event on the integrated circuit.

4. The integrated circuit as claimed in claim 3, wherein the event is a cross-triggered event or a user-triggered event.

5. The integrated circuit as claimed in claim 4, wherein, when the profile selector experiences the event the profile selector is configured to react to, the profile selector selects a different register.

6. The integrated circuit as claimed in 1 to 5, wherein the monitor is configured to observe transactions transported by the interconnect circuitry between the sub-blocks.

7. The integrated circuit as claimed in claim 1 to 6, wherein, when implemented at the filter, each individual configuration profile is configured to cause the filter to filter transactions according to the configuration profile.

8. The integrated circuit as claimed in claims 1 to 7, wherein the monitor is an embedded logic analyser configured to observe signals obtained from the integrated circuit.

9. The integrated circuit as claimed in claims 1 to 8, wherein the registers are adapted to be runtime configurable.

10. The integrated circuit as claimed in any claims 1 to 9, wherein the profile selector is a multiplexer.

11. A method of monitoring behaviour in an integrated circuit comprising sub-blocks in a system-on-chip (SoC) arrangement, the method comprising: observing the integrated circuit; selecting, using a profile selector connected between at least two registers and a filter, a register of the at least two registers, each register comprising a configuration profile for the filter; and implementing the configuration profile of the selected register as an active configuration of the filter in response to the behaviour of the integrated circuit.

12. The method as claimed in claim 11, wherein the selecting of the register of the at least two registers is based on an event on the integrated circuit.

13. The method as claimed in claim 11 or 12, wherein the observing of the integrated circuit comprises observing transactions transported by interconnect circuitry between the sub-blocks.

14. The method as claimed in claim 11 to 13, wherein the observing of the integrated circuit comprises observing signals obtained from the integrated circuit.

15. A non-transitory computer readable storage comprising program code that, when executed by a processor, provides instructions to perform the method according to any one of claims 11 to 14.