WO2024053267A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2024053267A1
WO2024053267A1 PCT/JP2023/026844 JP2023026844W WO2024053267A1 WO 2024053267 A1 WO2024053267 A1 WO 2024053267A1 JP 2023026844 W JP2023026844 W JP 2023026844W WO 2024053267 A1 WO2024053267 A1 WO 2024053267A1
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Prior art keywords
trenches
semiconductor device
field plate
trench
semiconductor
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PCT/JP2023/026844
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French (fr)
Japanese (ja)
Inventor
一樹 吉田
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ローム株式会社
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Publication of WO2024053267A1 publication Critical patent/WO2024053267A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to a semiconductor device.
  • Patent Document 1 discloses a semiconductor device having a plurality of trench gate structures formed in a stripe shape. Each trench gate structure includes a gate trench and two electrodes buried separately in the depth direction of the gate trench.
  • the gate electrode and the field plate electrode When the gate electrode and the field plate electrode are buried separately in the gate trench, the gate electrode and the field plate electrode extend into the gate trench while facing each other. If the capacitance created by the gate electrode and the field plate electrode is relatively large, undesirable behavior of the semiconductor device, such as self-turn-on, can be caused.
  • a semiconductor device includes a semiconductor layer, a plurality of first trenches formed in the semiconductor layer and arranged in a mesh shape, and extending in a first direction in a plan view; a plurality of second trenches extending in a second direction intersecting the first direction when viewed, the plurality of first trenches and the plurality of second trenches intersecting and communicating with each other; an insulating layer formed on the semiconductor layer; a plurality of gate electrodes each embedded in the plurality of first trenches via the insulating layer and extending in the first direction; and a plurality of second trenches.
  • a plurality of field plate electrodes are respectively embedded in the trenches via the insulating layer and extend in the second direction.
  • the capacitance caused by the gate electrode and the field plate electrode can be reduced.
  • FIG. 1 is a schematic cross-sectional perspective view of an exemplary semiconductor device according to one embodiment.
  • FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. 1.
  • FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG.
  • FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG.
  • FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG.
  • FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 in FIG.
  • FIG. 7 is a schematic cross-sectional perspective view of an exemplary semiconductor device according to a comparative example.
  • FIG. 8 is a schematic cross-sectional view of the semiconductor device shown in FIG. 7.
  • FIG. 9 is a schematic plan view of a semiconductor device according to a modification example.
  • FIG. 1 is a schematic cross-sectional perspective view of an exemplary semiconductor device 10 according to one embodiment.
  • FIG. 2 is a schematic plan view of the semiconductor device 10.
  • the semiconductor device 10 may be, for example, a MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) having a trench gate structure.
  • the semiconductor device 10 includes a semiconductor layer 12 , a cell trench 14 formed in the semiconductor layer 12 , and an insulating layer 16 formed on the semiconductor layer 12 .
  • the semiconductor layer 12 may include a semiconductor substrate 18 and an epitaxial layer 20, and the cell trench 14 may be formed in the epitaxial layer 20.
  • the semiconductor substrate 18 may be a silicon (Si) substrate.
  • the epitaxial layer 20 may be a Si epitaxial layer.
  • the top surface 12A of the semiconductor layer 12 may be included in the epitaxial layer 20, while the bottom surface 12B of the semiconductor layer 12 may be included in the semiconductor substrate 18.
  • Insulating layer 16 may include at least one of a silicon oxide (SiO 2 ) layer and a silicon nitride (SiN) layer.
  • a cross-sectional view and a plan view of the semiconductor device 10 at the position of the upper surface 12A of the semiconductor layer 12 are shown, respectively, for ease of understanding (line F1-F1 in FIG. 3). reference). It should be noted that, as shown in FIG. 3, the insulating layer 16 is formed not only within the cell trench 14 but also on the upper surface 12A of the semiconductor layer 12.
  • the semiconductor device 10 may further include a drain electrode 22 formed on the bottom surface 12B of the semiconductor layer 12.
  • Drain electrode 22 may be formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, Cu alloy, and Al alloy. .
  • the cell trench 14 includes a plurality of first trenches 24 extending in a first direction in plan view and a plurality of second trenches extending in a second direction intersecting the first direction in plan view. 26.
  • the Z-axis direction of the mutually orthogonal XYZ axes shown in FIGS. 1 and 2 is a direction that is orthogonal to the surface of the semiconductor layer 12.
  • the term "planar view” used in this specification refers to viewing the semiconductor device 10 from above along the Z-axis direction, unless explicitly stated otherwise.
  • the first direction is the longitudinal direction of the first trench 24, and the second direction is the longitudinal direction of the second trench 26. In the example shown in FIGS.
  • the first direction may be the Y-axis direction
  • the second direction may be the X-axis direction. Therefore, in the illustrated example, the angle between the first direction and the second direction is 90 degrees. Note that, as will be described later with reference to FIG. 9, the first direction and the second direction do not necessarily have to correspond to the Y-axis direction and the X-axis direction, respectively.
  • the cell trench 14 has an opening in the upper surface 12A of the semiconductor layer 12 and has a depth in the Z-axis direction.
  • the plurality of first trenches 24 and the plurality of second trenches 26 intersect and communicate with each other. Thereby, the cell trenches 14 are arranged in a mesh shape.
  • the cell trench 14 includes a plurality of intersection regions 14A where a plurality of first trenches 24 and a plurality of second trenches 26 intersect with each other, and a plurality of first trenches 24 and a plurality of second trenches 26. and a plurality of non-intersecting regions 14B that do not intersect with each other.
  • the plurality of first trenches 24 may be arranged in stripes.
  • each of the plurality of first trenches 24 has a width W1.
  • the width W1 of the first trench 24 corresponds to the dimension of the first trench 24 in the lateral direction (that is, the direction perpendicular to the first direction) in plan view.
  • the plurality of first trenches 24 can be arranged parallel to each other at a constant interval S1.
  • the plurality of second trenches 26 may be arranged in a stripe pattern.
  • each of the plurality of second trenches 26 has a width W2.
  • the width W2 of the second trench 26 corresponds to the dimension of the second trench 26 in the lateral direction (that is, the direction orthogonal to the second direction) in plan view.
  • the plurality of second trenches 26 can be arranged parallel to each other at constant intervals S2.
  • the interval S1 between the plurality of first trenches 24 may be larger than the width W1 of each of the plurality of first trenches 24.
  • the interval S2 between the plurality of second trenches 26 may be larger than the width W2 of each of the plurality of second trenches 26.
  • the width W2 of each of the plurality of second trenches 26 may be larger than the width W1 of each of the plurality of first trenches 24.
  • the interval S2 between the plurality of second trenches 26 may be larger than the interval S1 between the plurality of first trenches 24. Therefore, the pitch P2 (the sum of the width W2 and the interval S2) of the second trenches 26 may be larger than the pitch P1 (the sum of the width W1 and the interval S1) of the first trenches 24.
  • the pitch P1 of the first trenches 24 may be approximately the same as the spacing S2 of the second trenches 26.
  • the semiconductor device 10 further includes a plurality of gate electrodes 28 embedded in the plurality of first trenches 24 with an insulating layer 16 interposed therebetween.
  • the plurality of gate electrodes 28 extend in the first direction.
  • the semiconductor device 10 further includes a plurality of field plate electrodes 30 embedded in the plurality of second trenches 26 with the insulating layer 16 interposed therebetween.
  • the plurality of field plate electrodes 30 extend in the second direction.
  • Gate electrode 28 and field plate electrode 30 may be formed from conductive polysilicon, in one example. In other examples, gate electrode 28 and field plate electrode 30 may be formed from any other metallic material.
  • the plurality of gate electrodes 28 are located above the plurality of field plate electrodes 30 (closer to the upper surface 12A of the semiconductor layer 12) in the cell trench 14.
  • the plurality of gate electrodes 28 are separated from the plurality of field plate electrodes 30 by the insulating layer 16.
  • Each of the plurality of gate electrodes 28 crosses the plurality of field plate electrodes 30 by passing over the plurality of field plate electrodes 30.
  • Each of the plurality of field plate electrodes 30 intersects with the plurality of gate electrodes 28 by passing under the plurality of gate electrodes 28 .
  • one of the plurality of gate electrodes 28 intersects with one of the plurality of field plate electrodes 30 in each of the plurality of intersection regions 14A. Further, in each of the plurality of non-intersecting regions 14B, one of the plurality of gate electrodes 28 or one of the field plate electrodes 30 is arranged in the cell trench 14.
  • the semiconductor layer 12 can include a plurality of mesh regions 32 (see FIG. 2) surrounded by cell trenches 14 arranged in a mesh shape. Each of the plurality of mesh regions 32 may have a rectangular shape in plan view.
  • the semiconductor device 10 may further include a plurality of source contact plugs 34 arranged in the plurality of mesh regions 32, respectively. Details of the source contact plug 34 will be described later with reference to FIG. 3.
  • FIG. 3 is a schematic cross-sectional view of the semiconductor device 10 taken along line F3-F3 in FIG.
  • FIG. 3 shows a cross section of the first trench 24 in the XZ plane in the non-intersecting region 14B (see FIG. 2), which corresponds to a cross section of the first trench 24 along the short direction.
  • Epitaxial layer 20 includes a drift region 36 formed on semiconductor substrate 18 corresponding to a drain region, a body region 38 formed on drift region 36, and a source region 40 formed on body region 38. .
  • the drain region formed by the semiconductor substrate 18 may be an n-type region containing n-type impurities.
  • the n-type impurity concentration of the semiconductor substrate 18 may be 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • the semiconductor substrate 18 may have a thickness of 50 ⁇ m or more and 450 ⁇ m or less.
  • the drift region 36 may be an n-type region containing n-type impurities at a lower concentration than the semiconductor substrate 18 (drain region).
  • the n-type impurity concentration of the drift region 36 may be 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the drift region 36 may have a thickness of 1 ⁇ m or more and 25 ⁇ m or less.
  • Body region 38 may be a p-type region containing p-type impurities.
  • the p-type impurity concentration of the body region 38 may be 1 ⁇ 10 16 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • Body region 38 may have a thickness of 0.2 ⁇ m or more and 1.0 ⁇ m or less.
  • Source region 40 may be an n-type region containing a higher concentration of n-type impurities than drift region 36 .
  • the n-type impurity concentration of the source region 40 may be 1 ⁇ 10 19 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the source region 40 may have a thickness of 0.1 ⁇ m or more and 1 ⁇ m or less.
  • the n-type is also referred to as a first conductivity type, and the p-type is also referred to as a second conductivity type.
  • the n-type impurity may be, for example, phosphorus (P) or arsenic (As).
  • the p-type impurity may be, for example, boron (B), aluminum (Al), or the like.
  • the first trench 24 has an opening in the upper surface 12A of the semiconductor layer 12, and has a side wall 24A and a bottom wall 24B.
  • First trench 24 penetrates source region 40 and body region 38 of epitaxial layer 20 and reaches drift region 36 . Therefore, the bottom wall 24B of the first trench 24 is adjacent to the drift region 36.
  • the first trench 24 may have a depth of 1 ⁇ m or more and 10 ⁇ m or less. Note that the depth of the first trench 24 may correspond to the distance from the top surface 12A of the semiconductor layer 12 to the bottom wall 24B of the first trench 24 in the Z-axis direction.
  • the sidewall 24A of the first trench 24 may extend in the Z-axis direction (direction perpendicular to the upper surface 12A of the semiconductor layer 12) or may be inclined with respect to the Z-axis direction. In one example, the side wall 24A may be inclined with respect to the Z-axis direction so that the width of the first trench 24 becomes smaller toward the bottom wall 24B. Note that in that case, the width W1 of the first trench 24 shown in FIG. 2 may be the width of the first trench 24 at the position of the upper surface 12A of the semiconductor layer 12. Further, the bottom wall 24B of the first trench 24 does not necessarily have to be flat, and may be partially or entirely curved, for example.
  • the gate electrode 28 is buried in the first trench 24 with the insulating layer 16 interposed therebetween.
  • the gate electrode 28 is separated from the semiconductor layer 12 (epitaxial layer 20) by the insulating layer 16.
  • Gate electrode 28 may be configured to have a gate voltage applied thereto. At least a portion of the gate electrode 28 may be arranged to face the body region 38 in the second direction with the insulating layer 16 in between.
  • the gate electrode 28 may include a top surface 28A covered with the insulating layer 16 and a bottom surface 28B opposite to the top surface 28A.
  • the insulating layer 16 is embedded between the bottom surface 28B of the gate electrode 28 and the bottom wall 24B of the first trench 24, and the field plate electrode 30 (see FIG. 1) are not placed.
  • the upper surface 28A of the gate electrode 28 may be located below the upper surface 12A of the semiconductor layer 12 in the Z-axis direction. Further, the bottom surface 28B of the gate electrode 28 is located near the interface between the drift region 36 and the body region 38 in the Z-axis direction, and preferably may be located below the interface.
  • the top surface 28A and bottom surface 28B of the gate electrode 28 may be flat or curved.
  • the semiconductor device 10 may further include a source wiring 42 formed on the insulating layer 16.
  • the source wiring 42 may be configured to be applied with a reference voltage (source voltage).
  • the source wiring 42 is connected to the source contact plug 34.
  • Epitaxial layer 20 may further include a contact region 44 adjacent body region 38 .
  • Contact region 44 may be a p-type region containing p-type impurities.
  • the p-type impurity concentration of the contact region 44 is higher than that of the body region 38, and may be 1 ⁇ 10 19 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • Source contact plug 34 extends through insulating layer 16 and source region 40 so as to be in contact with contact region 44 .
  • Contact region 44 may be adjacent to the bottom of source contact plug 34 .
  • Contact region 44 is electrically connected to source wiring 42 via source contact plug 34 .
  • the insulating layer 16 includes a gate insulating portion 46 that is interposed between the gate electrode 28 and the semiconductor layer 12 (epitaxial layer 20) and covers the side wall 24A of the first trench 24.
  • the gate insulating portion 46 is a part of the insulating layer 16 between the side surface 28C of the gate electrode 28 and the side wall 24A of the first trench 24.
  • Gate electrode 28 faces semiconductor layer 12 with gate insulating section 46 in between.
  • a predetermined voltage gate voltage
  • the semiconductor device 10 can control the flow of electrons in the Z-axis direction between the n-type source region 40 and the n-type drift region 36 via this channel.
  • FIG. 4 is a schematic cross-sectional view of the semiconductor device 10 taken along line F4-F4 in FIG.
  • FIG. 4 shows a cross section of the second trench 26 in the YZ plane in the non-intersecting region 14B (see FIG. 2), which corresponds to a cross section of the second trench 26 along the short direction.
  • the second trench 26 has an opening in the upper surface 12A of the semiconductor layer 12, and has a side wall 26A and a bottom wall 26B. Second trench 26 penetrates source region 40 and body region 38 of epitaxial layer 20 and reaches drift region 36 . Therefore, the bottom wall 26B of the second trench 26 is adjacent to the drift region 36.
  • the second trench 26 may have a depth of 1 ⁇ m or more and 10 ⁇ m or less. Note that the depth of the second trench 26 may correspond to the distance from the top surface 12A of the semiconductor layer 12 to the bottom wall 26B of the second trench 26 in the Z-axis direction.
  • the sidewall 26A of the second trench 26 may extend in the Z-axis direction (direction perpendicular to the upper surface 12A of the semiconductor layer 12) or may be inclined with respect to the Z-axis direction. In one example, the side wall 26A may be inclined with respect to the Z-axis direction so that the width of the second trench 26 becomes smaller toward the bottom wall 26B. Note that in that case, the width W2 of the second trench 26 shown in FIG. 2 may be the width of the second trench 26 at the position of the upper surface 12A of the semiconductor layer 12. Further, the bottom wall 26B of the second trench 26 does not necessarily have to be flat, and may be partially or entirely curved, for example.
  • the field plate electrode 30 is embedded in the second trench 26 with the insulating layer 16 interposed therebetween.
  • Field plate electrode 30 is separated from semiconductor layer 12 (epitaxial layer 20) by insulating layer 16.
  • the field plate electrode 30 may be configured to be applied with a reference voltage (source voltage). Therefore, the field plate electrode 30 may be electrically connected to the source wiring 42.
  • Field plate electrode 30 is arranged below the interface between drift region 36 and body region 38 in the depth direction (Z-axis direction) of cell trench 14 .
  • the field plate electrode 30 may include a top surface 30A covered with the insulating layer 16 and a bottom surface 30B opposite to the top surface 30A.
  • the insulating layer 16 is embedded in the second trench 26 above the upper surface 30A of the field plate electrode 30, and the gate electrode 28 (see FIG. 1) is Not placed.
  • the top surface 30A and bottom surface 30B of the field plate electrode 30 may be flat or curved.
  • each field plate electrode 30 in the first direction is smaller than the dimension of each gate electrode 28 (see FIG. 3) in the second direction (X-axis direction in the illustrated example). good.
  • FIG. 5 is a schematic cross-sectional view of the semiconductor device 10 taken along line F5-F5 in FIG. 2.
  • FIG. 5 shows a cross section of the first trench 24 in the YZ plane, which corresponds to a cross section along the longitudinal direction of the first trench 24.
  • intersecting regions 14A and non-intersecting regions 14B included in the first trench 24 are arranged alternately in the first direction in which the first trench 24 extends (in the illustrated example, the Y-axis direction).
  • gate electrode 28 passes above field plate electrode 30.
  • the field plate electrode 30 is not arranged below the gate electrode 28.
  • FIG. 6 is a schematic cross-sectional view of the semiconductor device 10 taken along line F6-F6 in FIG.
  • FIG. 6 shows a cross section of the second trench 26 in the XZ plane, which corresponds to a cross section along the longitudinal direction of the second trench 26.
  • the intersecting regions 14A and non-intersecting regions 14B included in the second trench 26 are arranged alternately in the second direction in which the second trench 26 extends (in the illustrated example, the X-axis direction).
  • the field plate electrode 30 passes below the gate electrode 28.
  • the gate electrode 28 is not arranged above the field plate electrode 30.
  • a field plate electrode 30 is arranged below the gate electrode 28 in the cell trench 14 in the intersection region 14A. At least a portion of the bottom surface 28B of the gate electrode 28 faces the top surface 30A of the field plate electrode 30 with the insulating layer 16 in between. Note that, as shown in FIG. 6, in the intersection region 14A, the side surface 28C of the gate electrode 28 does not face the side wall 24A of the first trench 24. Therefore, no channel is formed around the gate electrode 28 in the intersection region 14A. Therefore, as the ratio of the interval S2 between the second trenches 26 to the pitch P2 of the second trenches 26 is increased, a wider channel is formed, so that the on-resistance of the semiconductor device 10 can be reduced (see FIG. 2). .
  • the non-intersecting region 14B only one of the gate electrode 28 and the field plate electrode 30 is arranged in the cell trench 14. More specifically, as shown in FIG. 5, in the non-intersecting region 14B included in the first trench 24, only the gate electrode 28 is disposed in the cell trench 14. Further, as shown in FIG. 6, in the non-intersecting region 14B included in the second trench 26, only the field plate electrode 30 is disposed in the cell trench 14. Therefore, in the non-intersecting region 14B, the gate electrode 28 and the field plate electrode 30 do not face each other in the depth direction (Z-axis direction) of the cell trench 14. As a result, the larger the ratio of the interval S1 of the first trenches 24 to the pitch P1 of the first trenches 24 is, the more the capacitance generated by the gate electrode 28 and the field plate electrode 30 can be reduced (see FIG. 2).
  • the gate electrode 28 extends in the first direction, while the field plate electrode 30 extends in the second direction intersecting the first direction. Since the gate electrode 28 and the field plate electrode 30 do not extend in the same direction but intersect with each other, the capacitance caused by the gate electrode 28 and the field plate electrode 30 can be reduced.
  • FIG. 7 is a schematic cross-sectional perspective view of an exemplary semiconductor device 100 according to a comparative example.
  • the same components as those of the semiconductor device 10 shown in FIGS. 1 to 6 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.
  • the semiconductor device 100 may be a MISFET having a trench gate structure.
  • the semiconductor device 100 includes a drain electrode 22, a semiconductor layer 12 formed on the drain electrode 22, a plurality of cell trenches 102 formed in the semiconductor layer 12, and an insulating layer 16 formed on the semiconductor layer 12. include.
  • FIG. 7 shows a cross-sectional view of the semiconductor device 100 at the position of the upper surface 12A of the semiconductor layer 12. It should be noted that, as shown in FIG. 8, the insulating layer 16 is formed not only within the cell trench 102 but also on the upper surface 12A of the semiconductor layer 12.
  • the plurality of cell trenches 102 are arranged in a stripe pattern.
  • Each of the plurality of cell trenches 102 extends in one direction (in the illustrated example, the Y-axis direction), has an opening in the upper surface 12A of the semiconductor layer 12, and has a depth in the Z-axis direction.
  • the semiconductor device 100 includes a gate electrode 104 and a field plate electrode 106 buried in each cell trench 102 with an insulating layer 16 interposed therebetween. Gate electrode 104 and field plate electrode 106 extend in the direction in which cell trench 102 extends (ie, the Y-axis direction).
  • the gate electrode 104 is located above the field plate electrode 106 (closer to the upper surface 12A of the semiconductor layer 12). Gate electrode 104 is separated from field plate electrode 106 by insulating layer 16 . Like the cell trench 102, the gate electrode 104 and the field plate electrode 106 extend in the Y-axis direction.
  • the semiconductor device 100 further includes a plurality of source contact plugs 108.
  • Each source contact plug 108 is arranged between two cell trenches 102. Like the cell trench 102, the source contact plug 108 extends in the Y-axis direction.
  • FIG. 8 is a schematic cross-sectional view of the semiconductor device 100 shown in FIG. 7.
  • FIG. 8 shows a cross section of the cell trench 102 in the XZ plane, which corresponds to a cross section along the short direction of the cell trench 102.
  • Semiconductor device 100 further includes a source wiring 42 formed on insulating layer 16.
  • Source wiring 42 is connected to source contact plug 108.
  • the cell trench 102 has a side wall 102A and a bottom wall 102B. Cell trench 102 penetrates source region 40 and body region 38 of epitaxial layer 20 and reaches drift region 36 . Therefore, the bottom wall 102B of the cell trench 102 is adjacent to the drift region 36.
  • the gate electrode 104 includes a top surface 104A covered with the insulating layer 16 and a bottom surface 104B opposite to the top surface 104A. Further, the side surface 104C of the gate electrode 104 faces the side wall 102A of the cell trench 102 with the gate insulating section 46 interposed therebetween.
  • Field plate electrode 106 includes a top surface 106A covered by insulating layer 16, and a bottom surface 106B opposite top surface 106A. Field plate electrode 106 is arranged below gate electrode 104 within cell trench 102 . More specifically, the field plate electrode 106 is arranged between the bottom surface 104B of the gate electrode 104 and the bottom wall 102B of the cell trench 102. At least a portion of the bottom surface 104B of the gate electrode 104 faces the top surface 106A of the field plate electrode 106 with the insulating layer 16 in between.
  • the gate electrode 104 and the field plate electrode 106 are surrounded by an insulating layer 16.
  • Field plate electrode 106 has a smaller width than gate electrode 104. Due to the relatively small width of field plate electrode 106, the thickness of insulating layer 16 surrounding field plate electrode 106 is relatively large.
  • the gate electrode 104 is configured so that a gate voltage is applied. Further, the field plate electrode 106 is configured to be applied with a reference voltage (source voltage). Therefore, the field plate electrode 106 can be electrically connected to the source wiring 42.
  • a reference voltage source voltage
  • the gate electrode 104 and the field plate electrode 106 extend in the same direction within the cell trench 102 while facing each other, the gate-source capacitance can become relatively large. If the gate-source capacitance is large, undesirable operations of the semiconductor device 100 such as self-turn-on may occur.
  • the gate electrode 28 extends in the first direction in the cell trench 14 arranged in a mesh shape, while the field plate electrode 30 extends in the second direction intersecting the first direction. extending in the direction. Therefore, the capacitance caused by the gate electrode 28 and the field plate electrode 30 can be reduced.
  • the cell trench 14 includes a plurality of intersection regions 14A where a plurality of first trenches 24 and a plurality of second trenches 26 intersect with each other, and a plurality of intersection regions 14A where a plurality of first trenches 24 and a plurality of second trenches 26 intersect with each other. It includes a plurality of non-intersecting regions 14B that do not intersect with each other.
  • one of the plurality of gate electrodes 28 intersects with one of the plurality of field plate electrodes 30 in plan view.
  • one of the plurality of gate electrodes 28 or one of the field plate electrodes 30 is arranged in the cell trench 14.
  • each non-intersecting region 14B only one of the gate electrode 28 and the field plate electrode 30 is disposed in the cell trench 14, so that the capacitance caused by the gate electrode 28 and the field plate electrode 30 can be reduced. can.
  • a field plate electrode 30 is arranged below the gate electrode 28 in the cell trench 14. Therefore, a depletion layer can be expanded in the semiconductor layer 12 near the intersection region 14A, and as a result, the gate-drain capacitance of the semiconductor device 10 can be reduced.
  • the semiconductor device 10 of this embodiment has the following advantages. (1) In the cell trenches 14 arranged in a mesh shape, the gate electrode 28 extends in a first direction, while the field plate electrode 30 extends in a second direction intersecting the first direction. Since the gate electrode 28 and the field plate electrode 30 do not extend in the same direction but intersect with each other, the capacitance caused by the gate electrode 28 and the field plate electrode 30 can be reduced.
  • the cell trench 14 includes a plurality of intersection regions 14A where a plurality of first trenches 24 and a plurality of second trenches 26 intersect with each other, and a plurality of intersection regions 14A where a plurality of first trenches 24 and a plurality of second trenches 26 intersect with each other. It includes a plurality of non-intersecting regions 14B.
  • one of the plurality of gate electrodes 28 intersects with one of the plurality of field plate electrodes 30 in plan view.
  • one of the plurality of gate electrodes 28 or one of the field plate electrodes 30 is arranged in the cell trench 14. Therefore, both the gate electrode 28 and the field plate electrode 30 can be arranged in the intersection region 14A, and only one of the gate electrode 28 and the field plate electrode 30 can be arranged in the non-intersection region 14B. Can be done.
  • one of the plurality of field plate electrodes 30 is arranged below one of the plurality of gate electrodes 28 in the cell trench 14. Thereby, a depletion layer can be expanded in the semiconductor layer 12 near the intersection region 14A, and as a result, the gate-drain capacitance of the semiconductor device 10 can be reduced.
  • the plurality of first trenches 24 are arranged parallel to each other at constant intervals S1, and the interval S1 at which the plurality of first trenches 24 are arranged is larger than the width W1 of each of the plurality of first trenches 24. It's okay. Thereby, the ratio of the interval S1 between the first trenches 24 to the pitch P1 of the first trenches 24 can be increased, so that the capacitance caused by the gate electrode 28 and the field plate electrode 30 can be further reduced.
  • the plurality of second trenches 26 are arranged parallel to each other at constant intervals S2, and the interval S2 at which the plurality of second trenches 26 are arranged is larger than the width W2 of each of the plurality of second trenches 26. It's okay. As a result, the ratio of the interval S2 between the second trenches 26 to the pitch P2 of the second trenches 26 can be increased, so that a wider channel is formed, and as a result, the on-resistance of the semiconductor device 10 can be reduced. Can be done.
  • the width W2 of each of the plurality of second trenches 26 may be larger than the width W1 of each of the plurality of first trenches 24. As the width W2 of the second trench 26 is increased, the insulation layer 16 surrounding the field plate electrode 30 can be made thicker, so that the breakdown voltage of the semiconductor device 10 can be improved.
  • each field plate electrode 30 in the first direction may be smaller than the dimension of each gate electrode 28 in the second direction.
  • FIG. 9 is a schematic plan view of an exemplary semiconductor device 200 for explaining a modification of the cell trench.
  • the same components as those of the semiconductor device 10 shown in FIGS. 1 to 6 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.
  • the semiconductor device 200 includes a cell trench 202 formed in the semiconductor layer 12.
  • the cell trench 202 includes a plurality of first trenches 24 extending in a first direction in a plan view, and a plurality of second trenches 26 extending in a second direction intersecting the first direction in a plan view.
  • Cell trench 202 differs from exemplary cell trench 14 shown in FIGS. 1 and 2 in that the first direction in which first trench 24 extends does not coincide with the Y-axis direction.
  • the angle between the first direction and the second direction is not 90 degrees. That is, the first direction may be inclined with respect to the direction orthogonal to the second direction.
  • each of the plurality of first trenches 24 by tilting each of the plurality of first trenches 24 with respect to the Y-axis direction, they can be formed within a predetermined range of the semiconductor layer 12, compared to the example of FIG.
  • the length of the first trench 24 can be increased. Since the gate electrode 28 is disposed in the first trench 24, the gate electrode 28 can be made longer by making each of the plurality of first trenches 24 inclined with respect to the Y-axis direction. As a result, the on-resistance of the semiconductor device 200 can be reduced.
  • the first direction in which the first trenches 24 extend and the direction in which the second trenches 26 extend are The angle between the two directions is preferably within the range of 90 degrees ⁇ 10 degrees.
  • the depth of the cell trench 14 is shown to be constant in both the crossing region 14A and the non-crossing region 14B.
  • the depth of the cell trench 14 does not necessarily have to be constant.
  • the depth of the cell trench 14 in the crossing region 14A may be greater than the depth of the cell trench 14 in the non-crossing region 14B.
  • the depth of the cell trench 14 in the crossing region 14A may be smaller than the depth of the cell trench 14 in the non-crossing region 14B.
  • the depth of the first trench 24 may be the same as or different from the depth of the second trench 26.
  • the depth of the second trench 26 may be greater than the depth of the first trench 24.
  • the depth of second trench 26 may be less than the depth of first trench 24.
  • the source contact plug 34 extends in the Y-axis direction in plan view, but may be arranged so as to extend in the first direction parallel to the first trench 24.
  • a structure in which the conductivity type of each region in the semiconductor layer 12 is reversed may be adopted. That is, the p-type region may be made into an n-type region, and the n-type region may be made into a p-type region.
  • An additional wiring structure may be formed on the layer including the source wiring 42.
  • the term “on” includes the meanings of “on” and “above” unless the context clearly indicates otherwise.
  • the phrase “the first layer is formed on the second layer” refers to the fact that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other embodiments. It is contemplated that the first layer may be placed above the second layer without contacting the second layer. That is, the term “on” does not exclude structures in which other layers are formed between the first layer and the second layer.
  • the Z-axis direction used in the present disclosure does not necessarily need to be a vertical direction, nor does it need to completely coincide with the vertical direction.
  • the X-axis direction may be a vertical direction
  • the Y-axis direction may be a vertical direction.
  • a semiconductor layer (12) Cell trenches (14) formed in the semiconductor layer (12) and arranged in a mesh pattern include a plurality of first trenches (24) extending in a first direction in plan view; a plurality of second trenches (26) extending in a second direction intersecting the direction, the plurality of first trenches (24) and the plurality of second trenches (26) intersect with each other and communicate with each other.
  • a semiconductor device comprising: a plurality of field plate electrodes (30) embedded in the plurality of second trenches (26) via the insulating layer (16) and extending in the second direction.
  • the cell trench (14) includes a plurality of intersection regions (14A) where the plurality of first trenches (24) and the plurality of second trenches (26) intersect with each other, and the plurality of first trenches (24). and a plurality of non-intersecting regions (14B) in which the plurality of second trenches (26) do not intersect with each other, In each of the plurality of crossing regions (14A), one of the plurality of gate electrodes (28) intersects with one of the plurality of field plate electrodes (30), In each of the plurality of non-intersecting regions (14B), one of the plurality of gate electrodes (28) or one of the field plate electrodes (30) is located in the cell trench (14).
  • the semiconductor device according to supplementary note 1, which is arranged.
  • one of the plurality of field plate electrodes (30) is connected to one of the plurality of gate electrodes (28) in the cell trench (14).
  • one of the plurality of field plate electrodes (30) is separated from one of the plurality of gate electrodes (28) by the insulating layer (16).
  • the intersecting regions (14A) and the non-intersecting regions (14B) included in each of the plurality of first trenches (24) are arranged alternately in the first direction
  • the intersecting regions (14A) and the non-intersecting regions (14B) included in each of the plurality of second trenches (26) are semiconductors according to appendix 2 or 3, wherein the intersecting regions (14A) and the non-intersecting regions (14B) are arranged alternately in the second direction.
  • the semiconductor layer (12) includes a first conductivity type drift region (36), a second conductivity type body region (38) formed on the drift region (36), and a second conductivity type body region (38) formed on the body region (38).
  • the source region (40) of the first conductivity type formed in At least a portion of each gate electrode (28) is arranged to face the body region (38) in the second direction with the insulating layer (16) interposed therebetween;
  • Each field plate electrode (30) is arranged below the interface between the drift region (36) and the body region (38) in the depth direction of the cell trench (14).
  • the semiconductor layer (12) includes a plurality of mesh regions (32) surrounded by the cell trenches (14) arranged in a mesh shape, The semiconductor device according to any one of appendices 1 to 6, wherein the plurality of source contact plugs (34) are respectively arranged in the plurality of mesh regions (32).
  • Appendix 10 The semiconductor device according to any one of appendices 1 to 9, wherein the angle between the first direction and the second direction is within a range of 90 degrees ⁇ 10 degrees.
  • the plurality of first trenches (24) are arranged parallel to each other at regular intervals (S1), Any one of Supplementary Notes 1 to 10, wherein the interval (S1) in which the plurality of first trenches (24) are arranged is larger than the width (W1) of each of the plurality of first trenches (24).
  • the semiconductor device described in is described in .
  • the width (W2) of each of the plurality of second trenches (26) is greater than the width (W1) of each of the plurality of first trenches (24), according to any one of Supplementary notes 1 to 12.

Abstract

This semiconductor device (10) is provided with: a semiconductor layer (12); a cell trench (14) which is formed in the shape of a mesh in the semiconductor layer (12), while comprising a plurality of first trenches (24) that extend in a first direction when viewed in plan and a plurality of second trenches (26) that extend in a second direction that intersects with the first direction when viewed in plan so that the plurality of first trenches (24) and the plurality of second trenches (26) intersect with and in communication with each other; an insulating layer (16) which is formed on the semiconductor layer (12); a plurality of gate electrodes (28) which are respectively buried in the plurality of first trenches (24) by the intermediary of the insulating layer (16), while extending in the first direction; and a plurality of field plate electrodes (30) which are respectively buried in the plurality of second trenches (26) by the intermediary of the insulating layer (16), while extending in the second direction.

Description

半導体装置semiconductor equipment
　本開示は、半導体装置に関する。 The present disclosure relates to a semiconductor device.
　特許文献１は、ストライプ状に形成された複数のトレンチゲート構造を有する半導体装置を開示している。各トレンチゲート構造は、ゲートトレンチと、ゲートトレンチの深さ方向に分離して埋め込まれた２つの電極を含んでいる。 Patent Document 1 discloses a semiconductor device having a plurality of trench gate structures formed in a stripe shape. Each trench gate structure includes a gate trench and two electrodes buried separately in the depth direction of the gate trench.
特開２０２１－１２５６４９号公報JP 2021-125649 Publication
　ゲートトレンチ内にゲート電極およびフィールドプレート電極が分離して埋め込まれる場合、ゲート電極とフィールドプレート電極とは、互いに対向しつつ、ゲートトレンチ内に延在している。ゲート電極とフィールドプレート電極とにより生じる容量が比較的大きい場合、セルフターンオンなどの半導体装置の望ましくない動作が引き起こされ得る。 When the gate electrode and the field plate electrode are buried separately in the gate trench, the gate electrode and the field plate electrode extend into the gate trench while facing each other. If the capacitance created by the gate electrode and the field plate electrode is relatively large, undesirable behavior of the semiconductor device, such as self-turn-on, can be caused.
　本開示の一態様による半導体装置は、半導体層と、前記半導体層に形成されるとともにメッシュ状に配置されたセルトレンチであって、平面視で第１方向に延びる複数の第１トレンチと、平面視で前記第１方向と交差する第２方向に延びる複数の第２トレンチとを含み、前記複数の第１トレンチと前記複数の第２トレンチとは互いに交差し、かつ連通している、セルトレンチと、前記半導体層上に形成された絶縁層と、前記複数の第１トレンチ内に前記絶縁層を介してそれぞれ埋め込まれるとともに、前記第１方向に延びる複数のゲート電極と、前記複数の第２トレンチ内に前記絶縁層を介してそれぞれ埋め込まれるとともに、前記第２方向に延びる複数のフィールドプレート電極とを備えている。 A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer, a plurality of first trenches formed in the semiconductor layer and arranged in a mesh shape, and extending in a first direction in a plan view; a plurality of second trenches extending in a second direction intersecting the first direction when viewed, the plurality of first trenches and the plurality of second trenches intersecting and communicating with each other; an insulating layer formed on the semiconductor layer; a plurality of gate electrodes each embedded in the plurality of first trenches via the insulating layer and extending in the first direction; and a plurality of second trenches. A plurality of field plate electrodes are respectively embedded in the trenches via the insulating layer and extend in the second direction.
　本開示の半導体装置によれば、ゲート電極とフィールドプレート電極とにより生じる容量を低減することができる。 According to the semiconductor device of the present disclosure, the capacitance caused by the gate electrode and the field plate electrode can be reduced.
図１は、一実施形態に係る例示的な半導体装置の概略断面斜視図である。FIG. 1 is a schematic cross-sectional perspective view of an exemplary semiconductor device according to one embodiment. 図２は、図１に示す半導体装置の概略平面図である。FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. 1. 図３は、図２のＦ３－Ｆ３線に沿った半導体装置の概略断面図である。FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. 図４は、図２のＦ４－Ｆ４線に沿った半導体装置の概略断面図である。FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG. 図５は、図２のＦ５－Ｆ５線に沿った半導体装置の概略断面図である。FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. 図６は、図２のＦ６－Ｆ６線に沿った半導体装置の概略断面図である。FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 in FIG. 図７は、比較例に係る例示的な半導体装置の概略断面斜視図である。FIG. 7 is a schematic cross-sectional perspective view of an exemplary semiconductor device according to a comparative example. 図８は、図７に示す半導体装置の概略断面図である。FIG. 8 is a schematic cross-sectional view of the semiconductor device shown in FIG. 7. 図９は、変更例に係る半導体装置の概略平面図である。FIG. 9 is a schematic plan view of a semiconductor device according to a modification example.
　以下、添付図面を参照して本開示の半導体装置のいくつかの実施形態を説明する。なお、説明を簡単かつ明確にするために、図面に示される構成要素は必ずしも一定の縮尺で描かれていない。また、理解を容易にするために、断面図では、ハッチング線が省略されている場合がある。添付の図面は、本開示の実施形態を例示するに過ぎず、本開示を制限するものとみなされるべきではない。 Hereinafter, some embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. It should be noted that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Further, in order to facilitate understanding, hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the disclosure and should not be considered as limiting the disclosure.
　以下の詳細な記載は、本開示の例示的な実施形態を具体化する装置、システム、および方法を含む。この詳細な記載は本来説明のためのものに過ぎず、本開示の実施形態またはこのような実施形態の適用および使用を限定することを意図しない。 The following detailed description includes devices, systems, and methods that embody example embodiments of the present disclosure. This detailed description is illustrative in nature and is not intended to limit the embodiments of the disclosure or the application and uses of such embodiments.
　図１は、一実施形態に係る例示的な半導体装置１０の概略断面斜視図である。図２は、半導体装置１０の概略平面図である。半導体装置１０は、例えばトレンチゲート構造を有するＭＩＳＦＥＴ（Metal-Insulator-Semiconductor Field Effect Transistor）であってよい。半導体装置１０は、半導体層１２と、半導体層１２に形成されたセルトレンチ１４と、半導体層１２上に形成された絶縁層１６とを含む。図１に示すように、半導体層１２は、半導体基板１８と、エピタキシャル層２０とを含んでいてよく、セルトレンチ１４は、エピタキシャル層２０に形成されていてよい。本実施形態において、半導体基板１８は、シリコン（Ｓｉ）基板であってよい。また、エピタキシャル層２０は、Ｓｉエピタキシャル層であってよい。半導体層１２の上面１２Ａは、エピタキシャル層２０に含まれ、一方、半導体層１２の底面１２Ｂは、半導体基板１８に含まれていてよい。絶縁層１６は、酸化シリコン（ＳｉＯ２）層および窒化シリコン（ＳｉＮ）層のうちの少なくとも１つを含んでいてよい。 FIG. 1 is a schematic cross-sectional perspective view of an exemplary semiconductor device 10 according to one embodiment. FIG. 2 is a schematic plan view of the semiconductor device 10. The semiconductor device 10 may be, for example, a MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) having a trench gate structure. The semiconductor device 10 includes a semiconductor layer 12 , a cell trench 14 formed in the semiconductor layer 12 , and an insulating layer 16 formed on the semiconductor layer 12 . As shown in FIG. 1, the semiconductor layer 12 may include a semiconductor substrate 18 and an epitaxial layer 20, and the cell trench 14 may be formed in the epitaxial layer 20. In this embodiment, the semiconductor substrate 18 may be a silicon (Si) substrate. Further, the epitaxial layer 20 may be a Si epitaxial layer. The top surface 12A of the semiconductor layer 12 may be included in the epitaxial layer 20, while the bottom surface 12B of the semiconductor layer 12 may be included in the semiconductor substrate 18. Insulating layer 16 may include at least one of a silicon oxide (SiO 2 ) layer and a silicon nitride (SiN) layer.
　なお、理解を容易にするために、図１および図２においては、半導体層１２の上面１２Ａの位置における半導体装置１０の断面図および平面図がそれぞれ示されている（図３のＦ１－Ｆ１線参照）。図３に示すように、絶縁層１６は、セルトレンチ１４内だけでなく、半導体層１２の上面１２Ａ上にも形成されている点に留意されたい。 1 and 2, a cross-sectional view and a plan view of the semiconductor device 10 at the position of the upper surface 12A of the semiconductor layer 12 are shown, respectively, for ease of understanding (line F1-F1 in FIG. 3). reference). It should be noted that, as shown in FIG. 3, the insulating layer 16 is formed not only within the cell trench 14 but also on the upper surface 12A of the semiconductor layer 12.
　半導体装置１０は、半導体層１２の底面１２Ｂに形成されたドレイン電極２２をさらに含んでいてよい。ドレイン電極２２は、チタン（Ｔｉ）、ニッケル（Ｎｉ）、金（Ａｕ）、銀（Ａｇ）、銅（Ｃｕ）、Ａｌ、Ｃｕ合金、およびＡｌ合金のうちの少なくとも１つから形成されていてよい。 The semiconductor device 10 may further include a drain electrode 22 formed on the bottom surface 12B of the semiconductor layer 12. Drain electrode 22 may be formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, Cu alloy, and Al alloy. .
　（セルトレンチの詳細）
　図１および図２に示すように、セルトレンチ１４は、平面視で第１方向に延びる複数の第１トレンチ２４と、平面視で第１方向と交差する第２方向に延びる複数の第２トレンチ２６とを含む。なお、図１および図２に示される互いに直交するＸＹＺ軸のＺ軸方向は、半導体層１２の面と直交する方向である。本明細書において使用される「平面視」という用語は、明示的に別段の記載がない限り、Ｚ軸方向に沿って上方から半導体装置１０を視ることをいう。第１方向は、第１トレンチ２４の長手方向であり、第２方向は、第２トレンチ２６の長手方向である。図１および図２に示す例では、第１方向はＹ軸方向であり、第２方向はＸ軸方向であってよい。したがって、図示の例では、第１方向と第２方向とのなす角度は９０度である。なお、図９を参照して後述するように、第１方向および第２方向は、必ずしもＹ軸方向およびＸ軸方向にそれぞれ一致している必要はない。セルトレンチ１４は、半導体層１２の上面１２Ａに開口を有するとともに、Ｚ軸方向に深さを有している。複数の第１トレンチ２４と複数の第２トレンチ２６とは互いに交差し、かつ連通している。これにより、セルトレンチ１４は、メッシュ状に配置されている。 (Details of cell trench)
As shown in FIGS. 1 and 2, the cell trench 14 includes a plurality of first trenches 24 extending in a first direction in plan view and a plurality of second trenches extending in a second direction intersecting the first direction in plan view. 26. Note that the Z-axis direction of the mutually orthogonal XYZ axes shown in FIGS. 1 and 2 is a direction that is orthogonal to the surface of the semiconductor layer 12. The term "planar view" used in this specification refers to viewing the semiconductor device 10 from above along the Z-axis direction, unless explicitly stated otherwise. The first direction is the longitudinal direction of the first trench 24, and the second direction is the longitudinal direction of the second trench 26. In the example shown in FIGS. 1 and 2, the first direction may be the Y-axis direction, and the second direction may be the X-axis direction. Therefore, in the illustrated example, the angle between the first direction and the second direction is 90 degrees. Note that, as will be described later with reference to FIG. 9, the first direction and the second direction do not necessarily have to correspond to the Y-axis direction and the X-axis direction, respectively. The cell trench 14 has an opening in the upper surface 12A of the semiconductor layer 12 and has a depth in the Z-axis direction. The plurality of first trenches 24 and the plurality of second trenches 26 intersect and communicate with each other. Thereby, the cell trenches 14 are arranged in a mesh shape.
　図２に示すように、セルトレンチ１４は、複数の第１トレンチ２４と複数の第２トレンチ２６とが互いに交差する複数の交差領域１４Ａと、複数の第１トレンチ２４と複数の第２トレンチ２６とが互いに交差していない複数の非交差領域１４Ｂとを含んでいる。複数の第１トレンチ２４は、ストライプ状に配置されていてよい。一例では、複数の第１トレンチ２４の各々は、幅Ｗ１を有している。第１トレンチ２４の幅Ｗ１は、平面視における第１トレンチ２４の短手方向（すなわち、第１方向と直交する方向）の寸法に相当する。複数の第１トレンチ２４は、一定の間隔Ｓ１で互いに平行に配置することができる。同様に、複数の第２トレンチ２６は、ストライプ状に配置されていてよい。一例では、複数の第２トレンチ２６の各々は、幅Ｗ２を有している。第２トレンチ２６の幅Ｗ２は、平面視における第２トレンチ２６の短手方向（すなわち、第２方向と直交する方向）の寸法に相当する。複数の第２トレンチ２６は、一定の間隔Ｓ２で互いに平行に配置することができる。 As shown in FIG. 2, the cell trench 14 includes a plurality of intersection regions 14A where a plurality of first trenches 24 and a plurality of second trenches 26 intersect with each other, and a plurality of first trenches 24 and a plurality of second trenches 26. and a plurality of non-intersecting regions 14B that do not intersect with each other. The plurality of first trenches 24 may be arranged in stripes. In one example, each of the plurality of first trenches 24 has a width W1. The width W1 of the first trench 24 corresponds to the dimension of the first trench 24 in the lateral direction (that is, the direction perpendicular to the first direction) in plan view. The plurality of first trenches 24 can be arranged parallel to each other at a constant interval S1. Similarly, the plurality of second trenches 26 may be arranged in a stripe pattern. In one example, each of the plurality of second trenches 26 has a width W2. The width W2 of the second trench 26 corresponds to the dimension of the second trench 26 in the lateral direction (that is, the direction orthogonal to the second direction) in plan view. The plurality of second trenches 26 can be arranged parallel to each other at constant intervals S2.
　一例では、複数の第１トレンチ２４が配置される間隔Ｓ１は、複数の第１トレンチ２４の各々の幅Ｗ１よりも大きくてよい。また、一例では、複数の第２トレンチ２６が配置される間隔Ｓ２は、複数の第２トレンチ２６の各々の幅Ｗ２よりも大きくてよい。 In one example, the interval S1 between the plurality of first trenches 24 may be larger than the width W1 of each of the plurality of first trenches 24. Further, in one example, the interval S2 between the plurality of second trenches 26 may be larger than the width W2 of each of the plurality of second trenches 26.
　一例では、複数の第２トレンチ２６の各々の幅Ｗ２は、複数の第１トレンチ２４の各々の幅Ｗ１よりも大きくてよい。また、一例では、複数の第２トレンチ２６が配置される間隔Ｓ２は、複数の第１トレンチ２４が配置される間隔Ｓ１よりも大きくてよい。したがって、第２トレンチ２６のピッチＰ２（幅Ｗ２と間隔Ｓ２との合計）は、第１トレンチ２４のピッチＰ１（幅Ｗ１と間隔Ｓ１との合計）よりも大きくてよい。一例では、第１トレンチ２４のピッチＰ１は、第２トレンチ２６の間隔Ｓ２と同程度であってよい。 In one example, the width W2 of each of the plurality of second trenches 26 may be larger than the width W1 of each of the plurality of first trenches 24. Further, in one example, the interval S2 between the plurality of second trenches 26 may be larger than the interval S1 between the plurality of first trenches 24. Therefore, the pitch P2 (the sum of the width W2 and the interval S2) of the second trenches 26 may be larger than the pitch P1 (the sum of the width W1 and the interval S1) of the first trenches 24. In one example, the pitch P1 of the first trenches 24 may be approximately the same as the spacing S2 of the second trenches 26.
　図１および図２に示すように、半導体装置１０は、複数の第１トレンチ２４内に絶縁層１６を介してそれぞれ埋め込まれた複数のゲート電極２８をさらに含む。複数のゲート電極２８は、第１方向に延びている。また、半導体装置１０は、複数の第２トレンチ２６内に絶縁層１６を介してそれぞれ埋め込まれた複数のフィールドプレート電極３０をさらに含む。複数のフィールドプレート電極３０は、第２方向に延びている。ゲート電極２８およびフィールドプレート電極３０は、一例では、導電性のポリシリコンから形成されていてよい。別の例では、ゲート電極２８およびフィールドプレート電極３０は、他の任意の金属材料から形成されていてもよい。 As shown in FIGS. 1 and 2, the semiconductor device 10 further includes a plurality of gate electrodes 28 embedded in the plurality of first trenches 24 with an insulating layer 16 interposed therebetween. The plurality of gate electrodes 28 extend in the first direction. Further, the semiconductor device 10 further includes a plurality of field plate electrodes 30 embedded in the plurality of second trenches 26 with the insulating layer 16 interposed therebetween. The plurality of field plate electrodes 30 extend in the second direction. Gate electrode 28 and field plate electrode 30 may be formed from conductive polysilicon, in one example. In other examples, gate electrode 28 and field plate electrode 30 may be formed from any other metallic material.
　複数のゲート電極２８は、セルトレンチ１４内において、複数のフィールドプレート電極３０よりも上方（半導体層１２の上面１２Ａ寄り）に位置している。複数のゲート電極２８は、絶縁層１６によって複数のフィールドプレート電極３０から離隔されている。複数のゲート電極２８の各々は、複数のフィールドプレート電極３０の上方を通ることにより、複数のフィールドプレート電極３０と交差している。複数のフィールドプレート電極３０の各々は、複数のゲート電極２８の下方を通ることにより、複数のゲート電極２８と交差している。 The plurality of gate electrodes 28 are located above the plurality of field plate electrodes 30 (closer to the upper surface 12A of the semiconductor layer 12) in the cell trench 14. The plurality of gate electrodes 28 are separated from the plurality of field plate electrodes 30 by the insulating layer 16. Each of the plurality of gate electrodes 28 crosses the plurality of field plate electrodes 30 by passing over the plurality of field plate electrodes 30. Each of the plurality of field plate electrodes 30 intersects with the plurality of gate electrodes 28 by passing under the plurality of gate electrodes 28 .
　図２に示すように、複数の交差領域１４Ａの各々において、複数のゲート電極２８のうちの１つが、複数のフィールドプレート電極３０のうちの１つと交差している。また、複数の非交差領域１４Ｂの各々において、セルトレンチ１４内には、複数のゲート電極２８のうちの１つ、またはフィールドプレート電極３０のうちの１つが配置されている。 As shown in FIG. 2, one of the plurality of gate electrodes 28 intersects with one of the plurality of field plate electrodes 30 in each of the plurality of intersection regions 14A. Further, in each of the plurality of non-intersecting regions 14B, one of the plurality of gate electrodes 28 or one of the field plate electrodes 30 is arranged in the cell trench 14.
　半導体層１２は、メッシュ状に配置されたセルトレンチ１４によって囲まれた複数のメッシュ領域３２（図２参照）を含むことができる。複数のメッシュ領域３２の各々は、平面視で矩形状であってよい。半導体装置１０は、複数のメッシュ領域３２にそれぞれ配置された複数のソースコンタクトプラグ３４をさらに含んでいてよい。ソースコンタクトプラグ３４の詳細は、図３を参照して後述する。 The semiconductor layer 12 can include a plurality of mesh regions 32 (see FIG. 2) surrounded by cell trenches 14 arranged in a mesh shape. Each of the plurality of mesh regions 32 may have a rectangular shape in plan view. The semiconductor device 10 may further include a plurality of source contact plugs 34 arranged in the plurality of mesh regions 32, respectively. Details of the source contact plug 34 will be described later with reference to FIG. 3.
　（半導体装置の断面構造）
　図３は、図２のＦ３－Ｆ３線に沿った半導体装置１０の概略断面図である。図３では、非交差領域１４Ｂ（図２参照）における第１トレンチ２４のＸＺ平面の断面が示されており、これは、第１トレンチ２４の短手方向に沿った断面に相当する。 (Cross-sectional structure of semiconductor device)
FIG. 3 is a schematic cross-sectional view of the semiconductor device 10 taken along line F3-F3 in FIG. FIG. 3 shows a cross section of the first trench 24 in the XZ plane in the non-intersecting region 14B (see FIG. 2), which corresponds to a cross section of the first trench 24 along the short direction.
　エピタキシャル層２０は、ドレイン領域に相当する半導体基板１８上に形成されたドリフト領域３６と、ドリフト領域３６上に形成されたボディ領域３８と、ボディ領域３８上に形成されたソース領域４０とを含む。 Epitaxial layer 20 includes a drift region 36 formed on semiconductor substrate 18 corresponding to a drain region, a body region 38 formed on drift region 36, and a source region 40 formed on body region 38. .
　半導体基板１８により形成されるドレイン領域は、ｎ型不純物を含むｎ型領域であってよい。半導体基板１８のｎ型不純物濃度は、１×１０１８ｃｍ－３以上１×１０２０ｃｍ－３以下であってよい。半導体基板１８は、５０μｍ以上４５０μｍ以下の厚さを有していてよい。 The drain region formed by the semiconductor substrate 18 may be an n-type region containing n-type impurities. The n-type impurity concentration of the semiconductor substrate 18 may be 1×10 18 cm −3 or more and 1×10 20 cm −3 or less. The semiconductor substrate 18 may have a thickness of 50 μm or more and 450 μm or less.
　ドリフト領域３６は、半導体基板１８（ドレイン領域）よりも低い濃度のｎ型不純物を含むｎ型領域であってよい。ドリフト領域３６のｎ型不純物濃度は、１×１０１５ｃｍ－３以上１×１０１８ｃｍ－３以下であってよい。ドリフト領域３６は、１μｍ以上２５μｍ以下の厚さを有していてよい。 The drift region 36 may be an n-type region containing n-type impurities at a lower concentration than the semiconductor substrate 18 (drain region). The n-type impurity concentration of the drift region 36 may be 1×10 15 cm −3 or more and 1×10 18 cm −3 or less. The drift region 36 may have a thickness of 1 μm or more and 25 μm or less.
　ボディ領域３８は、ｐ型不純物を含むｐ型領域であってよい。ボディ領域３８のｐ型不純物濃度は、１×１０１６ｃｍ－３以上１×１０１８ｃｍ－３以下であってよい。ボディ領域３８は、０．２μｍ以上１．０μｍ以下の厚さを有していてよい。 Body region 38 may be a p-type region containing p-type impurities. The p-type impurity concentration of the body region 38 may be 1×10 16 cm −3 or more and 1×10 18 cm −3 or less. Body region 38 may have a thickness of 0.2 μm or more and 1.0 μm or less.
　ソース領域４０は、ドリフト領域３６よりも高い濃度のｎ型不純物を含むｎ型領域であってよい。ソース領域４０のｎ型不純物濃度は、１×１０１９ｃｍ－３以上１×１０２１ｃｍ－３以下であってよい。ソース領域４０は、０．１μｍ以上１μｍ以下の厚さを有していてよい。 Source region 40 may be an n-type region containing a higher concentration of n-type impurities than drift region 36 . The n-type impurity concentration of the source region 40 may be 1×10 19 cm −3 or more and 1×10 21 cm −3 or less. The source region 40 may have a thickness of 0.1 μm or more and 1 μm or less.
　なお、本開示において、ｎ型を第１導電型、およびｐ型を第２導電型ともいう。ｎ型不純物は、例えば、リン（Ｐ）、ヒ素（Ａｓ）などであってよい。また、ｐ型不純物は、例えば、ホウ素（Ｂ）、アルミニウム（Ａｌ）などであってよい。 Note that in this disclosure, the n-type is also referred to as a first conductivity type, and the p-type is also referred to as a second conductivity type. The n-type impurity may be, for example, phosphorus (P) or arsenic (As). Furthermore, the p-type impurity may be, for example, boron (B), aluminum (Al), or the like.
　第１トレンチ２４は、半導体層１２の上面１２Ａに開口を有するとともに、側壁２４Ａおよび底壁２４Ｂを有している。第１トレンチ２４は、エピタキシャル層２０のソース領域４０およびボディ領域３８を貫通してドリフト領域３６に達している。したがって、第１トレンチ２４の底壁２４Ｂは、ドリフト領域３６に隣接している。第１トレンチ２４は、１μｍ以上１０μｍ以下の深さを有していてよい。なお、第１トレンチ２４の深さは、半導体層１２の上面１２Ａから第１トレンチ２４の底壁２４ＢまでのＺ軸方向における距離に相当し得る。 The first trench 24 has an opening in the upper surface 12A of the semiconductor layer 12, and has a side wall 24A and a bottom wall 24B. First trench 24 penetrates source region 40 and body region 38 of epitaxial layer 20 and reaches drift region 36 . Therefore, the bottom wall 24B of the first trench 24 is adjacent to the drift region 36. The first trench 24 may have a depth of 1 μm or more and 10 μm or less. Note that the depth of the first trench 24 may correspond to the distance from the top surface 12A of the semiconductor layer 12 to the bottom wall 24B of the first trench 24 in the Z-axis direction.
　第１トレンチ２４の側壁２４Ａは、Ｚ軸方向（半導体層１２の上面１２Ａに対して垂直な方向）に延びていてもよいし、Ｚ軸方向に対して傾斜していてもよい。一例では、側壁２４Ａは、第１トレンチ２４の幅が底壁２４Ｂに向かって小さくなるようにＺ軸方向に対して傾斜していてもよい。なお、その場合、図２に示す第１トレンチ２４の幅Ｗ１は、半導体層１２の上面１２Ａの位置における第１トレンチ２４の幅であり得る。また、第１トレンチ２４の底壁２４Ｂは、必ずしも平坦でなくてもよく、例えば、その一部または全体が湾曲していてもよい。 The sidewall 24A of the first trench 24 may extend in the Z-axis direction (direction perpendicular to the upper surface 12A of the semiconductor layer 12) or may be inclined with respect to the Z-axis direction. In one example, the side wall 24A may be inclined with respect to the Z-axis direction so that the width of the first trench 24 becomes smaller toward the bottom wall 24B. Note that in that case, the width W1 of the first trench 24 shown in FIG. 2 may be the width of the first trench 24 at the position of the upper surface 12A of the semiconductor layer 12. Further, the bottom wall 24B of the first trench 24 does not necessarily have to be flat, and may be partially or entirely curved, for example.
　ゲート電極２８は、第１トレンチ２４内に絶縁層１６を介して埋め込まれている。ゲート電極２８は、絶縁層１６によって半導体層１２（エピタキシャル層２０）から離隔されている。ゲート電極２８は、ゲート電圧が印加されるように構成され得る。ゲート電極２８の少なくとも一部は、絶縁層１６を介してボディ領域３８と第２方向に対向するように配置されていてよい。 The gate electrode 28 is buried in the first trench 24 with the insulating layer 16 interposed therebetween. The gate electrode 28 is separated from the semiconductor layer 12 (epitaxial layer 20) by the insulating layer 16. Gate electrode 28 may be configured to have a gate voltage applied thereto. At least a portion of the gate electrode 28 may be arranged to face the body region 38 in the second direction with the insulating layer 16 in between.
　ゲート電極２８は、絶縁層１６に覆われた上面２８Ａ、および上面２８Ａと反対の底面２８Ｂを含んでいてよい。第１トレンチ２４に含まれる非交差領域１４Ｂにおいては、ゲート電極２８の底面２８Ｂと、第１トレンチ２４の底壁２４Ｂとの間には絶縁層１６が埋め込まれており、フィールドプレート電極３０（図１参照）は配置されていない。 The gate electrode 28 may include a top surface 28A covered with the insulating layer 16 and a bottom surface 28B opposite to the top surface 28A. In the non-intersecting region 14B included in the first trench 24, the insulating layer 16 is embedded between the bottom surface 28B of the gate electrode 28 and the bottom wall 24B of the first trench 24, and the field plate electrode 30 (see FIG. 1) are not placed.
　ゲート電極２８の上面２８Ａは、Ｚ軸方向において、半導体層１２の上面１２Ａよりも下方に位置していてよい。また、ゲート電極２８の底面２８Ｂは、Ｚ軸方向において、ドリフト領域３６とボディ領域３８との界面との近くに位置しており、好ましくは、当該界面よりも下方にあってよい。ゲート電極２８の上面２８Ａおよび底面２８Ｂは、平坦であってもよいし、湾曲していてもよい。 The upper surface 28A of the gate electrode 28 may be located below the upper surface 12A of the semiconductor layer 12 in the Z-axis direction. Further, the bottom surface 28B of the gate electrode 28 is located near the interface between the drift region 36 and the body region 38 in the Z-axis direction, and preferably may be located below the interface. The top surface 28A and bottom surface 28B of the gate electrode 28 may be flat or curved.
　半導体装置１０は、絶縁層１６上に形成されたソース配線４２をさらに含んでいてよい。ソース配線４２は、基準電圧（ソース電圧）が印加されるように構成され得る。ソース配線４２は、ソースコンタクトプラグ３４に接続されている。 The semiconductor device 10 may further include a source wiring 42 formed on the insulating layer 16. The source wiring 42 may be configured to be applied with a reference voltage (source voltage). The source wiring 42 is connected to the source contact plug 34.
　エピタキシャル層２０は、ボディ領域３８に隣接するコンタクト領域４４をさらに含んでいてよい。コンタクト領域４４は、ｐ型不純物を含むｐ型領域であってよい。コンタクト領域４４のｐ型不純物濃度は、ボディ領域３８よりも高く、１×１０１９ｃｍ－３以上１×１０２１ｃｍ－３以下であってよい。ソースコンタクトプラグ３４は、絶縁層１６およびソース領域４０を貫通して、コンタクト領域４４に接するように延びている。コンタクト領域４４は、ソースコンタクトプラグ３４の底部と隣接していてよい。コンタクト領域４４は、ソースコンタクトプラグ３４を介してソース配線４２に電気的に接続されている。 Epitaxial layer 20 may further include a contact region 44 adjacent body region 38 . Contact region 44 may be a p-type region containing p-type impurities. The p-type impurity concentration of the contact region 44 is higher than that of the body region 38, and may be 1×10 19 cm −3 or more and 1×10 21 cm −3 or less. Source contact plug 34 extends through insulating layer 16 and source region 40 so as to be in contact with contact region 44 . Contact region 44 may be adjacent to the bottom of source contact plug 34 . Contact region 44 is electrically connected to source wiring 42 via source contact plug 34 .
　絶縁層１６は、ゲート電極２８と半導体層１２（エピタキシャル層２０）との間に介在して第１トレンチ２４の側壁２４Ａを覆うゲート絶縁部４６を含む。ゲート絶縁部４６は、ゲート電極２８の側面２８Ｃと第１トレンチ２４の側壁２４Ａとの間にある絶縁層１６の一部である。ゲート電極２８は、ゲート絶縁部４６を介して半導体層１２と対向している。ゲート電極２８に所定の電圧（ゲート電圧）が印加されると、ゲート絶縁部４６と隣接するｐ型のボディ領域３８内にチャネルが形成される。半導体装置１０は、このチャネルを介したｎ型のソース領域４０とｎ型のドリフト領域３６との間のＺ軸方向の電子の流れの制御を可能とすることができる。 The insulating layer 16 includes a gate insulating portion 46 that is interposed between the gate electrode 28 and the semiconductor layer 12 (epitaxial layer 20) and covers the side wall 24A of the first trench 24. The gate insulating portion 46 is a part of the insulating layer 16 between the side surface 28C of the gate electrode 28 and the side wall 24A of the first trench 24. Gate electrode 28 faces semiconductor layer 12 with gate insulating section 46 in between. When a predetermined voltage (gate voltage) is applied to the gate electrode 28, a channel is formed in the p-type body region 38 adjacent to the gate insulating portion 46. The semiconductor device 10 can control the flow of electrons in the Z-axis direction between the n-type source region 40 and the n-type drift region 36 via this channel.
　図４は、図２のＦ４－Ｆ４線に沿った半導体装置１０の概略断面図である。図４では、非交差領域１４Ｂ（図２参照）における第２トレンチ２６のＹＺ平面の断面が示されており、これは、第２トレンチ２６の短手方向に沿った断面に相当する。 FIG. 4 is a schematic cross-sectional view of the semiconductor device 10 taken along line F4-F4 in FIG. FIG. 4 shows a cross section of the second trench 26 in the YZ plane in the non-intersecting region 14B (see FIG. 2), which corresponds to a cross section of the second trench 26 along the short direction.
　第２トレンチ２６は、半導体層１２の上面１２Ａに開口を有するとともに、側壁２６Ａおよび底壁２６Ｂを有している。第２トレンチ２６は、エピタキシャル層２０のソース領域４０およびボディ領域３８を貫通してドリフト領域３６に達している。したがって、第２トレンチ２６の底壁２６Ｂは、ドリフト領域３６に隣接している。第２トレンチ２６は、１μｍ以上１０μｍ以下の深さを有していてよい。なお、第２トレンチ２６の深さは、半導体層１２の上面１２Ａから第２トレンチ２６の底壁２６ＢまでのＺ軸方向における距離に相当し得る。 The second trench 26 has an opening in the upper surface 12A of the semiconductor layer 12, and has a side wall 26A and a bottom wall 26B. Second trench 26 penetrates source region 40 and body region 38 of epitaxial layer 20 and reaches drift region 36 . Therefore, the bottom wall 26B of the second trench 26 is adjacent to the drift region 36. The second trench 26 may have a depth of 1 μm or more and 10 μm or less. Note that the depth of the second trench 26 may correspond to the distance from the top surface 12A of the semiconductor layer 12 to the bottom wall 26B of the second trench 26 in the Z-axis direction.
　第２トレンチ２６の側壁２６Ａは、Ｚ軸方向（半導体層１２の上面１２Ａに対して垂直な方向）に延びていてもよいし、Ｚ軸方向に対して傾斜していてもよい。一例では、側壁２６Ａは、第２トレンチ２６の幅が底壁２６Ｂに向かって小さくなるようにＺ軸方向に対して傾斜していてもよい。なお、その場合、図２に示す第２トレンチ２６の幅Ｗ２は、半導体層１２の上面１２Ａの位置における第２トレンチ２６の幅であり得る。また、第２トレンチ２６の底壁２６Ｂは、必ずしも平坦でなくてもよく、例えば、その一部または全体が湾曲していてもよい。 The sidewall 26A of the second trench 26 may extend in the Z-axis direction (direction perpendicular to the upper surface 12A of the semiconductor layer 12) or may be inclined with respect to the Z-axis direction. In one example, the side wall 26A may be inclined with respect to the Z-axis direction so that the width of the second trench 26 becomes smaller toward the bottom wall 26B. Note that in that case, the width W2 of the second trench 26 shown in FIG. 2 may be the width of the second trench 26 at the position of the upper surface 12A of the semiconductor layer 12. Further, the bottom wall 26B of the second trench 26 does not necessarily have to be flat, and may be partially or entirely curved, for example.
　フィールドプレート電極３０は、第２トレンチ２６内に絶縁層１６を介して埋め込まれている。フィールドプレート電極３０は、絶縁層１６によって半導体層１２（エピタキシャル層２０）から離隔されている。フィールドプレート電極３０は、基準電圧（ソース電圧）が印加されるように構成されていてよい。よって、フィールドプレート電極３０は、ソース配線４２に電気的に接続されていてよい。フィールドプレート電極３０は、セルトレンチ１４の深さ方向（Ｚ軸方向）において、ドリフト領域３６とボディ領域３８との界面よりも下方に配置されている。 The field plate electrode 30 is embedded in the second trench 26 with the insulating layer 16 interposed therebetween. Field plate electrode 30 is separated from semiconductor layer 12 (epitaxial layer 20) by insulating layer 16. The field plate electrode 30 may be configured to be applied with a reference voltage (source voltage). Therefore, the field plate electrode 30 may be electrically connected to the source wiring 42. Field plate electrode 30 is arranged below the interface between drift region 36 and body region 38 in the depth direction (Z-axis direction) of cell trench 14 .
　フィールドプレート電極３０は、絶縁層１６に覆われた上面３０Ａ、および上面３０Ａと反対の底面３０Ｂを含んでいてよい。第２トレンチ２６に含まれる非交差領域１４Ｂにおいては、フィールドプレート電極３０の上面３０Ａよりも上方の第２トレンチ２６内には絶縁層１６が埋め込まれており、ゲート電極２８（図１参照）は配置されていない。フィールドプレート電極３０の上面３０Ａおよび底面３０Ｂは、平坦であってもよいし、湾曲していてもよい。 The field plate electrode 30 may include a top surface 30A covered with the insulating layer 16 and a bottom surface 30B opposite to the top surface 30A. In the non-intersecting region 14B included in the second trench 26, the insulating layer 16 is embedded in the second trench 26 above the upper surface 30A of the field plate electrode 30, and the gate electrode 28 (see FIG. 1) is Not placed. The top surface 30A and bottom surface 30B of the field plate electrode 30 may be flat or curved.
　各フィールドプレート電極３０の第１方向（図示の例ではＹ軸方向）の寸法は、各ゲート電極２８（図３参照）の第２方向（図示の例ではＸ軸方向）の寸法よりも小さくてよい。 The dimension of each field plate electrode 30 in the first direction (Y-axis direction in the illustrated example) is smaller than the dimension of each gate electrode 28 (see FIG. 3) in the second direction (X-axis direction in the illustrated example). good.
　図５は、図２のＦ５－Ｆ５線に沿った半導体装置１０の概略断面図である。図５では、第１トレンチ２４のＹＺ平面の断面が示されており、これは、第１トレンチ２４の長手方向に沿った断面に相当する。 FIG. 5 is a schematic cross-sectional view of the semiconductor device 10 taken along line F5-F5 in FIG. 2. FIG. 5 shows a cross section of the first trench 24 in the YZ plane, which corresponds to a cross section along the longitudinal direction of the first trench 24. In FIG.
　図５に示すように、第１トレンチ２４に含まれる交差領域１４Ａと非交差領域１４Ｂとが、第１トレンチ２４が延びる第１方向（図示の例ではＹ軸方向）に交互に並んでいる。交差領域１４Ａにおいて、ゲート電極２８は、フィールドプレート電極３０の上方を通っている。第１トレンチ２４に含まれる非交差領域１４Ｂにおいては、ゲート電極２８の下方にフィールドプレート電極３０は配置されていない。 As shown in FIG. 5, intersecting regions 14A and non-intersecting regions 14B included in the first trench 24 are arranged alternately in the first direction in which the first trench 24 extends (in the illustrated example, the Y-axis direction). In intersection region 14A, gate electrode 28 passes above field plate electrode 30. In the non-intersecting region 14B included in the first trench 24, the field plate electrode 30 is not arranged below the gate electrode 28.
　図６は、図２のＦ６－Ｆ６線に沿った半導体装置１０の概略断面図である。図６では、第２トレンチ２６のＸＺ平面の断面が示されており、これは、第２トレンチ２６の長手方向に沿った断面に相当する。 FIG. 6 is a schematic cross-sectional view of the semiconductor device 10 taken along line F6-F6 in FIG. FIG. 6 shows a cross section of the second trench 26 in the XZ plane, which corresponds to a cross section along the longitudinal direction of the second trench 26.
　図６に示すように、第２トレンチ２６に含まれる交差領域１４Ａと非交差領域１４Ｂとが、第２トレンチ２６が延びる第２方向（図示の例ではＸ軸方向）に交互に並んでいる。交差領域１４Ａにおいて、フィールドプレート電極３０は、ゲート電極２８の下方を通っている。第２トレンチ２６に含まれる非交差領域１４Ｂにおいては、フィールドプレート電極３０の上方にゲート電極２８は配置されていない。 As shown in FIG. 6, the intersecting regions 14A and non-intersecting regions 14B included in the second trench 26 are arranged alternately in the second direction in which the second trench 26 extends (in the illustrated example, the X-axis direction). In the intersection region 14A, the field plate electrode 30 passes below the gate electrode 28. In the non-intersecting region 14B included in the second trench 26, the gate electrode 28 is not arranged above the field plate electrode 30.
　図５および図６に示すように、交差領域１４Ａにおいて、セルトレンチ１４内には、フィールドプレート電極３０が、ゲート電極２８の下方に配置されている。ゲート電極２８の底面２８Ｂの少なくとも一部は、絶縁層１６を挟んでフィールドプレート電極３０の上面３０Ａと対向している。なお、図６に示すように、交差領域１４Ａにおいては、ゲート電極２８の側面２８Ｃは、第１トレンチ２４の側壁２４Ａとは対向していない。したがって、交差領域１４Ａにおいては、ゲート電極２８の周囲にチャネルは形成されない。よって、第２トレンチ２６のピッチＰ２に占める第２トレンチ２６の間隔Ｓ２の割合を大きくするほど、広いチャネルが形成されるため、半導体装置１０のオン抵抗を低減することができる（図２参照）。 As shown in FIGS. 5 and 6, a field plate electrode 30 is arranged below the gate electrode 28 in the cell trench 14 in the intersection region 14A. At least a portion of the bottom surface 28B of the gate electrode 28 faces the top surface 30A of the field plate electrode 30 with the insulating layer 16 in between. Note that, as shown in FIG. 6, in the intersection region 14A, the side surface 28C of the gate electrode 28 does not face the side wall 24A of the first trench 24. Therefore, no channel is formed around the gate electrode 28 in the intersection region 14A. Therefore, as the ratio of the interval S2 between the second trenches 26 to the pitch P2 of the second trenches 26 is increased, a wider channel is formed, so that the on-resistance of the semiconductor device 10 can be reduced (see FIG. 2). .
　一方、非交差領域１４Ｂにおいて、セルトレンチ１４内には、ゲート電極２８およびフィールドプレート電極３０のうちの一方しか配置されていない。より詳細には、図５に示すように、第１トレンチ２４に含まれる非交差領域１４Ｂにおいて、セルトレンチ１４内には、ゲート電極２８しか配置されていない。また、図６に示すように、第２トレンチ２６に含まれる非交差領域１４Ｂにおいて、セルトレンチ１４内には、フィールドプレート電極３０しか配置されていない。したがって、非交差領域１４Ｂにおいては、ゲート電極２８とフィールドプレート電極３０とが、セルトレンチ１４の深さ方向（Ｚ軸方向）に対向していない。この結果、第１トレンチ２４のピッチＰ１に占める第１トレンチ２４の間隔Ｓ１の割合を大きくするほど、ゲート電極２８とフィールドプレート電極３０とにより生じる容量を低減することができる（図２参照）。 On the other hand, in the non-intersecting region 14B, only one of the gate electrode 28 and the field plate electrode 30 is arranged in the cell trench 14. More specifically, as shown in FIG. 5, in the non-intersecting region 14B included in the first trench 24, only the gate electrode 28 is disposed in the cell trench 14. Further, as shown in FIG. 6, in the non-intersecting region 14B included in the second trench 26, only the field plate electrode 30 is disposed in the cell trench 14. Therefore, in the non-intersecting region 14B, the gate electrode 28 and the field plate electrode 30 do not face each other in the depth direction (Z-axis direction) of the cell trench 14. As a result, the larger the ratio of the interval S1 of the first trenches 24 to the pitch P1 of the first trenches 24 is, the more the capacitance generated by the gate electrode 28 and the field plate electrode 30 can be reduced (see FIG. 2).
　（半導体装置の作用）
　以下、本実施形態の半導体装置１０の作用について説明する。本実施形態によれば、メッシュ状に配置されたセルトレンチ１４内において、ゲート電極２８は第１方向に延び、一方、フィールドプレート電極３０は第１方向と交差する第２方向に延びている。ゲート電極２８とフィールドプレート電極３０とは同じ方向に延びずに交差しているので、ゲート電極２８とフィールドプレート電極３０とにより生じる容量を低減することができる。 (Function of semiconductor device)
The operation of the semiconductor device 10 of this embodiment will be explained below. According to this embodiment, within the cell trench 14 arranged in a mesh shape, the gate electrode 28 extends in the first direction, while the field plate electrode 30 extends in the second direction intersecting the first direction. Since the gate electrode 28 and the field plate electrode 30 do not extend in the same direction but intersect with each other, the capacitance caused by the gate electrode 28 and the field plate electrode 30 can be reduced.
　以下、図７に示す比較例に係る半導体装置１００を参照して、半導体装置１０の作用をさらに説明する。図７は、比較例に係る例示的な半導体装置１００の概略断面斜視図である。図７において、図１～図６に示す半導体装置１０と同様の構成要素には同じ符号が付されている。また、半導体装置１０と同様な構成要素については詳細な説明を省略する。 Hereinafter, the operation of the semiconductor device 10 will be further described with reference to the semiconductor device 100 according to the comparative example shown in FIG. FIG. 7 is a schematic cross-sectional perspective view of an exemplary semiconductor device 100 according to a comparative example. In FIG. 7, the same components as those of the semiconductor device 10 shown in FIGS. 1 to 6 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.
　半導体装置１００は、半導体装置１０と同様、トレンチゲート構造を有するＭＩＳＦＥＴであってよい。半導体装置１００は、ドレイン電極２２と、ドレイン電極２２上に形成された半導体層１２と、半導体層１２に形成された複数のセルトレンチ１０２と、半導体層１２上に形成された絶縁層１６とを含む。 Similarly to the semiconductor device 10, the semiconductor device 100 may be a MISFET having a trench gate structure. The semiconductor device 100 includes a drain electrode 22, a semiconductor layer 12 formed on the drain electrode 22, a plurality of cell trenches 102 formed in the semiconductor layer 12, and an insulating layer 16 formed on the semiconductor layer 12. include.
　なお、理解を容易にするために、図７においては、半導体層１２の上面１２Ａの位置における半導体装置１００の断面図が示されている。図８に示すように、絶縁層１６は、セルトレンチ１０２内だけでなく、半導体層１２の上面１２Ａ上にも形成されている点に留意されたい。 Note that in order to facilitate understanding, FIG. 7 shows a cross-sectional view of the semiconductor device 100 at the position of the upper surface 12A of the semiconductor layer 12. It should be noted that, as shown in FIG. 8, the insulating layer 16 is formed not only within the cell trench 102 but also on the upper surface 12A of the semiconductor layer 12.
　メッシュ状に配置された半導体装置１０のセルトレンチ１４とは異なり、複数のセルトレンチ１０２は、ストライプ状に配置されている。複数のセルトレンチ１０２の各々は、一方向（図示の例ではＹ軸方向）に延び、半導体層１２の上面１２Ａに開口を有するとともに、Ｚ軸方向に深さを有している。 Unlike the cell trenches 14 of the semiconductor device 10 that are arranged in a mesh pattern, the plurality of cell trenches 102 are arranged in a stripe pattern. Each of the plurality of cell trenches 102 extends in one direction (in the illustrated example, the Y-axis direction), has an opening in the upper surface 12A of the semiconductor layer 12, and has a depth in the Z-axis direction.
　半導体装置１００は、各セルトレンチ１０２内に絶縁層１６を介して埋め込まれたゲート電極１０４およびフィールドプレート電極１０６を含む。ゲート電極１０４およびフィールドプレート電極１０６は、セルトレンチ１０２が延びる方向（すなわち、Ｙ軸方向）に延びている。 The semiconductor device 100 includes a gate electrode 104 and a field plate electrode 106 buried in each cell trench 102 with an insulating layer 16 interposed therebetween. Gate electrode 104 and field plate electrode 106 extend in the direction in which cell trench 102 extends (ie, the Y-axis direction).
　各セルトレンチ１０２内において、ゲート電極１０４は、フィールドプレート電極１０６よりも上方（半導体層１２の上面１２Ａ寄り）に位置している。ゲート電極１０４は、絶縁層１６によってフィールドプレート電極１０６から離隔されている。ゲート電極１０４とフィールドプレート電極１０６とは、セルトレンチ１０２と同様、Ｙ軸方向に延びている。 In each cell trench 102, the gate electrode 104 is located above the field plate electrode 106 (closer to the upper surface 12A of the semiconductor layer 12). Gate electrode 104 is separated from field plate electrode 106 by insulating layer 16 . Like the cell trench 102, the gate electrode 104 and the field plate electrode 106 extend in the Y-axis direction.
　半導体装置１００は、複数のソースコンタクトプラグ１０８をさらに含む。各ソースコンタクトプラグ１０８は、２つのセルトレンチ１０２の間に配置されている。ソースコンタクトプラグ１０８は、セルトレンチ１０２と同様、Ｙ軸方向に延びている。 The semiconductor device 100 further includes a plurality of source contact plugs 108. Each source contact plug 108 is arranged between two cell trenches 102. Like the cell trench 102, the source contact plug 108 extends in the Y-axis direction.
　図８は、図７に示す半導体装置１００の概略断面図である。図８では、セルトレンチ１０２のＸＺ平面の断面が示されており、これは、セルトレンチ１０２の短手方向に沿った断面に相当する。 FIG. 8 is a schematic cross-sectional view of the semiconductor device 100 shown in FIG. 7. FIG. 8 shows a cross section of the cell trench 102 in the XZ plane, which corresponds to a cross section along the short direction of the cell trench 102.
　半導体装置１００は、絶縁層１６上に形成されたソース配線４２をさらに含む。ソース配線４２は、ソースコンタクトプラグ１０８に接続されている。
　セルトレンチ１０２は、側壁１０２Ａおよび底壁１０２Ｂを有している。セルトレンチ１０２は、エピタキシャル層２０のソース領域４０およびボディ領域３８を貫通してドリフト領域３６に達している。したがって、セルトレンチ１０２の底壁１０２Ｂは、ドリフト領域３６に隣接している。 Semiconductor device 100 further includes a source wiring 42 formed on insulating layer 16. Source wiring 42 is connected to source contact plug 108.
The cell trench 102 has a side wall 102A and a bottom wall 102B. Cell trench 102 penetrates source region 40 and body region 38 of epitaxial layer 20 and reaches drift region 36 . Therefore, the bottom wall 102B of the cell trench 102 is adjacent to the drift region 36.
　ゲート電極１０４は、絶縁層１６に覆われた上面１０４Ａ、および上面１０４Ａと反対の底面１０４Ｂを含む。また、ゲート電極１０４の側面１０４Ｃは、ゲート絶縁部４６を介してセルトレンチ１０２の側壁１０２Ａと対向している。フィールドプレート電極１０６は、絶縁層１６に覆われた上面１０６Ａ、および上面１０６Ａと反対の底面１０６Ｂを含む。フィールドプレート電極１０６は、セルトレンチ１０２内において、ゲート電極１０４の下方に配置されている。より詳細には、フィールドプレート電極１０６は、ゲート電極１０４の底面１０４Ｂとセルトレンチ１０２の底壁１０２Ｂとの間に配置されている。ゲート電極１０４の底面１０４Ｂの少なくとも一部は、絶縁層１６を挟んでフィールドプレート電極１０６の上面１０６Ａと対向している。 The gate electrode 104 includes a top surface 104A covered with the insulating layer 16 and a bottom surface 104B opposite to the top surface 104A. Further, the side surface 104C of the gate electrode 104 faces the side wall 102A of the cell trench 102 with the gate insulating section 46 interposed therebetween. Field plate electrode 106 includes a top surface 106A covered by insulating layer 16, and a bottom surface 106B opposite top surface 106A. Field plate electrode 106 is arranged below gate electrode 104 within cell trench 102 . More specifically, the field plate electrode 106 is arranged between the bottom surface 104B of the gate electrode 104 and the bottom wall 102B of the cell trench 102. At least a portion of the bottom surface 104B of the gate electrode 104 faces the top surface 106A of the field plate electrode 106 with the insulating layer 16 in between.
　ゲート電極１０４およびフィールドプレート電極１０６は、周囲を絶縁層１６によって囲まれている。フィールドプレート電極１０６は、ゲート電極１０４よりも小さい幅を有している。フィールドプレート電極１０６が比較的小さい幅を有することにより、フィールドプレート電極１０６を囲む絶縁層１６の厚さは比較的大きい。 The gate electrode 104 and the field plate electrode 106 are surrounded by an insulating layer 16. Field plate electrode 106 has a smaller width than gate electrode 104. Due to the relatively small width of field plate electrode 106, the thickness of insulating layer 16 surrounding field plate electrode 106 is relatively large.
　ゲート電極１０４は、ゲート電圧が印加されるように構成されている。また、フィールドプレート電極１０６は、基準電圧（ソース電圧）が印加されるように構成されている。よって、フィールドプレート電極１０６は、ソース配線４２に電気的に接続され得る。半導体装置１００においては、ゲート電極１０４の下方にフィールドプレート電極１０６を配置することにより、セルトレンチ１０２内の電界集中を緩和するとともに、ゲート・ドレイン間容量を低減することができる。 The gate electrode 104 is configured so that a gate voltage is applied. Further, the field plate electrode 106 is configured to be applied with a reference voltage (source voltage). Therefore, the field plate electrode 106 can be electrically connected to the source wiring 42. In the semiconductor device 100, by arranging the field plate electrode 106 below the gate electrode 104, electric field concentration within the cell trench 102 can be alleviated, and the gate-drain capacitance can be reduced.
　一方、ゲート電極１０４とフィールドプレート電極１０６とは、互いに対向しつつ、セルトレンチ１０２内で同じ方向に延びているため、ゲート・ソース間容量が比較的大きくなり得る。ゲート・ソース間容量が大きいと、セルフターンオン等の半導体装置１００の望ましくない動作が発生し得る。 On the other hand, since the gate electrode 104 and the field plate electrode 106 extend in the same direction within the cell trench 102 while facing each other, the gate-source capacitance can become relatively large. If the gate-source capacitance is large, undesirable operations of the semiconductor device 100 such as self-turn-on may occur.
　この点、本実施形態の半導体装置１０においては、メッシュ状に配置されたセルトレンチ１４内において、ゲート電極２８は第１方向に延び、一方、フィールドプレート電極３０は第１方向と交差する第２方向に延びている。したがって、ゲート電極２８とフィールドプレート電極３０とにより生じる容量を低減することができる。 In this regard, in the semiconductor device 10 of this embodiment, the gate electrode 28 extends in the first direction in the cell trench 14 arranged in a mesh shape, while the field plate electrode 30 extends in the second direction intersecting the first direction. extending in the direction. Therefore, the capacitance caused by the gate electrode 28 and the field plate electrode 30 can be reduced.
　より詳細には、セルトレンチ１４は、複数の第１トレンチ２４と複数の第２トレンチ２６とが互いに交差する複数の交差領域１４Ａと、複数の第１トレンチ２４と複数の第２トレンチ２６とが互いに交差していない複数の非交差領域１４Ｂとを含んでいる。複数の交差領域１４Ａの各々において、複数のゲート電極２８のうちの１つが、平面視で複数のフィールドプレート電極３０のうちの１つと交差している。また、複数の非交差領域１４Ｂの各々において、セルトレンチ１４内には、複数のゲート電極２８のうちの１つ、またはフィールドプレート電極３０のうちの１つが配置されている。 More specifically, the cell trench 14 includes a plurality of intersection regions 14A where a plurality of first trenches 24 and a plurality of second trenches 26 intersect with each other, and a plurality of intersection regions 14A where a plurality of first trenches 24 and a plurality of second trenches 26 intersect with each other. It includes a plurality of non-intersecting regions 14B that do not intersect with each other. In each of the plurality of intersection regions 14A, one of the plurality of gate electrodes 28 intersects with one of the plurality of field plate electrodes 30 in plan view. Further, in each of the plurality of non-intersecting regions 14B, one of the plurality of gate electrodes 28 or one of the field plate electrodes 30 is arranged in the cell trench 14.
　各非交差領域１４Ｂにおいて、セルトレンチ１４内には、ゲート電極２８およびフィールドプレート電極３０のうちの一方しか配置されていないため、ゲート電極２８とフィールドプレート電極３０とにより生じる容量を低減することができる。 In each non-intersecting region 14B, only one of the gate electrode 28 and the field plate electrode 30 is disposed in the cell trench 14, so that the capacitance caused by the gate electrode 28 and the field plate electrode 30 can be reduced. can.
　一方、各交差領域１４Ａにおいて、セルトレンチ１４内には、フィールドプレート電極３０が、ゲート電極２８の下方に配置されている。したがって、交差領域１４Ａ近傍の半導体層１２中に空乏層を広げることができ、その結果、半導体装置１０のゲート・ドレイン間容量を低減することができる。 On the other hand, in each intersection region 14A, a field plate electrode 30 is arranged below the gate electrode 28 in the cell trench 14. Therefore, a depletion layer can be expanded in the semiconductor layer 12 near the intersection region 14A, and as a result, the gate-drain capacitance of the semiconductor device 10 can be reduced.
　本実施形態の半導体装置１０は、以下の利点を有する。
　（１）メッシュ状に配置されたセルトレンチ１４内において、ゲート電極２８は第１方向に延び、一方、フィールドプレート電極３０は第１方向と交差する第２方向に延びている。ゲート電極２８とフィールドプレート電極３０とは同じ方向に延びずに交差しているため、ゲート電極２８とフィールドプレート電極３０とにより生じる容量を低減することができる。 The semiconductor device 10 of this embodiment has the following advantages.
(1) In the cell trenches 14 arranged in a mesh shape, the gate electrode 28 extends in a first direction, while the field plate electrode 30 extends in a second direction intersecting the first direction. Since the gate electrode 28 and the field plate electrode 30 do not extend in the same direction but intersect with each other, the capacitance caused by the gate electrode 28 and the field plate electrode 30 can be reduced.
　（２）セルトレンチ１４は、複数の第１トレンチ２４と複数の第２トレンチ２６とが互いに交差する複数の交差領域１４Ａと、複数の第１トレンチ２４と複数の第２トレンチ２６とが互いに交差していない複数の非交差領域１４Ｂとを含んでいる。複数の交差領域１４Ａの各々において、複数のゲート電極２８のうちの１つが、平面視で複数のフィールドプレート電極３０のうちの１つと交差している。また、複数の非交差領域１４Ｂの各々において、セルトレンチ１４内には、複数のゲート電極２８のうちの１つ、またはフィールドプレート電極３０のうちの１つが配置されている。よって、交差領域１４Ａには、ゲート電極２８およびフィールドプレート電極３０の両方を配置することができるとともに、非交差領域１４Ｂには、ゲート電極２８およびフィールドプレート電極３０のうちの一方だけを配置することができる。 (2) The cell trench 14 includes a plurality of intersection regions 14A where a plurality of first trenches 24 and a plurality of second trenches 26 intersect with each other, and a plurality of intersection regions 14A where a plurality of first trenches 24 and a plurality of second trenches 26 intersect with each other. It includes a plurality of non-intersecting regions 14B. In each of the plurality of intersection regions 14A, one of the plurality of gate electrodes 28 intersects with one of the plurality of field plate electrodes 30 in plan view. Further, in each of the plurality of non-intersecting regions 14B, one of the plurality of gate electrodes 28 or one of the field plate electrodes 30 is arranged in the cell trench 14. Therefore, both the gate electrode 28 and the field plate electrode 30 can be arranged in the intersection region 14A, and only one of the gate electrode 28 and the field plate electrode 30 can be arranged in the non-intersection region 14B. Can be done.
　（３）複数の交差領域１４Ａの各々において、セルトレンチ１４内には、複数のフィールドプレート電極３０のうちの１つが、複数のゲート電極２８のうちの１つの下方に配置されている。これにより、交差領域１４Ａ近傍の半導体層１２中に空乏層を広げることができ、その結果、半導体装置１０のゲート・ドレイン間容量を低減することができる。 (3) In each of the plurality of intersection regions 14A, one of the plurality of field plate electrodes 30 is arranged below one of the plurality of gate electrodes 28 in the cell trench 14. Thereby, a depletion layer can be expanded in the semiconductor layer 12 near the intersection region 14A, and as a result, the gate-drain capacitance of the semiconductor device 10 can be reduced.
　（４）複数の第１トレンチ２４は、一定の間隔Ｓ１で互いに平行に配置され、複数の第１トレンチ２４が配置される間隔Ｓ１は、複数の第１トレンチ２４の各々の幅Ｗ１よりも大きくてよい。これにより、第１トレンチ２４のピッチＰ１に占める第１トレンチ２４の間隔Ｓ１の割合をより大きくすることができるため、ゲート電極２８とフィールドプレート電極３０とにより生じる容量をさらに低減することができる。 (4) The plurality of first trenches 24 are arranged parallel to each other at constant intervals S1, and the interval S1 at which the plurality of first trenches 24 are arranged is larger than the width W1 of each of the plurality of first trenches 24. It's okay. Thereby, the ratio of the interval S1 between the first trenches 24 to the pitch P1 of the first trenches 24 can be increased, so that the capacitance caused by the gate electrode 28 and the field plate electrode 30 can be further reduced.
　（５）複数の第２トレンチ２６は、一定の間隔Ｓ２で互いに平行に配置され、複数の第２トレンチ２６が配置される間隔Ｓ２は、複数の第２トレンチ２６の各々の幅Ｗ２よりも大きくてよい。これにより、第２トレンチ２６のピッチＰ２に占める第２トレンチ２６の間隔Ｓ２の割合をより大きくすることができるため、より広いチャネルが形成され、その結果、半導体装置１０のオン抵抗を低減することができる。 (5) The plurality of second trenches 26 are arranged parallel to each other at constant intervals S2, and the interval S2 at which the plurality of second trenches 26 are arranged is larger than the width W2 of each of the plurality of second trenches 26. It's okay. As a result, the ratio of the interval S2 between the second trenches 26 to the pitch P2 of the second trenches 26 can be increased, so that a wider channel is formed, and as a result, the on-resistance of the semiconductor device 10 can be reduced. Can be done.
　（６）複数の第２トレンチ２６の各々の幅Ｗ２は、複数の第１トレンチ２４の各々の幅Ｗ１よりも大きくてよい。第２トレンチ２６の幅Ｗ２を大きくするほど、フィールドプレート電極３０を囲む絶縁層１６を厚くすることができるため、半導体装置１０の耐圧を向上させることができる。 (6) The width W2 of each of the plurality of second trenches 26 may be larger than the width W1 of each of the plurality of first trenches 24. As the width W2 of the second trench 26 is increased, the insulation layer 16 surrounding the field plate electrode 30 can be made thicker, so that the breakdown voltage of the semiconductor device 10 can be improved.
　（７）各フィールドプレート電極３０の第１方向の寸法は、各ゲート電極２８の第２方向の寸法よりも小さくてよい。フィールドプレート電極３０の第１方向の寸法を小さくするほど、フィールドプレート電極３０を囲む絶縁層１６を厚くすることができるため、半導体装置１０の耐圧を向上させることができる。 (7) The dimension of each field plate electrode 30 in the first direction may be smaller than the dimension of each gate electrode 28 in the second direction. The smaller the dimension of the field plate electrode 30 in the first direction is, the thicker the insulating layer 16 surrounding the field plate electrode 30 can be, so the withstand voltage of the semiconductor device 10 can be improved.
　［セルトレンチの変更例］
　図９は、セルトレンチの変更例を説明するための例示的な半導体装置２００の概略平面図である。図９において、図１～図６に示す半導体装置１０と同様の構成要素には同じ符号が付されている。また、半導体装置１０と同様な構成要素については詳細な説明を省略する。 [Example of changing cell trench]
FIG. 9 is a schematic plan view of an exemplary semiconductor device 200 for explaining a modification of the cell trench. In FIG. 9, the same components as those of the semiconductor device 10 shown in FIGS. 1 to 6 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.
　半導体装置２００は、半導体層１２に形成されたセルトレンチ２０２を含む。セルトレンチ２０２は、平面視で第１方向に延びる複数の第１トレンチ２４と、平面視で第１方向と交差する第２方向に延びる複数の第２トレンチ２６とを含む。セルトレンチ２０２は、第１トレンチ２４が延びる第１方向がＹ軸方向に一致していないという点において、図１および図２に示す例示的なセルトレンチ１４と相違している。図示の例では、第１方向と第２方向とがなす角度は９０度ではない。すなわち、第１方向は、第２方向と直交する方向に対して傾斜していてよい。 The semiconductor device 200 includes a cell trench 202 formed in the semiconductor layer 12. The cell trench 202 includes a plurality of first trenches 24 extending in a first direction in a plan view, and a plurality of second trenches 26 extending in a second direction intersecting the first direction in a plan view. Cell trench 202 differs from exemplary cell trench 14 shown in FIGS. 1 and 2 in that the first direction in which first trench 24 extends does not coincide with the Y-axis direction. In the illustrated example, the angle between the first direction and the second direction is not 90 degrees. That is, the first direction may be inclined with respect to the direction orthogonal to the second direction.
　図９に示すように、複数の第１トレンチ２４の各々をＹ軸方向に対して傾斜させることにより、図２の例と比較して、半導体層１２の所定の範囲内に形成することができる第１トレンチ２４の長さを増加させることができる。第１トレンチ２４にはゲート電極２８が配置されるため、複数の第１トレンチ２４の各々をＹ軸方向に対して傾斜させることにより、ゲート電極２８を長くすることができる。その結果、半導体装置２００のオン抵抗を低減することができる。なお、半導体層１２の所定の範囲内に形成することができる第１トレンチ２４の数の減少を抑制するという観点からは、第１トレンチ２４が延びる第１方向と、第２トレンチ２６が延びる第２方向とのなす角度は、９０度±１０度の範囲内であることが好ましい。 As shown in FIG. 9, by tilting each of the plurality of first trenches 24 with respect to the Y-axis direction, they can be formed within a predetermined range of the semiconductor layer 12, compared to the example of FIG. The length of the first trench 24 can be increased. Since the gate electrode 28 is disposed in the first trench 24, the gate electrode 28 can be made longer by making each of the plurality of first trenches 24 inclined with respect to the Y-axis direction. As a result, the on-resistance of the semiconductor device 200 can be reduced. Note that from the viewpoint of suppressing a decrease in the number of first trenches 24 that can be formed within a predetermined range of the semiconductor layer 12, the first direction in which the first trenches 24 extend and the direction in which the second trenches 26 extend are The angle between the two directions is preferably within the range of 90 degrees ±10 degrees.
　［他の変更例］
　上記実施形態および変更例は、以下のように変更して実施することができる。
　・図５および図６において、セルトレンチ１４の深さは、交差領域１４Ａおよび非交差領域１４Ｂのどちらでも一定であるように示されている。しかしながら、セルトレンチ１４の深さは必ずしも一定でなくてもよい。例えば、交差領域１４Ａにおけるセルトレンチ１４の深さは、非交差領域１４Ｂにおけるセルトレンチ１４の深さよりも大きくてもよい。別の例では、交差領域１４Ａにおけるセルトレンチ１４の深さは、非交差領域１４Ｂにおけるセルトレンチ１４の深さよりも小さくてもよい。 [Other change examples]
The above embodiment and modification example can be modified and implemented as follows.
- In FIGS. 5 and 6, the depth of the cell trench 14 is shown to be constant in both the crossing region 14A and the non-crossing region 14B. However, the depth of the cell trench 14 does not necessarily have to be constant. For example, the depth of the cell trench 14 in the crossing region 14A may be greater than the depth of the cell trench 14 in the non-crossing region 14B. In another example, the depth of the cell trench 14 in the crossing region 14A may be smaller than the depth of the cell trench 14 in the non-crossing region 14B.
　・第１トレンチ２４の深さは、第２トレンチ２６の深さと同じであってもよいし、異なっていてもよい。例えば、第２トレンチ２６の深さは、第１トレンチ２４の深さよりも大きくてもよい。別の例では、第２トレンチ２６の深さは、第１トレンチ２４の深さよりも小さくてもよい。 - The depth of the first trench 24 may be the same as or different from the depth of the second trench 26. For example, the depth of the second trench 26 may be greater than the depth of the first trench 24. In another example, the depth of second trench 26 may be less than the depth of first trench 24.
　・図９に示す半導体装置２００において、ソースコンタクトプラグ３４は、平面視でＹ軸方向に延びているが、第１トレンチ２４と平行に第１方向に延びるように配置されていてもよい。 - In the semiconductor device 200 shown in FIG. 9, the source contact plug 34 extends in the Y-axis direction in plan view, but may be arranged so as to extend in the first direction parallel to the first trench 24.
　・半導体層１２内の各領域の導電型が反転された構造が採用されてもよい。すなわち、ｐ型の領域がｎ型の領域とされ、ｎ型の領域がｐ型の領域とされてもよい。
　・ソース配線４２を含む層の上に、さらなる配線構造が形成されていてもよい。 - A structure in which the conductivity type of each region in the semiconductor layer 12 is reversed may be adopted. That is, the p-type region may be made into an n-type region, and the n-type region may be made into a p-type region.
- An additional wiring structure may be formed on the layer including the source wiring 42.
　本明細書に記載の様々な例のうちの１つまたは複数を、技術的に矛盾しない範囲で組み合わせることができる。
　本明細書において、「ＡおよびＢのうちの少なくとも１つ」とは、「Ａのみ、または、Ｂのみ、または、ＡおよびＢの両方」を意味するものとして理解されるべきである。 One or more of the various examples described herein can be combined to the extent not technically inconsistent.
As used herein, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."
　本明細書において、「～上に」という用語は、文脈によって明らかにそうでないことが示されない限り、「～上に」と「～の上方に」の意味を含む。したがって、「第１層が第２層上に形成される」という表現は、或る実施形態では第１層が第２層に接触して第２層上に直接配置され得るが、他の実施形態では第１層が第２層に接触することなく第２層の上方に配置され得ることが意図される。すなわち、「～上に」という用語は、第１層と第２層との間に他の層が形成される構造を排除しない。 As used herein, the term "on" includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "the first layer is formed on the second layer" refers to the fact that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other embodiments. It is contemplated that the first layer may be placed above the second layer without contacting the second layer. That is, the term "on" does not exclude structures in which other layers are formed between the first layer and the second layer.
　本明細書で使用される「垂直」、「水平」、「上方」、「下方」、「上」、「下」、「前方」、「後方」、「縦」、「横」、「左」、「右」、「前」、「後」などの方向を示す用語は、説明および図示された装置の特定の向きに依存する。本開示においては、様々な代替的な向きを想定することができ、したがって、これらの方向を示す用語は、狭義に解釈されるべきではない。 "Vertical", "horizontal", "above", "downward", "above", "below", "front", "rear", "vertical", "lateral", "left" as used herein Directional terms such as , "right," "front," "back," etc., depend on the particular orientation of the device described and illustrated. Various alternative orientations may be envisioned in this disclosure, and therefore, these directional terms should not be construed narrowly.
　例えば、本開示で使用されるＺ軸方向は必ずしも鉛直方向である必要はなく、鉛直方向に完全に一致している必要もない。例えば、Ｘ軸方向が鉛直方向であってもよく、またはＹ軸方向が鉛直方向であってもよい。 For example, the Z-axis direction used in the present disclosure does not necessarily need to be a vertical direction, nor does it need to completely coincide with the vertical direction. For example, the X-axis direction may be a vertical direction, or the Y-axis direction may be a vertical direction.
　［付記］
　上記実施形態および変更例の各々から把握できる技術的思想を以下に記載する。なお、限定する意図ではなく理解の補助のために、付記に記載した構成について実施形態中の対応する符号を括弧書きで示す。符号は、理解の補助のために例として示すものであり、各付記に記載された構成要素は、符号で示される構成要素に限定されるべきではない。 [Additional notes]
The technical ideas that can be grasped from each of the above embodiments and modified examples are described below. It should be noted that, for the purpose of assisting understanding rather than with the intention of limiting, the corresponding reference numerals in the embodiments for the configurations described in the supplementary notes are shown in parentheses. The symbols are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the symbols.
　（付記１）
　半導体層（１２）と、
　前記半導体層（１２）に形成されるとともにメッシュ状に配置されたセルトレンチ（１４）であって、平面視で第１方向に延びる複数の第１トレンチ（２４）と、平面視で前記第１方向と交差する第２方向に延びる複数の第２トレンチ（２６）とを含み、前記複数の第１トレンチ（２４）と前記複数の第２トレンチ（２６）とは互いに交差し、かつ連通している、セルトレンチ（１４）と、
　前記半導体層（１２）上に形成された絶縁層（１６）と、
　前記複数の第１トレンチ（２４）内に前記絶縁層（１６）を介してそれぞれ埋め込まれるとともに、前記第１方向に延びる複数のゲート電極（２８）と、
　前記複数の第２トレンチ（２６）内に前記絶縁層（１６）を介してそれぞれ埋め込まれるとともに、前記第２方向に延びる複数のフィールドプレート電極（３０）と
　を備える、半導体装置。 (Additional note 1)
a semiconductor layer (12);
Cell trenches (14) formed in the semiconductor layer (12) and arranged in a mesh pattern include a plurality of first trenches (24) extending in a first direction in plan view; a plurality of second trenches (26) extending in a second direction intersecting the direction, the plurality of first trenches (24) and the plurality of second trenches (26) intersect with each other and communicate with each other. There is a cell trench (14),
an insulating layer (16) formed on the semiconductor layer (12);
a plurality of gate electrodes (28) each embedded in the plurality of first trenches (24) via the insulating layer (16) and extending in the first direction;
A semiconductor device comprising: a plurality of field plate electrodes (30) embedded in the plurality of second trenches (26) via the insulating layer (16) and extending in the second direction.
　（付記２）
　前記セルトレンチ（１４）は、前記複数の第１トレンチ（２４）と前記複数の第２トレンチ（２６）とが互いに交差する複数の交差領域（１４Ａ）と、前記複数の第１トレンチ（２４）と前記複数の第２トレンチ（２６）とが互いに交差していない複数の非交差領域（１４Ｂ）とを含み、
　前記複数の交差領域（１４Ａ）の各々において、前記複数のゲート電極（２８）のうちの１つが、前記複数のフィールドプレート電極（３０）のうちの１つと交差しており、
　前記複数の非交差領域（１４Ｂ）の各々において、前記セルトレンチ（１４）内には、前記複数のゲート電極（２８）のうちの１つ、または前記フィールドプレート電極（３０）のうちの１つが配置されている、付記１に記載の半導体装置。 (Additional note 2)
The cell trench (14) includes a plurality of intersection regions (14A) where the plurality of first trenches (24) and the plurality of second trenches (26) intersect with each other, and the plurality of first trenches (24). and a plurality of non-intersecting regions (14B) in which the plurality of second trenches (26) do not intersect with each other,
In each of the plurality of crossing regions (14A), one of the plurality of gate electrodes (28) intersects with one of the plurality of field plate electrodes (30),
In each of the plurality of non-intersecting regions (14B), one of the plurality of gate electrodes (28) or one of the field plate electrodes (30) is located in the cell trench (14). The semiconductor device according to supplementary note 1, which is arranged.
　（付記３）
　前記複数の交差領域（１４Ａ）の各々において、前記セルトレンチ（１４）内には、前記複数のフィールドプレート電極（３０）のうちの１つが、前記複数のゲート電極（２８）のうちの１つの下方に配置されている、付記２に記載の半導体装置。 (Additional note 3)
In each of the plurality of intersection regions (14A), one of the plurality of field plate electrodes (30) is connected to one of the plurality of gate electrodes (28) in the cell trench (14). The semiconductor device according to appendix 2, which is disposed below.
　（付記４）
　前記複数の交差領域（１４Ａ）の各々において、前記複数のフィールドプレート電極（３０）のうちの１つは、前記絶縁層（１６）によって前記複数のゲート電極（２８）のうちの１つから離隔されている、付記２または３に記載の半導体装置。 (Additional note 4)
In each of the plurality of intersection regions (14A), one of the plurality of field plate electrodes (30) is separated from one of the plurality of gate electrodes (28) by the insulating layer (16). The semiconductor device according to appendix 2 or 3, wherein
　（付記５）
　前記複数の第１トレンチ（２４）の各々に含まれる前記交差領域（１４Ａ）と前記非交差領域（１４Ｂ）とは、前記第１方向に交互に並んでおり、
　前記複数の第２トレンチ（２６）の各々に含まれる前記交差領域（１４Ａ）と前記非交差領域（１４Ｂ）とは、前記第２方向に交互に並んでいる、付記２または３に記載の半導体装置。 (Appendix 5)
The intersecting regions (14A) and the non-intersecting regions (14B) included in each of the plurality of first trenches (24) are arranged alternately in the first direction,
The intersecting regions (14A) and the non-intersecting regions (14B) included in each of the plurality of second trenches (26) are semiconductors according to appendix 2 or 3, wherein the intersecting regions (14A) and the non-intersecting regions (14B) are arranged alternately in the second direction. Device.
　（付記６）
　前記半導体層（１２）は、第１導電型のドリフト領域（３６）と、前記ドリフト領域（３６）上に形成された第２導電型のボディ領域（３８）と、前記ボディ領域（３８）上に形成された前記第１導電型のソース領域（４０）とを含み、
　各ゲート電極（２８）の少なくとも一部は、前記絶縁層（１６）を介して前記ボディ領域（３８）と前記第２方向に対向するように配置され、
　各フィールドプレート電極（３０）は、前記セルトレンチ（１４）の深さ方向において、前記ドリフト領域（３６）と前記ボディ領域（３８）との界面よりも下方に配置されている、付記１～５のうちのいずれか１つに記載の半導体装置。 (Appendix 6)
The semiconductor layer (12) includes a first conductivity type drift region (36), a second conductivity type body region (38) formed on the drift region (36), and a second conductivity type body region (38) formed on the body region (38). the source region (40) of the first conductivity type formed in
At least a portion of each gate electrode (28) is arranged to face the body region (38) in the second direction with the insulating layer (16) interposed therebetween;
Each field plate electrode (30) is arranged below the interface between the drift region (36) and the body region (38) in the depth direction of the cell trench (14). The semiconductor device according to any one of the above.
　（付記７）
　前記絶縁層（１６）上に形成されたソース配線（４２）と、
　前記ソース配線（４２）に接続された複数のソースコンタクトプラグ（３４）と
　をさらに備え、
　前記半導体層（１２）は、前記メッシュ状に配置されたセルトレンチ（１４）によって囲まれた複数のメッシュ領域（３２）を含み、
　前記複数のソースコンタクトプラグ（３４）は、前記複数のメッシュ領域（３２）にそれぞれ配置されている、付記１～６のうちのいずれか１つに記載の半導体装置。 (Appendix 7)
a source wiring (42) formed on the insulating layer (16);
further comprising a plurality of source contact plugs (34) connected to the source wiring (42),
The semiconductor layer (12) includes a plurality of mesh regions (32) surrounded by the cell trenches (14) arranged in a mesh shape,
The semiconductor device according to any one of appendices 1 to 6, wherein the plurality of source contact plugs (34) are respectively arranged in the plurality of mesh regions (32).
　（付記８）
　前記第１方向は、前記第２方向と直交している、付記１～７のうちのいずれか１つに記載の半導体装置。 (Appendix 8)
8. The semiconductor device according to any one of appendices 1 to 7, wherein the first direction is orthogonal to the second direction.
　（付記９）
　前記第１方向は、前記第２方向と直交する方向に対して傾斜している、付記１～７のうちのいずれか１つに記載の半導体装置。 (Appendix 9)
8. The semiconductor device according to any one of appendices 1 to 7, wherein the first direction is inclined with respect to a direction perpendicular to the second direction.
　（付記１０）
　前記第１方向と前記第２方向とがなす角度は、９０度±１０度の範囲内にある、付記１～９のうちのいずれか１つに記載の半導体装置。 (Appendix 10)
The semiconductor device according to any one of appendices 1 to 9, wherein the angle between the first direction and the second direction is within a range of 90 degrees ±10 degrees.
　（付記１１）
　前記複数の第１トレンチ（２４）は、一定の間隔（Ｓ１）で互いに平行に配置され、
　前記複数の第１トレンチ（２４）が配置される前記間隔（Ｓ１）は、前記複数の第１トレンチ（２４）の各々の幅（Ｗ１）よりも大きい、付記１～１０のうちのいずれか１つに記載の半導体装置。 (Appendix 11)
The plurality of first trenches (24) are arranged parallel to each other at regular intervals (S1),
Any one of Supplementary Notes 1 to 10, wherein the interval (S1) in which the plurality of first trenches (24) are arranged is larger than the width (W1) of each of the plurality of first trenches (24). The semiconductor device described in .
　（付記１２）
　前記複数の第２トレンチ（２６）は、一定の間隔（Ｓ２）で互いに平行に配置され、
　前記複数の第２トレンチ（２６）が配置される前記間隔（Ｓ２）は、前記複数の第２トレンチ（２６）の各々の幅（Ｗ２）よりも大きい、付記１～１１のうちのいずれか１つに記載の半導体装置。 (Appendix 12)
The plurality of second trenches (26) are arranged parallel to each other at regular intervals (S2),
Any one of Supplementary Notes 1 to 11, wherein the interval (S2) in which the plurality of second trenches (26) are arranged is larger than the width (W2) of each of the plurality of second trenches (26). The semiconductor device described in .
　（付記１３）
　前記複数の第２トレンチ（２６）の各々の幅（Ｗ２）は、前記複数の第１トレンチ（２４）の各々の幅（Ｗ１）よりも大きい、付記１～１２のうちのいずれか１つに記載の半導体装置。 (Appendix 13)
The width (W2) of each of the plurality of second trenches (26) is greater than the width (W1) of each of the plurality of first trenches (24), according to any one of Supplementary notes 1 to 12. The semiconductor device described.
　（付記１４）
　各フィールドプレート電極（３０）の前記第１方向の寸法は、各ゲート電極（２８）の前記第２方向の寸法よりも小さい、付記１～１３のうちのいずれか１つに記載の半導体装置。 (Appendix 14)
14. The semiconductor device according to any one of appendices 1 to 13, wherein a dimension of each field plate electrode (30) in the first direction is smaller than a dimension of each gate electrode (28) in the second direction.
　１０，１００，２００…半導体装置
　１２…半導体層
　１２Ａ…上面
　１２Ｂ…底面
　１４，１０２，２０２…セルトレンチ
　１４Ａ…交差領域
　１４Ｂ…非交差領域
　１６…絶縁層
　１８…半導体基板
　２０…エピタキシャル層
　２２…ドレイン電極
　２４…第１トレンチ
　２６…第２トレンチ
　２８，１０４…ゲート電極
　３０，１０６…フィールドプレート電極
　３２…メッシュ領域
　３４，１０８…ソースコンタクトプラグ
　３６…ドリフト領域
　３８…ボディ領域
　４０…ソース領域
　４２…ソース配線
　４４…コンタクト領域
　４６…ゲート絶縁部
　Ｗ１，Ｗ２…幅
　Ｓ１，Ｓ２…間隔 DESCRIPTION OF SYMBOLS 10, 100, 200...Semiconductor device 12...Semiconductor layer 12A...Top surface 12B...Bottom surface 14,102,202...Cell trench 14A...Intersection region 14B...Non-intersection region 16...Insulating layer 18...Semiconductor substrate 20...Epitaxial layer 22...Drain Electrode 24...First trench 26...Second trench 28,104...Gate electrode 30,106...Field plate electrode 32...Mesh region 34,108...Source contact plug 36...Drift region 38...Body region 40...Source region 42...Source Wiring 44...Contact area 46...Gate insulating part W1, W2...Width S1, S2...Spacing

Claims (14)

  1. 　半導体層と、
    　前記半導体層に形成されるとともにメッシュ状に配置されたセルトレンチであって、平面視で第１方向に延びる複数の第１トレンチと、平面視で前記第１方向と交差する第２方向に延びる複数の第２トレンチとを含み、前記複数の第１トレンチと前記複数の第２トレンチとは互いに交差し、かつ連通している、セルトレンチと、
    　前記半導体層上に形成された絶縁層と、
    　前記複数の第１トレンチ内に前記絶縁層を介してそれぞれ埋め込まれるとともに、前記第１方向に延びる複数のゲート電極と、
    　前記複数の第２トレンチ内に前記絶縁層を介してそれぞれ埋め込まれるとともに、前記第２方向に延びる複数のフィールドプレート電極と
    　を備える、半導体装置。     a semiconductor layer;
    cell trenches formed in the semiconductor layer and arranged in a mesh shape, including a plurality of first trenches extending in a first direction in a plan view and extending in a second direction intersecting the first direction in a plan view; a cell trench including a plurality of second trenches, the plurality of first trenches and the plurality of second trenches intersecting and communicating with each other;
    an insulating layer formed on the semiconductor layer;
    a plurality of gate electrodes each embedded in the plurality of first trenches via the insulating layer and extending in the first direction;
    A semiconductor device comprising: a plurality of field plate electrodes embedded in the plurality of second trenches via the insulating layer and extending in the second direction.
  2. 　前記セルトレンチは、前記複数の第１トレンチと前記複数の第２トレンチとが互いに交差する複数の交差領域と、前記複数の第１トレンチと前記複数の第２トレンチとが互いに交差していない複数の非交差領域とを含み、
    　前記複数の交差領域の各々において、前記複数のゲート電極のうちの１つが、前記複数のフィールドプレート電極のうちの１つと交差しており、
    　前記複数の非交差領域の各々において、前記セルトレンチ内には、前記複数のゲート電極のうちの１つ、または前記フィールドプレート電極のうちの１つが配置されている、請求項１に記載の半導体装置。     The cell trench includes a plurality of intersection regions where the plurality of first trenches and the plurality of second trenches intersect with each other, and a plurality of intersection regions where the plurality of first trenches and the plurality of second trenches do not intersect with each other. and a non-intersecting region of
    In each of the plurality of crossing regions, one of the plurality of gate electrodes intersects with one of the plurality of field plate electrodes,
    The semiconductor according to claim 1, wherein in each of the plurality of non-intersecting regions, one of the plurality of gate electrodes or one of the field plate electrodes is disposed within the cell trench. Device.
  3. 　前記複数の交差領域の各々において、前記セルトレンチ内には、前記複数のフィールドプレート電極のうちの１つが、前記複数のゲート電極のうちの１つの下方に配置されている、請求項２に記載の半導体装置。 3. In each of the plurality of intersection regions, one of the plurality of field plate electrodes is disposed within the cell trench below one of the plurality of gate electrodes. semiconductor devices.
  4. 　前記複数の交差領域の各々において、前記複数のフィールドプレート電極のうちの１つは、前記絶縁層によって前記複数のゲート電極のうちの１つから離隔されている、請求項２または３に記載の半導体装置。 4. The method of claim 2 or 3, wherein in each of the plurality of intersection regions, one of the plurality of field plate electrodes is separated from one of the plurality of gate electrodes by the insulating layer. Semiconductor equipment.
  5. 　前記複数の第１トレンチの各々に含まれる前記交差領域と前記非交差領域とは、前記第１方向に交互に並んでおり、
    　前記複数の第２トレンチの各々に含まれる前記交差領域と前記非交差領域とは、前記第２方向に交互に並んでいる、請求項２または３に記載の半導体装置。     The intersecting regions and the non-intersecting regions included in each of the plurality of first trenches are arranged alternately in the first direction,
    4. The semiconductor device according to claim 2, wherein the intersecting regions and the non-intersecting regions included in each of the plurality of second trenches are arranged alternately in the second direction.
  6. 　前記半導体層は、第１導電型のドリフト領域と、前記ドリフト領域上に形成された第２導電型のボディ領域と、前記ボディ領域上に形成された前記第１導電型のソース領域とを含み、
    　各ゲート電極の少なくとも一部は、前記絶縁層を介して前記ボディ領域と前記第２方向に対向するように配置され、
    　各フィールドプレート電極は、前記セルトレンチの深さ方向において、前記ドリフト領域と前記ボディ領域との界面よりも下方に配置されている、請求項１～５のうちのいずれか一項に記載の半導体装置。     The semiconductor layer includes a drift region of a first conductivity type, a body region of a second conductivity type formed on the drift region, and a source region of the first conductivity type formed on the body region. ,
    At least a portion of each gate electrode is arranged to face the body region in the second direction with the insulating layer interposed therebetween;
    6. The semiconductor according to claim 1, wherein each field plate electrode is disposed below an interface between the drift region and the body region in the depth direction of the cell trench. Device.
  7. 　前記絶縁層上に形成されたソース配線と、
    　前記ソース配線に接続された複数のソースコンタクトプラグと
    　をさらに備え、
    　前記半導体層は、前記メッシュ状に配置されたセルトレンチによって囲まれた複数のメッシュ領域を含み、
    　前記複数のソースコンタクトプラグは、前記複数のメッシュ領域にそれぞれ配置されている、請求項１～６のうちのいずれか一項に記載の半導体装置。     a source wiring formed on the insulating layer;
    further comprising a plurality of source contact plugs connected to the source wiring,
    The semiconductor layer includes a plurality of mesh regions surrounded by the cell trenches arranged in a mesh shape,
    7. The semiconductor device according to claim 1, wherein the plurality of source contact plugs are respectively arranged in the plurality of mesh regions.
  8. 　前記第１方向は、前記第２方向と直交している、請求項１～７のうちのいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first direction is perpendicular to the second direction.
  9. 　前記第１方向は、前記第２方向と直交する方向に対して傾斜している、請求項１～７のうちのいずれか一項に記載の半導体装置。 8. The semiconductor device according to claim 1, wherein the first direction is inclined with respect to a direction perpendicular to the second direction.
  10. 　前記第１方向と前記第２方向とがなす角度は、９０度±１０度の範囲内にある、請求項１～９のうちのいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 9, wherein the angle between the first direction and the second direction is within a range of 90 degrees ±10 degrees.
  11. 　前記複数の第１トレンチは、一定の間隔で互いに平行に配置され、
    　前記複数の第１トレンチが配置される前記間隔は、前記複数の第１トレンチの各々の幅よりも大きい、請求項１～１０のうちのいずれか一項に記載の半導体装置。     The plurality of first trenches are arranged parallel to each other at regular intervals,
    11. The semiconductor device according to claim 1, wherein the interval between the plurality of first trenches is larger than the width of each of the plurality of first trenches.
  12. 　前記複数の第２トレンチは、一定の間隔で互いに平行に配置され、
    　前記複数の第２トレンチが配置される前記間隔は、前記複数の第２トレンチの各々の幅よりも大きい、請求項１～１１のうちのいずれか一項に記載の半導体装置。     The plurality of second trenches are arranged parallel to each other at regular intervals,
    12. The semiconductor device according to claim 1, wherein the interval between the plurality of second trenches is larger than the width of each of the plurality of second trenches.
  13. 　前記複数の第２トレンチの各々の幅は、前記複数の第１トレンチの各々の幅よりも大きい、請求項１～１２のうちのいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the width of each of the plurality of second trenches is larger than the width of each of the plurality of first trenches.
  14. 　各フィールドプレート電極の前記第１方向の寸法は、各ゲート電極の前記第２方向の寸法よりも小さい、請求項１～１３のうちのいずれか一項に記載の半導体装置。 14. The semiconductor device according to claim 1, wherein a dimension of each field plate electrode in the first direction is smaller than a dimension of each gate electrode in the second direction.
PCT/JP2023/026844 2022-09-06 2023-07-21 Semiconductor device WO2024053267A1 (en)

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JP2012059943A (en) * 2010-09-09 2012-03-22 Toshiba Corp Semiconductor device
US20130105886A1 (en) * 2011-11-01 2013-05-02 Alpha And Omega Semiconductor Incorporated Two-dimensional shielded gate transistor device and method of manufacture
US9252263B1 (en) * 2014-07-31 2016-02-02 Infineon Technologies Austria Ag Multiple semiconductor device trenches per cell pitch
JP2021192400A (en) * 2020-06-05 2021-12-16 ローム株式会社 Semiconductor device
JP2022045628A (en) * 2020-09-09 2022-03-22 株式会社東芝 Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012059943A (en) * 2010-09-09 2012-03-22 Toshiba Corp Semiconductor device
US20130105886A1 (en) * 2011-11-01 2013-05-02 Alpha And Omega Semiconductor Incorporated Two-dimensional shielded gate transistor device and method of manufacture
US9252263B1 (en) * 2014-07-31 2016-02-02 Infineon Technologies Austria Ag Multiple semiconductor device trenches per cell pitch
JP2021192400A (en) * 2020-06-05 2021-12-16 ローム株式会社 Semiconductor device
JP2022045628A (en) * 2020-09-09 2022-03-22 株式会社東芝 Semiconductor device

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