WO2024029398A1

WO2024029398A1 - Semiconductor device

Info

Publication number: WO2024029398A1
Application number: PCT/JP2023/027163
Authority: WO
Inventors: 啓示クレンデネン
Original assignee: ローム株式会社
Priority date: 2022-08-01
Filing date: 2023-07-25
Publication date: 2024-02-08

Abstract

A semiconductor device (10) comprises: a semiconductor layer (14) including a peripheral region (40) and an inner region (42); a gate wire (44); and a source wire (34). A plurality of peripheral gate fingers (46) of the gate wire (44) are spaced apart from each other by a plurality of gaps (48) disposed along the outer edge of the inner region (42). The inner region (42) includes a plurality of sub-regions (52) divided by at least two mutually intersecting inner gate fingers (50) of the gate wire (44). A peripheral segment (58) of the source wire (34) is continuous with at least two of a plurality of inner segments (56) that are respectively disposed in the plurality of sub-regions (52). Each of the at least two inner segments (56) is connected to the peripheral segment (58) via a gap (48), among the plurality of gaps (48), that is adjacent to the sub-region (52) in which the inner segment (56) is disposed.

Description

semiconductor equipment

The present disclosure relates to a semiconductor device.

Patent Document 1 discloses a semiconductor device having a trench gate structure in which a gate electrode is embedded in a gate trench. The semiconductor device described in Patent Document 1 includes a gate main surface electrode that integrally includes a gate pad electrode and a gate finger electrode. The gate finger electrode is electrically connected to the gate electrodes of the plurality of trench gate structures via the plurality of gate plug electrodes.

JP 2021-125649 Publication

In a semiconductor device having a trench gate structure, the shorter the length of the gate trench, the lower the resistance of the electrode (eg, gate electrode) embedded in the gate trench. However, resistance and parasitic capacitance caused by wiring layout (eg, gate fingers) to reduce the length of the gate trench may adversely affect the switching characteristics of the semiconductor device.

A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, and including an outer peripheral region and an inner region having a rectangular outer edge surrounded by the outer peripheral region in plan view. , a plurality of gate trenches formed in the semiconductor layer, an insulating layer formed on the semiconductor layer, and a plurality of gate electrodes, each of which is connected to a corresponding one of the plurality of gate trenches. A plurality of gate electrodes and a plurality of field plate electrodes are embedded through an insulating layer, each of which is embedded in a corresponding one of the plurality of gate trenches while being spaced apart from the gate electrode. a plurality of field plate electrodes embedded through the layer, a gate wiring formed on the insulating layer and electrically connected to the plurality of gate electrodes, and a gate wiring formed on the insulating layer and electrically connected to the plurality of gate electrodes; The source wiring is separated from the wiring and electrically connected to the plurality of field plate electrodes. The gate wiring includes a plurality of outer circumference gate fingers arranged in the outer circumference region, the plurality of outer circumference gate fingers spaced apart from each other by a plurality of gaps arranged along the outer edge of the inner region, and the inner region. a plurality of inner gate fingers disposed in the plurality of outer circumferential gate fingers, each inner gate finger being connected to at least one of the plurality of outer circumferential gate fingers. The inner region includes a plurality of sub-regions separated by at least two intersecting inner gate fingers among the plurality of inner gate fingers. The source wiring includes a plurality of inner segments arranged in each of the plurality of sub-regions and an outer peripheral segment arranged in the outer peripheral region. The outer peripheral segment is continuous with at least two of the plurality of inner segments, and each of the at least two inner segments is adjacent to a sub-region of the plurality of gaps in which the inner segment is disposed. It is connected to the outer peripheral segment via a gap.

According to the semiconductor device of the present disclosure, switching characteristics can be improved by reducing resistance and parasitic capacitance caused by wiring layout.

FIG. 1 is a schematic plan view of an exemplary semiconductor device according to the first embodiment. FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line F2-F2 in FIG. FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. FIG. 4 is a schematic plan view of an exemplary semiconductor device according to a comparative example. FIG. 5 is a graph showing the feedback capacitance of a semiconductor device. FIG. 6 is a schematic plan view of an exemplary semiconductor device according to the second embodiment. FIG. 7 is a schematic plan view of an exemplary semiconductor device according to the third embodiment. FIG. 8 is a schematic cross-sectional view of an exemplary semiconductor device for explaining a modification of the trench gate structure.

Hereinafter, some embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. It should be noted that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Further, in order to facilitate understanding, hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the disclosure and should not be considered as limiting the disclosure.

The following detailed description includes devices, systems, and methods that embody example embodiments of the present disclosure. This detailed description is illustrative in nature and is not intended to limit the embodiments of the disclosure or the application and uses of such embodiments.

[First embodiment]
FIG. 1 is a schematic plan view of an exemplary semiconductor device 10 according to the first embodiment. The semiconductor device 10 may be, for example, a MISFET having a trench gate structure. The semiconductor device 10 includes a semiconductor substrate 12, a semiconductor layer 14 formed on the semiconductor substrate 12, a plurality of gate trenches 16 formed in the semiconductor layer 14, and an insulating layer 18 formed on the semiconductor layer 14. include. The Z-axis direction of the mutually orthogonal XYZ axes shown in FIG. 1 is a direction orthogonal to the surface of the semiconductor substrate 12. Note that the term "planar view" used in this specification refers to viewing the semiconductor device 10 from above along the Z-axis direction, unless explicitly stated otherwise.

In this embodiment, the semiconductor substrate 12 may be a Si substrate. Further, the semiconductor layer 14 may be a Si epitaxial layer. In FIG. 1,

numerals

12 and 14 indicate rectangular outer edges of the semiconductor substrate 12 and the semiconductor layer 14. In FIG. The area defined by the outer edge of semiconductor substrate 12 shown in FIG. 1 may correspond to one chip (die). Insulating layer 18 may include at least one of a silicon oxide (SiO ₂ ) layer and a silicon nitride (SiN) layer.

(Example of trench gate structure)
FIG. 2 is a schematic cross-sectional view of the semiconductor device 10 taken along line F2-F2 in FIG. Although FIG. 2 shows a cross section of the gate trench 16 of the first group S1 in the YZ plane, the cross sections of the gate trench 16 of the third group S3 and the gate trench 16 of the fifth group S5 are also similar to FIG. It's fine. Further, the cross sections of the gate trenches 16 of the second group S2 and the gate trenches 16 of the fourth group S4 in the XZ plane may also be similar to those in FIG. 2 . It should be noted that although primarily one gate trench 16 and associated configuration will be described below, such description may be applied to other gate trenches and associated configurations as well.

The semiconductor substrate 12 may include a top surface 12A and a bottom surface 12B opposite to the top surface 12A. The semiconductor substrate 12 may correspond to a drain region of a MISFET. The Z-axis direction is a direction perpendicular to the top surface 12A and bottom surface 12B of the semiconductor substrate 12.

The semiconductor layer 14 includes a drift region 20 formed on the semiconductor substrate (drain region) 12, a body region 22 formed on the drift region 20, and a source region 24 formed on the body region 22.

The drain region formed by the semiconductor substrate 12 may be an n-type region containing n-type impurities. The n-type impurity concentration of the semiconductor substrate 12 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less. The semiconductor substrate 12 may have a thickness of 50 μm or more and 450 μm or less.

The drift region 20 may be an n-type region containing n-type impurities at a lower concentration than the semiconductor substrate (drain region) 12. The n-type impurity concentration of the drift region 20 may be 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁸ cm ^{−3 or} less. Drift region 20 may have a thickness of 1 μm or more and 25 μm or less.

Body region 22 may be a p-type region containing p-type impurities. The p-type impurity concentration of body region 22 may be 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less. Body region 22 may have a thickness of 0.2 μm or more and 1.0 μm or less.

Source region 24 may be an n-type region containing a higher concentration of n-type impurities than drift region 20 . The n-type impurity concentration of the source region 24 may be 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less. The source region 24 may have a thickness of 0.1 μm or more and 1 μm or less.

Note that in this disclosure, the n-type is also referred to as a first conductivity type, and the p-type is also referred to as a second conductivity type. The n-type impurity may be, for example, phosphorus (P) or arsenic (As). Furthermore, the p-type impurity may be, for example, boron (B), aluminum (Al), or the like.

The semiconductor device 10 can further include a drain electrode 26 formed on the bottom surface 12B of the semiconductor substrate 12. The drain electrode 26 is electrically connected to the semiconductor substrate (drain region) 12. Drain electrode 26 may be formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, Cu alloy, and Al alloy. .

The gate trench 16 has an opening in the upper surface 14A of the semiconductor layer 14 and has a depth in the Z-axis direction. Gate trench 16 has sidewalls 16A and bottom walls 16B. Gate trench 16 penetrates source region 24 and body region 22 of semiconductor layer 14 to reach drift region 20 . Therefore, the bottom wall 16B of the gate trench 16 is adjacent to the drift region 20. The gate trench 16 may have a depth of 1 μm or more and 10 μm or less. Note that the depth of the gate trench 16 may correspond to the distance from the top surface 14A of the semiconductor layer 14 to the bottom wall 16B of the gate trench 16 in the Z-axis direction.

The sidewall 16A of the gate trench 16 may extend in the Z-axis direction (direction perpendicular to the upper surface 14A of the semiconductor layer 14), or may be inclined with respect to the Z-axis direction. In one example, the sidewall 16A may be inclined with respect to the Z-axis direction so that the width of the gate trench 16 becomes smaller toward the bottom wall 16B. Further, the bottom wall 16B of the gate trench 16 does not necessarily have to be flat, and may be partially or entirely curved, for example.

The semiconductor device 10 includes a plurality of gate electrodes 28 and a plurality of field plate electrodes 30. Each of the plurality of gate electrodes 28 is embedded in a corresponding one of the plurality of gate trenches 16 with an insulating layer 18 interposed therebetween. Each of the plurality of field plate electrodes 30 is embedded in a corresponding one of the plurality of gate trenches 16 with an insulating layer 18 interposed therebetween while being separated from the gate electrode 28 . Gate electrode 28 may be configured to have a gate voltage applied to it, and field plate electrode 30 may be configured to have a reference voltage (or source voltage) applied to it. Gate electrode 28 and field plate electrode 30 may be formed from conductive polysilicon, in one example.

The gate electrode 28 may include a top surface 28A covered with the insulating layer 18 and a bottom surface 28B opposite to the top surface 28A. Field plate electrode 30 is arranged below gate electrode 28 in gate trench 16 . More specifically, the field plate electrode 30 may be arranged between the bottom surface 28B of the gate electrode 28 and the bottom wall 16B of the gate trench 16. At least a portion of the bottom surface 28B of the gate electrode 28 faces the field plate electrode 30 with the insulating layer 18 in between. Gate electrode 28 further includes a side surface 28C that faces sidewall 16A of gate trench 16.

The upper surface 28A of the gate electrode 28 may be located below the upper surface 14A of the semiconductor layer 14. Further, the bottom surface 28B of the gate electrode 28 is located near the interface between the drift region 20 and the body region 22 in the Z-axis direction, and preferably may be located below the interface. The top surface 28A and bottom surface 28B of the gate electrode 28 may be flat or curved.

The gate electrode 28 and the field plate electrode 30 are surrounded by the insulating layer 18. Field plate electrode 30 may have a smaller width than gate electrode 28. Due to the relatively small width of field plate electrode 30, the thickness of insulating layer 18 surrounding field plate electrode 30 is relatively large.

The semiconductor device 10 may further include a source contact plug 32 that penetrates the insulating layer 18. The source contact plug 32 extends parallel to the gate trenches 16 in plan view, and may be disposed between the two gate trenches 16 (see FIG. 1). The semiconductor device 10 further includes a source wiring 34 formed on the insulating layer 18. The source wiring 34 may be configured to be applied with a reference voltage (or source voltage). The source wiring 34 is connected to the source contact plug 32.

Semiconductor layer 14 may further include contact region 36 . Contact region 36 may be a p-type region containing p-type impurities. The p-type impurity concentration of the contact region 36 is higher than that of the body region 22, and may be 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less. Source contact plug 32 extends through insulating layer 18 and source region 24 to contact contact region 36 . Contact region 36 is electrically connected to source wiring 34 via source contact plug 32 .

The insulating layer 18 includes a gate insulating portion 38 that is interposed between the gate electrode 28 and the semiconductor layer 14 and covers the side wall 16A of the gate trench 16. The gate insulating portion 38 is a part of the insulating layer 18 between the side surface 28C of the gate electrode 28 and the side wall 16A of the gate trench 16. Gate electrode 28 faces semiconductor layer 14 with gate insulating section 38 in between. When a predetermined voltage is applied to the gate electrode 28, a channel is formed in the p-type body region 22 adjacent to the gate insulating portion 38. The semiconductor device 10 can control the flow of electrons in the Z-axis direction between the n-type source region 24 and the n-type drift region 20 via this channel. Further, since the source wiring 34 is electrically connected to the field plate electrode 30, the electric field concentration within the gate trench 16 can be alleviated, and the withstand voltage of the semiconductor device 10 can be improved.

(Planar layout of semiconductor device)
Next, referring again to FIG. 1, the planar layout of the semiconductor device 10 will be described. The semiconductor layer 14 includes an outer peripheral region 40 and an inner region 42 having a rectangular outer edge surrounded by the outer peripheral region 40 in plan view. The boundary between the outer circumferential region 40 and the inner region 42 is indicated by a chain double-dashed line in FIG. The outer edge of the outer peripheral region 40 may coincide with the outer edge of the semiconductor layer 14 in plan view, or may be located inside the outer edge of the semiconductor layer 14. In one example, the outer peripheral region 40 may be located between the outer edge of the semiconductor layer 14 and the inner region 42. The rectangular outer edge of the inner region 42 has two sides extending in the Y-axis direction and two sides extending in the X-axis direction in plan view. Note that in this specification, the Y-axis direction may be referred to as a first direction, and the X-axis direction may be referred to as a second direction. The second direction is a direction perpendicular to the first direction in plan view.

The semiconductor device 10 further includes a gate wiring 44 formed on the insulating layer 18 and electrically connected to the plurality of gate electrodes 28 (see FIG. 2). The source wiring 34 is formed on the insulating layer 18 and is spaced apart from the gate wiring 44. The source wiring 34 may be separated from the gate wiring 44 by a predetermined distance (determined in consideration of breakdown voltage, etc.). As described above, the source wiring 34 is electrically connected to the plurality of field plate electrodes 30 (see FIG. 2).

The gate wiring 44 includes a plurality of outer peripheral gate fingers 46 arranged in the outer peripheral region 40. The plurality of peripheral gate fingers 46 are spaced apart from each other by a plurality of gaps 48 located along the outer edge of the inner region 42 . In the example of FIG. 1, the plurality of peripheral gate fingers 46 may include four

peripheral gate fingers

46A, 46B, 46C, and 46D. More specifically, the plurality of outer circumferential gate fingers 46 include a first outer circumferential gate finger 46A and a second outer circumferential gate finger 46B extending in the Y-axis direction, and a third outer circumferential gate finger 46C and a fourth outer circumferential gate finger extending in the X-axis direction. The finger 46D may be included.

The gate wiring 44 further includes a plurality of inner gate fingers 50 arranged in the inner region 42. Each of the plurality of inner gate fingers 50 is connected to at least one of the plurality of outer circumferential gate fingers 46. The plurality of inner gate fingers 50 may include a first inner gate finger 50A extending in the Y-axis direction and a second inner gate finger 50B extending in the X-axis direction.

The inner region 42 includes a plurality of sub-regions 52 separated by at least two of the plurality of inner gate fingers 50 that intersect with each other. Each of the plurality of sub-regions 52 is adjacent to at least one of the plurality of peripheral gate fingers 46 . In the example of FIG. 1, the first inner gate finger 50A and the second inner gate finger 50B cross each other. The plurality of sub-regions 52 include four

sub-regions

52A, 52B, 52C, and 52D. The four

sub-regions

52A, 52B, 52C, 52D are separated by a first inner gate finger 50A and a second inner gate finger 50B that intersect with each other. Each of the four

sub-regions

52A, 52B, 52C, and 52D is adjacent to the first inner gate finger 50A and the second inner gate finger 50B in plan view. Further, in the example of FIG. 1, four

gaps

48A, 48B, 48C, and 48D are adjacent to four

sub-regions

52A, 52B, 52C, and 52D, respectively.

The first inner gate finger 50A is connected to the third outer gate finger 46C and the fourth outer gate finger 46D. The second inner gate finger 50B is connected to the first outer gate finger 46A and the second outer gate finger 46B.

The gate wiring 44 may further include a gate pad 54. In the example of FIG. 1, gate pad 54 is connected to first inner gate finger 50A and fourth outer gate finger 46D.

The sub-region 52A is surrounded by the first inner gate finger 50A, the second inner gate finger 50B, and the first outer peripheral gate finger 46A in plan view. A gap 48A adjacent to the sub-region 52A is formed between the first outer circumferential gate finger 46A and the third outer circumferential gate finger 46C.

The sub-region 52B is surrounded by the first inner gate finger 50A, the second inner gate finger 50B, and the third outer peripheral gate finger 46C in plan view. A gap 48B adjacent to the sub-region 52B is formed between the third outer circumferential gate finger 46C and the second outer circumferential gate finger 46B.

The sub-region 52C is surrounded by the first inner gate finger 50A, the second inner gate finger 50B, and the fourth outer peripheral gate finger 46D in plan view. A gap 48C adjacent to the sub-region 52C is formed between the fourth outer circumferential gate finger 46D and the first outer circumferential gate finger 46A.

The sub-region 52D is surrounded by the first inner gate finger 50A, the second inner gate finger 50B, the second outer circumferential gate finger 46B, the fourth outer circumferential gate finger 46D, and the gate pad 54 in plan view. A gap 48D adjacent to the sub-region 52D is formed between the second outer circumferential gate finger 46B and the fourth outer circumferential gate finger 46D.

In this way, the outer edge of each sub-region 52 is surrounded by the gate wiring 44 except for the portion adjacent to the gap 48. Each sub-region 52 is rectangular in plan view and has four sides. At least two of the plurality of gaps 48 may be formed over a length at least equal to one side of the sub-region 52 to which the gaps 48 are adjacent. In the example of FIG. 1, three of the plurality of gaps 48 are formed over a length equivalent to one side of the sub-region 52 (52A, 52B, 52C) to which the gaps 48 are adjacent. In other words, each of the

sub-regions

52A, 52B, and 52C is surrounded by the gate wiring 44 on three sides.

The source wiring 34 includes a plurality of inner segments 56 arranged in each of the plurality of sub-regions 52 and an outer peripheral segment 58 arranged in the outer peripheral region 40 . The outer circumferential segment 58 is continuous with at least two of the plurality of inner segments 56. Each of the at least two inner segments 56 is connected to the outer peripheral segment 58 via a gap 48 of the plurality of gaps 48 adjacent to the sub-region 52 in which the inner segment 56 is disposed.

In the example of FIG. 1, the plurality of inner segments 56 includes four

inner segments

56A, 56B, 56C, and 56D arranged in four

sub-regions

52A, 52B, 52C, and 52D, respectively. The outer circumferential segment 58 is continuous with the four

inner segments

56A, 56B, 56C, 56D. Each of the four

inner segments

56A, 56B, 56C, and 56D connects to the outer circumferential segment 58 through a gap 48 adjacent to the sub-region 52 in which the inner segment 56 is disposed among the four

gaps

48A, 48B, 48C, and 48D. It is connected to the. That is, the inner segment 56A is connected to the outer peripheral segment 58 via the gap 48A adjacent to the sub-region 52A in which the inner segment 56A is arranged. Inner segment 56B is connected to outer circumferential segment 58 via gap 48B adjacent to sub-region 52B in which inner segment 56B is located. Inner segment 56C is connected to outer circumferential segment 58 via gap 48C adjacent to sub-region 52C in which inner segment 56C is located. Inner segment 56D is connected to outer circumferential segment 58 via gap 48D adjacent sub-region 52D in which inner segment 56D is located.

In this way, the outer circumferential segment 58 may be continuous with (all of) the plurality of inner segments 56. In this case, each of the plurality of inner segments 56 may be connected to the outer peripheral segment 58 through a plurality of gaps 48 that are adjacent to the sub-region 52 in which the inner segment 56 is arranged.

The outer peripheral segment 58 may extend along the outer edge of the semiconductor layer 14 in plan view, except for the region where the gate pad 54 is arranged.
(Gate trench arrangement)
Each of the plurality of gate trenches 16 can be arranged to intersect one of the plurality of outer circumferential gate fingers 46 or one of the plurality of inner gate fingers 50 in a plan view. The semiconductor device 10 may further include a plurality of gate contact plugs 60. The gate electrode 28 (see FIG. 2) embedded in each gate trench 16 connects one or more inner gates of the plurality of outer circumferential gate fingers 46 via at least one of the plurality of gate contact plugs 60. It may be connected to one of the fingers 50. The gate contact plug 60 can be arranged in a region where each of the plurality of gate trenches 16 intersects one of the plurality of outer peripheral gate fingers 46 or one of the plurality of inner gate fingers 50 in a plan view.

The plurality of gate trenches 16 may include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each gate trench 16 of the first set S1 extends in the Y-axis direction in plan view. Each gate trench 16 of the second set S2 extends in the X-axis direction in plan view. Each gate trench 16 of the first set S1 and the second set S2 intersects with one of the plurality of outer circumferential gate fingers 46 in plan view. The gate trenches 16 of the first set S1 and the second set S2 are arranged across the inner region 42 and the outer peripheral region 40.

The plurality of gate trenches 16 may include a third group S3 of gate trenches 16 and a fourth group S4 of gate trenches 16. Each gate trench 16 of the third group S3 extends in the Y-axis direction in plan view. Each gate trench 16 of the fourth group S4 extends in the X-axis direction in plan view. Each gate trench 16 of the third set S3 and the fourth set S4 intersects with one of the plurality of inner gate fingers 50 in plan view. The gate trenches 16 of the third set S3 and the fourth set S4 are entirely disposed within the inner region 42.

In the example of FIG. 1, the main portions of each gate trench 16 of the first set S1, excluding the ends, are arranged in the sub-region 52B or the sub-region 52C. The main portions of each gate trench 16 of the second set S2, excluding the ends, are arranged in the sub-region 52A or the sub-region 52D. The main portions of each gate trench 16 of the third group S3, excluding the ends, are arranged in the sub-region 52B or the sub-region 52C. The main portions of each gate trench 16 of the fourth set S4, excluding the ends, are arranged in the sub-region 52A or the sub-region 52D.

Optionally, the plurality of gate trenches 16 may include a fifth set S5 of gate trenches 16 (in FIG. 1 only one gate trench 16 is shown, but the fifth set includes a plurality of gate trenches 16). trench 16). Each gate trench 16 of the fifth set S5 extends in the Y-axis direction in a plan view, and intersects with the fourth outer circumferential gate finger 46D in a plan view. The main portion of each gate trench 16 of the fifth set S5, excluding the end portion, is arranged next to the gate pad 54 in the sub-region 52D.

Each set S1, S2, S3, S4, S5 may include one or more gate trenches 16. Some of the plurality of gate trenches 16 included in each set S1, S2, S3, S4, S5 may be arranged parallel to each other at equal intervals. The number of gate trenches included in each set S1, S2, S3, S4, S5 can be determined as appropriate depending on the layout.

The semiconductor device 10 may further include a field plate trench 62. An electrode having the same potential as the field plate electrode 30 (see FIG. 2) can be placed within the field plate trench 62. Field plate trenches 62 can be configured to communicate with aligned gate trenches 16 whose main portions are located in the same sub-region 52. The field plate trench 62 may include a portion 62A that communicates with the gate trench 16 and two portions 62B that extend parallel to the gate trench 16. Portion 62A may extend perpendicularly to gate trench 16. The two portions 62B may be provided on both sides of the gate trench 16 to be communicated with each other. The electrode placed in the field plate trench 62 may be integrally connected to the field plate electrode 30 (see FIG. 2) placed in the gate trench 16 communicating with the field plate trench 62.

FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. 1. FIG. 3 shows a cross section in the YZ plane of two gate trenches 16 (one of the first set S1 and one of the third set S3) located below the inner segment 56C.

A gate electrode 28 and a field plate electrode 30 are arranged within each gate trench 16. Gate electrode 28 is arranged above field plate electrode 30 and connected to gate wiring 44 via gate contact plug 60 .

The semiconductor device 10 may further include a plurality of field plate contact plugs 64. The field plate electrode 30 embedded in each gate trench 16 of the first set S1 has a first end 66 connected to the outer peripheral segment 58 via at least one of the plurality of field plate contact plugs 64; a second end 68 connected to one of the plurality of inner segments 56 (inner segment 56C in the example of FIG. 3) via at least one of the plurality of field plate contact plugs 64; good. The field plate electrode 30 embedded in each gate trench 16 of the third set S3 is connected to one of the plurality of inner segments 56 (FIG. 3) via at least one of the plurality of field plate contact plugs 64. A first end 70 connected to another one of the plurality of inner segments 56 (in the example shown in FIG. In the example, the inner segment 56A) may include a second end 72 connected to the inner segment 56A).

There is no gate electrode 28 above the

ends

66, 68, 70, 72. Since the ends 66, 68, 70, and 72 extend in the Z-axis direction from the bottom of the gate trench 16 to near the opening, they are connected to the source wiring 34 located above via the field plate contact plug 64. be able to.

(Function of semiconductor device)
The operation of the semiconductor device 10 of this embodiment will be explained below.
The gate wiring 44 includes a plurality of outer circumferential gate fingers 46 arranged in the outer circumferential region 40 . The plurality of peripheral gate fingers 46 are spaced apart from each other by a plurality of gaps 48 located along the outer edge of the inner region 42 . If each of the plurality of outer peripheral gate fingers 46 were to be extended and connected to each other so that the gap 48 would be eliminated, the extended portion would generate an extra gate-drain capacitance C _gd . The gate-drain capacitance C _gd corresponds to the feedback capacitance C _rss of the semiconductor device 10 . If the feedback capacitance C _rss is large, the switching speed of the semiconductor device 10 may decrease. Therefore, by arranging the plurality of gaps 48 along the outer edge of the inner region 42, the excess gate-drain capacitance C _gd can be suppressed.

Note that in this embodiment, each of the plurality of gate trenches 16 is arranged to intersect with one of the plurality of outer circumferential gate fingers 46 or one of the plurality of inner gate fingers 50 in plan view. . Therefore, it is possible to connect the gate electrode 28 embedded in each gate trench 16 to the gate wiring 44 even if the gate finger does not extend into the region where the gap 48 is arranged.

Further, the source wiring 34 includes a plurality of inner segments 56 arranged in each of the plurality of sub-regions 52 and an outer peripheral segment 58 arranged in the outer peripheral region 40. The outer peripheral segment 58 is continuous with at least two of the plurality of inner segments 56, and each of the at least two inner segments 56 is connected to a subregion 52 of the plurality of gaps 48 in which the inner segment 56 is disposed. It is connected to the outer peripheral segment 58 via an adjacent gap 48 . Therefore, the resistance caused by the source wiring 34 can be reduced.

Further, gate wiring 44 includes a plurality of inner gate fingers 50 arranged in inner region 42 . Each of the plurality of inner gate fingers 50 is connected to at least one of the plurality of outer circumferential gate fingers 46. Therefore, the area where the gate trench 16 can be placed can be expanded, and the on-resistance R _on of the semiconductor device 10 can be reduced.

(Comparative example semiconductor device)
Hereinafter, the reduction in resistance and parasitic capacitance by the semiconductor device 10 will be described in more detail with reference to FIG. 4. FIG. 4 is a schematic plan view of an exemplary semiconductor device 100 according to a comparative example. In FIG. 4, the same components as those of the semiconductor device 10 shown in FIG. 1 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.

The semiconductor device 100 includes a gate wiring 102 and a source wiring 104 that are different from the gate wiring 44 and source wiring 34 of the semiconductor device 10 of this embodiment.
The gate wiring 102 is formed on the insulating layer 18 and is electrically connected to the plurality of gate electrodes 28 (see FIG. 2). The source wiring 104 is formed on the insulating layer 18 and is spaced apart from the gate wiring 102. The source wiring 104 is electrically connected to a plurality of field plate electrodes 30 (see FIG. 2).

The gate wiring 102 includes a peripheral gate finger 106 arranged in the peripheral region 40 and a gate pad 108 connected to the peripheral gate finger 106. The outer peripheral gate finger 106 extends along the outer edge of the inner region 42, but does not completely surround the inner region 42 in plan view. Peripheral gate fingers 106 are interrupted by a gap 110 located in peripheral region 40 . The outer circumferential gate finger 106 includes a first portion 106A and a second portion 106B extending in the Y-axis direction, and a third portion 106C and a fourth portion 106D extending in the X-axis direction. The first portion 106A is connected between the third portion 106C and the fourth portion 106D. The second portion 106B is connected to the fourth portion 106D. The second portion 106B is not connected to the third portion 106C. A gap 110 is formed between the second portion 106B and the third portion 106C.

The gate wiring 102 further includes a first inner gate finger 112A and a second inner gate finger 112B arranged in the inner region 42. The first inner gate finger 112A extends in the Y-axis direction, and the second inner gate finger 112B extends in the X-axis direction. The first inner gate finger 112A and the second inner gate finger 112B cross each other. First inner gate finger 112A is connected to outer gate finger 106 and gate pad 108. On the other hand, the second inner gate finger 112B is not connected to the outer circumferential gate finger 106, but only to the first inner gate finger 112A. Further, one end of the first inner gate finger 112A and both ends of the second inner gate finger 112B are spaced apart from the outer circumferential gate finger 106. More specifically, one end of the first inner gate finger 112A is spaced apart from the third portion 106C of the outer circumferential gate finger 106 by a gap 114. Additionally, one end of the second inner gate finger 112B is separated from the first portion 106A of the outer circumferential gate finger 106 by a gap 116. The other end of the second inner gate finger 112B is spaced from the second portion 106B of the outer circumferential gate finger 106 by a gap 118. Thus, in the semiconductor device 10 of the comparative example, three

gaps

114, 116, and 118 exist in the inner region 42.

The inner region 42 includes four

sub-regions

120A, 120B, 120C, and 120D separated by a first inner gate finger 112A and a second inner gate finger 112B that intersect with each other. Each of the four

sub-regions

120A, 120B, 120C, and 120D is adjacent to the first inner gate finger 112A and the second inner gate finger 112B in plan view. Gap 110 arranged in outer peripheral region 40 is adjacent only to sub-region 120A. There is no gap in the outer peripheral region 40 adjacent to the

other sub-regions

120B, 120C, and 120D.

The source wiring 104 includes four

inner segments

122A, 122B, 122C, and 122D arranged in four

sub-regions

120A, 120B, 120C, and 120D, respectively, and an outer peripheral segment 124 arranged in the outer peripheral region 40. The outer circumferential segment 124 is continuous only with the inner segment 122A. Inner segment 122A is connected to outer circumferential segment 124 via gap 110 adjacent sub-region 120A in which inner segment 122A is located. The other

inner segments

122B, 122C, 122D are not directly connected to the outer circumferential segment 124, and the inner segment 122B is connected to the inner segment 122A through a gap 114 located in the inner region 42. Inner segment 122C is connected to inner segment 122A via gap 118 located in inner region 42. Inner segment 122D is connected to inner segment 122B via gap 116 located in inner region 42.

The outer peripheral segment 124 extends along the outer edge of the semiconductor layer 14 in plan view, except for the region where the gate pad 108 is arranged. Since outer circumferential segment 124 is directly connected only to inner segment 122A, there is a relatively long distance from a portion of outer circumferential segment 124 located near gate pad 108 to inner segment 122A.

Each of the plurality of gate trenches 16 can be arranged to intersect with the outer peripheral gate finger 106, the first inner gate finger 112A, or the second inner gate finger 112B in plan view.

The plurality of gate trenches 16 include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each gate trench 16 of the first set S1 extends in the Y-axis direction in plan view. Each gate trench 16 of the second set S2 extends in the X-axis direction in plan view. Each gate trench 16 of the first set S1 and the second set S2 intersects with the outer peripheral gate finger 106 in plan view. The gate trenches 16 of the first set S1 and the second set S2 are arranged across the inner region 42 and the outer peripheral region 40.

The plurality of gate trenches 16 include a third group S3 of gate trenches 16 and a fourth group S4 of gate trenches 16. Each gate trench 16 of the third group S3 extends in the Y-axis direction in plan view. Each gate trench 16 of the fourth group S4 extends in the X-axis direction in plan view. Each gate trench 16 of the third set S3 intersects with the second inner gate finger 112B in plan view. Each gate trench 16 of the fourth set S4 intersects with the first inner gate finger 112A in plan view. The gate trenches 16 of the third set S3 and the fourth set S4 are entirely disposed within the inner region 42.

The plurality of gate trenches 16 include the fifth set S5 of gate trenches 16 (although only one gate trench 16 is shown in FIG. 4, it may include a plurality of gate trenches 16). Each gate trench 16 of the fifth set S5 extends in the Y-axis direction in a plan view, and intersects with the outer peripheral gate finger 106 in a plan view. The main portion of each gate trench 16 of the fifth set S5, excluding the end portion, is arranged next to the gate pad 108 in the sub-region 120D.

In this manner, in the semiconductor device 100 of the comparative example, the outer peripheral gate fingers 106 extend to regions that do not intersect with the gate trenches 16. Specifically, the first portion 106A of the outer peripheral gate finger 106 adjacent to the sub-region 120B does not intersect with the gate trench 16. Further, the second portion 106B of the outer peripheral gate finger adjacent to the sub-region 120C does not intersect with the gate trench 16. Since the gate wiring 102 exists in a region that does not intersect with the gate trench 16, an extra gate-drain capacitance C _gd may occur in the semiconductor device 100.

In this regard, in the semiconductor device 10 of this embodiment, the plurality of outer peripheral gate fingers 46 are separated from each other by a plurality of gaps 48 arranged along the outer edge of the inner region 42. By arranging the plurality of gaps 48 along the outer edge of the inner region 42, excess gate-drain capacitance C _gd can be suppressed.

FIG. 5 is a graph showing the feedback capacitance C _rss of the semiconductor devices of the example and the comparative example. The vertical axis represents the feedback capacitance, and the horizontal axis represents the drain-source voltage. Note that the vertical and horizontal axes are logarithmic axes. The example corresponds to the semiconductor device 10 of the first embodiment, and the comparative example corresponds to the semiconductor device 100 shown in FIG. 4. When the drain-source voltage V _ds is relatively large, the feedback capacitance C _rss (=C _gd ) of the example is reduced by about 20% than that of the comparative example.

Furthermore, in the semiconductor device 100 of the comparative example, the outer peripheral segment 124 of the source wiring 104 is directly connected only to the inner segment 122A. There is a relatively long distance from the portion of outer circumferential segment 124 located near gate pad 108 to inner segment 122A, for example. In particular, the distance from the field plate contact plug 64 disposed in the area where the gate trench 16 and the outer peripheral segment 124 intersect, which are included in the fifth set S5 shown in FIG. It is relatively long, about 40% of the length. Therefore, in the semiconductor device 100, the resistance may increase due to the layout of the source wiring 104.

In this regard, in the semiconductor device 10 of the present embodiment, the outer peripheral segment 58 is continuous with at least two of the plurality of inner segments 56, and each of the at least two inner segments 56 is connected to one of the plurality of gaps 48. , is connected to the outer peripheral segment 58 via a gap 48 adjacent to the sub-region 52 in which the inner segment 56 is arranged. Therefore, the resistance caused by the source wiring 34 can be reduced.

Furthermore, in the semiconductor device 100 of the comparative example, one end of the first inner gate finger 112A and both ends of the second inner gate finger 112B are spaced apart from the outer peripheral gate finger 106. The lengths of the first inner gate finger 112A and the second inner gate finger 112B are reduced by the three

gaps

114, 116, 118 located in the inner region 42. This reduces the number of gate trenches 16 that can be placed across the first inner gate finger 112A or the second inner gate finger 112B. In the semiconductor device 100, since the connection between the four

inner segments

122A, 122B, 122C, and 122D is made through the three

gaps

114, 116, and 118 arranged in the inner region 42, the gate trench 16 is arranged. The area of possible active area is reduced. This can increase the on-resistance R _on of the semiconductor device 100.

In this regard, in the semiconductor device 10 of this embodiment, each of the plurality of inner gate fingers 50 is connected to at least one of the plurality of outer peripheral gate fingers 46. Therefore, the area where the gate trench 16 can be placed can be expanded, and the on-resistance R _on of the semiconductor device 10 can be reduced.

In this way, according to the semiconductor device 10 of this embodiment, the resistance and parasitic capacitance caused by the wiring layout can be reduced, and the switching characteristics can be improved.
The semiconductor device 10 of this embodiment has the following advantages.

(1-1) The plurality of outer peripheral gate fingers 46 are separated from each other by a plurality of gaps 48 arranged along the outer edge of the inner region 42. Each of the plurality of inner gate fingers 50 is connected to at least one of the plurality of outer circumferential gate fingers 46. The outer peripheral segment 58 is continuous with at least two of the plurality of inner segments 56, and each of the at least two inner segments 56 is connected to a subregion 52 of the plurality of gaps 48 in which the inner segment 56 is disposed. It is connected to the outer peripheral segment 58 via an adjacent gap 48 .

Therefore, the resistance and parasitic capacitance caused by the wiring layout can be reduced, and the switching characteristics of the semiconductor device 10 can be improved.
(1-2) At least two of the plurality of gaps 48 may be formed over a length at least equivalent to one side of the sub-region 52 to which the gaps 48 are adjacent. By making the length of gap 48 relatively large, resistance and parasitic capacitance due to wiring layout can be further reduced.

(1-3) Each of the plurality of sub-regions 52 may be adjacent to at least one of the plurality of outer peripheral gate fingers 46. Thereby, the gate trench 16 that intersects the outer peripheral gate finger 46 in plan view can be arranged in each sub-region 52.

(1-4) The outer peripheral segment 58 is continuous with the plurality of inner segments 56, and each of the plurality of inner segments 56 is adjacent to the sub-region 52 in which the inner segment 56 is arranged among the plurality of gaps 48. The outer circumferential segment 58 may be connected to the outer circumferential segment 58 via a gap 48 . By connecting all of the plurality of inner segments 56 arranged in the plurality of sub-regions 52 to the outer peripheral segment 58, the resistance and parasitic capacitance caused by the wiring layout can be further reduced.

(1-5) Each of the plurality of gate trenches 16 may be arranged to intersect with one of the plurality of outer circumferential gate fingers 46 or one of the plurality of inner gate fingers 50 in plan view. This makes it possible to connect the gate electrode 28 in each gate trench 16 to the gate wiring 44.

(1-6) The plurality of gate trenches 16 may include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each gate trench 16 of the first group S1 extends in the Y-axis direction (first direction) in plan view, and each gate trench 16 of the second group S2 extends in the X-axis direction (second direction) in plan view. There is. Each of the gate trenches 16 of the first set S1 and the second set S2 may intersect with one of the plurality of outer circumferential gate fingers 46 in plan view. This makes it possible to reduce warpage of the semiconductor substrate 12 during wafer processing, compared to the case where only the gate trenches 16 extending in the same direction are arranged so as to intersect the outer peripheral gate fingers 46.

(1-7) The plurality of gate trenches 16 may further include a third group S3 of gate trenches 16 and a fourth group S4 of gate trenches 16. Each gate trench 16 of the third group S3 extends in the Y-axis direction (first direction) in a plan view, and each gate trench 16 of the fourth group S4 extends in the X-axis direction (second direction) in a plan view. There is. Each gate trench 16 of the third set S3 and the fourth set S4 may intersect with one of the plurality of inner gate fingers 50 in plan view. Thereby, warping of the semiconductor substrate 12 during wafer processing can be reduced compared to the case where only the gate trenches 16 extending in the same direction are arranged so as to intersect the inner gate fingers 50.

(1-8) The field plate electrode 30 embedded in each gate trench 16 of the first set S1 is connected to the outer peripheral segment 58 through at least one of the plurality of field plate contact plugs 64. and a second end 68 connected to one of the plurality of inner segments 56 via at least one of the plurality of field plate contact plugs 64 . The field plate electrode 30 embedded in each gate trench 16 of the third set S3 is connected to one of the plurality of inner segments 56 via at least one of the plurality of field plate contact plugs 64. a first end 70 and a second end 72 connected to another one of the plurality of inner segments 56 via at least one of the plurality of field plate contact plugs 64. good.

Since two ends of the field plate electrode 30 are connected to the source wiring 34, the resistance due to the length of the field plate electrode 30 is reduced compared to the case where only one end is connected. I can do it.

[Second embodiment]
FIG. 6 is a schematic cross-sectional view of an exemplary semiconductor device 200 according to the second embodiment. In FIG. 6, the same components as those of the semiconductor device 10 shown in FIGS. 1 to 3 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.

The semiconductor device 200 may be a MISFET having a trench gate structure as shown in FIG. 2, for example. The semiconductor device 200 includes a gate wiring 202 and a source wiring 204 that are different from the gate wiring 44 and the source wiring 34 of the semiconductor device 10 of the first embodiment.

The gate wiring 202 is formed on the insulating layer 18 and is electrically connected to the plurality of gate electrodes 28 (see FIG. 2). The source wiring 204 is formed on the insulating layer 18 and is spaced apart from the gate wiring 202. The source wiring 204 is electrically connected to a plurality of field plate electrodes 30 (see FIG. 2).

The gate wiring 202 includes a plurality of outer peripheral gate fingers 206 arranged in the outer peripheral region 40. The plurality of peripheral gate fingers 206 are spaced apart from each other by a plurality of gaps 208 located along the outer edge of the inner region 42 . In the example of FIG. 6, the plurality of circumferential gate fingers 206 may include six

circumferential gate fingers

206A, 206B, 206C, 206D, 206E, and 206F. More specifically, the plurality of outer circumferential gate fingers 206 include a first outer circumferential gate finger 206A, a second outer circumferential gate finger 206B, and a third outer circumferential gate finger 206C extending in the Y-axis direction, and a fourth outer circumferential gate finger extending in the X-axis direction. It may include a gate finger 206D and a fifth outer gate finger 206E. The plurality of outer circumferential gate fingers 206 may further include a sixth outer circumferential gate finger 206F that is continuous with a second inner gate finger 210B, which will be described later.

The gate wiring 202 further includes a plurality of inner gate fingers 210 arranged in the inner region 42. Each of the plurality of inner gate fingers 210 is connected to at least one of the plurality of outer circumferential gate fingers 206. The plurality of inner gate fingers 210 may include a first inner gate finger 210A extending in the Y-axis direction, and a second inner gate finger 210B and a third inner gate finger 210C extending in the X-axis direction.

The inner region 42 includes a plurality of sub-regions 212 separated by at least two of the inner gate fingers 210 that intersect with each other. In the example of FIG. 6, the first inner gate finger 210A intersects the second inner gate finger 210B and the third inner gate finger 210C. The plurality of sub-regions 212 include six

sub-regions

212A, 212B, 212C, 212D, 212E, and 212F. Each of the six

sub-regions

212A, 212B, 212C, 212D, 212E, and 212F is adjacent to the first inner gate finger 210A in plan view, and is also adjacent to the second inner gate finger 210B or the third inner gate finger 210C. There is. Further, in the example of FIG. 6, six gaps 208 are adjacent to six

sub-regions

212A, 212B, 212C, 212D, 212E, and 212F, respectively.

The first inner gate finger 210A is connected to the fourth outer gate finger 206D and the fifth outer gate finger 206E. The second inner gate finger 210B is connected to the first outer gate finger 206A and the sixth outer gate finger 206F. Third inner gate finger 210C is connected to second outer circumferential gate finger 206B and third outer circumferential gate finger 206C.

The gate wiring 202 may further include a gate pad 214. In the example of FIG. 6, gate pad 214 is connected to first inner gate finger 210A and fifth outer gate finger 206E.

The sub-region 212A is surrounded by the first inner gate finger 210A, the second inner gate finger 210B, and the first outer peripheral gate finger 206A in plan view. A gap 208A adjacent to the sub-region 212A is formed between the first outer gate finger 206A and the fourth outer gate finger 206D.

The sub-region 212B is surrounded by the first inner gate finger 210A, the second inner gate finger 210B, and the fourth outer circumferential gate finger 206D in plan view. A gap 208B adjacent to the sub-region 212B is formed between the fourth outer circumferential gate finger 206D and the sixth outer circumferential gate finger 206F.

The sub-region 212C is surrounded by the first inner gate finger 210A, the second inner gate finger 210B, and the third inner gate finger 210C in plan view. A gap 208C adjacent to the sub-region 212C is formed between the first outer gate finger 206A and the third outer gate finger 206C.

The sub-region 212D is surrounded by the first inner gate finger 210A, the second inner gate finger 210B, the third inner gate finger 210C, and the second outer peripheral gate finger 206B in plan view. A gap 208D adjacent to the sub-region 212D is formed between the second inner gate finger 210B and the second outer circumferential gate finger 206B.

The sub-region 212E is surrounded by the first inner gate finger 210A, the third inner gate finger 210C, the third outer gate finger 206C, the fifth outer gate finger 206E, and the gate pad 214 in plan view. A gap 208E adjacent to the sub-region 212E is formed between the third outer gate finger 206C and the fifth outer gate finger 206E.

The sub-region 212F is surrounded by the first inner gate finger 210A, the third inner gate finger 210C, and the fifth outer circumferential gate finger 206E in plan view. A gap 208F adjacent to the sub-region 212F is formed between the second outer circumferential gate finger 206B and the fifth outer circumferential gate finger 206E.

One of the six sub-regions 212 (212C) is not adjacent to any of the plurality of outer circumferential gate fingers 206 and is adjacent to the first inner gate finger 210A, the second inner gate finger 210B, and the third inner gate finger 210B. It is adjacent to gate finger 210C. The other five of the six sub-regions 212 (212A, 212B, 212D, 212E, 212F) are adjacent to at least one of the plurality of outer gate fingers 206.

In this way, the outer edge of each sub-region 212 is surrounded by the gate wiring 202 except for the portion adjacent to the gap 208. Each sub-region 212 is rectangular in plan view and has four sides. At least two of the plurality of gaps 208 may be formed over a length at least equal to one side of the sub-region 212 to which the gaps 208 are adjacent. In the example of FIG. 6, four of the plurality of gaps 208 are formed over a length equivalent to one side of the sub-region 212 (212A, 212B, 212C, 212F) to which the gaps 208 are adjacent. In other words, each of the

sub-regions

212A, 212B, 212C, and 212F is surrounded by the gate wiring 202 on three sides.

The source wiring 204 includes a plurality of inner segments 216 arranged in each of the plurality of sub-regions 212 and an outer peripheral segment 218 arranged in the outer peripheral region 40. The outer circumferential segment 218 is continuous with at least two of the plurality of inner segments 216. Each of the at least two inner segments 216 is connected to the outer peripheral segment 58 via a gap 208 of the plurality of gaps 208 that is adjacent to the sub-region 212 in which the inner segment 216 is located.

In the example of FIG. 6, the plurality of inner segments 216 includes six

inner segments

216A, 216B, 216C, 216D, 216E, 216F, respectively located in six

sub-regions

212A, 212B, 212C, 212D, 212E, 212F. . The outer circumferential segment 218 is continuous with six

inner segments

216A, 216B, 216C, 216D, 216E, 216F. Each of the six

inner segments

216A, 216B, 216C, 216D, 216E, 216F is adjacent to the sub-region 212 in which the inner segment 216 is located among the six

gaps

208A, 208B, 208C, 208D, 208E, 208F. It is connected to outer circumferential segment 218 via gap 208 . That is, inner segment 216A is connected to outer circumferential segment 218 via gap 208A adjacent to sub-region 212A in which inner segment 216A is located. Inner segment 216B is connected to outer circumferential segment 218 via gap 208B adjacent sub-region 212B in which inner segment 216B is located. Inner segment 216C is connected to outer circumferential segment 218 via gap 208C adjacent to sub-region 212C in which inner segment 216C is located. Inner segment 216D is connected to outer circumferential segment 218 via gap 208D adjacent sub-region 212D in which inner segment 216D is located. Inner segment 216E is connected to outer circumferential segment 218 via gap 208E adjacent sub-region 212E in which inner segment 216E is located. Inner segment 216F is connected to outer circumferential segment 218 via gap 208F adjacent to sub-region 212F in which inner segment 216F is located.

In this way, the outer circumferential segment 218 may be continuous with (all of) the plurality of inner segments 216. In this case, each of the plurality of inner segments 216 may be connected to the outer peripheral segment 218 through a plurality of gaps 208 that are adjacent to the sub-region 212 in which the inner segment 216 is disposed.

The outer peripheral segment 218 may extend along the outer edge of the semiconductor layer 14 in plan view, except for the region where the gate pad 214 is arranged.
(Gate trench arrangement)
Each of the plurality of gate trenches 16 can be arranged to intersect one of the plurality of outer circumferential gate fingers 206 or one of the plurality of inner gate fingers 210 in plan view. The semiconductor device 200 may further include a plurality of gate contact plugs 60. The gate electrode 28 (see FIG. 2) embedded in each gate trench 16 connects one or more inner gates of the plurality of outer circumferential gate fingers 206 via at least one of the plurality of gate contact plugs 60. It may be connected to one of the fingers 210. The gate contact plug 60 can be arranged in a region where each of the plurality of gate trenches 16 intersects one of the plurality of outer circumferential gate fingers 206 or one of the plurality of inner gate fingers 210 in a plan view.

The plurality of gate trenches 16 may include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each gate trench 16 of the first set S1 extends in the Y-axis direction in plan view. Each gate trench 16 of the second set S2 extends in the X-axis direction in plan view. Each gate trench 16 of the first set S1 and the second set S2 intersects with one of the plurality of outer circumferential gate fingers 206 in a plan view. The gate trenches 16 of the first set S1 and the second set S2 are arranged across the inner region 42 and the outer peripheral region 40.

The plurality of gate trenches 16 may include a third group S3 of gate trenches 16 and a fourth group S4 of gate trenches 16. Each gate trench 16 of the third group S3 extends in the Y-axis direction in plan view. Each gate trench 16 of the fourth group S4 extends in the X-axis direction in plan view. Each gate trench 16 of the third set S3 and the fourth set S4 intersects with one of the plurality of inner gate fingers 210 in plan view. The gate trenches 16 of the third set S3 and the fourth set S4 are entirely disposed within the inner region 42.

In the example of FIG. 6, the main portions of each gate trench 16 of the first set S1, excluding the ends, are arranged in the sub-region 212B or the sub-region 212F. The main portion of each gate trench 16 of the second set S2, excluding the end, is arranged in the sub-region 212A, the sub-region 212D, or the sub-region 212E. The main portions of each gate trench 16 of the third group S3, excluding the ends, are arranged in the sub-region 212B, the sub-region 212C, or the sub-region 212F. The main portions of each gate trench 16 of the fourth set S4, excluding the ends, are arranged in the sub-region 212A, the sub-region 212D, or the sub-region 212E.

Optionally, the plurality of gate trenches 16 may include a fifth set S5 of gate trenches 16 (in FIG. 6 only one gate trench 16 is shown, but the fifth set S5 includes a plurality of gate trenches 16). (may include a gate trench 16). Each gate trench 16 of the fifth set S5 extends in the Y-axis direction in a plan view, and intersects with the fifth outer circumferential gate finger 206E in a plan view. The main portion of each gate trench 16 of the fifth set S5, excluding the end, is arranged next to the gate pad 214 in the sub-region 212E.

The semiconductor device 200 may further include a field plate trench 62. An electrode having the same potential as the field plate electrode 30 (see FIG. 2) can be placed within the field plate trench 62. Field plate trenches 62 can be configured to communicate with aligned gate trenches 16 whose main portions are located in the same sub-region 212. The field plate trench 62 may include a portion 62A that communicates with the gate trench 16 and two portions 62B that extend parallel to the gate trench 16. Portion 62A may extend perpendicularly to gate trench 16. The two portions 62B may be provided on both sides of the gate trench 16 to be communicated with each other. The electrode placed in the field plate trench 62 may be integrally connected to the field plate electrode 30 (see FIG. 2) placed in the gate trench 16 communicating with the field plate trench 62.

The semiconductor device 200 may further include a plurality of field plate contact plugs 64. The field plate electrode 30 (see FIG. 2) embedded in each gate trench 16 is connected to one of the outer circumferential segment 218 or one of the plurality of inner segments 216 via at least one of the plurality of field plate contact plugs 64. It may include two ends connected to.

(Function of semiconductor device)
The operation of the semiconductor device 200 of this embodiment will be described below.
Gate wiring 202 includes a plurality of outer circumferential gate fingers 206 arranged in outer circumferential region 40 . The plurality of peripheral gate fingers 206 are spaced apart from each other by a plurality of gaps 208 located along the outer edge of the inner region 42 . If each of the plurality of outer circumferential gate fingers 206 is extended and connected to each other so that the gap 208 is eliminated, the extended portion causes an extra gate-drain capacitance C _gd . The gate-drain capacitance C _gd corresponds to the feedback capacitance C _rss of the semiconductor device 200. If the feedback capacitance C _rss is large, the switching speed of the semiconductor device 200 may decrease. Therefore, by arranging the plurality of gaps 208 along the outer edge of the inner region 42, the excess gate-drain capacitance C _gd can be suppressed.

Note that in this embodiment, each of the plurality of gate trenches 16 is arranged to intersect with one of the plurality of outer circumferential gate fingers 206 or one of the plurality of inner gate fingers 210 in plan view. . Therefore, it is possible to connect the gate electrode 28 embedded in each gate trench 16 to the gate wiring 202 even if the gate finger does not extend into the region where the gap 208 is arranged.

Further, the source wiring 204 includes a plurality of inner segments 216 arranged in each of the plurality of sub-regions 212 and an outer peripheral segment 218 arranged in the outer peripheral region 40 . The outer circumferential segment 218 is continuous with at least two of the plurality of inner segments 216, and each of the at least two inner segments 216 is connected to a subregion 212 of the plurality of gaps 208 in which the inner segment 216 is disposed. It is connected to outer circumferential segment 218 via an adjacent gap 208 . Therefore, the resistance caused by the source wiring 204 can be reduced.

Further, the gate wiring 202 includes a plurality of inner gate fingers 210 arranged in the inner region 42 . Each of the plurality of inner gate fingers 210 is connected to at least one of the plurality of outer circumferential gate fingers 206. Therefore, the area where the gate trench 16 can be placed can be expanded, and the on-resistance R _on of the semiconductor device 200 can be reduced.

In this way, according to the semiconductor device 200 of this embodiment, the resistance and parasitic capacitance caused by the wiring layout can be reduced, and the switching characteristics can be improved.
The semiconductor device 200 of this embodiment has the following advantages.

(2-1) The plurality of outer peripheral gate fingers 206 are separated from each other by a plurality of gaps 208 arranged along the outer edge of the inner region 42. Each of the plurality of inner gate fingers 210 is connected to at least one of the plurality of outer circumferential gate fingers 206. The outer circumferential segment 218 is continuous with at least two of the plurality of inner segments 216, and each of the at least two inner segments 216 is connected to a subregion 212 of the plurality of gaps 208 in which the inner segment 216 is disposed. It is connected to outer circumferential segment 218 via an adjacent gap 208 .

Therefore, the resistance and parasitic capacitance caused by the wiring layout can be reduced, and the switching characteristics of the semiconductor device 200 can be improved.
(2-2) At least two of the plurality of gaps 208 may be formed over a length at least equivalent to one side of the sub-region 212 to which the gaps 208 are adjacent. By making the length of gap 208 relatively large, resistance and parasitic capacitance due to wiring layout can be further reduced.

(2-3) The outer peripheral segment 218 is continuous with the plurality of inner segments 216, and each of the plurality of inner segments 216 is adjacent to the sub-region 212 in which the inner segment 216 is arranged among the plurality of gaps 208. The outer peripheral segment 218 may be connected to the outer circumferential segment 218 via a gap 208 . By connecting all of the plurality of inner segments 216 arranged in the plurality of sub-regions 212 to the outer peripheral segment 218, the resistance and parasitic capacitance caused by the wiring layout can be further reduced.

(2-4) Each of the plurality of gate trenches 16 may be arranged to intersect with one of the plurality of outer circumferential gate fingers 206 or one of the plurality of inner gate fingers 210 in plan view. This makes it possible to connect the gate electrode 28 in each gate trench 16 to the gate wiring 202.

(2-5) The plurality of gate trenches 16 may include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each gate trench 16 of the first group S1 extends in the Y-axis direction (first direction) in plan view, and each gate trench 16 of the second group S2 extends in the X-axis direction (second direction) in plan view. There is. Each gate trench 16 of the first set S1 and the second set S2 may intersect with one of the plurality of outer circumferential gate fingers 206 in plan view. This makes it possible to reduce warping of the semiconductor substrate 12 during wafer processing, compared to the case where only the gate trenches 16 extending in the same direction are arranged so as to intersect the outer gate fingers 206.

(2-6) The plurality of gate trenches 16 may further include a third group S3 of gate trenches 16 and a fourth group S4 of gate trenches 16. Each gate trench 16 of the third group S3 extends in the Y-axis direction (first direction) in a plan view, and each gate trench 16 of the fourth group S4 extends in the X-axis direction (second direction) in a plan view. There is. Each gate trench 16 of the third set S3 and the fourth set S4 may intersect with one of the plurality of inner gate fingers 210 in plan view. This makes it possible to reduce warping of the semiconductor substrate 12 during wafer processing, compared to the case where only the gate trenches 16 extending in the same direction are arranged so as to intersect the inner gate fingers 210.

(2-7) The field plate electrode 30 embedded in each gate trench 16 is connected to one of the outer circumferential segment 218 or one of the plurality of inner segments 216 via at least one of the plurality of field plate contact plugs 64. It may include two ends connected to. Since two ends of the field plate electrode 30 are connected to the source wiring 204, the resistance due to the length of the field plate electrode 30 is reduced compared to the case where only one end is connected. I can do it.

[Third embodiment]
FIG. 7 is a schematic cross-sectional view of an exemplary semiconductor device 300 according to the third embodiment. In FIG. 7, the same components as those of the semiconductor device 10 shown in FIGS. 1 to 3 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.

The semiconductor device 300 may be a MISFET having a trench gate structure as shown in FIG. 2, for example. The semiconductor device 300 includes a gate wiring 302 and a source wiring 304 that are different from the gate wiring 44 and source wiring 34 of the semiconductor device 10 of the first embodiment.

The gate wiring 302 is formed on the insulating layer 18 and is electrically connected to the plurality of gate electrodes 28 (see FIG. 2). The source wiring 304 is formed on the insulating layer 18 and is spaced apart from the gate wiring 302. The source wiring 304 is electrically connected to a plurality of field plate electrodes 30 (see FIG. 2).

The gate wiring 302 includes a plurality of outer peripheral gate fingers 306 arranged in the outer peripheral region 40. The plurality of peripheral gate fingers 306 are spaced apart from each other by a plurality of gaps 308 located along the outer edge of the inner region 42 . In the example of FIG. 7, the plurality of circumferential gate fingers 306 may include three

circumferential gate fingers

306A, 306B, and 306C. More specifically, the plurality of outer circumferential gate fingers 306 include a first outer circumferential gate finger 306A extending in the Y-axis direction, a second outer circumferential gate finger 306B extending in the X-axis direction, and a portion extending in the Y-axis direction and a portion extending in the X-axis direction. and a third outer circumferential gate finger 306C including a portion extending to The third outer circumferential gate finger 306C may be L-shaped in plan view. Gate pads 314, which will be described later, may be arranged at the corners of the third outer circumferential gate finger 306C so as to overlap with each other.

The gate wiring 302 further includes a plurality of inner gate fingers 310 arranged in the inner region 42. Each of the plurality of inner gate fingers 310 is connected to at least one of the plurality of outer circumferential gate fingers 306. The plurality of inner gate fingers 310 may include a first inner gate finger 310A extending in the Y-axis direction and a second inner gate finger 310B extending in the X-axis direction.

The inner region 42 includes a plurality of sub-regions 312 separated by at least two of the plurality of inner gate fingers 310 that intersect with each other. Each of the plurality of sub-regions 312 is adjacent to at least one of the plurality of peripheral gate fingers 306. In the example of FIG. 7, the first inner gate fingers 310A and the second inner gate fingers 310B intersect with each other. The plurality of sub-regions 312 include four

sub-regions

312A, 312B, 312C, and 312D. The four

sub-regions

312A, 312B, 312C, 312D are separated by a first inner gate finger 310A and a second inner gate finger 310B that intersect with each other. Each of the four

sub-regions

312A, 312B, 312C, and 312D is adjacent to the first inner gate finger 310A and the second inner gate finger 310B in plan view. Further, in the example of FIG. 7, three gaps 308 are adjacent to three

sub-regions

312A, 312B, and 312C, respectively. The sub-region 312D is not adjacent to the gap arranged in the outer peripheral region 40.

The first inner gate finger 310A is connected to the second outer circumferential gate finger 306B. The second inner gate finger 310B is connected to the first outer circumferential gate finger 306A and the third outer circumferential gate finger 306C.

The gate wiring 302 may further include a gate pad 314. In the example of FIG. 7, gate pad 314 is connected to third outer gate finger 306C. The gate pad 314 is arranged so as to overlap a corner of the L-shaped third outer peripheral gate finger 306C. Thereby, in the semiconductor device 300, the gate pad 314 can be placed near the corner of the inner region 42 in plan view.

The sub-region 312A is surrounded by the first inner gate finger 310A, the second inner gate finger 310B, and the first outer peripheral gate finger 306A in plan view. A gap 308A adjacent to the sub-region 312A is formed between the first outer circumferential gate finger 306A and the second outer circumferential gate finger 306B.

The sub-region 312B is surrounded by the first inner gate finger 310A, the second inner gate finger 310B, and the second outer peripheral gate finger 206B in plan view. A gap 308B adjacent to the sub-region 312B is formed between the second outer circumferential gate finger 306B and the third outer circumferential gate finger 306C.

The sub-region 312C is surrounded by the first inner gate finger 310A, the second inner gate finger 310B, and the third outer peripheral gate finger 306C in plan view. A gap 308C adjacent to the sub-region 312C is formed between the first outer gate finger 306A and the third outer gate finger 306C. The sub-region 312C is also adjacent to the gap 316 located in the inner region 42. A gap 316 is formed between the first inner gate finger 310A and the third outer gate finger 306C.

The sub-region 312D is surrounded by the first inner gate finger 310A, the second inner gate finger 310B, the third outer peripheral gate finger 306C, and the gate pad 314 in plan view. As described above, the sub-region 312D is not adjacent to the gap arranged in the outer peripheral region 40. Instead, sub-region 312D is adjacent to gap 316 located in inner region 42.

In this way, the outer edge of each sub-region 312 is surrounded by the gate wiring 302 except for the portions adjacent to the gaps 308 and 316. Each sub-region 312 is rectangular in plan view and has four sides. At least two of the plurality of gaps 308 may be formed over a length at least equal to one side of the sub-region 312 to which the gaps 308 are adjacent. In the example of FIG. 7, three gaps 308A, 308B, and 308C are formed over a length equivalent to one side of the sub-region 312 (312A, 312B, 312C) to which the gaps 308 are adjacent.

The source wiring 304 includes a plurality of inner segments 318 arranged in each of the plurality of sub-regions 312 and an outer peripheral segment 320 arranged in the outer peripheral region 40 . The outer circumferential segment 320 is continuous with at least two of the plurality of inner segments 318. Each of the at least two inner segments 318 is connected to the outer peripheral segment 320 through a gap 308 of the plurality of gaps 308 that is adjacent to the sub-region 312 in which the inner segment 318 is disposed.

In the example of FIG. 7, the plurality of inner segments 318 include a first inner segment 318A, a second inner segment 318B, and a third inner segment 318C arranged in four

sub-regions

312A, 312B, 312C, and 312D, respectively. a fourth inner segment 318D. The outer circumferential segment 320 is continuous with the first inner segment 318A, the second inner segment 318B, and the third inner segment 318C. Each of the first inner segment 318A, the second inner segment 318B, and the third inner segment 318C defines a gap 308 of the plurality of gaps 308A, 308B, and 308C that is adjacent to the sub-region 312 in which the inner segment 318 is disposed. The outer circumferential segment 320 is connected to the outer peripheral segment 320 via the outer peripheral segment 320 . That is, the first inner segment 318A is connected to the outer peripheral segment 320 via the gap 308A adjacent to the sub-region 312A in which the first inner segment 318A is disposed. The second inner segment 318B is connected to the outer circumferential segment 320 via a gap 308B adjacent to the sub-region 312B in which the second inner segment 318B is located. The third inner segment 318C is connected to the outer circumferential segment 320 via a gap 308C adjacent to the sub-region 312C in which the third inner segment 318C is located.

On the other hand, the fourth inner segment 318D is connected to one of the first inner segment 318A, the second inner segment 318B, and the third inner segment 318C in the inner region 42. In the example of FIG. 7, fourth inner segment 318D is connected to third inner segment 318C via gap 316 located in inner region 42. In the example of FIG.

The outer peripheral segment 320 may extend along the outer edge of the semiconductor layer 14 in plan view, except for the region where the gate pad 314 is arranged.
(Gate trench arrangement)
Each of the plurality of gate trenches 16 can be arranged to intersect one of the plurality of outer circumferential gate fingers 306 or one of the plurality of inner gate fingers 310 in plan view. The semiconductor device 300 may further include a plurality of gate contact plugs 60. The gate electrode 28 (see FIG. 2) embedded in each gate trench 16 connects to one or more inner gates of the plurality of outer circumferential gate fingers 306 via at least one of the plurality of gate contact plugs 60. It may be connected to one of the fingers 310. The gate contact plug 60 can be arranged in a region where each of the plurality of gate trenches 16 intersects one of the plurality of outer circumferential gate fingers 306 or one of the plurality of inner gate fingers 310 in a plan view.

The plurality of gate trenches 16 may include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each gate trench 16 of the first set S1 extends in the Y-axis direction in plan view. Each gate trench 16 of the second set S2 extends in the X-axis direction in plan view. Each gate trench 16 of the first set S1 and the second set S2 intersects with one of the plurality of outer circumferential gate fingers 306 in a plan view. The gate trenches 16 of the first set S1 and the second set S2 are arranged across the inner region 42 and the outer peripheral region 40.

The plurality of gate trenches 16 may include a third group S3 of gate trenches 16 and a fourth group S4 of gate trenches 16. Each gate trench 16 of the third group S3 extends in the Y-axis direction in plan view. Each gate trench 16 of the fourth group S4 extends in the X-axis direction in plan view. Each gate trench 16 of the third set S3 and the fourth set S4 intersects with one of the plurality of inner gate fingers 310 in plan view. The gate trenches 16 of the third set S3 and the fourth set S4 are entirely disposed within the inner region 42.

In the example of FIG. 7, the main portions of each gate trench 16 of the first set S1, excluding the ends, are arranged in the sub-region 312B or the sub-region 312C. The main portions of each gate trench 16 of the second set S2, excluding the ends, are arranged in the sub-region 312A or the sub-region 312D. The main portions of each gate trench 16 of the third set S3, excluding the ends, are arranged in the sub-region 312B or the sub-region 312C. The main portions of each gate trench 16 of the fourth set S4, excluding the ends, are arranged in the sub-region 312A or the sub-region 312D.

Optionally, the plurality of gate trenches 16 may include a fifth set S5 of gate trenches 16. Each gate trench 16 of the fifth set S5 extends in the Y-axis direction in a plan view, and intersects with the third outer peripheral gate finger 306C in a plan view. The main portion of each gate trench 16 of the fifth set S5, excluding the end portion, is arranged next to the gate pad 314 in the sub-region 312D.

The semiconductor device 300 may further include a field plate trench 62. An electrode having the same potential as the field plate electrode 30 (see FIG. 2) can be placed within the field plate trench 62. Field plate trenches 62 can be configured to communicate with aligned gate trenches 16 whose main portions are located in the same sub-region 312. The field plate trench 62 may include a portion 62A that communicates with the gate trench 16 and two portions 62B that extend parallel to the gate trench 16. Portion 62A may extend perpendicularly to gate trench 16. The two portions 62B may be provided on both sides of the gate trench 16 to be communicated with each other. The electrode placed in the field plate trench 62 may be integrally connected to the field plate electrode 30 (see FIG. 2) placed in the gate trench 16 communicating with the field plate trench 62.

The semiconductor device 300 may further include a plurality of field plate contact plugs 64. The field plate electrode 30 (see FIG. 2) embedded in each gate trench 16 is connected to one of the outer circumferential segment 320 or one of the plurality of inner segments 318 via at least one of the plurality of field plate contact plugs 64. It may include two ends connected to.

(Function of semiconductor device)
The operation of the semiconductor device 300 of this embodiment will be described below.
Gate wiring 302 includes a plurality of outer peripheral gate fingers 306 arranged in outer peripheral region 40 . The plurality of peripheral gate fingers 306 are spaced apart from each other by a plurality of gaps 308 located along the outer edge of the inner region 42 . If each of the plurality of outer peripheral gate fingers 306 were to be extended and connected to each other so that the gap 308 is eliminated, the extended portion would generate an extra gate-drain capacitance C _gd . The gate-drain capacitance C _gd corresponds to the feedback capacitance C _rss of the semiconductor device 300. If the feedback capacitance C _rss is large, the switching speed of the semiconductor device 300 may decrease. Therefore, by arranging the plurality of gaps 308 along the outer edge of the inner region 42, the excess gate-drain capacitance C _gd can be suppressed.

Note that in this embodiment, each of the plurality of gate trenches 16 is arranged to intersect with one of the plurality of outer circumferential gate fingers 306 or one of the plurality of inner gate fingers 310 in plan view. . Therefore, it is possible to connect the gate electrode 28 embedded in each gate trench 16 to the gate wiring 302 even if the gate finger does not extend into the region where the gap 308 is arranged.

Further, the source wiring 304 includes a plurality of inner segments 318 arranged in each of the plurality of sub-regions 312 and an outer peripheral segment 320 arranged in the outer peripheral region 40 . The outer circumferential segment 320 is continuous with at least two of the plurality of inner segments 318, and each of the at least two inner segments 318 is connected to a subregion 312 of the plurality of gaps 308 in which the inner segment 318 is disposed. It is connected to the peripheral segment 320 via an adjacent gap 308 . Therefore, the resistance caused by the source wiring 304 can be reduced.

Furthermore, gate wiring 302 includes a plurality of inner gate fingers 310 disposed in inner region 42 . Each of the plurality of inner gate fingers 310 is connected to at least one of the plurality of outer circumferential gate fingers 306. Therefore, the area where the gate trench 16 can be placed can be expanded, and the on-resistance R _on of the semiconductor device 300 can be reduced.

In this way, according to the semiconductor device 300 of this embodiment, the resistance and parasitic capacitance caused by the wiring layout can be reduced, and the switching characteristics can be improved.
The semiconductor device 300 of this embodiment has the following advantages.

(3-1) The plurality of outer peripheral gate fingers 306 are separated from each other by a plurality of gaps 308 arranged along the outer edge of the inner region 42. Each of the plurality of inner gate fingers 310 is connected to at least one of the plurality of outer circumferential gate fingers 306. The outer circumferential segment 320 is continuous with at least two of the plurality of inner segments 318, and each of the at least two inner segments 318 is connected to a subregion 312 of the plurality of gaps 308 in which the inner segment 318 is disposed. It is connected to the peripheral segment 320 via an adjacent gap 308 .

Therefore, the resistance and parasitic capacitance caused by the wiring layout can be reduced, and the switching characteristics of the semiconductor device 300 can be improved.
(3-2) At least two of the plurality of gaps 308 may be formed over a length at least equivalent to one side of the sub-region 312 to which the gaps 308 are adjacent. By making the length of gap 308 relatively large, resistance and parasitic capacitance due to wiring layout can be further reduced.

(3-3) Each of the plurality of sub-regions 312 may be adjacent to at least one of the plurality of outer peripheral gate fingers 306. Thereby, the gate trench 16 that intersects the outer peripheral gate finger 306 in plan view can be arranged in each sub-region 52.

(3-4) Each of the plurality of gate trenches 16 may be arranged to intersect with one of the plurality of outer circumferential gate fingers 306 or one of the plurality of inner gate fingers 310 in plan view. This makes it possible to connect the gate electrode 28 in each gate trench 16 to the gate wiring 302.

(3-5) The plurality of gate trenches 16 may include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each gate trench 16 of the first group S1 extends in the Y-axis direction (first direction) in plan view, and each gate trench 16 of the second group S2 extends in the X-axis direction (second direction) in plan view. There is. Each of the gate trenches 16 of the first set S1 and the second set S2 may intersect with one of the plurality of outer circumferential gate fingers 306 in plan view. Thereby, warping of the semiconductor substrate 12 during wafer processing can be reduced compared to a case where only the gate trenches 16 extending in the same direction are arranged so as to intersect the outer peripheral gate fingers 306.

(3-6) The plurality of gate trenches 16 may further include a third group S3 of gate trenches 16 and a fourth group S4 of gate trenches 16. Each gate trench 16 of the third group S3 extends in the Y-axis direction (first direction) in a plan view, and each gate trench 16 of the fourth group S4 extends in the X-axis direction (second direction) in a plan view. There is. Each gate trench 16 of the third set S3 and the fourth set S4 may intersect with one of the plurality of inner gate fingers 310 in plan view. Thereby, warping of the semiconductor substrate 12 during wafer processing can be reduced compared to the case where only the gate trenches 16 extending in the same direction are arranged so as to intersect the inner gate fingers 310.

(3-7) The field plate electrode 30 embedded in each gate trench 16 is connected to one of the outer circumferential segment 320 or one of the plurality of inner segments 318 via at least one of the plurality of field plate contact plugs 64. It may include two ends connected to. Since two ends of the field plate electrode 30 are connected to the source wiring 304, the resistance due to the length of the field plate electrode 30 is reduced compared to the case where only one end is connected. I can do it.

[Example of change in trench gate structure]
FIG. 8 is a schematic cross-sectional view of an exemplary semiconductor device 400 for explaining a modification of the trench gate structure.

The semiconductor device 400 may be a MISFET using a SiC substrate. The semiconductor device 400 includes a semiconductor substrate 402, a semiconductor layer 404 formed on the semiconductor substrate 402, a plurality of gate trenches 406 formed in the semiconductor layer 404, and a plurality of source trenches 408 formed in the semiconductor layer 404. including. Gate trenches 406 and source trenches 408 may be arranged alternately.

Semiconductor substrate 402 may be a SiC substrate. Furthermore, the semiconductor layer 404 may be a SiC epitaxial layer.
The semiconductor substrate 402 may include a top surface 402A and a bottom surface 402B opposite the top surface 402A. The semiconductor substrate 402 may correspond to a drain region of a MISFET. The Z-axis direction is a direction perpendicular to the top surface 402A and bottom surface 402B of the semiconductor substrate 402.

The semiconductor layer 404 includes a drift region 410 formed on a semiconductor substrate (drain region) 402, a body region 412 formed on the drift region 410, and a source region 414 formed on the body region 412.

The drain region formed by the semiconductor substrate 402 may be an n-type region containing n-type impurities. The n-type impurity concentration of the semiconductor substrate 402 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less. The semiconductor substrate 402 may have a thickness of 5 μm or more and 300 μm or less.

Drift region 410 may be an n-type region containing n-type impurities at a lower concentration than semiconductor substrate (drain region) 402. The n-type impurity concentration of the drift region 410 may be 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁸ cm ^{−3 or} less. Drift region 410 may have a thickness of 5 μm or more and 20 μm or less.

The drift region 410 is formed on the semiconductor substrate 402 and has a relatively low concentration first concentration region 416 (low concentration region), and is formed on the first concentration region 416 and has a higher concentration than the first concentration region 416. A second concentration region 418 (high concentration region) may be included. The n-type impurity concentration of the first concentration region 416 may be 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁷ cm ^{−3 or} less. The n-type impurity concentration of the second concentration region 418 may be greater than or equal to 1×10 ¹⁶ cm ⁻³ and less than or equal to 1×10 ¹⁸ cm ⁻³ .

Although not shown, a buffer region may be formed between the semiconductor substrate 402 and the drift region 410. The buffer region may have a concentration gradient in which the n-type impurity concentration gradually decreases from the n-type impurity concentration of the semiconductor substrate 402 to the n-type impurity concentration of the drift region 410.

Body region 412 may be a p-type region containing p-type impurities. The p-type impurity concentration of body region 412 may be 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less.
Source region 414 may be an n-type region containing n-type impurities at a higher concentration than second concentration region 418 . The n-type impurity concentration of the source region 414 may be greater than or equal to 1×10 ¹⁸ cm ⁻³ and less than or equal to 1×10 ²¹ cm ⁻³ .

Note that in this disclosure, the n-type is also referred to as a first conductivity type, and the p-type is also referred to as a second conductivity type. The n-type impurity may be, for example, phosphorus (P) or arsenic (As). Furthermore, the p-type impurity may be, for example, boron (B) or aluminum (Al).

The semiconductor device 400 may further include a drain electrode 420 formed on the bottom surface 402B of the semiconductor substrate 402. Drain electrode 420 is electrically connected to semiconductor substrate (drain region) 402. Drain electrode 420 may be formed of at least one of titanium (Ti), nickel (Ni), palladium (Pd), gold (Au), and silver (Ag).

The gate trench 406 has an opening in the upper surface 404A of the semiconductor layer 404 and has a depth in the Z-axis direction. The gate trench 406 may have a depth of 0.1 μm or more and 3 μm or less. Gate trench 406 has side walls 406A and bottom wall 406B. Gate trench 406 penetrates source region 414 and body region 412 of semiconductor layer 404 . The semiconductor layer 404 may further include a first well region 422 formed between the second concentration region 418 and the sidewalls 406A and bottom walls 406B of the gate trench 406. The first well region 422 may be a p-type region containing p-type impurities at a higher concentration than the body region 412. The p-type impurity concentration of the first well region 422 may be 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁸ cm ^{−3 or} less.

The source trench 408 has an opening in the upper surface 404A of the semiconductor layer 404 and has a depth in the Z-axis direction. Source trench 408 may have a depth of 0.5 μm or more and 10 μm or less. Source trench 408 has sidewalls 408A and bottom wall 408B. Source trench 408 penetrates source region 414 and body region 412 of semiconductor layer 404 . Semiconductor layer 404 may further include a second well region 424 formed between second concentration region 418 and sidewall 408A and bottom wall 408B of source trench 408. The second well region 424 may be a p-type region containing p-type impurities at a higher concentration than the body region 412. The p-type impurity concentration of the second well region 424 may be 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁸ cm ^{−3 or} less.

The semiconductor device 400 further includes an insulating layer 426 formed on the semiconductor layer 404 and a plurality of gate electrodes 428. Each of the plurality of gate electrodes 428 is embedded in a corresponding one of the plurality of gate trenches 406 with an insulating layer 426 interposed therebetween.

The semiconductor device 400 further includes a plurality of source electrodes 430. Each of the plurality of source electrodes 430 is embedded in a corresponding one of the plurality of source trenches 408 with an insulating layer 426 interposed therebetween.

The gate electrode 428 may be configured to have a gate voltage applied to it, and the source electrode 430 may be configured to have a reference voltage (or source voltage) applied to it. Gate electrode 428 and source electrode 430 may be formed from conductive polysilicon, in one example.

The semiconductor device 400 may further include a plurality of gate contact electrodes 432. The plurality of gate contact electrodes 432 cover a portion of the upper surface 404A of the semiconductor layer 404, and are connected to the plurality of gate electrodes 428, respectively.

The semiconductor device 400 may further include an insulating layer 434 formed on the upper surface 404A of the semiconductor layer 404. The insulating layer 434 is formed thicker than the gate contact electrode 432. The insulating layer 434 has a plurality of gate openings 434A that expose the plurality of gate contact electrodes 432, respectively.

The semiconductor device 400 may further include a gate wiring 436 formed on the insulating layer 434. Gate wiring 436 includes a barrier layer 438 formed on insulating layer 434 and a wiring layer 440 formed on barrier layer 438. Barrier layer 438 may include at least one of a Ti layer and a TiN layer. The barrier layer 438 may have a thickness of 10 nm or more and 500 nm or less. The wiring layer 440 may include at least one of a Cu layer, an Al layer, an AlCu alloy layer, an AlSi alloy layer, and an AlSiCu alloy layer. The wiring layer 440 may have a thickness of 0.5 μm or more and 10 μm or less.

The gate trench 406 of the semiconductor device 400 using SiC as described above can be arranged in the planar layout of the semiconductor device 10 of the first embodiment shown in FIG. Specifically, the gate trench 406 shown in FIG. 8 can be placed at the position of the gate trench 16 shown in FIG. In that case, the gate wiring 436 corresponds to the gate wiring 44 shown in FIG. 1, and therefore, FIG. 8 shows a cross section in a region where the gate wiring 436 formed as a gate finger is arranged. The source electrode 430 can be electrically connected to a source wiring (not shown) corresponding to the source wiring 34 shown in FIG. Furthermore, it is also possible to arrange the gate trench 406 of the semiconductor device 400 according to the planar layout of the semiconductor device 200 of the second embodiment shown in FIG. 6 or the planar layout of the semiconductor device 300 of the third embodiment shown in FIG. be. Thereby, even in the semiconductor device 400 using SiC, the resistance and parasitic capacitance caused by the wiring layout can be reduced, and the switching characteristics can be improved.

[Other change examples]
Each of the above embodiments and modified examples can be modified and implemented as follows.
- The length of each gate trench 16 in the first group S1 may be the same as or different from the length of each gate trench 16 in the third group S3. Similarly, the length of each gate trench 16 in the second set S2 may be the same as or different from the length of each gate trench 16 in the fourth set S4.

- The number of the plurality of inner gate fingers 50 may be four or more.
- Some of the plurality of gaps 48 may be formed over a small length that is shorter than one side of the sub-region 52 to which the gap 48 is adjacent.

- A structure in which the conductivity type of each region in the semiconductor layer 14 is reversed may be adopted. That is, the p-type region may be made into an n-type region, and the n-type region may be made into a p-type region.
- An additional wiring structure may be formed on the layer including the source wiring 34 and the gate wiring 44.

- An additional electrode structure may be formed outside the outer peripheral segment 58 of the source wiring 34 in plan view.
- In the example shown in FIG. 6, the plurality of outer circumferential gate fingers 206 may not include the sixth outer circumferential gate finger 206F. In this case, one gap may be formed between the second outer circumferential gate finger 206B and the fourth outer circumferential gate finger 206D.

One or more of the various examples described herein can be combined to the extent not technically inconsistent.
As used herein, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

As used in this disclosure, the term "on" includes the meanings of "on" and "over" unless the context clearly dictates otherwise. Thus, the phrase "the first layer is formed on the second layer" refers to the fact that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other embodiments. It is contemplated that the first layer may be placed above the second layer without contacting the second layer. That is, the term "on" does not exclude structures in which other layers are formed between the first layer and the second layer.

"Vertical", "horizontal", "above", "downward", "above", "below", "front", "rear", "portrait", "lateral", "left", as used in this disclosure; Directional terms such as "right", "front", "rear", etc. depend on the particular orientation of the device as described and illustrated. Various alternative orientations may be envisioned in this disclosure, and therefore, these directional terms should not be construed narrowly.

For example, the Z-axis direction used in the present disclosure does not necessarily need to be a vertical direction, nor does it need to completely coincide with the vertical direction. For example, the X-axis direction may be a vertical direction, or the Y-axis direction may be a vertical direction.

[Additional notes]
The technical ideas that can be understood from the above embodiment and each modification example will be described below. It should be noted that, for the purpose of assisting understanding rather than with the intention of limiting, the corresponding reference numerals in the embodiments for the configurations described in the supplementary notes are shown in parentheses. The symbols are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the symbols.

(Appendix A1)
a semiconductor substrate (12);
A semiconductor layer (14) formed on the semiconductor substrate (12) and including an outer peripheral region (40) and an inner region (42) having a rectangular outer edge surrounded by the outer peripheral region (40) in plan view. and,
a plurality of gate trenches (16) formed in the semiconductor layer (14);
an insulating layer (18) formed on the semiconductor layer (14);
a plurality of gate electrodes (28), each of which is embedded in a corresponding one of the plurality of gate trenches (16) via the insulating layer (18); and,
a plurality of field plate electrodes (30) each connected to a corresponding one of the plurality of gate trenches (16) and spaced apart from the gate electrode (28) through the insulating layer (18); a plurality of embedded field plate electrodes (30);
a gate wiring (44) formed on the insulating layer (18) and electrically connected to the plurality of gate electrodes (28);
a source wiring (34) formed on the insulating layer (18), separated from the gate wiring (44), and electrically connected to the plurality of field plate electrodes (30);
The gate wiring (44) is
a plurality of circumferential gate fingers (46) disposed in the outer circumferential region (40), the plurality of circumferential gate fingers (46) being spaced apart from each other by a plurality of gaps (48) disposed along the outer edge of the inner region (42); Gate finger (46) and
a plurality of inner gate fingers (50) disposed in the inner region (42), each inner gate finger being connected to at least one of the plurality of outer circumferential gate fingers (46); (50) and
The inner region (42) includes a plurality of sub-regions (52) separated by at least two intersecting inner gate fingers (50) among the plurality of inner gate fingers (50),
The source wiring (34) is
a plurality of inner segments (56) respectively arranged in the plurality of sub-regions (52);
a peripheral segment (58) disposed in the peripheral region (40);
The outer circumferential segment (58) is continuous with at least two of the plurality of inner segments (56), and each of the at least two inner segments (56) has one of the plurality of gaps (48). A semiconductor device connected to the outer peripheral segment (58) via a gap (48) adjacent to the sub-region (52) in which the inner segment (56) is arranged.

(Appendix A2)
Each sub-region (52) is rectangular in plan view and has four sides,
The semiconductor according to appendix A1, wherein at least two of the plurality of gaps (48) are formed over a length at least equivalent to one side of an adjacent sub-region (52). Device.

(Additional note 3)
The semiconductor device according to appendix A1 or A2, wherein each of the plurality of sub-regions (52) is adjacent to at least one of the plurality of outer peripheral gate fingers (46).

(Appendix A4)
The outer peripheral segment (58) is continuous with the plurality of inner segments (56), and each of the plurality of inner segments (56) is connected to the inner segment (56) of the plurality of gaps (48). The semiconductor device according to any one of appendices A1 to A3, wherein the semiconductor device is connected to the outer peripheral segment (58) via a gap (48) adjacent to a sub-region (52) in which a semiconductor device is arranged.

(Appendix A5)
The rectangular outer edge of the inner region (42) has two sides extending in a first direction in plan view and two sides extending in a second direction orthogonal to the first direction in plan view. ,
The plurality of inner gate fingers (50) include a first inner gate finger (50A) extending in the first direction and a second inner gate finger (50B) extending in the second direction. A semiconductor device according to any one of the above.

(Appendix A6)
The plurality of sub-regions (52) include four sub-regions (52A, 52B, 52C, 52D), and each of the four sub-regions (52A, 52B, 52C, 52D) is different from the first one in plan view. The semiconductor device according to appendix 5, which is adjacent to the inner gate finger (50A) and the second inner gate finger (50B).

(Appendix A7)
The plurality of inner segments (56) include four inner segments (56A, 56B, 56C, 56D) arranged in the four sub-regions (52A, 52B, 52C, 52D), respectively,
The plurality of gaps (48) include four gaps (48A, 48B, 48C, 48C) adjacent to the four sub-regions (52A, 52B, 52C, 52D), respectively,
The outer peripheral segment (58) is continuous with the four inner segments (56A, 56B, 56C, 56D), and each of the four inner segments (56A, 56B, 56C, 56D) is connected to the four gaps. (48A, 48B, 48C, 48C), which is connected to the outer peripheral segment (58) through a gap (48) adjacent to the sub-region (52) in which the inner segment (56) is arranged. The semiconductor device according to A6.

(Appendix A8)
The plurality of outer circumferential gate fingers (46) include a first outer circumferential gate finger (46A) and a second outer circumferential gate finger (46B) extending in the first direction, and a third outer circumferential gate finger (46C) extending in the second direction. and a fourth outer peripheral gate finger (46D),
The first inner gate finger (50A) is connected to the third outer gate finger (46C) and the fourth outer gate finger (46D),
The second inner gate finger (50B) is connected to the first outer circumferential gate finger (46A) and the second outer circumferential gate finger (46B), according to any one of appendices A5 to A7. Semiconductor equipment.

(Appendix A9)
The plurality of inner segments (318) include first, second, third, and fourth inner segments (318A, 318B, 318C, 318D) arranged in the four sub-regions (312), respectively;
the outer circumferential segment (320) is continuous with the first, second, and third inner segments (318A, 318B, 318C);
Each of the first, second, and third inner segments (318A, 318B, 318C) is adjacent to a sub-region (312) in which the inner segment (318) is located in the plurality of gaps (308). connected to the outer peripheral segment (320) via a gap (308),
The fourth inner segment (318D) is connected to one of the first, second and third inner segments (318A, 318B, 318C) in the inner region (42), according to appendix A6 or A7. The semiconductor device described in .

(Appendix A10)
The gate wiring (302) includes a gate pad (314),
The plurality of outer circumferential gate fingers (306) include a first outer circumferential gate finger (306A) extending in the first direction, a second outer circumferential gate finger (306B) extending in the second direction, and a portion extending in the first direction. and a third outer peripheral gate finger (306C) including a portion extending in the second direction,
the first inner gate finger (310A) is connected to the second outer circumferential gate finger (306B);
The second inner gate finger (310B) is connected to the first outer gate finger (306A) and the third outer gate finger (306C),
The semiconductor device according to appendix A9, wherein the gate pad (314) is connected to the third outer peripheral gate finger (306C).

(Appendix A11)
The rectangular outer edge of the inner region (42) has two sides extending in a first direction in plan view and two sides extending in a second direction orthogonal to the first direction in plan view,
The plurality of inner gate fingers (210) include a first inner gate finger (210A) extending in the first direction, a second inner gate finger (210B) extending in the second direction, and a second inner gate finger (210B) extending in the second direction. 3 inner gate fingers (210C);
The semiconductor device according to appendix A1 or A2, wherein the first inner gate finger (210A) intersects the second inner gate finger (210B) and the third inner gate finger (210C).

(Appendix A12)
The plurality of sub-regions (212) include six sub-regions (212A, 212B, 212C, 212D, 212E, 212F), and each of the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F) is adjacent to the first inner gate finger (210A) in plan view, and is adjacent to the second inner gate finger (210B) or the third inner gate finger (210C) in plan view, according to appendix A11. The semiconductor device described.

(Appendix A13)
The plurality of inner segments (216) include six inner segments (216A, 216B, 216C, 216D, 216E, 216F) arranged in the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F), respectively. including;
The plurality of gaps (208) include six gaps (208A, 208B, 208C, 208D, 208E, 208F) adjacent to the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F),
The outer peripheral segment (218) is continuous with the six inner segments (216A, 216B, 216C, 216D, 216E, 216F); of the six gaps (208A, 208B, 208C, 208D, 208E, 208F) through the gap (208) adjacent to the sub-region (212) in which the inner segment (216) is located The semiconductor device according to appendix A12, which is connected to the outer peripheral segment (218).

(Appendix A14)
One of the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F) is not adjacent to any of the plurality of outer peripheral gate fingers (206) and is 2, and the semiconductor device according to appendix A12 or A13, which is adjacent to the third inner gate finger (210A, 210B, 210C).

(Appendix A15)
Each of the plurality of gate trenches (16) is arranged to intersect with one of the plurality of outer peripheral gate fingers (46) or one of the plurality of inner gate fingers (50) in plan view. The semiconductor device according to any one of Appendices A1 to A14.

(Appendix A16)
further comprising a plurality of gate contact plugs (60),
The gate electrode (28) embedded in each gate trench (16) is connected to one of the plurality of outer peripheral gate fingers (46) via at least one of the plurality of gate contact plugs (60). Alternatively, the semiconductor device according to any one of Appendices A1 to A14, which is connected to one of the plurality of inner gate fingers (50).

(Appendix A17)
The rectangular outer edge of the inner region (42) has two sides extending in a first direction in plan view and two sides extending in a second direction orthogonal to the first direction in plan view,
The plurality of gate trenches (16) include a first set (S1) of gate trenches and a second set (S2) of gate trenches, and each gate trench of the first set (S1) is different from the first set (S1) of gate trenches in plan view. Each gate trench of the second set (S2) extends in one direction, and each gate trench of the first set (S1) and the second set (S2) extends in the second direction in plan view. The semiconductor device according to any one of appendices A1 to A14, which intersects one of the plurality of outer peripheral gate fingers (46) when viewed.

(Appendix A18)
The plurality of gate trenches (16) further include a third set (S3) of gate trenches and a fourth set (S4) of gate trenches, and each gate trench of the third set (S3) has the same shape as the gate trench in plan view. Each gate trench of the fourth group (S4) extends in the first direction, and each gate trench of the third group (S3) and the fourth group (S4) extends in the second direction in plan view. The semiconductor device according to appendix A17, which intersects with one of the plurality of inner gate fingers (50) in plan view.

(Appendix A19)
The first set (S1) and the second set (S2) of gate trenches are arranged across the inner region (42) and the outer peripheral region (40),
The semiconductor device according to appendix A18, wherein the third set (S3) and the fourth set (S4) of gate trenches are entirely disposed within the inner region (42).

(Appendix A20)
further comprising a plurality of field plate contact plugs (64);
The field plate electrode (30) embedded in each gate trench of the first set (S1) is connected to the outer peripheral segment (58) via at least one of the plurality of field plate contact plugs (64). a first end (66) connected to one of said plurality of inner segments (56) via at least one of said plurality of field plate contact plugs (64); an end (68);
The field plate electrode (30) embedded in each gate trench of the third set (S3) connects to the plurality of inner segments (56) via at least one of the plurality of field plate contact plugs (64). ) of the plurality of inner segments (56) through at least one of the plurality of field plate contact plugs (64). and a second end (72) connected to another one, the semiconductor device according to appendix A18 or A19.

(Appendix A21)
The semiconductor layer (14) includes a first conductivity type drift region (20), a second conductivity type body region (22) formed on the drift region (20), and a second conductivity type body region (22) formed on the body region (22). a first conductivity type source region (24) formed in
The gate trench (16) penetrates the source region (24) and the body region (22) and reaches the drift region (20), according to any one of appendices A1 to A20. semiconductor devices.

(Appendix B1)
a semiconductor substrate (12);
A semiconductor layer (14) formed on the semiconductor substrate (12) and including an outer peripheral region (40) and an inner region (42) having a rectangular outer edge surrounded by the outer peripheral region (40) in plan view. and,
a plurality of gate trenches (16) formed in the semiconductor layer (14);
an insulating layer (18) formed on the semiconductor layer (14);
a plurality of gate electrodes (28), each of which is embedded in a corresponding one of the plurality of gate trenches (16) via the insulating layer (18); and,
a plurality of field plate electrodes (30) each connected to a corresponding one of the plurality of gate trenches (16) and spaced apart from the gate electrode (28) through the insulating layer (18); a plurality of embedded field plate electrodes (30);
a gate wiring (44) formed on the insulating layer (18) and electrically connected to the plurality of gate electrodes (28);
a source wiring (34) formed on the insulating layer (18), separated from the gate wiring (44), and electrically connected to the plurality of field plate electrodes (30);
The gate wiring (44) is
a plurality of circumferential gate fingers (46) disposed in the outer circumferential region (40), the plurality of circumferential gate fingers (46) being spaced apart from each other by a plurality of gaps (48) disposed along the outer edge of the inner region (42); Gate finger (46) and
a plurality of inner gate fingers (50) disposed in the inner region (42), each inner gate finger being connected to at least one of the plurality of outer circumferential gate fingers (46); (50) and
The inner region (42) includes a plurality of sub-regions (52) separated by at least two intersecting inner gate fingers (50) among the plurality of inner gate fingers (50),
The source wiring (34) is
a plurality of inner segments (56) respectively arranged in the plurality of sub-regions (52);
a peripheral segment (58) disposed in the peripheral region (40);
The outer peripheral segment (58) is continuous with the plurality of inner segments (56), and each of the plurality of inner segments (56) is connected to the inner segment (56) of the plurality of gaps (48). The semiconductor device is connected to the outer peripheral segment (58) via a gap (48) adjacent to a sub-region (52) in which a semiconductor device is arranged.

(Appendix B2)
Each sub-region (52) is rectangular in plan view and has four sides,
The semiconductor according to appendix B1, wherein at least two of the plurality of gaps (48) are formed over a length at least equal to one side of an adjacent sub-region (52). Device.

(Appendix B3)
The semiconductor device according to appendix B1 or B2, wherein each of the plurality of sub-regions (52) is adjacent to at least one of the plurality of outer peripheral gate fingers (46).

(Appendix B4)
The rectangular outer edge of the inner region (42) has two sides extending in a first direction in plan view and two sides extending in a second direction orthogonal to the first direction in plan view. ,
The plurality of inner gate fingers (50) include a first inner gate finger (50A) extending in the first direction and a second inner gate finger (50B) extending in the second direction. A semiconductor device according to any one of the above.

(Appendix B5)
The plurality of sub-regions (52) include four sub-regions (52A, 52B, 52C, 52D), and each of the four sub-regions (52A, 52B, 52C, 52D) is different from the first one in plan view. The semiconductor device according to appendix B4, which is adjacent to the inner gate finger (50A) and the second inner gate finger (50B).

(Appendix B6)
The plurality of inner segments (56) include four inner segments (56A, 56B, 56C, 56D) arranged in the four sub-regions (52A, 52B, 52C, 52D), respectively,
The plurality of gaps (48) include four gaps (48A, 48B, 48C, 48C) adjacent to the four sub-regions (52A, 52B, 52C, 52D), respectively,
The outer peripheral segment (58) is continuous with the four inner segments (56A, 56B, 56C, 56D), and each of the four inner segments (56A, 56B, 56C, 56D) is connected to the four gaps. (48A, 48B, 48C, 48C), which is connected to the outer peripheral segment (58) through a gap (48) adjacent to the sub-region (52) in which the inner segment (56) is arranged. The semiconductor device according to B5.

(Appendix B7)
The plurality of outer circumferential gate fingers (46) include a first outer circumferential gate finger (46A) and a second outer circumferential gate finger (46B) extending in the first direction, and a third outer circumferential gate finger (46C) extending in the second direction. and a fourth outer peripheral gate finger (46D),
The first inner gate finger (50A) is connected to the third outer gate finger (46C) and the fourth outer gate finger (46D),
The second inner gate finger (50B) is connected to the first outer circumferential gate finger (46A) and the second outer circumferential gate finger (46B), according to any one of appendices B4 to B6. Semiconductor equipment.

(Appendix B8)
The rectangular outer edge of the inner region (42) has two sides extending in a first direction in plan view and two sides extending in a second direction orthogonal to the first direction in plan view,
The plurality of inner gate fingers (210) include a first inner gate finger (210A) extending in the first direction, a second inner gate finger (210B) extending in the second direction, and a second inner gate finger (210B) extending in the second direction. 3 inner gate fingers (210C);
The semiconductor device according to appendix B1 or B2, wherein the first inner gate finger (210A) intersects the second inner gate finger (210B) and the third inner gate finger (210C).

(Appendix B9)
The plurality of sub-regions (212) include six sub-regions (212A, 212B, 212C, 212D, 212E, 212F), and each of the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F) is adjacent to the first inner gate finger (210A) in plan view, and is adjacent to the second inner gate finger (210B) or the third inner gate finger (210C) in plan view, according to appendix B8. The semiconductor device described.

(Appendix B10)
The plurality of inner segments (216) include six inner segments (216A, 216B, 216C, 216D, 216E, 216F) arranged in the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F), respectively. including;
The plurality of gaps (208) include six gaps (208A, 208B, 208C, 208D, 208E, 208F) adjacent to the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F),
The outer peripheral segment (218) is continuous with the six inner segments (216A, 216B, 216C, 216D, 216E, 216F); Of the six gaps (208A, 208B, 208C, 208D, 208E, 208F), each of the outer peripheral segments ( 218), the semiconductor device according to appendix B9.

(Appendix B11)
One of the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F) is not adjacent to any of the plurality of outer peripheral gate fingers (206) and is 2, and the semiconductor device according to appendix B9 or B10, which is adjacent to the third inner gate finger (210A, 210B, 210C).

(Appendix B12)
Each of the plurality of gate trenches (16) is arranged to intersect with one of the plurality of outer peripheral gate fingers (46) or one of the plurality of inner gate fingers (50) in plan view. The semiconductor device according to any one of Appendices B1 to B11.

(Appendix B13)
further comprising a plurality of gate contact plugs (60),
The gate electrode (28) embedded in each gate trench (16) is connected to one of the plurality of outer peripheral gate fingers (46) via at least one of the plurality of gate contact plugs (60). Alternatively, the semiconductor device according to any one of Appendices B1 to B12, which is connected to one of the plurality of inner gate fingers (50).

(Appendix B14)
The rectangular outer edge of the inner region (42) has two sides extending in a first direction in plan view and two sides extending in a second direction orthogonal to the first direction in plan view,
The plurality of gate trenches (16) include a first set (S1) of gate trenches and a second set (S2) of gate trenches, and each gate trench of the first set (S1) is different from the first set (S1) of gate trenches in plan view. Each gate trench of the second set (S2) extends in one direction, and each gate trench of the first set (S1) and the second set (S2) extends in the second direction in plan view. The semiconductor device according to any one of appendices B1 to B13, which intersects one of the plurality of outer peripheral gate fingers (46) when viewed.

(Appendix B15)
The plurality of gate trenches (16) further include a third set (S3) of gate trenches and a fourth set (S4) of gate trenches, and each gate trench of the third set (S3) has the same shape as the gate trench in plan view. Each gate trench of the fourth group (S4) extends in the first direction, and each gate trench of the third group (S3) and the fourth group (S4) extends in the second direction in plan view. The semiconductor device according to appendix B14, which intersects with one of the plurality of inner gate fingers (50) in plan view.

(Appendix B16)
The first set (S1) and the second set (S2) of gate trenches are arranged across the inner region (42) and the outer peripheral region (40),
The semiconductor device according to appendix B15, wherein the third set (S3) and the fourth set (S4) of gate trenches are entirely disposed within the inner region (42).

(Appendix B17)
further comprising a plurality of field plate contact plugs (64);
The field plate electrode (30) embedded in each gate trench of the first set (S1) is connected to the outer peripheral segment (58) via at least one of the plurality of field plate contact plugs (64). a first end (66) connected to one of said plurality of inner segments (56) via at least one of said plurality of field plate contact plugs (64); an end (68);
The field plate electrode (30) embedded in each gate trench of the third set (S3) connects to the plurality of inner segments (56) via at least one of the plurality of field plate contact plugs (64). ) of the plurality of inner segments (56) through at least one of the plurality of field plate contact plugs (64). and a second end (72) connected to another one, the semiconductor device according to appendix B15 or B16.

(Appendix B18)
The semiconductor layer (14) includes a first conductivity type drift region (20), a second conductivity type body region (22) formed on the drift region (20), and a second conductivity type body region (22) formed on the body region (22). a first conductivity type source region (24) formed in
The gate trench (16) penetrates the source region (24) and the body region (22) and reaches the drift region (20), according to any one of appendices B1 to B17. semiconductor devices.

(Appendix C1)
a semiconductor substrate (12);
A semiconductor layer (14) formed on the semiconductor substrate (12) and including an outer peripheral region (40) and an inner region (42) having a rectangular outer edge surrounded by the outer peripheral region (40) in plan view. and,
a plurality of gate trenches (16) formed in the semiconductor layer (14);
an insulating layer (18) formed on the semiconductor layer (14);
a plurality of gate electrodes (28), each of which is embedded in a corresponding one of the plurality of gate trenches (16) via the insulating layer (18); and,
a plurality of field plate electrodes (30) each connected to a corresponding one of the plurality of gate trenches (16) and spaced apart from the gate electrode (28) through the insulating layer (18); a plurality of embedded field plate electrodes (30);
a gate wiring (302) formed on the insulating layer (18) and electrically connected to the plurality of gate electrodes (28);
a source wiring (304) formed on the insulating layer (18), separated from the gate wiring (302), and electrically connected to the plurality of field plate electrodes (30);
The gate wiring (302) is
three outer peripheral gate fingers (306A, 306B, 306C) arranged in the outer peripheral region (40), and three gaps (308A, 308B, 308C) arranged along the outer edge of the inner region (42); three peripheral gate fingers (306A, 306B, 306C) spaced apart from each other by;
two inner gate fingers (310A, 310B) disposed in the inner region (42), each connected to at least one of the three outer circumferential gate fingers (306A, 306B, 306C); , two inner gate fingers (310A, 310B);
The inner region (42) includes four sub-regions (312A, 312B, 312C, 312D) separated by the two inner gate fingers (310A, 310B) that intersect with each other,
The source wiring (304) is
first, second, third, and fourth inner segments (318A, 318B, 318C, 318D) arranged in the four sub-regions (312A, 312B, 312C, 312D), respectively;
a peripheral segment (320) disposed in the peripheral region (40);
The outer circumferential segment (320) is continuous with the first, second, and third inner segments (318A, 318B, 318C), and is continuous with the first, second, and third inner segments (318A, 318B, Of the three gaps (308A, 308B, 308C), each of the outer peripheral segments (318C) connects the outer circumferential segment (320 ) is connected to a semiconductor device.

(Appendix C2)
Each sub-region (312) is rectangular in plan view and has four sides,
At least two of the three gaps (308A, 308B, 308C) are formed over a length at least equivalent to one side of the sub-region (312) to which the gap (308) is adjacent. The semiconductor device described in .

(Appendix C3)
The semiconductor according to appendix C1 or C2, wherein each of the four sub-regions (312A, 312B, 312C, 312D) is adjacent to at least one of the three peripheral gate fingers (306A, 306B, 306C). Device.

(Appendix C4)
Notes C1-C3, wherein the fourth inner segment (318D) is connected to one of the first, second and third inner segments (318A, 318B, 318C) in the inner region (42). The semiconductor device according to any one of the above.

(Appendix C5)
The rectangular outer edge of the inner region (42) has two sides extending in a first direction in plan view and two sides extending in a second direction orthogonal to the first direction in plan view. ,
The two inner gate fingers (310A, 310B) include a first inner gate finger (310A) extending in the first direction and a second inner gate finger (310B) extending in the second direction. The semiconductor device according to any one of C4.

(Appendix C6)
The gate wiring (302) includes a gate pad,
The three outer circumferential gate fingers (306A, 306B, 306C) include a first outer circumferential gate finger (306A) extending in the first direction, a second outer circumferential gate finger (306B) extending in the second direction, and a second outer circumferential gate finger (306B) extending in the second direction. a third outer circumferential gate finger (306C) including a portion extending in the direction and a portion extending in the second direction;
the first inner gate finger (310A) is connected to the second outer circumferential gate finger (306B);
The second inner gate finger (310B) is connected to the first outer gate finger (306A) and the third outer gate finger (306C),
The semiconductor device according to appendix C5, wherein the gate pad is connected to the third outer peripheral gate finger (306C).

(Appendix C7)
Each of the plurality of gate trenches (16) is connected to one of the three outer gate fingers (306A, 306B, 306C) or one of the two inner gate fingers (310A, 310B) in plan view. The semiconductor device according to any one of appendices C1 to C6, which are arranged so as to cross each other.

(Appendix C8)
further comprising a plurality of gate contact plugs (60),
The gate electrode (28) embedded in each gate trench (16) is connected to the three outer gate fingers (306A, 306B, 306C) through at least one of the plurality of gate contact plugs (60). or one of the two inner gate fingers (310A, 310B), the semiconductor device according to any one of appendices C1 to C7.

(Appendix C9)
The rectangular outer edge of the inner region (42) has two sides extending in a first direction in plan view and two sides extending in a second direction orthogonal to the first direction in plan view,
The plurality of gate trenches (16) include a first set (S1) of gate trenches and a second set (S2) of gate trenches, and each gate trench of the first set (S1) is different from the first set (S1) of gate trenches in plan view. Each gate trench of the second set (S2) extends in one direction, and each gate trench of the first set (S1) and the second set (S2) extends in the second direction in plan view. The semiconductor device according to any one of appendices C1 to C8, which visually intersects one of the three outer peripheral gate fingers (306A, 306B, 306C).

(Appendix C10)
The plurality of gate trenches (16) further include a third set (S3) of gate trenches and a fourth set (S4) of gate trenches, and each gate trench of the third set (S3) has the same shape as the gate trench in plan view. Each gate trench of the fourth group (S4) extends in the first direction, and each gate trench of the third group (S3) and the fourth group (S4) extends in the second direction in plan view. The semiconductor device according to appendix C9, which intersects with one of the two inner gate fingers (310A, 310B) in plan view.

(Appendix C11)
The first set (S1) and the second set (S2) of gate trenches are arranged across the inner region (42) and the outer peripheral region (40),
The semiconductor device according to appendix C10, wherein the third set (S3) and the fourth set (S4) of gate trenches are entirely disposed within the inner region (42).

(Appendix C12)
further comprising a plurality of field plate contact plugs (64);
The field plate electrode (30) embedded in each gate trench of the first set (S1) is connected to the outer peripheral segment (320) through at least one of the plurality of field plate contact plugs (64). said first, second, third, and fourth inner segments (318A, 318B, 318C) via a connected first end and at least one of said plurality of field plate contact plugs (64). , 318D);
The field plate electrode (30) embedded in each gate trench of the third set (S3) connects the first, second, a first end connected to one of the third and fourth inner segments (318A, 318B, 318C, 318D) and through at least one of the plurality of field plate contact plugs (64); and a second end connected to another one of said first, second, third, and fourth inner segments (318A, 318B, 318C, 318D). The semiconductor device described.

(Appendix C13)
The semiconductor layer (14) includes a first conductivity type drift region (20), a second conductivity type body region (22) formed on the drift region (20), and a second conductivity type body region (22) formed on the body region (22). a first conductivity type source region (24) formed in
The gate trench (16) penetrates the source region (24) and the body region (22) and reaches the drift region (20), as described in any one of appendices C1 to C12. semiconductor devices.

10,100,200,300,400...Semiconductor device 12,402...Semiconductor substrate 12A, 402A...Top surface 12B, 402B...Bottom surface 14,404...Semiconductor layer 16,406...Gate trench 18,426,434...Insulating layer 20, 410...Drift region 22,412...Body region 24,414...Source region 26,420...Drain electrode 28,428...Gate electrode 28A...Top surface 28B...Bottom surface 28C...Side surface 30...Field plate electrode 32...Source contact plug 34,104 , 204...Source wiring 36...Contact region 38...Gate insulating part 40...Outer peripheral region 42...Inner region 44,102,202,302,436...Gate wiring 46,106,206,306...Outer periphery gate finger 46A, 206A, 306A ...First outer circumference gate finger 46B, 206B, 306B...Second outer circumference gate finger 46C, 206C, 306C...Third outer circumference gate finger 46D, 206D...Fourth outer circumference gate finger 206E...Fifth outer circumference gate finger 206F...Sixth outer circumference gate Finger 48, 48A, 48B, 48C, 48D, 110, 114, 116, 118, 208, 208A, 208B, 208C, 208D, 208E, 208F, 308, 308A, 208B, 308C, 316...Gap 50, 112, 210, 310...Inner gate finger 50A, 112A, 210A, 310A...First inner gate finger 50B, 112B, 210B, 310B...Second inner gate finger 210C...Third inner gate finger 52, 52A, 52B, 52C, 52D, 120A, 120B, 120C, 120D, 212, 212A, 212B, 212C, 212D, 212E, 212F, 312, 312A, 312B, 312C, 312D...

Sub-region

54, 108, 214, 314...

Gate pad

56, 56A, 56B, 56C, 56D, 122A, 122B, 122C, 122D, 216, 216A, 216B, 216C, 216D, 216E, 216F, 318, 318A, 318B, 318C, 318D...

Inner segment

58, 124, 218, 320... Outer segment 60... Gate contact Plug 62... Field plate trench 64... Field

plate contact plug

66, 68, 70, 72... End portion 408... Source trench 422... First well region 424... Second well region 430... Source electrode 432... Gate contact electrode 438... Barrier Layer 440...Wiring layer S1...First set S2...Second set S3...Third set S4...Fourth set

Claims

a semiconductor substrate;
a semiconductor layer formed on the semiconductor substrate and including an outer peripheral region and an inner region having a rectangular outer edge surrounded by the outer peripheral region in plan view;
a plurality of gate trenches formed in the semiconductor layer;
an insulating layer formed on the semiconductor layer;
a plurality of gate electrodes, each of which is embedded in a corresponding one of the plurality of gate trenches via the insulating layer;
a plurality of field plate electrodes, each of which is embedded in a corresponding one of the plurality of gate trenches through the insulating layer while being spaced apart from the gate electrode;
a gate wiring formed on the insulating layer and electrically connected to the plurality of gate electrodes;
a source wiring formed on the insulating layer, separated from the gate wiring, and electrically connected to the plurality of field plate electrodes;
The gate wiring is
a plurality of outer circumferential gate fingers disposed in the outer circumferential region, the plurality of outer circumferential gate fingers being separated from each other by a plurality of gaps disposed along an outer edge of the inner region;
a plurality of inner gate fingers disposed in the inner region, each inner gate finger being connected to at least one of the plurality of outer circumferential gate fingers;
The inner region includes a plurality of sub-regions separated by at least two inner gate fingers intersecting each other among the plurality of inner gate fingers,
The source wiring is
a plurality of inner segments respectively arranged in the plurality of sub-regions;
a peripheral segment disposed in the peripheral region;
The outer peripheral segment is continuous with at least two of the plurality of inner segments, and each of the at least two inner segments is adjacent to a sub-region of the plurality of gaps in which the inner segment is disposed. A semiconductor device connected to the outer peripheral segment via a gap.
Each sub-region is rectangular in plan view and has four sides,
2. The semiconductor device according to claim 1, wherein at least two of the plurality of gaps are formed over a length at least equal to one side of an adjacent sub-region.
3. The semiconductor device according to claim 1, wherein each of the plurality of sub-regions is adjacent to at least one of the plurality of outer peripheral gate fingers.
The outer circumferential segment is continuous with the plurality of inner segments, and each of the plurality of inner segments connects to the outer circumference through a gap adjacent to a sub-region in which the inner segment is arranged among the plurality of gaps. 4. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a segment.
The rectangular outer edge of the inner region has two sides extending in a first direction in plan view and two sides extending in a second direction orthogonal to the first direction in plan view,
5. The plurality of inner gate fingers include a first inner gate finger extending in the first direction and a second inner gate finger extending in the second direction. semiconductor devices.
The plurality of sub-regions include four sub-regions, and each of the four sub-regions is adjacent to the first inner gate finger and the second inner gate finger in plan view. semiconductor devices.
The plurality of inner segments include four inner segments respectively arranged in the four sub-regions,
The plurality of gaps include four gaps adjacent to each of the four sub-regions,
The outer circumferential segment is continuous with the four inner segments, and each of the four inner segments connects to the outer circumference through a gap adjacent to a sub-region in which the inner segment is arranged among the four gaps. 7. The semiconductor device according to claim 6, wherein the semiconductor device is connected to a segment.
The plurality of outer circumferential gate fingers include a first outer circumferential gate finger and a second outer circumferential gate finger extending in the first direction, and a third outer circumferential gate finger and a fourth outer circumferential gate finger extending in the second direction,
The first inner gate finger is connected to the third outer gate finger and the fourth outer gate finger,
8. The semiconductor device according to claim 5, wherein the second inner gate finger is connected to the first outer gate finger and the second outer gate finger.
The plurality of inner segments include first, second, third, and fourth inner segments arranged in the four sub-regions, respectively,
the outer circumferential segment is continuous with the first, second, and third inner segments;
Each of the first, second, and third inner segments is connected to the outer peripheral segment through a gap adjacent to a sub-region in which the inner segment is arranged among the plurality of gaps,
8. The semiconductor device according to claim 6, wherein the fourth inner segment is connected to one of the first, second, and third inner segments in the inner region.
The gate wiring includes a gate pad,
The plurality of outer circumferential gate fingers include a first outer circumferential gate finger extending in the first direction, a second outer circumferential gate finger extending in the second direction, a portion extending in the first direction, and a portion extending in the second direction. and a third outer circumferential gate finger,
the first inner gate finger is connected to the second outer circumferential gate finger;
the second inner gate finger is connected to the first outer gate finger and the third outer gate finger;
10. The semiconductor device according to claim 9, wherein the gate pad is connected to the third outer peripheral gate finger.
The rectangular outer edge of the inner region has two sides extending in a first direction in plan view and two sides extending in a second direction orthogonal to the first direction in plan view,
The plurality of inner gate fingers include a first inner gate finger extending in the first direction, a second inner gate finger extending in the second direction, and a third inner gate finger extending in the second direction,
3. The semiconductor device according to claim 1, wherein the first inner gate finger intersects with the second inner gate finger and the third inner gate finger.
The plurality of sub-regions include six sub-regions, and each of the six sub-regions is adjacent to the first inner gate finger in plan view and is adjacent to the second inner gate finger or the third inner gate finger in plan view. 12. The semiconductor device of claim 11, adjacent the inner gate finger.
The plurality of inner segments include six inner segments respectively arranged in the six sub-regions,
The plurality of gaps include six gaps adjacent to each of the six sub-regions,
The outer circumferential segment is continuous with the six inner segments, and each of the six inner segments connects to the outer circumference through a gap adjacent to a sub-region in which the inner segment is arranged among the six gaps. 13. The semiconductor device according to claim 12, wherein the semiconductor device is connected to a segment.
5. One of the six sub-regions is not adjacent to any of the plurality of outer circumferential gate fingers and is adjacent to the first, second, and third inner gate fingers. 14. The semiconductor device according to 12 or 13.
15. The gate trench according to claim 1, wherein each of the plurality of gate trenches is arranged to intersect one of the plurality of outer circumferential gate fingers or one of the plurality of inner gate fingers in a plan view. The semiconductor device according to any one of the above.
Further includes multiple gate contact plugs,
The gate electrode embedded in each gate trench is connected to one of the plurality of outer circumferential gate fingers or one of the plurality of inner gate fingers via at least one of the plurality of gate contact plugs. 15. The semiconductor device according to claim 1, wherein the semiconductor device is connected to.
The rectangular outer edge of the inner region has two sides extending in a first direction in plan view and two sides extending in a second direction orthogonal to the first direction in plan view,
The plurality of gate trenches include a first set of gate trenches and a second set of gate trenches, each gate trench of the first set extending in the first direction in plan view, and each gate trench of the second set extending in the first direction. 1 . The trench extends in the second direction in a plan view, and each gate trench of the first set and the second set intersects with one of the plurality of outer circumferential gate fingers in a plan view. 15. The semiconductor device according to any one of 14 to 14.
The plurality of gate trenches further include a third set of gate trenches and a fourth set of gate trenches, each gate trench of the third set extending in the first direction in plan view, and each gate trench of the fourth set extending in the first direction. The gate trench extends in the second direction in a plan view, and each gate trench of the third set and the fourth set intersects with one of the plurality of inner gate fingers in a plan view. 18. The semiconductor device according to 17.
The first set and the second set of gate trenches are arranged across the inner region and the outer peripheral region,
19. The semiconductor device according to claim 18, wherein the third set and the fourth set of gate trenches are entirely disposed within the inner region.
Further equipped with multiple field plate contact plugs,
A field plate electrode embedded in each gate trench of the first set has a first end connected to the outer peripheral segment via at least one of the plurality of field plate contact plugs, and a first end connected to the outer peripheral segment through at least one of the plurality of field plate contact plugs. a second end connected to one of the plurality of inner segments via at least one of a field plate contact plug;
A field plate electrode embedded in each gate trench of the third set has a first electrode connected to one of the plurality of inner segments via at least one of the plurality of field plate contact plugs. and a second end connected to another one of the plurality of inner segments via at least one of the plurality of field plate contact plugs. The semiconductor device described in .