WO2024050136A1

WO2024050136A1 - Switch

Info

Publication number: WO2024050136A1
Application number: PCT/US2023/031923
Authority: WO
Inventors: Jignesh Shah
Original assignee: Samtec, Inc.
Priority date: 2022-09-02
Filing date: 2023-09-01
Publication date: 2024-03-07

Abstract

An orthogonal switch includes one or more of a front panel, a host substrate, such as printed circuit board, and an auxiliary substrate, such as a poser or a control printed circuit board. The host substrate is directly or indirectly physically connected to the auxiliary substrate, electrically connected to the auxiliary substrate or both, and the host substrate that has a first major surface, and an opposed second major surface and at least three edges, wherein the first major surface is positioned generally parallel to the front panel. The front panel defines a plurality of panel openings arranged in rows and columns.

Description

SWITCH

BACKGROUND

[0001] As shown in Fig. 1A, a conventional switch can include RF45 or RJ11 connector ports arranged in two parallel rows.

[0002] An improved modular switch, as compared to the conventional switch shown in Fig. 1A, is shown in Figs. 1B-1D. Compared to the conventional switch shown in Fig. 1A, a modular switch typically includes a front panel, an opposed rear end, and a host printed circuit board that extends in a direction from the front panel to the opposed rear end. A first end of the host printed circuit board, positioned adjacent to the front panel, can be populated with panel mount connectors, such as QSFP, QSFP+, QSFP-DD, QSFP-DD 800, FQSFP, OSFP, CXP, and CFP right angle connectors. Each of the panel mount connectors can be at least partially surrounded by a respective EMI shield cage. A mating transceiver, either copper or optical, can be inserted into a respective EMI shield cage and mated to a corresponding panel mount connector. A second end of the host printed circuit board can be populated with fan modules that can draw or force cooling air through the router switch. An ASIC module can be mounted to a first side of the host printed circuit board, opposite to a second side of the printed circuit board. As shown in Fig. ID, thirty-two OSFP-type ports fits within a 1RU panel.

[0003] One of the problems with the modular switch of Figs. 1A-1D is that traces within a host board create unwanted loss and noise. To help address these problems, and referring now to Figs. 2A and 2B, it is known that unwanted trace losses can be reduced by spanning panel mounted connectors, such as FQSFP-DD connectors, and second electrical connectors, such as the CPI or SI-FLY connectors, all commercially available from SAMTEC, Inc., New Albany, IN, with twin axial or coaxial cables. Fig. 2A shows a co-packaged second electrical connector. Fig. 2B shows a near packaged second electrical connector.

SUMMARY

[0004] As data transfer speeds increase to 112G/sec PAM-4, 224G/sec PAM-4 (roughly 70GHz of bandwidth - 56GHz Nyquist frequency plus some additional bandwidth, such as approximately 10-20GHz or approximately more), or even 224G/sec PAM-6 (approximately 40-45 GHz) or 224G/sec PAM-8 (approximately 35-40 GHz) signaling, the twin axial and coaxial cables, alone or in combination with the second electrical connectors, can produce enough unwanted noise and/or loss to cause transmission lines, such as single-ended or differential signal transmission lines, to have too much signal transmission loss, too high insertion loss, too much noise, etc. to be commercially or practically viable.

[0005] I have found that additional signal integrity improvements, including a further reduction in unwanted signal loss and/or signal noise, can be achieved by eliminating the twin axial or coaxial cables and/or a respective second electrical connector physically connected, electrically connected or both to the twin axial or coaxial cables. Stated another way, a mating transceiver or other type of mating connector or plug can be directly plugged into a corresponding panel mount connector that is co-packaged with an ASIC or chip or near packaged (positioned adjacent to) an ASIC or chip package and electrically connected to the ASIC or chip by traces in the host printed circuit board. Signaling of 224G/sec PAM-4, at approximately 6ps (20%-80%), with approximately -40dB or -45dB of crosstalk is therefore achievable.

[0006] Without being bound by theory, as compared to the prior art switch architectures shown in Figs. 1A-2B, the orthogonal switch can provide a shorter physical signal length, a shorter electrical signal length or both between an electrical connector co-packaged with a die package, such as an ASIC die package or near packaged with a die package, such as an ASIC die package. A shorter physical and/or electrical length can be achieved by eliminating twin axial or coaxial cables that extend between the panel mount connector and an associated ASIC.

[0007] The above and other features, elements, characteristics, steps, and advantages of the present invention will become more apparent from the following detailed description of the embodiments of the present invention with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Fig. 1A is a perspective, partially transparent, top view of a conventional switch;

[0009] Fig. IB is a perspective, partially transparent, top view of a conventional modular switch; [0010] Fig. 1C is a cross-sectional side view of the conventional modular switch shown in Fig. IB; [0011] Fig. ID is a schematic front view of OSFP-brand ports defined in a 1RU panel and belly- to-belly OSFP connectors; [0012] Fig. 2A is a schematic side view of a conventional modular switch with a co-packaged CPI/SI-FLY brand connector;

[0013] Fig. 2B is a schematic side view of a convention modular switch with a near packaged CPI/SI-FLY brand connector;

[0014] Fig. 3A is a perspective top view of a novel orthogonal switch with the top cover removed for clarity;

[0015] Fig. 3B is a perspective front view of the novel orthogonal switch shown in Fig. 3A;

[0016] Fig. 3C is a perspective front view of the novel orthogonal switch shown in Fig. 3B with a front panel removed; and

[0017] Fig. 4 is a schematic, side, cross-sectional view of the novel orthogonal switch shown in Figs. 3A-3C.

DETAILED DESCRIPTION

[0018] As a brief introduction, Fig. 3A generally shows an orthogonal switch 10. The orthogonal switch 10 can include one or more of a front panel 12, a host substrate 18, such as printed circuit board, and an auxiliary substrate 40, such as power or control printed circuit board. The host substrate 18 can be directly or indirectly physically connected to the auxiliary substrate 40, electrically connected to the auxiliary substrate 40 or both.

[0019] Fig. 3B generally shows an orthogonal switch 10 that can include the front panel 12 and the host substrate 18. The host substrate 18 can include a first major surface 20, an opposed second major surface 22 and at least three edges 24. The first major surface 20 can be positioned generally parallel to the front panel 12. The front panel 12 can define a plurality of panel openings 26 arranged in rows and columns.

[0020] There can be more than two rows of panel openings 26. For example, the plurality of panel openings 26 can define at least three rows of panel openings 26 and at least three columns of panel openings 26. For example, the plurality of panel openings 26 can define a first row R1 of panel openings 26. The first row R1 can extend along a first-row line RL1. A second row R2 of panel openings 26, which can be immediately adjacent to the first row R1 of panel openings 26 can extend along a second-row line RL2. A third row R3 of panel openings 26, which can be immediately adjacent to the second row R2 of panel openings 26, can extend along a second- row line RL2. The first, second and third row lines RL1, RL2, RLS can all be parallel to one another. The first row R1 of panel openings 26 can have a different number of panel openings 26 than the second row R2 and the third row R3. A fourth row R4 of panel openings 26 that extend along a fourth-row line RL4 and can be positioned immediately adjacent to the third row R3 or third row line RL3. A fifth row R5 of panel openings 26 can be immediately adjacent to the fourth row R4 of panel openings 26 and can extend along a fifth-row line RL5. The first, second, third, fourth and fifth rows R1-R5 and/or the first through fifth row lines RL1-RL5 can all be parallel to one another.

[0021] There can also be more than two columns of panel openings 26. At least three columns of panel openings 26 can include a first column Cl of panel openings 26 that extend along a first column line CL1, a second column C2 of panel openings 26 that can be immediately adjacent to the first column Cl of panel openings 26 and that can extend along a second column line CL2, and a third column C3 of panel openings 26 that can be immediately adjacent to the second column C2 of panel openings 26 and that can extend along a third column line CL3, wherein the first, second and third column lines CL1-CL3 can each be parallel to one another. The first column Cl of panel openings 26 can have a different number of panel openings 26 than the second column C2 and the third column C3. A fourth column C4 of panel openings 26 can extend along a fourth column line CL4. A fifth column C5 of panel openings 26 can be immediately adjacent to the fourth column C4 of panel openings 26 and can extend along a fifth column line CL5. The first, second, third, fourth and fifth column lines CL1-CL5 can each be parallel to one another.

[0022] A first central opening 28 can be defined by the front panel 12. First ones of the plurality of panel openings 26 can be positioned around a periphery of the first central opening 28. A second central opening 30 can be defined by the front panel 12. Second ones of the plurality of panel openings 26 can be positioned around a periphery of the second central opening 30.

[0023] The first central opening 28 can receive or at least partially surround a heat sink or cold plate or fluid cooled heat sink positioned on or over a first ASIC or chip positioned on corresponding first package substrate 32A. The second central opening 30 can receive or at least partially surround a heat sink or cold plate or fluid cooled heat sink position over a second ASIC or chip positioned on a corresponding second package substrate 32B. One benefit is that the heat sinks/cold plates/heat removal devices can be exposed to moving air outside of the front panel 12/orthogonal switch 10 box.

[0024] A plurality of electrical connectors 34 can be positioned on the first major surface 20 of the host substrate 18. The plurality of electrical connectors 34 can be positioned on the first package substrate 32A. The plurality of electrical connectors can be positioned on the second package substrate 32B. Each of the plurality of electrical connectors 34 can be a vertical electrical connector, such as a non-right angle electrical connector. Each of the plurality of electrical connectors 34 can aligned with a corresponding one of the plurality of panel openings 26. Each of the plurality of electrical connectors can have a form factor that corresponds to a QSFP, QSFP+, QSFP-DD, QSFP-DD 800, FQSFP, OSFP, CXP, CFP, NOVARAY I/O form factor. However, some, most or all these electrical connectors may have to be structurally modified, internally, externally, or both, to achieve data transfer or data signaling rates of at least 224G/sec PAM-4 with no more than -35dB or -40dB of crosstalk. Alternatively, each of the plurality of electrical connectors 34 can have a different type of form factor capable of achieving 112G/sec PAM-4 signaling, 224G/sec PAM-4 signaling or both. Each of the plurality of electrical connectors 34 can further include differential signal pairs. Each of the plurality of electrical connectors 34 can be configured to receive a card edge of a mating connector 38. Alternatively, each of the plurality of electrical connectors 34 can be configured not to receive a card edge of a mating connector 38.

[0025] The mating connector 38 can have the form factor of an electrical or optical transceiver such as a SFP, QSFP, QSFP-DD or OSFP type of transceiver or an I/O plug, such as a NOVARAY I/O connector commercially available from SAMTEC, Inc., New Albany, IN. However, some, most, or all these mating connectors 38 may have to be structurally modified, internally, externally, or both, to achieve data transfer or data signaling rates of at least 224G/sec PAM-4 with no more than -35dB or -40dB of crosstalk. Alternatively, each mating connector 38 can have a different type of form factor capable of achieving 112G/sec PAM-4 signaling, 224G/sec PAM-4 signaling or both. Each mating connector 38 can further include differential signal pairs. Each mating connector 38 can include coaxial cable, twin axial cable or both. [0026] A plurality of shield cages 36 can be positioned between the front panel 12 and the first major surface 20 of the host substrate 18. Each of the plurality of shield cages 18 can be aligned with a corresponding one of the plurality of panel openings 26. A plurality of shield cages 36 can be positioned between the front panel 12 and the first major surface 20 of the host substrate 18. Each of the plurality of shield cages 36 can be aligned with a corresponding one of the plurality of panel openings 26. Each of the shield cages 36 can include at least three or at least four shield walls and the shield walls, in combination, can define a shield cavity that can be configured to receive a mating connector 38. Each of the plurality of shield cages 36 can cover or envelop or overlap or overhang or touch at least three or at least four exterior sides or exterior walls of a corresponding electrical connector 34. Each of the plurality of shield cages 36 can be configured to receive the mating connector 38. Each of the plurality of panel openings 26 can be configured to receive the mating connector 38.

[0027] Fig. 3C generally shows a system architecture, such as an orthogonal switch 10, host substrate 18 with first major surface 20, first package substrate 32A, second package substrate 32B, electrical connectors 34, and mating connectors 38,

[0028] An auxiliary substrate 40 can be positioned adjacent to and generally parallel to the host substrate 18. There can be no coaxial or twin axial cables positioned between the plurality of electrical connectors 26 and the first major surface 20 of the host substrate 18.

[0029] The electrical connector 34, such as a vertical, non-right angle electrical connector, can be physically attached, electrically attached or both to the first major surface 20 of a host substrate 18. The electrical connector 34 can be configured to mate with a mating connector 38 that can extend through a front panel 12. The electrical connector 26 can define a card edge slot. The electrical connector 34 can physically and directly mate with the mating connector 38. The electrical connector 34 can be received in a corresponding shield cage 36. One or more shield cages 36 can be positioned between the first major surface 20 of the host substrate 18 and a second front panel side 16 of a front panel 12.

[0030] A panel mount system can include a front panel 12 that can define a panel opening 26, a host substrate 18 that can define a first major surface 20 and an opposed, second major surface 22 and a shield cage 36. An electrical connector 34 can be carried by the first major surface 20 of the host substrate 18. The host substrate 18 can be spaced away from the front panel 12, the shield cage 36 can at least partially surround the electrical connector 34, and the shield cage 36 can bridge between the front panel 12 and the host substrate 18. The electrical connector 34 can be configured to transmit data at a data transfer speed of least 112G/sec PAM-4. The electrical connector 34 can be configured to transmit date at a data transfer speed of at least 224G/sec PAM-4. A mating connector 38 can be configured to releasably mate with the electrical connector 34. The mating connector can a form factor is selected from the group including QSFP, QSFP+, QSFP-DD, QSFP-DD 800, FQSFP, OSFP, CXP, CFP, and NOVARAY I/O. The mating connector 38 can be configured to be releasable mated to the electrical connector 34. The mating connector can be configured to be received inside of the shield cage 36. The front panel 12 can be physically spaced from the host substrate 18. The front panel 12 can be electrically connected to the host substrate 18 by the shield cage 36.

[0031] A panel architecture can provide 224G/sec PAM-4 signaling with no more than -40dB of crosstalk. A panel architecture, such as an orthogonal switch 10 can include a host substrate 18 and an electrical connector 34 configured to be accessed through a front panel 12, wherein the electrical connector 34 can be physically connected to a first package substrate 32A that can carry a chip, such as an ASIC. A panel architecture, such as an orthogonal switch 10 can include a host substrate 18. An electrical connector 34 can be configured to be accessed through a front panel 12. The electrical connector 34 can be positioned immediately adjacent to a first package substrate 32A, as second package substrate 32B, an ASIC, or any of these. A panel architecture, such as an orthogonal switch 10 can include a host substrate 18 and an electrical connector 34 configured to be accessed through a front panel 12 wherein the electrical connector 34 can be devoid of differential cables. The electrical connector 34 can be configured to not be connected to an electrical trace in the host substrate 18 that is longer than two inches. A mating connector 38 can be configured to be inserted through the front panel 12 and can be configured to be mated to the electrical connector 34. The electrical connector 34 can be is spaced from the front panel 12. The shield cage 36 can bridge the host substrate 18 and the front panel 12.

[0032] The foregoing description is only illustrative of the present invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the present invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variances that fall within the scope of the appended claims.

Claims

1. An orthogonal switch comprising: a front panel; and a host substrate that has a first major surface, and opposed second major surface and at least three edges, wherein the first major surface is positioned generally parallel to the front panel.

2. The orthogonal switch of claim 1 wherein the front panel defines a plurality of panel openings arranged in rows and columns, wherein there are more than two rows and more than two columns of panel openings.

3. The orthogonal switch of claim 2 wherein the plurality of panel openings defines at least three rows of panel openings and at least three columns of panel openings.

4. The orthogonal switch of claim 3 wherein the at least three row of panel openings defines a first row of panel openings that extend along a first row line, a second row of panel openings that are immediately adjacent to the first row of panel openings and that extend along a second row line, and a third row of panel openings that are immediately adjacent to the second row of panel openings and that extend along a second row line, wherein the first, second and third row lines are parallel to one another.

5. The orthogonal switch of claim 4 wherein the first row of panel openings has a different number of panel openings than the second row and the third row.

6. The orthogonal switch of any one of claims 4-5 further comprising a fourth row of panel openings that extend along a fourth-row line and a fifth row of panel openings that are immediately adjacent to the fourth row of panel openings and that extend along a fifth-row line wherein the first, second, third, fourth and fifth row lines are parallel to one another.

7. The orthogonal switch of any one of claims 2-6 wherein the at least three columns of panel openings defines a first column of panel openings that extend along a first column line, a second column of panel openings that are immediately adjacent to the first column of panel openings and that extend along a second column line, and a third column of panel openings that are immediately adjacent to the second column of panel openings and that extend along a second column line, wherein the first, second and third column lines are parallel to one another.

8. The orthogonal switch of claim 7 wherein the first column of panel openings has a different number of panel openings than the second column and the third column.

9. The orthogonal switch of any one of claims 7-8 further comprising a fourth column of panel openings that extend along a fourth column line and a fifth column of panel openings that are immediately adjacent to the fourth column of panel openings and that extend along a fifth column line wherein the first, second, third, fourth and fifth column lines are parallel to one another.

10. The orthogonal switch of any one of claims 2-9 further comprising a first central opening and first one of the plurality of panel openings are positioned around a periphery of the first central opening.

11. The orthogonal switch of any one of claims 2-20 further comprising a second central opening and a second ones of the plurality of panel openings are positioned around the second central opening.

12. The orthogonal switch of any one of claims 1-11 further comprising a plurality of electrical connectors positioned on the first surface of the host substrate, on an ASIC package positioned on the first major surface of the host substrate, on an ASIC package positioned on the second major surface of the host substrate, or any one of these combinations.

13. The orthogonal switch of claim 12 wherein each of the plurality of electrical connectors is a vertical electrical connector.

14. The orthogonal switch of any one of claims 12 and 13 wherein each of the plurality of electrical connectors is aligned with a corresponding one of the plurality of panel openings.

15. The orthogonal switch of any one of claims 12-14 wherein each of the plurality of electrical connectors is configured to receive a card edge of a mating connector.

16. The orthogonal switch of any one of claims 12-14 wherein each of the plurality of electrical connectors does not receive a card edge of a mating connector.

17. The orthogonal switch of any one of claims 15-16 wherein the mating connector is an electrical or optical transceiver.

18. The orthogonal switch of any one of claims 12-17 wherein each of the plurality of electrical connectors further comprises differential signal pairs.

19. The orthogonal switch of any one of claims 1-18 further comprising a plurality of shield cages positioned between the front panel and the first major surface of the host substrate.

20. The orthogonal switch of claim 19 wherein each of the plurality of shield cages is aligned with a corresponding one of the plurality of panel openings.

21. The orthogonal switch of any one of claims 1-14 further comprising a plurality of shield cages positioned between the front panel and the first major surface of the host substrate, wherein each of the plurality of shield cages is aligned with a corresponding one of the plurality of panel opening, each of the plurality of shield cages is configured to receive a mating connector and each of the plurality of panel openings is configured to receive the mating connector.

22. The orthogonal switch of any one of claims 1-21 further comprising an auxiliary substrate positioned adjacent to and generally parallel to the host substrate.

23. The orthogonal switch of any one of claims 12-14 wherein there are no coaxial or twin axial cables positioned between the plurality of electrical connectors and the first surface of the host substrate.

24. A vertical electrical connector attached to a first surface of a host substrate, wherein the vertical electrical connector is configured to mate with a mating connector that extends through a front panel.

25. The vertical electrical connector of claim 24 further comprising a card edge slot.

26. The vertical electrical connector of any one of claims 24 and 25 wherein the vertical electrical connector physically and directly mates with the mating connector.

27. The vertical electrical connector of any one of claims 24-26 wherein the vertical electrical connector is received in a corresponding shield cage.

28. The vertical connector of claim 27 wherein the shield cage is positioned between the first surface of the host substrate and front panel.

30. A panel mount system comprising: a front panel that defines a panel opening; a host substrate that defines a first major surface and an opposed, second major surface; an electrical connector carried by the first major surface of the host substrate; and a shield cage, wherein the host substrate is spaced away from the front panel, the shield cage at least partially surrounds the electrical connector, and the shield cage bridges the front panel and the host substrate.

31. The panel mount system of claim 30 wherein the electrical connector is configured to transmit data at a data transfer speed of least 112G/sec PAM-4.

32. The panel mount system of claim 30 wherein the electrical connector is configured to transmit date at a data transfer speed of at least 224G/sec PAM-4.

33. The panel mount system of any one of claims 30-32 further comprising a mating connector configured to releasably mate with the electrical connector, wherein the mating connector has a form factor is selected from the group comprising QSFP, QSFP+, QSFP-DD, QSFP-DD 800, FQSFP, OSFP, CXP, CFP, and NOVARAY I/O.

34. The panel mount system of claim 33 wherein mating connector is configured to be releasable mated to the electrical connector.

35. The pane mount system of any one of claims 33 and 34 wherein the mating connector is configured to be received inside of the shield cage.

36. The panel mount system of any one of claims 30-35 wherein the front panel is physically spaced from the host substrate.

37. The panel mount system of any one of claims 30-36 wherein the front panel is electrically connected to the host substrate by the shield cage.

38. A panel architecture that provides 224G/sec PAM-4 signaling with no more than -40dB of crosstalk.

39. An orthogonal switch comprising a host substrate and an electrical connector configured to be accessed through a front panel, wherein the electrical connector is physically connected to a first package substrate that carries a chip, such as an ASIC.

40. An orthogonal switch comprising a host substrate and an electrical connector configured to be accessed through a front panel, wherein the electrical connector is positioned immediately adjacent to a first package substrate, an ASIC, or both.

41. An orthogonal switch comprising a host substrate and an electrical connector configured to be accessed through a front panel wherein the electrical connector is devoid of differential cables and the electrical connector is not connected to an electrical trace in the host substrate that is longer than two inches.

42. The orthogonal switch of any one of claims 39-41 further comprising a mating connector wherein the mating connector is configured to be inserted through a front panel and mated to the electrical connector.

43. The orthogonal switch of any one of claims 39-42 further comprising a front panel wherein the electrical connector is spaced from the front panel.

44. The orthogonal switch of claim 43 further comprising a shield cage that bridges the host substrate and the front panel.