WO2024045895A1 - 基带芯片、混合预编码方法及终端设备 - Google Patents

基带芯片、混合预编码方法及终端设备 Download PDF

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Publication number
WO2024045895A1
WO2024045895A1 PCT/CN2023/106131 CN2023106131W WO2024045895A1 WO 2024045895 A1 WO2024045895 A1 WO 2024045895A1 CN 2023106131 W CN2023106131 W CN 2023106131W WO 2024045895 A1 WO2024045895 A1 WO 2024045895A1
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matrix
memristor
unit
array
precoding
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English (en)
French (fr)
Inventor
高滨
秦琦
胡明
祝叶华
孙炜
吴华强
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Tsinghua University
Guangdong Oppo Mobile Telecommunications Corp Ltd
Zeku Technology Shanghai Corp Ltd
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Tsinghua University
Guangdong Oppo Mobile Telecommunications Corp Ltd
Zeku Technology Shanghai Corp Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/088—Non-supervised learning, e.g. competitive learning
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems
    • H04B7/0456—Selection of precoding matrices or codebooks, e.g. using matrices antenna weighting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present invention relates to the field of chip design, and in particular, to a baseband chip, a hybrid precoding method and a terminal device.
  • hybrid precoding is applied at the transmitter end of the communication system, so that the energy concentration direction of the transmitted signal can be controlled.
  • Embodiments of the present application provide a baseband chip, a hybrid precoding method, and a terminal device.
  • embodiments of the present application provide a baseband chip, which includes a memristor-based storage unit, a digital baseband unit and a phase shifter array, wherein,
  • the memristor-based storage and calculation unit is configured to determine an analog precoding matrix according to the channel state information matrix, and transmit the analog precoding matrix to the digital baseband unit and the phase shifter array respectively;
  • the digital baseband unit is configured to determine a digital precoding matrix according to the analog precoding matrix, and perform conversion processing on the signal to be transmitted based on the digital precoding matrix to obtain a converted signal;
  • the phase shifter array is configured to obtain a processed signal corresponding to the converted signal, and perform phase shifting processing on the processed signal according to the analog precoding matrix to obtain a phase-shifted signal to pass through the antenna array Send the phase-shifted signal.
  • inventions of the present application provide a hybrid precoding method.
  • the hybrid precoding method is applied to a terminal device.
  • the terminal device is configured with a baseband chip and an antenna array.
  • the baseband chip includes a memristor-based memory. arithmetic unit, digital baseband unit and phase shifter array, the method includes:
  • the memristor-based storage and calculation unit determines the simulated precoding matrix according to the channel state information matrix, and converts the simulated precoding matrix respectively transmitted to the digital baseband unit and the phase shifter array;
  • the digital baseband unit determines a digital precoding matrix according to the analog precoding matrix, and performs conversion processing on the signal to be transmitted based on the digital precoding matrix to obtain a converted signal;
  • the phase shifter array acquires the processed signal corresponding to the converted signal, and performs phase shifting processing on the processed signal according to the analog precoding matrix to obtain the phase-shifted signal;
  • the antenna array transmits the phase-shifted signal.
  • embodiments of the present application provide a terminal device, which includes an antenna array and a baseband chip as described in the first aspect, wherein,
  • the baseband chip is configured to perform hybrid precoding processing on the signal to be transmitted to obtain the phase-shifted signal
  • the antenna array is configured to transmit the phase-shifted signal.
  • Figure 1 is a schematic diagram of a memristor unit
  • Figure 2 is the schematic diagram 2 of the memristor unit
  • Figure 3 is a schematic diagram of a memristor-based storage and calculation unit
  • Figure 4 is a schematic diagram 2 of a memristor-based storage and calculation unit
  • Figure 5 is a schematic diagram of preprocessing of the channel state information matrix
  • Figure 6 is a schematic diagram of an unsupervised neural network based on the attention mechanism
  • Figure 7 is a schematic diagram of the attention mechanism layer
  • Figure 8 is a schematic structural diagram of the convolution layer
  • Figure 9 is a schematic diagram 1 of matrix inversion processing
  • Figure 10 is a schematic diagram 2 of matrix inversion processing
  • Figure 11 is a schematic diagram of using a memristor-based storage and calculation unit to implement hybrid precoding
  • Figure 12 is a schematic diagram of the composition and structure of the baseband chip
  • Figure 13 is the second structural diagram of the baseband chip
  • Figure 14 is a schematic diagram 2 of an unsupervised neural network based on the attention mechanism
  • Figure 15 is a schematic flow chart of the implementation of the hybrid precoding method proposed in the embodiment of the present application.
  • Figure 16 is a schematic structural diagram of the terminal equipment.
  • the digital precoding part and the analog precoding part can respectively convert and phase shift the signals before and after passing through the radio frequency chain.
  • the digital precoding part is completed by a digital baseband chip
  • the analog precoding part is composed of computing units and phase shifter arrays such as Field-Programmable Gate Array (FPGA).
  • FPGA Field-Programmable Gate Array
  • the channel state information at the transmitter is first transmitted to the computing unit FPGA, and then the FPGA runs cross-entropy and other optimization algorithms to obtain the key analog precoding matrix; then the obtained analog precoding matrix is simultaneously transmitted to the digital baseband chip and phase shifter array Middle; According to the input analog precoding matrix, the digital baseband chip runs the zero-forcing (ZF) algorithm to obtain the digital precoding matrix, and performs conversion operations on the input modulation signal based on this matrix.
  • ZF zero-forcing
  • the analog precoding matrix is mapped to the phase shifter array, used to control the size of the phase shift of each phase shifter in the phase shifter array; the phase shifter array performs a phase shift operation on the signal after passing through the radio frequency chain, completing the entire hybrid precoding process; The signal after the shifting operation is transmitted to the antenna array and transmitted to the user.
  • the analog precoding matrix is usually calculated and obtained by the FPGA. Accordingly, the analog precoding matrix and other data obtained through the FPGA need to be relocated between the FPGA and the communication unit.
  • the computing power required for hybrid precoding also needs to continue to increase.
  • the data in the hybrid precoding process based on the external computing unit (FPGA) as mentioned above.
  • the relocation problem will lead to the defects of large delay and high power consumption, and due to the limited area and power consumption constraints, it is impossible to integrate the existing Complementary Metal Oxide Semiconductor (CMOS)-based computing power with sufficient computing power.
  • CMOS Complementary Metal Oxide Semiconductor
  • the processor is integrated into the communication unit.
  • hybrid precoding processing that integrates calculation and storage can be implemented based on a memristor array.
  • memristor-based storage and computing units can be used to accelerate the calculation process of analog precoding matrices in hybrid precoding, which can provide high energy-efficiency computing power
  • memristor-based storage and computing units, digital baseband units and phase shifting The processor array is integrated into a baseband chip to reduce data transfer delays. It can be seen that the hybrid precoding processing scheme based on memristor-based storage and calculation units can reduce power consumption and delay, thereby improving communication efficiency and communication performance.
  • An embodiment of the present application provides a baseband chip, which includes a memristor-based storage unit, a digital baseband unit, and a phase shifter array.
  • the memristor-based storage and calculation unit can be configured to determine the analog precoding matrix according to the channel state information matrix, and then transmit the analog precoding matrix to the digital baseband unit and the mobile phone respectively. Phaser array.
  • the memristor-based storage unit may include a memristor array, where the memristor array Can be constructed from multiple memristor units.
  • a memristor matrix with p rows and q columns is composed of p ⁇ q memristor units.
  • p and q are both integers greater than or equal to 1.
  • the computing power of the memristor-based storage and calculation unit can be achieved by using multiple memristor units arranged and configured as a memristor array capable of performing multiplication and sum operations. .
  • Memristor is a new type of electronic device in which the conductance value of the memristor can be controlled by an external voltage. It is based on this characteristic that the memristor can be used to represent the weight value in a neural network. Therefore, memristor arrays and necessary peripheral circuits can be used to implement matrix-vector multiplication operations and accelerate neural network algorithms.
  • Memristor is a non-volatile memory device. By applying currents of different sizes to both ends of the memristor, its conductance value can be changed, thereby modifying the data stored in the memristor. Arrange the memristor in a certain way. Form a rectangular array and connect them in the row and column directions to form a memristor memory array. At present, memristor memory is often used for matrix-vector product operations. Taking the fully connected layer calculation of a neural network as an example, it is essentially a matrix multiplication operation of a weight matrix and an input vector to obtain an output vector.
  • memristor memory integrates storage and calculation functions, reducing data migration, greatly improving data throughput and computing parallelism, and reducing energy consumption.
  • memristor memory As a new type of non-volatile device, the storage density of memristor memory has been greatly improved compared with traditional memory. Due to the above excellent characteristics, new computing chips based on memristor memory have now become an important means to improve the energy and time efficiency of data-intensive algorithms such as neural network calculations.
  • the multiple memristor units are all 1T1R structures, that is, the structure of any one memristor unit in the memristor array can be 1T1R, or multiple memristor units. They are all 2T2R structures, that is, the structure of any memristor unit in the memristor array can be 2T2R. This application does not limit the structure of the memristor unit, and other structural forms of memristor units that can implement multiplication and accumulation operations can also be used.
  • the memristor unit of the 1T1R structure may include one transistor and one memristor
  • the memristor unit of the 2T2R structure may include two transistors and two memristors.
  • 2T2R is a new type of wireless technology. Among traditional wireless network products, most of them are 1T1R. 1T1R is an antenna responsible for receiving and transmitting signals. Its information load is large, so there is a bottleneck in the LAN transmission rate, and it can only Provides 11G IEEE transmission standard, with a LAN bandwidth of 54M. 2T2R uses dual-antenna technology. The two antennas are responsible for receiving and transmitting respectively. Broadly speaking, it can be understood as dual-channel transmission. In this way, the transmission efficiency of the LAN will be increased by 50% or even more than 100%, thus reaching 11G IEEE. The LAN rate can be Reaching transmission speed of 150M-300M.
  • FIG. 1 is a schematic diagram of a memristor unit.
  • each memristor unit includes a transistor and a memristor.
  • Figure 2 is a schematic diagram 2 of a memristor unit.
  • each memristor unit includes two transistors and two memristors.
  • WL represents the word line, and the gate of the transistor in each row of memristor unit is connected to the corresponding word line of the row
  • BL represents the bit line, and the memristor in each column of memristor unit corresponds to the column.
  • SL represents the source line, and the source electrode of the transistor in each row of memristor unit is connected to the corresponding source line of the row.
  • a memristor array composed of memristor units can complete multiplication and accumulation calculations in parallel.
  • the memristor-based storage and calculation unit may also include a multi-way gate, a sample and hold unit, an analog-to-digital conversion unit, a shift accumulation unit, etc.
  • Figure 3 is a schematic diagram 1 of a memristor-based storage and calculation unit.
  • the memristor-based storage and calculation unit includes a memristor array, and multiple channels are selected. Passer, sample and hold unit, analog-to-digital conversion unit, shift accumulation unit, etc.
  • Each memristor unit in the memristor array includes a transistor and a memristor.
  • the memristor unit can be a positive conductive device or a negative conductive device, and a memristor unit as a positive conductive device and a memristor unit as a negative conductive device can represent a weight value.
  • Figure 4 is a schematic diagram 2 of a memristor-based storage and calculation unit.
  • the memristor-based storage and calculation unit includes a memristor array, and multiple channels are selected. pass, sample and hold unit, analog-to-digital conversion unit, shift accumulation unit, etc.
  • each memristor unit in the memristor array includes two transistors and two memristors.
  • a memristor unit can represent a weight value.
  • the memristor-based storage and calculation unit may be configured to preprocess the channel state information matrix before determining the analog precoding matrix.
  • the channel state information matrix needs to be preprocessed as the input of the memristor-based storage and calculation unit, where the channel state information matrix can be expanded from a complex matrix to a real matrix, respectively:
  • the real part matrix and the imaginary part matrix are then spliced together to facilitate the use of neural networks to calculate complex matrices and reduce the computational complexity.
  • Figure 5 is a schematic diagram of preprocessing of the channel state information matrix.
  • the channel state information matrix is a complex matrix C with m rows and n columns.
  • m ⁇ n when preprocessing the channel state information matrix, the real part and imaginary part of the channel state information matrix can be separated into two real number matrices, that is, the real part matrix R 1 of m rows and n columns m ⁇ n and m
  • the imaginary part matrix R 2 m ⁇ n with rows and n columns can then be spliced together to obtain a real matrix with 2m rows and n columns.
  • m and n are both integers greater than or equal to 1
  • k is the number of channel state information matrices
  • k is a positive integer.
  • the memristor-based storage and calculation unit determines the analog precoding matrix according to the channel state information matrix, it is also configured to determine the attention matrix corresponding to the channel state information matrix according to the channel state information matrix. ; Then determine the sum matrix of the attention matrix and the channel state information matrix, and then input the sum matrix to the convolution layer, and finally the simulated precoding matrix can be output.
  • the memristor-based storage and calculation unit can first linearly transform the channel state information matrix to generate the corresponding attention matrix, and then use The attention matrix and convolutional layer further obtain the simulated precoding matrix.
  • the architecture of the memristor-based storage and computing unit can implement an unsupervised learning neural network algorithm based on the attention mechanism, thereby enabling the generation of a simulated precoding matrix.
  • Figure 6 is a schematic diagram of an unsupervised neural network based on the attention mechanism.
  • the unsupervised neural network based on the attention mechanism can include an attention mechanism layer (linear transformation operation, etc.) and a convolution layer.
  • a memristor array is provided in the memristor-based storage unit.
  • the linear transformation in the attention mechanism layer and the weight value in the convolution layer can be mapped to the conductance value of the memristor array, so that the memristor array can be The array enables low-power, energy-efficient computing.
  • the memristor-based storage and calculation unit determines the attention matrix corresponding to the channel state information matrix according to the channel state information matrix, it is also configured to perform parallel linear processing on the channel state information matrix, Obtain the first matrix, the second matrix and the third matrix respectively; then generate the attention matrix based on the first matrix, the second matrix and the third matrix.
  • the memristor-based storage and calculation unit can use different fully connected layers to perform parallel linear processing on the input channel state information matrix, thereby obtaining different matrices, that is, the first matrix, second matrix and third matrix, These different matrices can then be used to determine the attention matrix.
  • the memristor-based storage and calculation unit when the memristor-based storage and calculation unit performs parallel linear processing on the channel state information matrix to obtain the first matrix, the second matrix and the third matrix respectively, it is also configured to perform The weight values of the first fully connected layer, the second fully connected layer and the third fully connected layer respectively configure the conductance values of the memristor array to obtain the first matrix, the second matrix and the third matrix.
  • the memristor-based storage and calculation unit when the memristor-based storage and calculation unit generates the attention matrix based on the first matrix, the second matrix and the third matrix, it can also be configured to combine the first matrix and the second matrix. Perform matrix multiplication on the transposed matrix to obtain the multiplication result matrix; then use the softmax activation function to process the multiplication result matrix to obtain the processed matrix; then perform matrix multiplication on the processed matrix and the third matrix, and finally obtain the attention matrix .
  • the method for the memristor-based storage and calculation unit to generate the attention matrix P based on the first matrix Q, the second matrix K, and the third matrix V can be as follows:
  • the unsupervised learning neural network algorithm based on the attention mechanism can realize the generation of the attention matrix through the storage and calculation unit based on the memristor, wherein the unsupervised learning neural network algorithm based on the attention mechanism can Supervised neural network algorithms can include attention mechanism layers.
  • the channel state information matrix first undergoes three different linear operations in parallel to obtain three matrices, which are called Query (Q) matrix (first matrix) and Key (K) matrix (second matrix). ), Value(V) matrix (the third matrix), and then the attention matrix can be calculated based on these three matrices.
  • the specific calculation process is to multiply the transpose matrix of the Q matrix and the K matrix and then pass the softmax activation function. The result is multiplied by the V matrix to generate the attention matrix.
  • Figure 7 is a schematic diagram of the attention mechanism layer.
  • the input channel state information matrix passes through three fully connected layers (such as the first fully connected layer, the second fully connected layer layer and the third fully connected layer) to implement parallel linear processing, and obtain three matrices respectively: Query (Q) matrix, Key (K) matrix, and Value (V) matrix.
  • the weight values used by the three fully connected layers are mapped to the conductance values of the memristor array, so that linear processing can be completed through the memristor-based storage and calculation unit.
  • the corresponding attention matrix can be calculated by passing the three matrices through the softmax activation function.
  • the attention matrix and the channel state information matrix are accumulated and normalized to determine the sum matrix of the two.
  • the memristor-based storage and calculation unit when the memristor-based storage and calculation unit obtains the analog precoding matrix, it is also configured to configure the conductance value of the memristor array according to the weight value of the convolution layer to obtain the analog precoding matrix. Coding matrix.
  • the unsupervised learning neural network algorithm based on the attention mechanism can realize the generation of the simulated precoding matrix through the storage and calculation unit based on the memristor
  • the attention mechanism-based Unsupervised neural network algorithms can include convolutional layers.
  • the convolutional layer the sum matrix of the attention matrix and the channel state information matrix is sent to the convolutional layer for encoding, and then the simulated precoding matrix is obtained.
  • the weight values used in the convolutional layer are mapped to the conductance values of the memristor array, so that the encoding process can be completed through the memristor-based storage and calculation unit.
  • FIG. 8 is a schematic structural diagram of a convolution layer. As shown in FIG. 8 , the specific number of layers and the size of the convolution kernel of the convolution layer can be adjusted according to specific communication system parameters.
  • the weight values in the linear transformation and convolutional layers can be trained.
  • the training process of weight values can be performed in an unsupervised manner, that is, there is no need to prepare a labeled data set in advance.
  • the unsupervised training method can be changed by changing the loss function Loss (W, H) of the neural network. It is realized by the sum rate function R (H i , F A , F D ), as follows:
  • W represents the weight value in the linear transformation or convolution layer
  • H 0 is the channel state information matrix generated by actual testing or simulation
  • k is the number of channel state information matrices
  • U is the number of users
  • ⁇ 2 is the noise power
  • ⁇ u is the Signal to Interference plus Noise Ratio (SINR) of the u-th user, configured to represent the strength of the useful signal received by the u-th user and the received interference The ratio of signal (noise and interference) strengths.
  • SINR Signal to Interference plus Noise Ratio
  • the digital baseband unit is configured to determine the digital precoding matrix based on the analog precoding matrix after acquiring the analog precoding matrix transmitted by the memristor-based storage and calculation unit, and based on The digital precoding matrix converts the signal to be transmitted to obtain the converted signal.
  • the digital baseband unit is also configured to determine the equivalent channel matrix based on the analog precoding matrix and the channel matrix corresponding to the antenna array, and then The equivalent channel matrix is then transmitted to the memristor-based storage and computing unit; accordingly, the memristor-based storage and computing unit is also configured to perform matrix inversion processing based on the equivalent channel matrix to obtain the channel inverse matrix, and then The channel inverse matrix is transmitted to the digital baseband unit; then, the digital baseband unit is further configured to determine the digital precoding matrix based on the channel inverse matrix.
  • the memristor array in the memristor-based storage and calculation unit can also be used to accelerate the matrix inversion operation process in the digital precoding calculation process.
  • the digital precoding matrix is generated by the digital baseband unit, in order to improve the efficiency of precoding, the inversion operation part with the highest computational complexity can be performed through the memristor array. deal with. Therefore, after the digital baseband unit determines the equivalent channel matrix based on the analog precoding matrix and the channel matrix corresponding to the antenna array, it can transmit the equivalent channel matrix to the memristor-based storage and calculation unit to pass the memristor-based The storage and calculation unit performs matrix inversion processing to obtain the channel inverse matrix.
  • the digital precoding matrix is obtained by processing the digital baseband unit according to the analog precoding matrix transmitted by the memristor-based storage unit.
  • the digital baseband unit can use a variety of algorithms, including but not limited to zero-forcing algorithm, regularized zero-forcing (RZF), truncated polynomial expansion (truncated polynomial expansion, TPE) and other methods.
  • the zero-forcing algorithm is used as an example to illustrate the method of obtaining the digital precoding matrix.
  • the analog precoding matrix can be defined as F A .
  • the equivalent channel matrix Heq can be expressed as the following formula:
  • H is the channel matrix between the antenna and the user. That is, by performing matrix multiplication on the analog precoding matrix and the channel matrix corresponding to the antenna array, the corresponding equivalent channel matrix can be obtained.
  • the digital precoding matrix F D can be determined through the following formula:
  • ⁇ is used to limit the power of the transmitted signal. It can be known
  • the matrix inversion operation is the most computationally complex part. You can use the memristor array in the memristor-based storage unit to perform matrix inversion processing to obtain the channel inverse matrix.
  • the channel inverse matrix can also be defined as H s -1 , and H s is expressed as the following formula:
  • FIG. 9 is a schematic diagram 1 of the matrix inversion process.
  • a memristor array can be used to perform the matrix inversion operation.
  • the input of the memristor array is the current
  • the voltage read is one of the columns of the inverse matrix.
  • Figure 10 is a schematic diagram 2 of the matrix inversion process.
  • the input is the unit coordinate vector e 1 in turn.
  • e 2 is the unit coordinate vector of the inverse matrix H s -1 .
  • the inverse matrix H s -1 of the Hx matrix can be obtained.
  • the digital baseband unit determines the digital precoding matrix based on the analog precoding matrix, it can use the digital precoding matrix to perform conversion processing on the signal to be transmitted, so as to obtain the conversion corresponding to the signal to be transmitted. post signal.
  • the baseband chip may also include a radio frequency chain unit, where the radio frequency chain unit may include modules such as power amplifiers and filters.
  • the digital baseband unit is also configured to transmit the converted signal to the radio frequency chain unit; the radio frequency chain unit is configured to process the converted signal to obtain the processed signal. The processed signal can then be transmitted to the phase shifter array.
  • the phase shifter array is configured to obtain the processed signal corresponding to the analog precoding matrix transmitted by the memristor-based storage and calculation unit and the converted signal transmitted by the radio frequency chain unit. , can be configured to perform phase-shifting processing on the processed signal according to the analog precoding matrix to obtain the phase-shifted signal, so that the phase-shifted signal can be sent through the antenna array.
  • the phase shifter array may include multiple phase shifters. Wherein, the phase shifter array is further configured to determine the phase of each phase shifter in the plurality of phase shifters according to the analog precoding matrix. Multiple phase shifters can then be used to complete the phase shifting processing of the processed signal.
  • the converted signal obtained after digital precoding conversion of the signal to be transmitted can be further transmitted to the radio frequency chain unit for processing to obtain the corresponding processed signal.
  • the processed signal is then sent to the phase shifter array for phase shifting operation.
  • the phase size of each phase shifter in the phase shifter array is mapped from the analog precoding matrix.
  • the phase-shifted signal after the phase-shifting operation is transmitted to the antenna array, and then the antenna array converts it into electromagnetic waves and sends them out.
  • Figure 11 is a schematic diagram of using a memristor-based storage and calculation unit to implement hybrid precoding.
  • hybrid precoding mainly includes a digital precoding part and an analog precoding part. part.
  • the simulated precoding part the channel state information matrix is transmitted to the memristor-based storage and calculation unit.
  • the memristor-based storage and calculation unit obtains the simulated precoding matrix by operating the neural network algorithm, and then the simulated precoding matrix can be
  • the encoding matrix is transmitted to the digital baseband unit and phase shifter array respectively.
  • the signal to be transmitted can undergo baseband processing through the digital baseband unit, where the baseband processing includes digital precoding processing.
  • the digital baseband unit calculates and obtains the digital precoding matrix by running a zero-forcing algorithm based on the analog precoding matrix transmitted by the memristor-based storage unit. Then the digital precoding matrix can be used to convert the signal to be transmitted to obtain the conversion post signal. After the converted signal after digital precoding conversion is processed by the radio frequency chain unit (including power amplifier, filter and other modules), the corresponding processed signal is obtained. Then, the processed signal is transmitted to the phase shifter array for shifting. Phase processing is performed to obtain the phase-shifted signal. Among them, during the phase-shifting process, The phase size of each phase shifter in the phase shifter array is mapped from the analog precoding matrix. Finally, the phase-shifted signal after the phase-shifting operation is transmitted to the antenna array, where it is converted into electromagnetic waves and sent out.
  • the baseband chip proposed in the embodiment of the present application can use a memristor-based storage and calculation unit to achieve more efficient and faster hybrid precoding processing.
  • the memristor array in the memristor-based storage and calculation unit can be used to run an unsupervised neural network algorithm based on the attention mechanism, and the simulated precoding matrix can be obtained based on the channel state information matrix. Since the memristor-based storage unit, digital baseband unit and phase shifter array are integrated in the same communication module, the time required for data transfer can be reduced when transmitting the analog precoding matrix to the digital baseband unit and phase shifter array. Delay. At the same time, when generating the numerical precoding matrix, the memristor array can also be used to accelerate the calculation process of matrix inversion, further improving the coding efficiency of hybrid precoding.
  • the baseband chip integrated with a memristor-based storage and calculation unit, a digital baseband unit and a phase shifter array proposed in the embodiment of the present application can, on the one hand, reduce the delay of data transfer and the bandwidth of calculation; on the other hand, it can By accelerating the matrix inversion process in the digital precoding calculation process. This will enable low-latency, low-power hybrid precoding to be achieved in future massive MIMO communication systems.
  • Embodiments of the present application provide a baseband chip.
  • the baseband chip includes a memristor-based storage and calculation unit, a digital baseband unit and a phase shifter array, wherein the memristor-based storage and calculation unit is configured to perform operation according to the channel state information.
  • the matrix determines the analog precoding matrix, and transmits the analog precoding matrix to the digital baseband unit and the phase shifter array respectively;
  • the digital baseband unit is configured to determine the digital precoding matrix based on the analog precoding matrix, and transmit it based on the digital precoding matrix
  • the signal is converted and processed to obtain the converted signal;
  • the phase shifter array is configured to obtain the processed signal corresponding to the converted signal, and perform phase shifting processing on the processed signal according to the analog precoding matrix to obtain the phase-shifted signal to pass
  • the antenna array transmits the phase-shifted signal. That is to say, in the embodiments of the present application, hybrid precoding processing that integrates calculation and storage can be implemented based on the memristor array.
  • memristor-based storage and computing units can be used to accelerate the calculation process of analog precoding matrices in hybrid precoding, which can provide high energy-efficiency computing power, and memristor-based storage and computing units, digital baseband units and phase shifting
  • the processor array is integrated into a baseband chip to reduce data transfer delays. It can be seen that the hybrid precoding processing scheme based on memristor-based storage and calculation units can reduce power consumption and delay, thereby improving communication efficiency and communication performance.
  • Figure 12 is a schematic structural diagram of a baseband chip.
  • the baseband chip 10 may include a memristor-based storage unit 11, a digital baseband unit 12 and phase shifter array 13.
  • the memristor-based storage and calculation unit 11 is configured to determine the analog precoding matrix according to the channel state information matrix, and transmit the analog precoding matrix to the digital baseband unit 12 and the phase shifter array 13 respectively;
  • the digital baseband unit 12 is configured to determine the digital precoding matrix based on the analog precoding matrix, and perform conversion processing on the signal to be transmitted based on the digital precoding matrix to obtain the converted signal;
  • the phase shifter array 13 is configured to obtain the processed signal corresponding to the converted signal, and perform phase shifting processing on the processed signal according to the analog precoding matrix to obtain the phase-shifted signal, so as to send the phase-shifted signal through the antenna array.
  • Figure 13 is a schematic diagram 2 of the composition structure of the baseband chip.
  • the memristor-based storage unit 11 includes a memristor array 111, where the memristor array 111 It is composed of multiple memristor units, and the multiple memristor units are all in a 1T1R structure, or the multiple memristor units are in a 2T2R structure.
  • the structure of any memristor unit in the memristor array may be 1T1R, or the structure of any memristor unit in the memristor array may be 2T2R.
  • This application does not limit the structure of the memristor unit, and other structural forms of memristor units that can implement multiplication and accumulation operations can also be used.
  • the memristor-based storage and calculation unit 11 is also configured to determine the attention matrix corresponding to the channel state information matrix according to the channel state information matrix; determine the sum of the attention matrix and the channel state information matrix value matrix, input the sum value matrix to the convolutional layer, and output the analog precoding matrix.
  • the memristor-based storage and calculation unit 11 is also configured to perform parallel linear processing on the channel state information matrix to obtain the first matrix, the second matrix and the third matrix respectively; according to the first The matrix, the second matrix and the third matrix generate the attention matrix.
  • the memristor-based storage unit 11 is also configured to respectively configure the memristor array according to the weight values of the first fully connected layer, the second fully connected layer, and the third fully connected layer. conductance values to obtain the first matrix, the second matrix and the third matrix.
  • the memristor-based storage and calculation unit 11 is also configured to perform matrix multiplication on the transpose matrix of the first matrix and the second matrix to obtain the multiplication result matrix; use a softmax activation function to process Multiply the result matrix to obtain the processed matrix; perform matrix multiplication between the processed matrix and the third matrix to obtain the attention matrix.
  • the memristor-based storage and calculation unit can first linearly transform the channel state information matrix, where the memristor-based storage and calculation unit Different fully connected layers, namely the first fully connected layer, the second fully connected layer and the third fully connected layer, can be used to perform parallel linear processing on the input channel state information matrix respectively, thereby obtaining different matrices, namely the first matrix , the second matrix and the third matrix, and then these different matrices can be used to determine the attention matrix.
  • the conductance values of the memristor arrays can be respectively configured according to the weight values of the first fully connected layer, the first fully connected layer and the third fully connected layer.
  • the memristor-based storage and calculation unit can perform matrix multiplication on the transposed matrix of the first matrix and the second matrix through the above formula (1) to obtain the multiplication result matrix; then use the softmax activation function to process the multiplication result matrix, Obtain the processed matrix; then perform matrix multiplication between the processed matrix and the third matrix, and finally obtain the attention matrix.
  • the memristor-based storage and calculation unit 11 is also configured to configure the conductance value of the memristor array according to the weight value of the convolution layer to obtain an analog precoding matrix.
  • the convolution layer in the convolution layer, the sum matrix of the attention matrix and the channel state information matrix is sent to the convolution layer for encoding, thereby obtaining a simulated precoding matrix.
  • the weight values used in the convolutional layer are mapped to the conductance values of the memristor array, so that the encoding process can be completed through the memristor-based storage and calculation unit.
  • the memristor-based storage and calculation unit 11 is also configured to preprocess the channel state information matrix.
  • the channel state information matrix needs to be preprocessed as the input of the memristor-based storage and calculation unit, where the channel state information matrix can be expanded from a complex matrix to a real matrix, respectively. are the real part matrix and the imaginary part matrix, and then the two matrices are spliced together to facilitate the use of neural networks to calculate complex matrices and reduce the computational complexity.
  • the digital baseband unit 12 is also configured to determine the equivalent channel matrix based on the analog precoding matrix and the channel matrix corresponding to the antenna array, and transmit the equivalent channel matrix to the memristor-based memory. computing unit;
  • the memristor-based storage and calculation unit 11 is also configured to perform matrix inversion processing based on the equivalent channel matrix, obtain the channel inverse matrix, and transmit the channel inverse matrix to the digital baseband unit;
  • the digital baseband unit 12 is also configured to determine the digital precoding matrix according to the inverse channel matrix.
  • the part of the inversion operation with the highest computational complexity can be processed through a memristor array. Therefore, after the digital baseband unit determines the equivalent channel matrix based on the analog precoding matrix and the channel matrix corresponding to the antenna array, it can transmit the equivalent channel matrix to the memristor-based storage and calculation unit to pass the memristor-based The storage and calculation unit performs matrix inversion processing to obtain the channel inverse matrix. Then, the digital baseband unit can further determine the digital precoding matrix based on the channel inverse matrix.
  • the digital baseband unit in the generation process of the digital precoding matrix, can adopt a variety of algorithms, including but not limited to zero-forcing algorithm, normalized zero-forcing, truncated polynomial expansion and other methods .
  • the baseband chip 10 also includes a radio frequency chain unit 14,
  • the digital baseband unit 12 is also configured to transmit the converted signal to the radio frequency chain unit;
  • the radio frequency chain unit 14 is configured to process the converted signal to obtain the processed signal.
  • the baseband chip may also include a radio frequency chain unit, where the radio frequency chain unit may include modules such as power amplifiers and filters.
  • the radio frequency chain unit processes the converted signal and obtains the processed signal, it can transmit the processed signal to the phase shifter array.
  • the phase shifter array 13 includes a plurality of phase shifters 131,
  • the phase shifter array 13 is further configured to determine the phase of each phase shifter in the plurality of phase shifters 131 according to the analog precoding matrix.
  • phase size of each phase shifter in the phase shifter array is mapped from the analog precoding matrix.
  • the phase-shifted signal after the phase-shifting operation is transmitted to the antenna array, and then the antenna array converts it into electromagnetic waves and sends them out.
  • the hybrid precoding process mainly includes a digital precoding part and an analog precoding part.
  • the analog precoding matrix required by the digital precoding part and the analog precoding part is generated by a memristor-based storage unit.
  • the matrix inversion operation in the digital precoding process is also accelerated by the memristor array in the memristor-based storage and calculation unit.
  • the channel state information matrix is transmitted to the memristor-based storage and computing unit.
  • the memristor-based storage and computing unit obtains the simulated precoding matrix by operating the neural network algorithm, and then the simulated precoding matrix can be Sent to the digital baseband unit and phase shifter array respectively.
  • the architecture of the memristor-based storage and computing unit can implement an unsupervised learning neural network algorithm based on the attention mechanism, thereby enabling the generation of a simulated precoding matrix.
  • Figure 14 is a schematic diagram 2 of an unsupervised neural network based on the attention mechanism.
  • the unsupervised neural network based on the attention mechanism can include an attention mechanism layer (linear transformation operation, etc.) and a convolution layer.
  • a memristor array is provided in the memristor-based storage unit.
  • the linear transformation in the attention mechanism layer and the weight value in the convolution layer can be mapped to the conductance value of the memristor array, so that the memristor array can be
  • the array enables low-power, energy-efficient computing.
  • the input channel state information matrix undergoes parallel linear processing through three fully connected layers (such as the first fully connected layer, the second fully connected layer, and the third fully connected layer) to obtain three matrices. They are called Query (Q) matrix (first matrix), Key (K) matrix (second matrix), and Value (V) matrix (third matrix).
  • the attention matrix can then be calculated based on these three matrices.
  • the specific calculation process is to multiply the transpose matrix of the Q matrix and the K matrix and then pass the softmax activation function. The result is multiplied by the V matrix to generate the attention matrix. Finally, the attention matrix and the channel state information matrix are accumulated and normalized to determine the sum matrix of the two, and then the sum matrix is input to the convolutional layer for encoding, thereby obtaining the simulated precoding matrix.
  • the weights used by the convolutional layer The heavy value is mapped to the conductance value of the memristor array, so that the encoding process can be completed through the memristor-based storage unit.
  • the signal to be transmitted can undergo baseband processing through the digital baseband unit, where the baseband processing includes digital precoding processing.
  • the digital baseband unit calculates and obtains the digital precoding matrix by running a zero-forcing algorithm based on the analog precoding matrix transmitted by the memristor-based storage unit. Then the digital precoding matrix can be used to convert the signal to be transmitted to obtain the conversion post signal. After the converted signal after digital precoding conversion is processed by the radio frequency chain unit (including power amplifier, filter and other modules), the corresponding processed signal is obtained.
  • the processed signal is sent to the phase shifter array for phase shifting processing to obtain the phase shifted signal.
  • the phase size of each phase shifter in the phase shifter array is mapped from the analog precoding matrix.
  • the phase-shifted signal after the phase-shifting operation is transmitted to the antenna array, where it is converted into electromagnetic waves and sent out.
  • the baseband chip proposed in the embodiments of this application can implement hybrid precoding processing that integrates computing and storage based on memristor arrays, break through the "storage wall" bottleneck of the von Neumann architecture, and accelerate matrix-vector multiplication.
  • memristor-based storage and computing units can be used to accelerate the calculation process of analog precoding matrices in hybrid precoding; at the same time, memristor-based storage and computing units have the characteristics of small area and can provide high energy-efficiency computing power , so it can be integrated into a communication unit (such as a baseband chip) to reduce the data transfer delay of the communication unit and computing unit.
  • the memristor array can be used to accelerate the calculation of the inversion of the matrix, further increasing the computational energy efficiency of the digital precoding part in the hybrid precoding process. Therefore, the hybrid precoding processing of memristor-based storage and calculation units provides a high energy efficiency, low delay, and small area hybrid precoding solution for future communication systems.
  • Embodiments of the present application provide a baseband chip.
  • the baseband chip includes a memristor-based storage and calculation unit, a digital baseband unit and a phase shifter array, wherein the memristor-based storage and calculation unit is configured to perform operation according to the channel state information.
  • the matrix determines the analog precoding matrix, and transmits the analog precoding matrix to the digital baseband unit and the phase shifter array respectively;
  • the digital baseband unit is configured to determine the digital precoding matrix based on the analog precoding matrix, and transmit it based on the digital precoding matrix
  • the signal is converted and processed to obtain the converted signal;
  • the phase shifter array is configured to obtain the processed signal corresponding to the converted signal, and perform phase shifting processing on the processed signal according to the analog precoding matrix to obtain the phase-shifted signal to pass
  • the antenna array transmits the phase-shifted signal. That is to say, in the embodiments of the present application, hybrid precoding processing that integrates calculation and storage can be implemented based on the memristor array.
  • memristor-based storage and computing units can be used to accelerate the calculation process of analog precoding matrices in hybrid precoding, which can provide high energy-efficiency computing power, and memristor-based storage and computing units, digital baseband units and phase shifting
  • the processor array is integrated into a baseband chip to reduce data transfer delays. It can be seen that the hybrid precoding processing scheme based on memristor-based storage and calculation units can reduce power consumption and delay, thereby improving communication efficiency and communication performance.
  • an embodiment of the present application provides a hybrid precoding method.
  • the hybrid precoding method can be applied to terminal equipment, where the terminal equipment can be configured with a baseband chip, and the baseband chip can include a memristor-based storage unit, digital baseband unit and phase shifter array.
  • Figure 15 is a schematic flow chart of the implementation of the hybrid precoding method proposed by the embodiment of the present application. As shown in Figure 15, the method for a terminal device to perform hybrid precoding may include the following steps:
  • Step 101 The baseband chip determines the analog precoding matrix based on the channel state information matrix, determines the digital precoding matrix based on the analog precoding matrix, and performs conversion processing on the signal to be transmitted based on the digital precoding matrix to obtain the converted signal; obtain the corresponding signal after conversion The processed signal is processed, and the processed signal is phase-shifted according to the analog precoding matrix to obtain the phase-shifted signal.
  • the baseband chip when it performs step 101, it may include: a memristor-based storage and calculation unit according to the channel state information matrix Determine the analog precoding matrix, and transmit the analog precoding matrix to the digital baseband unit and phase shifter array respectively; the digital baseband unit determines the digital precoding matrix based on the analog precoding matrix, and performs conversion processing on the signal to be transmitted based on the digital precoding matrix , to obtain the converted signal; the phase shifter array obtains the processed signal corresponding to the converted signal, and performs phase shifting on the processed signal according to the analog precoding matrix to obtain the phase-shifted signal.
  • the memristor-based storage and calculation unit can first determine the analog precoding matrix according to the channel state information matrix, and then transmit the analog precoding matrix to the digital baseband unit and the phase shifter array respectively.
  • the memristor-based storage unit may include a memristor array, where the memristor array may be composed of multiple memristor units.
  • the memristor array may be composed of multiple memristor units.
  • a memristor matrix with p rows and q columns is composed of p ⁇ q memristor units.
  • p and q are both integers greater than or equal to 1.
  • the computing power of the memristor-based storage and calculation unit can be achieved by using multiple memristor units arranged and configured as a memristor array capable of performing multiplication and sum operations. .
  • the multiple memristor units are all 1T1R structures, that is, the structure of any one memristor unit in the memristor array can be 1T1R, or multiple memristor units. They are all 2T2R structures, that is, the structure of any memristor unit in the memristor array can be 2T2R. This application does not limit the structure of the memristor unit, and other structural forms of memristor units that can implement multiplication and accumulation operations can also be used.
  • the memristor unit of the 1T1R structure may include one transistor and one memristor
  • the memristor unit of the 2T2R structure may include two transistors and two memristors.
  • a memristor array composed of memristor units can complete multiplication and accumulation calculations in parallel.
  • the memristor-based storage and calculation unit includes a memristor array, a multi-way gate, a sample and hold unit, an analog-to-digital conversion unit, a shift unit, and a memristor array. Accumulation unit, etc.
  • Each memristor unit in the memristor array includes a transistor and a memristor.
  • the memristor unit can be a positive conductive device or a negative conductive device, and a memristor unit as a positive conductive device and a memristor unit as a negative conductive device can represent a weight value.
  • the memristor-based storage and calculation unit includes a memristor array, a multi-way gate, a sample and hold unit, an analog-to-digital conversion unit, a shift unit, and a memristor array. Accumulation unit etc.
  • each memristor unit in the memristor array includes two transistors and two memristors.
  • a memristor unit can represent a weight value.
  • the memristor-based storage and calculation unit can also preprocess the channel state information matrix.
  • the channel state information matrix needs to be preprocessed as the input of the memristor-based storage and calculation unit, where the channel state information matrix can be expanded from a complex matrix to a real matrix, respectively:
  • the real part matrix and the imaginary part matrix are then spliced together to facilitate the use of neural networks to calculate complex matrices and reduce the computational complexity.
  • the memristor-based storage and calculation unit when the memristor-based storage and calculation unit determines the simulated precoding matrix based on the channel state information matrix, it can also determine the attention matrix corresponding to the channel state information matrix based on the channel state information matrix; Then the sum matrix of the attention matrix and the channel state information matrix is determined, and then the sum matrix is input to the convolution layer, and finally the simulated precoding matrix can be output.
  • the memristor-based storage and calculation unit can first linearly transform the channel state information matrix to generate the corresponding attention matrix, and then use The attention matrix and convolutional layer further obtain the simulated precoding matrix.
  • the architecture of the memristor-based storage and computing unit can implement an unsupervised learning neural network algorithm based on the attention mechanism, thereby enabling the generation of a simulated precoding matrix.
  • the unsupervised neural network based on the attention mechanism can include an attention mechanism layer (linear transformation operation, etc.) and a convolution layer.
  • a memristor array is provided in the memristor-based storage unit. The linear transformation in the attention mechanism layer and the weight value in the convolution layer can be mapped to the conductance value of the memristor array, so that the memristor array can be The array enables low-power, energy-efficient computing.
  • the memristor-based storage and calculation unit determines the attention matrix corresponding to the channel state information matrix according to the channel state information matrix, it can also perform parallel linear processing on the channel state information matrix, respectively. Obtain the first matrix, the second matrix and the third matrix; then generate the attention matrix based on the first matrix, the second matrix and the third matrix.
  • the memristor-based storage and calculation unit can use different fully connected layers to perform parallel linear processing on the input channel state information matrix, thereby obtaining different matrices, that is, the first matrix, the second matrix and the third matrix, and then these different matrices can be used to determine the attention matrix.
  • the memristor-based storage and calculation unit when the memristor-based storage and calculation unit performs parallel linear processing on the channel state information matrix to obtain the first matrix, the second matrix and the third matrix respectively, it can also be based on the first matrix.
  • the weight values of the fully connected layer, the second fully connected layer and the third fully connected layer respectively configure the conductance values of the memristor array to obtain the first matrix, the second matrix and the third matrix.
  • the memristor-based storage and calculation unit when the memristor-based storage and calculation unit generates the attention matrix based on the first matrix, the second matrix and the third matrix, it can also transform the first matrix and the second matrix. Set the matrix and perform matrix multiplication to obtain the multiplication result matrix; then use the softmax activation function to process the multiplication result matrix to obtain the processed matrix; then perform matrix multiplication between the processed matrix and the third matrix to finally obtain the attention matrix.
  • the unsupervised learning neural network algorithm based on the attention mechanism can realize the generation of the attention matrix through the storage and calculation unit based on the memristor, wherein the unsupervised learning neural network algorithm based on the attention mechanism can Supervised neural network algorithms can include attention mechanism layers.
  • the input channel state information matrix undergoes parallel linear processing through three fully connected layers (such as the first fully connected layer, the second fully connected layer, and the third fully connected layer) to obtain three matrices. They are called Query (Q) matrix (first matrix), Key (K) matrix (second matrix), and Value (V) matrix (third matrix).
  • the attention matrix can then be calculated based on these three matrices.
  • the specific calculation process is to multiply the transpose matrix of the Q matrix and the K matrix and then pass the softmax activation function. The result is multiplied by the V matrix to generate the attention matrix. Finally, the attention matrix and the channel state information matrix are accumulated and normalized to determine the sum matrix of the two.
  • the memristor-based storage and calculation unit when the memristor-based storage and calculation unit obtains the analog precoding matrix, it can also configure the conductance value of the memristor array according to the weight value of the convolution layer to obtain the analog precoding matrix. matrix.
  • the unsupervised learning neural network algorithm based on the attention mechanism can realize the generation of the simulated precoding matrix through the storage and calculation unit based on the memristor
  • the attention mechanism-based Unsupervised neural network algorithms can include convolutional layers.
  • the convolutional layer the sum matrix of the attention matrix and the channel state information matrix is sent to the convolutional layer for encoding, and then the simulated precoding matrix is obtained.
  • the weight value used in the convolution layer is mapped to the conductance value of the memristor array, so that the memristor-based
  • the storage and computing unit completes the encoding process.
  • the specific number of convolutional layers and the size of the convolution kernel can be adjusted according to specific communication system parameters.
  • the weight values in the linear transformation and convolutional layers can be trained.
  • the training process of weight values can be performed in an unsupervised manner, that is, there is no need to prepare a labeled data set in advance.
  • Unsupervised training can be achieved by changing the loss function of the neural network to a sum rate function.
  • the digital baseband unit after the digital baseband unit obtains the analog precoding matrix transmitted by the memristor-based storage and calculation unit, it can determine the digital precoding matrix based on the analog precoding matrix, and then the digital precoding matrix is to be transmitted based on the digital precoding matrix.
  • the signal is converted and processed to obtain the converted signal.
  • the digital baseband unit can also determine the equivalent channel matrix based on the analog precoding matrix and the channel matrix corresponding to the antenna array, and then The equivalent channel matrix is transmitted to the memristor-based storage and computing unit; accordingly, the memristor-based storage and computing unit can also perform matrix inversion processing based on the equivalent channel matrix to obtain the channel inverse matrix, and then invert the channel matrix. Transmitted to the digital baseband unit; then, the digital baseband unit can also determine the digital precoding matrix based on the channel inverse matrix.
  • the memristor array in the memristor-based storage and calculation unit can also be used to accelerate the matrix inversion operation process in the digital precoding calculation process.
  • the digital precoding matrix is generated by the digital baseband unit, in order to improve the efficiency of precoding, the inversion operation part with the highest computational complexity can be performed through the memristor array. deal with. Therefore, after the digital baseband unit determines the equivalent channel matrix based on the analog precoding matrix and the channel matrix corresponding to the antenna array, it can transmit the equivalent channel matrix to the memristor-based storage and calculation unit to pass the memristor-based The storage and calculation unit performs matrix inversion processing to obtain the channel inverse matrix.
  • the digital precoding matrix is obtained by processing the digital baseband unit according to the analog precoding matrix transmitted by the memristor-based storage unit.
  • the digital baseband unit can adopt a variety of algorithms, including but not limited to zero-forcing algorithm, regularized zero-forcing, truncated polynomial expansion and other methods.
  • the digital baseband unit determines the digital precoding matrix based on the analog precoding matrix, it can use the digital precoding matrix to perform conversion processing on the signal to be transmitted, so as to obtain the conversion corresponding to the signal to be transmitted. post signal.
  • the baseband chip may also include a radio frequency chain unit, where the radio frequency chain unit may include modules such as power amplifiers and filters.
  • the digital baseband unit can also transmit the converted signal to the radio frequency chain unit; the radio frequency chain unit can process the converted signal to obtain the processed signal. The processed signal can then be transmitted to the phase shifter array.
  • the phase shifter array after acquiring the processed signal corresponding to the simulated precoding matrix transmitted by the memristor-based storage and calculation unit and the converted signal transmitted by the radio frequency chain unit, the phase shifter array can perform the processing according to the simulated precoding matrix.
  • the matrix performs phase-shifting processing on the processed signal to obtain the phase-shifted signal.
  • the phase shifter array may include multiple phase shifters.
  • the phase shifter array can also determine the phase of each phase shifter in the plurality of phase shifters according to the analog precoding matrix. Multiple phase shifters can then be used to complete the phase shifting processing of the processed signal.
  • the converted signal obtained after digital precoding conversion of the signal to be transmitted can be further transmitted to the radio frequency chain unit for processing to obtain the corresponding processed signal.
  • the processed signal is then sent to the phase shifter array for phase shifting operation.
  • the phase size of each phase shifter in the phase shifter array is mapped by the analog precoding matrix.
  • Step 102 The antenna array sends the phase-shifted signal.
  • the antenna array when the phase-shifted signal after the phase-shifting operation is transmitted to the antenna array, the antenna array can convert the phase-shifted signal into an electromagnetic wave and send it out, thereby completing the transmission of the signal to be transmitted.
  • the hybrid precoding method proposed in steps 101 to 104 is applied to a baseband chip integrating a memristor-based storage unit, a digital baseband unit, and a phase shifter array.
  • the hybrid precoding process is divided into a digital precoding part and an analog precoding part.
  • the digital precoding part is completed by a digital baseband chip
  • the analog precoding part is completed by a memristor-based storage unit and phase shifter array.
  • the memristor-based storage and computing unit obtains the simulated precoding matrix by running attention-based neural networks and convolutional neural networks, and obtains the weights of the neural network in an unsupervised manner.
  • the memristor-based storage unit, digital baseband unit and phase shifter array are integrated in the same communication module, the time required for data transfer can be reduced when transmitting the analog precoding matrix to the digital baseband unit and phase shifter array. Delay.
  • the memristor array when generating the numerical precoding matrix, can also be used to accelerate the calculation process of matrix inversion, further improving the coding efficiency of hybrid precoding.
  • the hybrid precoding method proposed in the embodiment of this application can reduce the data transfer of the communication unit and the computing unit, has the characteristics of low delay and low power consumption, and can provide a new hybrid precoding solution for future communication systems.
  • the embodiment of the present application provides a hybrid precoding method.
  • the hybrid precoding method should be configured as a terminal device.
  • the terminal device includes an antenna array and a baseband chip.
  • the baseband chip includes a memristor-based storage unit, a digital baseband unit and a mobile phone.
  • phase shifter array wherein the memristor-based storage and calculation unit is configured to determine the analog precoding matrix according to the channel state information matrix, and transmit the analog precoding matrix to the digital baseband unit and the phase shifter array respectively; the digital baseband unit, The phase shifter array is configured to determine the digital precoding matrix based on the analog precoding matrix, and perform conversion processing on the signal to be transmitted based on the digital precoding matrix to obtain the converted signal; the phase shifter array is configured to obtain the processed signal corresponding to the converted signal, and perform conversion processing based on the digital precoding matrix.
  • the analog precoding matrix performs phase-shifting processing on the processed signal to obtain the phase-shifted signal to send the phase-shifted signal through the antenna array.
  • hybrid precoding processing that integrates calculation and storage can be implemented based on the memristor array.
  • memristor-based storage and computing units can be used to accelerate the calculation process of analog precoding matrices in hybrid precoding, which can provide high energy-efficiency computing power
  • the processor array is integrated into a baseband chip to reduce data transfer delays. It can be seen that the hybrid precoding processing scheme based on memristor-based storage and calculation units can reduce power consumption and delay, thereby improving communication efficiency and communication performance.
  • yet another embodiment of the present application provides a terminal device, which may include an antenna array and a baseband chip.
  • the baseband chip can be configured to perform hybrid precoding processing on the signal to be transmitted to obtain the phase-shifted signal; correspondingly, the antenna array can be configured to transmit the phase-shifted signal.
  • FIG. 16 is a schematic structural diagram of a terminal device.
  • the terminal device 20 may include an antenna array 21 and a baseband chip 10 .
  • the baseband chip 10 may include a memristor-based storage unit 11, a digital baseband unit 12, a phase shifter array 13 and a radio frequency chain unit 14.
  • the memristor-based storage and calculation unit 11 is configured to determine the analog precoding matrix according to the channel state information matrix, and transmit the analog precoding matrix to the digital baseband unit 12 and the phase shifter array 13 respectively;
  • the digital baseband unit 12 is configured to determine the digital precoding matrix based on the analog precoding matrix, and perform conversion processing on the signal to be transmitted based on the digital precoding matrix to obtain the converted signal;
  • the phase shifter array 13 is configured to obtain the processed signal corresponding to the converted signal, and perform phase shifting processing on the processed signal according to the analog precoding matrix to obtain the phase-shifted signal, so as to send the phase-shifted signal through the antenna array.
  • the memristor-based storage unit 11 includes a memristor array 111, wherein the memristor array 111 is composed of a plurality of memristor units, and the plurality of memristor units are 1T1R structure, or multiple memristor units are all 2T2R structure.
  • the memristor-based storage and calculation unit 11 is also configured to determine the attention matrix corresponding to the channel state information matrix according to the channel state information matrix; determine the sum of the attention matrix and the channel state information matrix value matrix, input the sum value matrix to the convolutional layer, and output the analog precoding matrix.
  • the memristor-based storage and calculation unit 11 is also configured to perform parallel linear processing on the channel state information matrix to obtain the first matrix, the second matrix and the third matrix respectively; according to the first The matrix, the second matrix and the third matrix generate the attention matrix.
  • the memristor-based storage unit 11 is also configured to respectively configure the memristor array according to the weight values of the first fully connected layer, the second fully connected layer, and the third fully connected layer. conductance values to obtain the first matrix, the second matrix and the third matrix.
  • the memristor-based storage and calculation unit 11 is also configured to perform matrix multiplication on the transpose matrix of the first matrix and the second matrix to obtain the multiplication result matrix; use a softmax activation function to process Multiply the result matrix to obtain the processed matrix; perform matrix multiplication between the processed matrix and the third matrix to obtain the attention matrix.
  • the memristor-based storage and calculation unit 11 is also configured to configure the conductance value of the memristor array according to the weight value of the convolution layer to obtain an analog precoding matrix.
  • the memristor-based storage and calculation unit 11 is also configured to preprocess the channel state information matrix.
  • the digital baseband unit 12 is also configured to determine the equivalent channel matrix based on the analog precoding matrix and the channel matrix corresponding to the antenna array, and transmit the equivalent channel matrix to the memristor-based memory. computing unit;
  • the memristor-based storage and calculation unit 11 is also configured to perform matrix inversion processing based on the equivalent channel matrix, obtain the channel inverse matrix, and transmit the channel inverse matrix to the digital baseband unit;
  • the digital baseband unit 12 is also configured to determine the digital precoding matrix according to the inverse channel matrix.
  • the digital baseband unit 12 is also configured to transmit the converted signal to the radio frequency chain unit;
  • the radio frequency chain unit 14 is configured to process the converted signal to obtain the processed signal.
  • the phase shifter array 13 includes a plurality of phase shifters 131,
  • the phase shifter array 13 is further configured to determine the phase of each phase shifter in the plurality of phase shifters 131 according to the analog precoding matrix.
  • Embodiments of the present application provide a terminal device.
  • the terminal device includes an antenna array and a baseband chip.
  • the baseband chip includes a memristor-based storage unit, a digital baseband unit, and a phase shifter array.
  • the memristor-based storage unit The computing unit is configured to determine the analog precoding matrix based on the channel state information matrix, and transmit the analog precoding matrix to the digital baseband unit and phase shifter array respectively; the digital baseband unit is configured to determine the digital precoding matrix based on the analog precoding matrix.
  • the phase shifter array is configured to obtain the processed signal corresponding to the converted signal, and perform phase shifting processing on the processed signal according to the analog precoding matrix , obtain the phase-shifted signal to send the phase-shifted signal through the antenna array. That is to say, in this application, a hybrid precoding process that integrates computing and storage can be implemented based on the memristor array.
  • memristor-based storage and computing units can be used to accelerate the calculation process of analog precoding matrices in hybrid precoding, which can provide high energy-efficiency computing power, and memristor-based storage and computing units, digital baseband units and phase shifting
  • the processor array is integrated into a baseband chip to reduce data transfer delays. It can be seen that the hybrid precoding processing solution based on memristor-based storage and calculation units can reduce power consumption and delay, thereby improving communication efficiency and communication performance.
  • embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, magnetic disk storage and optical storage, etc.) embodying computer-usable program code therein.
  • a computer-usable storage media including, but not limited to, magnetic disk storage and optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions
  • the device implements the functions specified in implementing one process or processes in the flow diagram and/or one block or blocks in the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in implementing a process or processes of the flowchart diagram and/or a block or blocks of the block diagram.
  • hybrid precoding processing that integrates calculation and storage can be implemented based on the memristor array.
  • memristor-based storage and computing units can be used to accelerate the calculation process of analog precoding matrices in hybrid precoding, which can provide high energy-efficiency computing power
  • memristor-based storage and computing units, digital baseband units and phase shifting The processor array is integrated into a baseband chip to reduce data transfer delays. It can be seen that the hybrid precoding processing scheme based on memristor-based storage and calculation units can reduce power consumption and delay, thereby improving communication efficiency and communication performance.

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Abstract

本申请实施例公开了一种基带芯片，基带芯片包括基于忆阻器的存算单元，数字基带单元以及移相器阵列，其中，基于忆阻器的存算单元，配置为根据信道状态信息矩阵确定模拟预编码矩阵，并将模拟预编码矩阵分别传输至数字基带单元和移相器阵列；数字基带单元，配置为根据模拟预编码矩阵确定数字预编码矩阵，并基于数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；移相器阵列，配置为获取转换后信号对应的处理后信号，并根据模拟预编码矩阵对处理后信号进行移相处理，获得移相后信号，以通过天线阵列发送移相后信号。

Description

基带芯片、混合预编码方法及终端设备
相关申请的交叉引用
本申请基于申请号为202211047817.5，申请日为2022年8月30日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及芯片设计领域，尤其涉及一种基带芯片、混合预编码方法及终端设备。
背景技术
随着通信技术的不断发展，通信系统的数据传输带宽和速度也在不断提升。为了减少路径损耗和用户间的干扰，混合预编码被应用在通信系统发射端，从而可以控制所发射信号的能量集中方向。
然而，对于未来的大规模多进多出(Multiple-Input Multiple-Output，MIMO)通信系统来说，天线阵列的规模越来越大，因此混合预编码所需要的算力也急剧增加。而常用的计算芯片主要基于冯诺依曼结构，运行如基于交叉熵优化算法的传统算法，存在功耗高、延迟大的缺陷，进而影响通信效率和通信性能。
发明内容
本申请实施例提供了一种基带芯片、混合预编码方法及终端设备。
本申请实施例的技术方案是这样实现的：
第一方面，本申请实施例提供了一种基带芯片，所述基带芯片包括基于忆阻器的存算单元，数字基带单元以及移相器阵列，其中，
所述基于忆阻器的存算单元，配置为根据信道状态信息矩阵确定模拟预编码矩阵，并将所述模拟预编码矩阵分别传输至所述数字基带单元和所述移相器阵列；
所述数字基带单元，配置为根据所述模拟预编码矩阵确定数字预编码矩阵，并基于所述数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；
所述移相器阵列，配置为获取所述转换后信号对应的处理后信号，并根据所述模拟预编码矩阵对所述处理后信号进行移相处理，获得移相后信号，以通过天线阵列发送所述移相后信号。
第二方面，本申请实施例提供了一种混合预编码方法，所述混合预编码方法应用于终端设备，所述终端设备配置基带芯片和天线阵列，所述基带芯片包括基于忆阻器的存算单元，数字基带单元以及移相器阵列，所述方法包括：
所述基于忆阻器的存算单元根据信道状态信息矩阵确定模拟预编码矩阵，并将所述模拟预编码矩阵 分别传输至所述数字基带单元和所述移相器阵列；
所述数字基带单元根据所述模拟预编码矩阵确定数字预编码矩阵，并基于所述数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；
所述移相器阵列获取所述转换后信号对应的处理后信号，并根据所述模拟预编码矩阵对所述处理后信号进行移相处理，获得移相后信号；
所述天线阵列发送所述移相后信号。
第三方面，本申请实施例提供了一种终端设备，所述终端设备包括天线阵列和如上述第一方面所述的基带芯片，其中，
所述基带芯片，配置为对待传输信号进行混合预编码处理，获得移相后信号；
所述天线阵列，配置为发送所述移相后信号。
附图说明
图1为忆阻器单元的示意图一；
图2为忆阻器单元的示意图二；
图3为基于忆阻器的存算单元的示意图一；
图4为基于忆阻器的存算单元的示意图二；
图5为信道状态信息矩阵的预处理的示意图；
图6为基于注意力机制的非监督神经网络的示意图一；
图7为注意力机制层的示意图；
图8为卷积层的结构示意图；
图9为矩阵求逆处理的示意图一；
图10为矩阵求逆处理的示意图二；
图11为使用基于忆阻器的存算单元实现混合预编码的示意图；
图12为基带芯片的组成结构示意图一；
图13为基带芯片的组成结构示意图二；
图14为基于注意力机制的非监督神经网络的示意图二；
图15为本申请实施例提出的混合预编码方法的实现流程示意图；
图16为终端设备的组成结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
随着通信技术的不断发展，通信系统的数据传输带宽和速度也在不断提升。大规模MIMO和毫米波技术已经成为第五代移动通信技术(5th Generation Mobile Communication Technology，5G)以及第六代移 动通信技术(6th generation mobile networks，6G)中的关键技术。为了减少毫米波大规模MIMO通信系统本身的路径损耗和用户间的干扰，混合预编码被应用在通信系统发射端，从而可以控制所发射信号的能量集中方向。
然而，对于未来的大规模MIMO通信系统来说，天线阵列的规模越来越大，因此混合预编码所需要的算力也急剧增加。目前，大部分的计算芯片基于冯诺依曼结构，运行如基于交叉熵优化算法的传统算法，无法集成到通信单元上，导致计算所需的功耗和延迟很大，进而影响整体通信系统的性能。
常见的混合预编码主要分为数字预编码部分和模拟预编码部分。其中，对于混合预编码技术来说，模拟预编码矩阵的获取是最为关键的挑战之一。
在进行混合预编码时，利用发射端的信道状态信息，数字预编码部分和模拟预编码部分可以分别对经过射频链前后的信号进行转换和移相操作。其中，数字预编码部分由数字基带芯片完成，而模拟预编码部分则通过如现场可编程门阵列(Field-Programmable Gate Array，FPGA)的计算单元和移相器阵列组成。
例如，发射端的信道状态信息首先传送到计算单元FPGA中，然后由FPGA运行交叉熵等优化算法获得关键的模拟预编码矩阵；然后将获得模拟预编码矩阵同时传送到数字基带芯片和移相器阵列中；根据输入的模拟预编码矩阵，数字基带芯片运行迫零(zero-forcing，ZF)算法获得数字预编码矩阵，并依据这个矩阵对输入的调制信号进行转换操作，同时，模拟预编码矩阵映射到移相器阵列中，用于控制移相器阵列中每一个移相器所移相位的大小；移相器阵列对经过射频链之后的信号进行移相操作，完成整个混合预编码的过程；经过移向操作后的信号被传送到天线阵列，并发射给用户。
也就是说，在现有的混合预编码系统中，模拟预编码矩阵通常由FPGA计算获得，相应的，通过FPGA获得的模拟预编码矩阵等数据便需要在FPGA与通信单元之间搬迁。而在5G以及未来的6G通信系统中，随着天线数目的增加，混合预编码所需要的计算能力也需要不断提升，如上所述的基于外部计算单元(FPGA)的混合预编码过程中的数据搬迁问题，会导致延迟大、功耗大的缺陷，且由于在有限的面积和功耗限制下，无法将现有拥有足够算力的基于互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)的处理器集成到通信单元中。
为了解决上述问题，在本申请的实施例中，能够基于忆阻器阵列来实现将计算和存储融合的混合预编码处理。其中，基于忆阻器的存算单元可以被用来加速混合预编码中模拟预编码矩阵的计算过程，可以提供高能效算力，且基于忆阻器的存算单元、数字基带单元以及移相器阵列被集成到如基带芯片中，减少数据搬运延迟。可见，基于忆阻器的存算单元的混合预编码处理方案可以降低功耗，减小延迟，从而能够提升通信效率和通信性能。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
本申请一实施例提供了一种基带芯片，该基带芯片包括基于忆阻器的存算单元，数字基带单元以及移相器阵列。
需要说明的是，在本申请的实施例中，基于忆阻器的存算单元，可以配置为根据信道状态信息矩阵确定模拟预编码矩阵，然后将模拟预编码矩阵分别传输至数字基带单元和移相器阵列。
进一步地，在本申请的实施例中，基于忆阻器的存算单元可以包括忆阻器阵列，其中，忆阻器阵列 可以由多个忆阻器单元构成。例如，由p×q个忆阻器单元构成一个p行q列的忆阻器矩阵。其中，p和q均为大于或者等于1的整数。
也就是说，在本申请的实施例中，基于忆阻器的存算单元的计算能力，可以是利用排布的多个忆阻器单元且配置为能进行乘和运算忆阻器阵列实现的。
忆阻器是一种新型的电子器件，其中，忆阻器的电导值可由外部所加电压调控，正是基于这一特性，使得忆阻器可以用来代表神经网络中的权重值。因此，忆阻器阵列以及必要的外围电路可以被用来实现矩阵向量乘运算，加速神经网络算法。
忆阻器是一种非易失性存储器件，通过在忆阻器两端施加不同大小的电流可以改变其电导值，进而修改忆阻器中存储的数据；将忆阻器按一定方式排布成矩形阵列，并在行、列方向加以连接就构成了忆阻器存储阵列。目前，忆阻器存储器常用于矩阵-向量乘积运算，以神经网络的全连接层计算为例，其本质上是一次权重矩阵与输入向量进行矩阵乘法运算并得到输出向量的操作，将权重以忆阻器电导的形式写入到忆阻器存储阵列中，并将输入数据以电压的形式从行方向输入，在列方向即可以电流的形式得到输出向量。相较于CPU、GPU等传统计算机体系，忆阻器存储器将存储、计算两项功能相融合，减少了数据迁移，极大提高了数据吞吐量和计算并行度，降低了能耗，同时忆阻器作为一种新型非易失性器件，也使得忆阻器存储器的存储密度相较于传统存储器得到了较大提高。由于以上优秀特性，基于忆阻器存储器的新型计算芯片目前已经成为提升诸如神经网络计算等数据密集型算法的能量、时间效率的重要手段。
示例性的，在本申请的实施例中，多个忆阻器单元均为1T1R结构，即忆阻器阵列中的任意一个忆阻器单元的结构可以为1T1R，或者，多个忆阻器单元均为2T2R结构，即忆阻器阵列中的任意一个忆阻器单元的结构可以为2T2R。本申请对忆阻器单元的结构不作限制，也可以采用可以实现乘累加运算的其他结构形式的忆阻器单元。
可以理解的是，在本申请的实施例中，1T1R结构的忆阻器单元可以包括一个晶体管和一个忆阻器，2T2R结构的忆阻器单元可以包括两个晶体管和两个忆阻器。其中，2T2R是一种新型的无线技术，在传统的无线网络产品中，大多是1T1R，1T1R是一根天线负责接收和发射信号，它的信息负载量大，从而局域网传输速率出现瓶颈，只能提供11G的IEEE传输标准，局域网带宽为54M。而2T2R的采用双天线技术，两根天线分别负责接收和发送，广义上讲，可以理解成双通道传输，这样局域网的传输效率会提高50％甚至100％以上，从而达到11G IEEE，局域网速率可达150M-300M的传输速度。
示例性的，在本申请的实施例中，图1为忆阻器单元的示意图一，如图1所示，每个忆阻器单元包括一个晶体管和一个忆阻器。图2为忆阻器单元的示意图二，如图2所示，每个忆阻器单元包括两个晶体管和两个忆阻器。其中，WL表示字线，每一行的忆阻器单元中的晶体管的栅极和该行对应的字线连接；BL表示位线，每一列的忆阻器单元中的忆阻器和该列对应的位线连接；SL表示源线，每一行的忆阻器单元中的晶体管的源极和该行对应的源线连接。
可以理解的是，在本申请的实施例中，根据基尔霍夫定律，通过设置忆阻器单元的状态(例如阻值)，并且在字线与位线施加相应的字线信号与位线信号，由忆阻器单元构成的忆阻器阵列便可以并行地完成乘累加计算。
需要说明的是，在本申请的实施例中，基于忆阻器的存算单元中还可以包括多路选通器，采样保持单元，模数转换单元，移位累加单元等。
示例性的，在本申请的实施例中，图3为基于忆阻器的存算单元的示意图一，如图3所示，基于忆阻器的存算单元包括忆阻器阵列，多路选通器，采样保持单元，模数转换单元，移位累加单元等，忆阻器阵列中的每个忆阻器单元包括一个晶体管和一个忆阻器。其中，忆阻器单元可以为正导电器件或负导电器件，一个作为正导电器件的忆阻器单元和一个作为负导电器件的忆阻器单元可以代表一个权重值。
示例性的，在本申请的实施例中，图4为基于忆阻器的存算单元的示意图二，如图4所示，基于忆阻器的存算单元包括忆阻器阵列，多路选通器，采样保持单元，模数转换单元，移位累加单元等。其中，忆阻器阵列中的每个忆阻器单元包括两个晶体管和两个忆阻器。一个忆阻器单元可以代表一个权重值。
进一步地，在本申请的实施例中，基于忆阻器的存算单元，在进行模拟预编码矩阵的确定之前，还可以配置为对信道状态信息矩阵进行预处理。
也就是说，在本申请的实施例中，信道状态信息矩阵作为基于忆阻器的存算单元的输入需要进行预处理，其中，可以将信道状态信息矩阵由复数矩阵展开为实数矩阵，分别为实部矩阵和虚部矩阵，然后将两个矩阵拼接在一起，从而方便使用神经网络对复数矩阵进行计算，降低运算复杂度。
示例性的，在本申请的实施例中，图5为信道状态信息矩阵的预处理的示意图，如图5所示，在进行预处理之前，信道状态信息矩阵为m行n列的复数矩阵Cm×n，在对信道状态信息矩阵进行预处理时，可以将信道状态信息矩阵的实部和虚部分离为两个实数矩阵，即m行n列的实部矩阵R1 m×n和m行n列的虚部矩阵R2 m×n，接着，可以将这两个实数矩阵拼接在一起，从而获得2m行n列的实数矩阵。其中，m和n均为大于或者等于1的整数，k为信道状态信息矩阵的个数，k为正整数。
进一步地，在本申请的实施例中，基于忆阻器的存算单元在根据信道状态信息矩阵确定模拟预编码矩阵时，还配置为根据信道状态信息矩阵确定信道状态信息矩阵对应的注意力矩阵；然后确定注意力矩阵与信道状态信息矩阵的和值矩阵，再将和值矩阵输入至卷积层，最终便可以输出模拟预编码矩阵。
需要说明的是，在本申请的实施例中，对于输入的信道状态信息矩阵，基于忆阻器的存算单元可以先对信道状态信息矩阵进行线性变换，生成对应的注意力矩阵，然后再利用该注意力矩阵和卷积层进一步获取模拟预编码矩阵。
可以理解的是，在本申请的实施例中，基于忆阻器的存算单元的架构可以实现基于注意力机制的非监督学习神经网络算法，从而可以实现模拟预编码矩阵的生成。其中，图6为基于注意力机制的非监督神经网络的示意图一，如图6所示，基于注意力机制的非监督神经网络可以包括注意力机制层(线性变换操作等)和卷积层。基于忆阻器的存算单元中设置有忆阻器阵列，注意力机制层中的线性变换和卷积层中的权重值可以被映射为忆阻器阵列的电导值，从而可以通过忆阻器阵列实现低功耗，高能效的计算。
进一步地，在本申请的实施例中，基于忆阻器的存算单元在根据信道状态信息矩阵确定信道状态信息矩阵对应的注意力矩阵时，还配置为对信道状态信息矩阵进行并行线性处理，分别获得第一矩阵、第二矩阵以及第三矩阵；然后根据第一矩阵、第二矩阵以及第三矩阵生成注意力矩阵。
可以理解的是，在本申请的实施例中，基于忆阻器的存算单元可以使用不同的全连接层分别对输入的信道状态信息矩阵进行并行线性处理，从而获得不同的矩阵，即第一矩阵、第二矩阵以及第三矩阵， 进而可以利用这几个不同的矩阵确定注意力矩阵。
进一步地，在本申请的实施例中，基于忆阻器的存算单元在对信道状态信息矩阵进行并行线性处理，分别获得第一矩阵、第二矩阵以及第三矩阵时，还配置为根据第一全连接层、第二全连接层以及第三全连接层的权重值分别配置忆阻器阵列的电导值，以获得第一矩阵、第二矩阵以及第三矩阵。
进一步地，在本申请的实施例中，基于忆阻器的存算单元在根据第一矩阵、第二矩阵以及第三矩阵生成注意力矩阵时，还可以配置为将第一矩阵与第二矩阵的转置矩阵进行矩阵乘法运算，获得乘法结果矩阵；然后使用softmax激活函数处理乘法结果矩阵，获得处理后矩阵；接着将处理后矩阵与第三矩阵进行矩阵乘法运算，最终便可以获得注意力矩阵。
示例性的，在本申请的实施例中，基于忆阻器的存算单元根据第一矩阵Q、第二矩阵K以及第三矩阵V生成注意力矩阵P的方法可以如下公式所示：
可以理解的是，在本申请的实施例中，基于注意力机制的非监督学习神经网络算法可以通过基于忆阻器的存算单元来实现注意力矩阵的生成，其中，基于注意力机制的非监督神经网络算法可以包括注意力机制层。在注意力机制层中，信道状态信息矩阵首先并行经过三个不同的线性操作后得到三个矩阵，分别称之为Query(Q)矩阵(第一矩阵)，Key(K)矩阵(第二矩阵)，Value(V)矩阵(第三矩阵)，进而可以根据这三个矩阵计算出注意力矩阵。其中，具体的计算过程为Q矩阵与K矩阵的转置矩阵相乘后经过softmax激活函数，得到的结果与V矩阵相乘，生成注意力矩阵。
示例性的，图7为注意力机制层的示意图，如图7所示，基于注意力机制层，输入的信道状态信息矩阵经过三个全连接层(例如第一全连接层、第二全连接层以及第三全连接层)实现并行的线性处理，分别获得三个矩阵：Query(Q)矩阵，Key(K)矩阵，Value(V)矩阵。其中，三个全连接层所使用的权重值映射为忆阻器阵列的电导值，从而可以通过基于忆阻器的存算单元来完成线性处理。接着，三个矩阵经过softmax激活函数便可以计算获得对应的注意力矩阵。最后对注意力矩阵与信道状态信息矩阵进行累加和归一化处理，确定两者的和值矩阵。
进一步地，在本申请的实施例中，基于忆阻器的存算单元在获取模拟预编码矩阵时，还配置为根据卷积层的权重值配置忆阻器阵列的电导值，以获得模拟预编码矩阵。
可以理解的是，在本申请的实施例中，基于注意力机制的非监督学习神经网络算法可以通过基于忆阻器的存算单元来实现模拟预编码矩阵的生成，其中，基于注意力机制的非监督神经网络算法可以包括卷积层。在卷积层中，注意力矩阵与信道状态信息矩阵的和值矩阵被送入卷积层进行编码，进而获得模拟预编码矩阵。其中，卷积层所使用的权重值映射为忆阻器阵列的电导值，从而可以通过基于忆阻器的存算单元来完成编码处理。
示例性的，图8为卷积层的结构示意图，如图8所示，卷积层具体的层数和卷积核的大小可以根据具体的通信系统参数进行调整。
可以理解的是，在本申请的实施例中，线性变换和卷积层中的权重值是可以训练的。其中，权重值的训练过程可以由非监督的方式进行，即不需要提前准备带有标签的数据集。
示例性的，在本申请的实施例中，非监督的训练方式可以通过将神经网络的损失函数Loss(W,H)更改 为和速率函数R(Hi,FA,FD)的方式实现，如下公式：


其中，W代表线性变换或卷积层中的权重值，H0为实际测试或仿真产生的信道状态信息矩阵，k为信道状态信息矩阵的个数，为H0对应的数字预编码矩阵，为H0对应的模拟预编码矩阵，U代表用户的个数，σ2为噪声功率，为矩阵的共轭转置，γu为第u个用户的信号与干扰加噪声比(Signal to Interference plus Noise Ratio，SINR)，配置为表征第u个用户收到的有用信号的强度与接收到的干扰信号(噪声和干扰)的强度的比值。
进一步地，在本申请的实施例中，数字基带单元，配置为在获取到基于忆阻器的存算单元传输的模拟预编码矩阵之后，可以根据模拟预编码矩阵确定数字预编码矩阵，并基于数字预编码矩阵对待传输信号进行转换处理，从而获得转换后信号。
需要说明的是，在本申请的实施例中，在进行数字预编码矩阵的生成过程中，数字基带单元，还配置为根据模拟预编码矩阵和天线阵列对应的信道矩阵确定等效信道矩阵，然后再将等效信道矩阵传输至基于忆阻器的存算单元；相应的，基于忆阻器的存算单元，还配置为基于等效信道矩阵进行矩阵求逆处理，获得通道逆矩阵，然后再将通道逆矩阵传输至数字基带单元；接着，数字基带单元，还配置为根据通道逆矩阵确定数字预编码矩阵。
可以理解的是，在本申请的实施例中，基于忆阻器的存算单元中的忆阻器阵列，也可以被用来加速数字预编码计算过程中的矩阵求逆运算处理。
也就是说，在本申请的实施例中，虽然数字预编码矩阵是由数字基带单元生成的，然而为了提高预编码的效率，可以将计算复杂度最高的求逆操作部分通过忆阻器阵列来处理。因此，数字基带单元在根据模拟预编码矩阵和天线阵列对应的信道矩阵确定等效信道矩阵之后，便可以将等效信道矩阵传输至基于忆阻器的存算单元，以通过基于忆阻器的存算单元来进行矩阵求逆处理，获得通道逆矩阵。
需要说明的是，在本申请的实施例中，数字预编码矩阵是由数字基带单元根据基于忆阻器的存算单元传输的模拟预编码矩阵进行处理获得的。其中，数字基带单元可以采用多种算法，包括但不限于迫零算法，正规化迫零(Regularized Zero-Forcing，RZF)，截断多项式展开(truncated polynomial expansion，TPE)等方法。
示例性的，在本申请的实施例中，以迫零算法为例进行数字预编码矩阵的获取方法的说明，其中，可以将模拟预编码矩阵定义为FA，那么，经过数字预编码作用后的等效信道矩阵Heq可以表示为如下公式：
Heq＝HFA             (5)
其中，H为天线到用户间的信道矩阵。即对模拟预编码矩阵和天线阵列对应的信道矩阵进行矩阵乘法处理，便可以获得对应的等效信道矩阵。
接着，可以通过以下公式进行数字预编码矩阵FD的确定：
其中，ρ被用来限制发射信号的功率。可知的矩阵求逆操作是计算复杂度最高的部分，可以借助基于忆阻器的存算单元中的忆阻器阵列来进行矩阵求逆处理，获得通道逆矩阵也可以将通道逆矩阵定义为Hs -1，Hs表示为如下公式：
示例性的，在本申请的实施例中，图9为矩阵求逆处理的示意图一，如图9所示，可以利用忆阻器阵列进行矩阵求逆的操作。其中，忆阻器阵列的输入为电流，而读取的电压为所求的逆矩阵的其中一列。
示例性的，在本申请的实施例中，图10为矩阵求逆处理的示意图二，如图10所示，对于矩阵长宽为m的矩阵Hs来说，输入依次为单位坐标向量e1，e2，…，em，而对应的输出则依次为逆矩阵Hs -1的列向量。在经过m次计算之后，便可以获得Hx矩阵的逆矩阵Hs -1。
进一步地，在本申请的实施例中，数字基带单元在基于模拟预编码矩阵确定数字预编码矩阵之后，便可以利用数字预编码矩阵对待传输信号进行转换处理，从而可以获得待传输信号对应的转换后信号。
可以理解的是，在本申请的实施例中，基带芯片还可以包括射频链单元，其中，射频链单元可以包括功率放大器，滤波器等模块。相应的，数字基带单元，还配置为将转换后信号传输至射频链单元；射频链单元，配置为对转换后信号进行处理，获得处理后信号。进而可以将处理后信号传输至移相器阵列。
进一步地，在本申请的实施例中，移相器阵列，配置为在获取到基于忆阻器的存算单元传输的模拟预编码矩阵、射频链单元传输的转换后信号对应的处理后信号之后，可以配置为根据模拟预编码矩阵对处理后信号进行移相处理，获得移相后信号，从而可以通过天线阵列发送移相后信号。
需要说明的是，在本申请的实施例中，移相器阵列可以包括多个移相器。其中，移相器阵列，还配置为根据模拟预编码矩阵确定多个移相器中的每个移相器的相位。进而可以利用多个移相器完成对处理后信号的移相处理。
也就是说，在本申请的实施例中，基于数字基带单元，待传输信号在经过数字预编码转换之后所获得的转换后信号可以进一步传输至射频链单元进行处理，获得对应的处理后信号，然后处理后信号被传送到移相器阵列进行移相操作。其中，移相器阵列中的每个移相器的相位大小由模拟预编码矩阵映射而来。最后，经过移相操作后的移相后信号被传送到天线阵列，再由天线阵列转变成电磁波发送出去。
示例性的，在本申请的实施例中，图11为使用基于忆阻器的存算单元实现混合预编码的示意图，如图11所示，混合预编码主要包含数字预编码部分与模拟预编码部分。其中，在模拟预编码部分，信道状态信息矩阵被传送到基于忆阻器的存算单元中，基于忆阻器的存算单元通过运算神经网络算法，获得模拟预编码矩阵，然后可以将模拟预编码矩阵分别传送给数字基带单元和移相器阵列。在数字预编码部分，待传输信号可以通过数字基带单元进行基带处理，其中，基带处理包括数字预编码的处理。数字基带单元根据基于忆阻器的存算单元传输的模拟预编码矩阵，通过运行迫零算法等，计算获得数字预编码矩阵，然后便可以使用数字预编码矩阵对待传输信号进行转换处理，获得转换后信号。经过数字预编码转换后的转换后信号经过射频链单元(包含功率放大器，滤波器等模块)的处理后，获得对应的处理后信号，接着，处理后信号被传送到移相器阵列，进行移相处理，获得移相后信号。其中，在移相处理的过程中， 移相器阵列中的每个移相器的相位大小由模拟预编码矩阵映射而来。最后，经过移相操作后的移相后信号被传送到天线阵列，由天线阵列转变成电磁波发送出去。
综上所述，本申请实施例提出的一种基带芯片，可以利用基于忆阻器的存算单元来实现更加高效快速的混合预编码处理。其中，可以利用基于忆阻器的存算单元中的忆阻器阵列运行基于注意力机制的非监督神经网络算法，根据信道状态信息矩阵获得模拟预编码矩阵。由于基于忆阻器的存算单元、数字基带单元以及移相器阵列集成在同一通信模块中，进而在将模拟预编码矩阵传输至数字基带单元和移相器阵列时，能够减小数据搬运的延迟。同时，在进行数值预编码矩阵的生成时，还可以利用忆阻器阵列加速矩阵求逆的计算过程，进一步提升了混合预编码的编码效率。
可见，本申请实施例提出的集成有基于忆阻器的存算单元、数字基带单元以及移相器阵列的基带芯片，一方面，可以减少数据搬运的延迟和计算的带宽；另一方面，可以通过加速数字预编码计算过程中的矩阵求逆处理。进而能够在未来大规模MIMO通信系统中实现低延迟、低功耗的混合预编码。
本申请实施例提供了一种基带芯片，该基带芯片包括基于忆阻器的存算单元，数字基带单元以及移相器阵列，其中，基于忆阻器的存算单元，配置为根据信道状态信息矩阵确定模拟预编码矩阵，并将模拟预编码矩阵分别传输至数字基带单元和移相器阵列；数字基带单元，配置为根据模拟预编码矩阵确定数字预编码矩阵，并基于数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；移相器阵列，配置为获取转换后信号对应的处理后信号，并根据模拟预编码矩阵对处理后信号进行移相处理，获得移相后信号，以通过天线阵列发送移相后信号。也就是说，在本申请的实施例中，能够基于忆阻器阵列来实现将计算和存储融合的混合预编码处理。其中，基于忆阻器的存算单元可以被用来加速混合预编码中模拟预编码矩阵的计算过程，可以提供高能效算力，且基于忆阻器的存算单元、数字基带单元以及移相器阵列被集成到如基带芯片中，减少数据搬运延迟。可见，基于忆阻器的存算单元的混合预编码处理方案可以降低功耗，减小延迟，从而能够提升通信效率和通信性能。
基于上述实施例，在本申请的再一实施例中，图12为基带芯片的组成结构示意图一，如图12所示，基带芯片10可以包括基于忆阻器的存算单元11，数字基带单元12以及移相器阵列13。
基于忆阻器的存算单元11，配置为根据信道状态信息矩阵确定模拟预编码矩阵，并将模拟预编码矩阵分别传输至数字基带单元12和移相器阵列13；
数字基带单元12，配置为根据模拟预编码矩阵确定数字预编码矩阵，并基于数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；
移相器阵列13，配置为获取转换后信号对应的处理后信号，并根据模拟预编码矩阵对处理后信号进行移相处理，获得移相后信号，以通过天线阵列发送移相后信号。
进一步，在本申请的实施例中，图13为基带芯片的组成结构示意图二，如图13所示，基于忆阻器的存算单元11包括忆阻器阵列111，其中，忆阻器阵列111由多个忆阻器单元构成，多个忆阻器单元均为1T1R结构，或者，多个忆阻器单元均为2T2R结构。
也就是说，在本申请的实施例中，忆阻器阵列中的任意一个忆阻器单元的结构可以为1T1R，或者，忆阻器阵列中的任意一个忆阻器单元的结构可以为2T2R。本申请对忆阻器单元的结构不作限制，也可以采用可以实现乘累加运算的其他结构形式的忆阻器单元。
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为根据信道状态信息矩阵确定信道状态信息矩阵对应的注意力矩阵；确定注意力矩阵与信道状态信息矩阵的和值矩阵，将和值矩阵输入至卷积层，输出模拟预编码矩阵。
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为对信道状态信息矩阵进行并行线性处理，分别获得第一矩阵、第二矩阵以及第三矩阵；根据第一矩阵、第二矩阵以及第三矩阵生成注意力矩阵。
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为根据第一全连接层、第二全连接层以及第三全连接层的权重值分别配置忆阻器阵列的电导值，以获得第一矩阵、第二矩阵以及第三矩阵。
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为将第一矩阵与第二矩阵的转置矩阵进行矩阵乘法运算，获得乘法结果矩阵；使用softmax激活函数处理乘法结果矩阵，获得处理后矩阵；将处理后矩阵与第三矩阵进行矩阵乘法运算，获得注意力矩阵。
需要说明的是，在本申请的实施例中，对于输入的信道状态信息矩阵，基于忆阻器的存算单元可以先对信道状态信息矩阵进行线性变换，其中，基于忆阻器的存算单元可以使用不同的全连接层，即第一全连接层、第二全连接层、第三全连接层，分别对输入的信道状态信息矩阵进行并行线性处理，从而获得不同的矩阵，即第一矩阵、第二矩阵以及第三矩阵，进而可以利用这几个不同的矩阵确定注意力矩阵。在进行并行线性处理的过程中，可以根据第一全连接层、第一全连接层以及第三全连接层的权重值分别配置忆阻器阵列的电导值。接着，基于忆阻器的存算单元可以通过上述公式(1)，将第一矩阵与第二矩阵的转置矩阵进行矩阵乘法运算，获得乘法结果矩阵；然后使用softmax激活函数处理乘法结果矩阵，获得处理后矩阵；接着将处理后矩阵与第三矩阵进行矩阵乘法运算，最终便可以获得注意力矩阵。
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为根据卷积层的权重值配置忆阻器阵列的电导值，以获得模拟预编码矩阵。
可以理解的是，在本申请的实施例中，在卷积层中，注意力矩阵与信道状态信息矩阵的和值矩阵被送入卷积层进行编码，进而获得模拟预编码矩阵。其中，卷积层所使用的权重值映射为忆阻器阵列的电导值，从而可以通过基于忆阻器的存算单元来完成编码处理。
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为对信道状态信息矩阵进行预处理。
需要说明的是，在本申请的实施例中，信道状态信息矩阵作为基于忆阻器的存算单元的输入需要进行预处理，其中，可以将信道状态信息矩阵由复数矩阵展开为实数矩阵，分别为实部矩阵和虚部矩阵，然后将两个矩阵拼接在一起，从而方便使用神经网络对复数矩阵进行计算，降低运算复杂度。
进一步，在本申请的实施例中，数字基带单元12，还配置为根据模拟预编码矩阵和天线阵列对应的信道矩阵确定等效信道矩阵，并将等效信道矩阵传输至基于忆阻器的存算单元；
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为基于等效信道矩阵进行矩阵求逆处理，获得通道逆矩阵，并将通道逆矩阵传输至数字基带单元；
数字基带单元12，还配置为根据通道逆矩阵确定数字预编码矩阵。
可以理解的是，在本申请的实施例中，为了提高预编码的效率，可以将计算复杂度最高的求逆操作部分通过忆阻器阵列来处理。因此，数字基带单元在根据模拟预编码矩阵和天线阵列对应的信道矩阵确定等效信道矩阵之后，便可以将等效信道矩阵传输至基于忆阻器的存算单元，以通过基于忆阻器的存算单元来进行矩阵求逆处理，获得通道逆矩阵。进而数字基带单元可以进一步根据通道逆矩阵确定数字预编码矩阵。
需要说明的是，在本申请的实施例中，在数字预编码矩阵的生成过程中，数字基带单元可以采用多种算法，包括但不限于迫零算法，正规化迫零，截断多项式展开等方法。
进一步，在本申请的实施例中，基带芯片10还包括射频链单元14，
数字基带单元12，还配置为将转换后信号传输至射频链单元；
射频链单元14，配置为对转换后信号进行处理，获得处理后信号。
可以理解的是，在本申请的实施例中，基带芯片还可以包括射频链单元，其中，射频链单元可以包括功率放大器，滤波器等模块。相应的，射频链单元在对转换后信号进行处理，获得处理后信号之后，可以将处理后信号传输至移相器阵列。
进一步，在本申请的实施例中，移相器阵列13包括多个移相器131，
移相器阵列13，还配置为根据模拟预编码矩阵确定多个移相器131中的每个移相器的相位。
可以理解的是，在本申请的实施例中，移相器阵列中的每个移相器的相位大小由模拟预编码矩阵映射而来。最后，经过移相操作后的移相后信号被传送到天线阵列，再由天线阵列转变成电磁波发送出去。
也就是说，在本申请的实施例中，基于上述图11，混合预编码的处理过程主要包含数字预编码部分与模拟预编码部分。其中，数字预编码部分与模拟预编码部分所需的模拟预编码矩阵是由基于忆阻器的存算单元生成的。而数字预编码过程中的矩阵求逆操作也是由基于忆阻器的存算单元中的忆阻器阵列进行加速。
在模拟预编码部分，信道状态信息矩阵被传送到基于忆阻器的存算单元中，基于忆阻器的存算单元通过运算神经网络算法，获得模拟预编码矩阵，然后可以将模拟预编码矩阵分别传送给数字基带单元和移相器阵列。
可以理解的是，在本申请的实施例中，基于忆阻器的存算单元的架构可以实现基于注意力机制的非监督学习神经网络算法，从而可以实现模拟预编码矩阵的生成。其中，图14为基于注意力机制的非监督神经网络的示意图二，如图14所示，基于注意力机制的非监督神经网络可以包括注意力机制层(线性变换操作等)和卷积层。基于忆阻器的存算单元中设置有忆阻器阵列，注意力机制层中的线性变换和卷积层中的权重值可以被映射为忆阻器阵列的电导值，从而可以通过忆阻器阵列实现低功耗，高能效的计算。在注意力机制层中，输入的信道状态信息矩阵经过三个全连接层(例如第一全连接层、第二全连接层以及第三全连接层)实现并行的线性处理后得到三个矩阵，分别称之为Query(Q)矩阵(第一矩阵)，Key(K)矩阵(第二矩阵)，Value(V)矩阵(第三矩阵)，进而可以根据这三个矩阵计算出注意力矩阵。其中，具体的计算过程为Q矩阵与K矩阵的转置矩阵相乘后经过softmax激活函数，得到的结果与V矩阵相乘，生成注意力矩阵。最后对注意力矩阵与信道状态信息矩阵进行累加和归一化处理，确定两者的和值矩阵，再将和值矩阵输入至卷积层进行编码，进而获得模拟预编码矩阵。其中，卷积层所使用的权 重值映射为忆阻器阵列的电导值，从而可以通过基于忆阻器的存算单元来完成编码处理。
在数字预编码部分，待传输信号可以通过数字基带单元进行基带处理，其中，基带处理包括数字预编码的处理。数字基带单元根据基于忆阻器的存算单元传输的模拟预编码矩阵，通过运行迫零算法等，计算获得数字预编码矩阵，然后便可以使用数字预编码矩阵对待传输信号进行转换处理，获得转换后信号。经过数字预编码转换后的转换后信号经过射频链单元(包含功率放大器，滤波器等模块)的处理后，获得对应的处理后信号。
接着，处理后信号被传送到移相器阵列，进行移相处理，获得移相后信号。其中，在移相处理的过程中，移相器阵列中的每个移相器的相位大小由模拟预编码矩阵映射而来。最后，经过移相操作后的移相后信号被传送到天线阵列，由天线阵列转变成电磁波发送出去。
综上所述，本申请实施例提出的基带芯片，能够基于忆阻器阵列来实现将计算和存储融合的混合预编码处理，突破冯诺依曼架构的“存储墙”瓶颈，加速矩阵向量乘计算，基于忆阻器的存算单元可以被用来加速混合预编码中模拟预编码矩阵的计算过程；同时，基于忆阻器的存算单元具有面积小的特点，且能够提供高能效算力，因此可以被集成到通信单元(如基带芯片)中，减少通信单元和计算单元的数据搬运延迟。另外，忆阻器阵列可被用来加速计算矩阵的逆，进一步增大混合预编码过程中数字预编码部分的计算能效。因此，基于忆阻器的存算单元的混合预编码处理为未来通信系统提供了一种高能效，低延迟，面积小的混合预编码方案。
本申请实施例提供了一种基带芯片，该基带芯片包括基于忆阻器的存算单元，数字基带单元以及移相器阵列，其中，基于忆阻器的存算单元，配置为根据信道状态信息矩阵确定模拟预编码矩阵，并将模拟预编码矩阵分别传输至数字基带单元和移相器阵列；数字基带单元，配置为根据模拟预编码矩阵确定数字预编码矩阵，并基于数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；移相器阵列，配置为获取转换后信号对应的处理后信号，并根据模拟预编码矩阵对处理后信号进行移相处理，获得移相后信号，以通过天线阵列发送移相后信号。也就是说，在本申请的实施例中，能够基于忆阻器阵列来实现将计算和存储融合的混合预编码处理。其中，基于忆阻器的存算单元可以被用来加速混合预编码中模拟预编码矩阵的计算过程，可以提供高能效算力，且基于忆阻器的存算单元、数字基带单元以及移相器阵列被集成到如基带芯片中，减少数据搬运延迟。可见，基于忆阻器的存算单元的混合预编码处理方案可以降低功耗，减小延迟，从而能够提升通信效率和通信性能。
基于上述实施例，本申请一实施例提供了一种混合预编码方法，该混合预编码方法可以应用于终端设备中，其中，终端设备可以配置有基带芯片，基带芯片可以包括基于忆阻器的存算单元，数字基带单元以及移相器阵列。
图15为本申请实施例提出的混合预编码方法的实现流程示意图，如图15所示，终端设备进行混合预编码的方法可以包括以下步骤：
步骤101、基带芯片根据信道状态信息矩阵确定模拟预编码矩阵，根据模拟预编码矩阵确定数字预编码矩阵，并基于数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；获取转换后信号对应的处理后信号，并根据模拟预编码矩阵对处理后信号进行移相处理，获得移相后信号。
示例性的，基带芯片在执行步骤101时，可以包括：基于忆阻器的存算单元根据信道状态信息矩阵 确定模拟预编码矩阵，并将模拟预编码矩阵分别传输至数字基带单元和移相器阵列；数字基带单元根据模拟预编码矩阵确定数字预编码矩阵，并基于数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；移相器阵列获取转换后信号对应的处理后信号，并根据模拟预编码矩阵对处理后信号进行移相处理，获得移相后信号。
在本申请的实施例中，基于忆阻器的存算单元可以先根据信道状态信息矩阵确定模拟预编码矩阵，然后再将该模拟预编码矩阵分别传输至数字基带单元和移相器阵列。
进一步地，在本申请的实施例中，基于忆阻器的存算单元可以包括忆阻器阵列，其中，忆阻器阵列可以由多个忆阻器单元构成。例如，由p×q个忆阻器单元构成一个p行q列的忆阻器矩阵。其中，p和q均为大于或者等于1的整数。
也就是说，在本申请的实施例中，基于忆阻器的存算单元的计算能力，可以是利用排布的多个忆阻器单元且配置为能进行乘和运算忆阻器阵列实现的。
示例性的，在本申请的实施例中，多个忆阻器单元均为1T1R结构，即忆阻器阵列中的任意一个忆阻器单元的结构可以为1T1R，或者，多个忆阻器单元均为2T2R结构，即忆阻器阵列中的任意一个忆阻器单元的结构可以为2T2R。本申请对忆阻器单元的结构不作限制，也可以采用可以实现乘累加运算的其他结构形式的忆阻器单元。
可以理解的是，在本申请的实施例中，1T1R结构的忆阻器单元可以包括一个晶体管和一个忆阻器，2T2R结构的忆阻器单元可以包括两个晶体管和两个忆阻器。
可以理解的是，在本申请的实施例中，根据基尔霍夫定律，通过设置忆阻器单元的状态(例如阻值)，并且在字线与位线施加相应的字线信号与位线信号，由忆阻器单元构成的忆阻器阵列便可以并行地完成乘累加计算。
示例性的，在本申请的实施例中，如上述图3所示，基于忆阻器的存算单元包括忆阻器阵列，多路选通器，采样保持单元，模数转换单元，移位累加单元等，忆阻器阵列中的每个忆阻器单元包括一个晶体管和一个忆阻器。其中，忆阻器单元可以为正导电器件或负导电器件，一个作为正导电器件的忆阻器单元和一个作为负导电器件的忆阻器单元可以代表一个权重值。
示例性的，在本申请的实施例中，如上述图4所示，基于忆阻器的存算单元包括忆阻器阵列，多路选通器，采样保持单元，模数转换单元，移位累加单元等。其中，忆阻器阵列中的每个忆阻器单元包括两个晶体管和两个忆阻器。一个忆阻器单元可以代表一个权重值。
进一步地，在本申请的实施例中，在进行模拟预编码矩阵的确定之前，基于忆阻器的存算单元，还可以对信道状态信息矩阵进行预处理。
也就是说，在本申请的实施例中，信道状态信息矩阵作为基于忆阻器的存算单元的输入需要进行预处理，其中，可以将信道状态信息矩阵由复数矩阵展开为实数矩阵，分别为实部矩阵和虚部矩阵，然后将两个矩阵拼接在一起，从而方便使用神经网络对复数矩阵进行计算，降低运算复杂度。
进一步地，在本申请的实施例中，基于忆阻器的存算单元在根据信道状态信息矩阵确定模拟预编码矩阵时，还可以根据信道状态信息矩阵确定信道状态信息矩阵对应的注意力矩阵；然后确定注意力矩阵与信道状态信息矩阵的和值矩阵，再将和值矩阵输入至卷积层，最终便可以输出模拟预编码矩阵。
需要说明的是，在本申请的实施例中，对于输入的信道状态信息矩阵，基于忆阻器的存算单元可以先对信道状态信息矩阵进行线性变换，生成对应的注意力矩阵，然后再利用该注意力矩阵和卷积层进一步获取模拟预编码矩阵。
可以理解的是，在本申请的实施例中，基于忆阻器的存算单元的架构可以实现基于注意力机制的非监督学习神经网络算法，从而可以实现模拟预编码矩阵的生成。其中，基于注意力机制的非监督神经网络可以包括注意力机制层(线性变换操作等)和卷积层。基于忆阻器的存算单元中设置有忆阻器阵列，注意力机制层中的线性变换和卷积层中的权重值可以被映射为忆阻器阵列的电导值，从而可以通过忆阻器阵列实现低功耗，高能效的计算。
进一步地，在本申请的实施例中，基于忆阻器的存算单元在根据信道状态信息矩阵确定信道状态信息矩阵对应的注意力矩阵时，还可以对信道状态信息矩阵进行并行线性处理，分别获得第一矩阵、第二矩阵以及第三矩阵；然后根据第一矩阵、第二矩阵以及第三矩阵生成注意力矩阵。
可以理解的是，在本申请的实施例中，基于忆阻器的存算单元可以使用不同的全连接层分别对输入的信道状态信息矩阵进行并行线性处理，从而获得不同的矩阵，即第一矩阵、第二矩阵以及第三矩阵，进而可以利用这几个不同的矩阵确定注意力矩阵。
进一步地，在本申请的实施例中，基于忆阻器的存算单元在对信道状态信息矩阵进行并行线性处理，分别获得第一矩阵、第二矩阵以及第三矩阵时，还可以根据第一全连接层、第二全连接层以及第三全连接层的权重值分别配置忆阻器阵列的电导值，以获得第一矩阵、第二矩阵以及第三矩阵。
进一步地，在本申请的实施例中，基于忆阻器的存算单元在根据第一矩阵、第二矩阵以及第三矩阵生成注意力矩阵时，还可以将第一矩阵与第二矩阵的转置矩阵进行矩阵乘法运算，获得乘法结果矩阵；然后使用softmax激活函数处理乘法结果矩阵，获得处理后矩阵；接着将处理后矩阵与第三矩阵进行矩阵乘法运算，最终便可以获得注意力矩阵。
可以理解的是，在本申请的实施例中，基于注意力机制的非监督学习神经网络算法可以通过基于忆阻器的存算单元来实现注意力矩阵的生成，其中，基于注意力机制的非监督神经网络算法可以包括注意力机制层。在注意力机制层中，输入的信道状态信息矩阵经过三个全连接层(例如第一全连接层、第二全连接层以及第三全连接层)实现并行的线性处理后得到三个矩阵，分别称之为Query(Q)矩阵(第一矩阵)，Key(K)矩阵(第二矩阵)，Value(V)矩阵(第三矩阵)，进而可以根据这三个矩阵计算出注意力矩阵。其中，具体的计算过程为Q矩阵与K矩阵的转置矩阵相乘后经过softmax激活函数，得到的结果与V矩阵相乘，生成注意力矩阵。最后对注意力矩阵与信道状态信息矩阵进行累加和归一化处理，确定两者的和值矩阵。
进一步地，在本申请的实施例中，基于忆阻器的存算单元在获取模拟预编码矩阵时，还可以根据卷积层的权重值配置忆阻器阵列的电导值，以获得模拟预编码矩阵。
可以理解的是，在本申请的实施例中，基于注意力机制的非监督学习神经网络算法可以通过基于忆阻器的存算单元来实现模拟预编码矩阵的生成，其中，基于注意力机制的非监督神经网络算法可以包括卷积层。在卷积层中，注意力矩阵与信道状态信息矩阵的和值矩阵被送入卷积层进行编码，进而获得模拟预编码矩阵。其中，卷积层所使用的权重值映射为忆阻器阵列的电导值，从而可以通过基于忆阻器的 存算单元来完成编码处理。卷积层具体的层数和卷积核的大小可以根据具体的通信系统参数进行调整。
可以理解的是，在本申请的实施例中，线性变换和卷积层中的权重值是可以训练的。其中，权重值的训练过程可以由非监督的方式进行，即不需要提前准备带有标签的数据集。非监督的训练方式可以通过将神经网络的损失函数更改为和速率函数的方式实现。
在本申请的实施例中，数字基带单元在获取到基于忆阻器的存算单元传输的模拟预编码矩阵之后，可以根据模拟预编码矩阵确定数字预编码矩阵，然后基于数字预编码矩阵对待传输信号进行转换处理，从而获得转换后信号。
需要说明的是，在本申请的实施例中，在进行数字预编码矩阵的生成过程中，数字基带单元还可以根据模拟预编码矩阵和天线阵列对应的信道矩阵确定等效信道矩阵，然后再将等效信道矩阵传输至基于忆阻器的存算单元；相应的，基于忆阻器的存算单元还可以基于等效信道矩阵进行矩阵求逆处理，获得通道逆矩阵，然后再将通道逆矩阵传输至数字基带单元；接着，数字基带单元还可以根据通道逆矩阵确定数字预编码矩阵。
可以理解的是，在本申请的实施例中，基于忆阻器的存算单元中的忆阻器阵列，也可以被用来加速数字预编码计算过程中的矩阵求逆运算处理。
也就是说，在本申请的实施例中，虽然数字预编码矩阵是由数字基带单元生成的，然而为了提高预编码的效率，可以将计算复杂度最高的求逆操作部分通过忆阻器阵列来处理。因此，数字基带单元在根据模拟预编码矩阵和天线阵列对应的信道矩阵确定等效信道矩阵之后，便可以将等效信道矩阵传输至基于忆阻器的存算单元，以通过基于忆阻器的存算单元来进行矩阵求逆处理，获得通道逆矩阵。
需要说明的是，在本申请的实施例中，数字预编码矩阵是由数字基带单元根据基于忆阻器的存算单元传输的模拟预编码矩阵进行处理获得的。其中，数字基带单元可以采用多种算法，包括但不限于迫零算法，正规化迫零，截断多项式展开等方法。
进一步地，在本申请的实施例中，数字基带单元在基于模拟预编码矩阵确定数字预编码矩阵之后，便可以利用数字预编码矩阵对待传输信号进行转换处理，从而可以获得待传输信号对应的转换后信号。
可以理解的是，在本申请的实施例中，基带芯片还可以包括射频链单元，其中，射频链单元可以包括功率放大器，滤波器等模块。相应的，数字基带单元还可以将转换后信号传输至射频链单元；射频链单元则可以对转换后信号进行处理，获得处理后信号。进而可以将处理后信号传输至移相器阵列。
在本申请的实施例中，移相器阵列在获取到基于忆阻器的存算单元传输的模拟预编码矩阵、射频链单元传输的转换后信号对应的处理后信号之后，可以根据模拟预编码矩阵对处理后信号进行移相处理，获得移相后信号。
需要说明的是，在本申请的实施例中，移相器阵列可以包括多个移相器。其中，移相器阵列还可以根据模拟预编码矩阵确定多个移相器中的每个移相器的相位。进而可以利用多个移相器完成对处理后信号的移相处理。
也就是说，在本申请的实施例中，基于数字基带单元，待传输信号在经过数字预编码转换之后所获得的转换后信号可以进一步传输至射频链单元进行处理，获得对应的处理后信号，然后处理后信号被传送到移相器阵列进行移相操作。其中，移相器阵列中的每个移相器的相位大小由模拟预编码矩阵映射而 来。
步骤102、天线阵列发送移相后信号。
在本申请的实施例中，当经过移相操作后的移相后信号被传送到天线阵列之后，天线阵列便可以将移相后信号转变成电磁波发送出去，从而完成了待传输信号的发送。
综上所述，在本申请的实施例中，步骤101至步骤104所提出的混合预编码方法应用于集成有基于忆阻器的存算单元、数字基带单元以及移相器阵列的基带芯片的终端设备中，混合预编码过程分为数字预编码部分和模拟预编码部分。其中数字预编码部分由数字基带芯片完成，而模拟预编码部分由基于忆阻器的存算单元和移相器阵列完成。其中，基于忆阻器的存算单元通过运行基于注意力的神经网络和卷积神经网络来获得模拟预编码矩阵，并且通过非监督的方式获取神经网络的权值。由于基于忆阻器的存算单元、数字基带单元以及移相器阵列集成在同一通信模块中，进而在将模拟预编码矩阵传输至数字基带单元和移相器阵列时，能够减小数据搬运的延迟。同时，在进行数值预编码矩阵的生成时，还可以利用忆阻器阵列加速矩阵求逆的计算过程，进一步提升了混合预编码的编码效率。
可见，本申请实施例提出的混合预编码方法，能够减小通信单元和计算单元的数据搬运，具有延迟低，功耗低的特点，可以为未来通信系统提供新的混合预编码解决方案。
本申请实施例提供了一种混合预编码方法，混合预编码方法应配置为终端设备，该终端设备包括天线阵列和基带芯片，基带芯片包括基于忆阻器的存算单元，数字基带单元以及移相器阵列，其中，基于忆阻器的存算单元，配置为根据信道状态信息矩阵确定模拟预编码矩阵，并将模拟预编码矩阵分别传输至数字基带单元和移相器阵列；数字基带单元，配置为根据模拟预编码矩阵确定数字预编码矩阵，并基于数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；移相器阵列，配置为获取转换后信号对应的处理后信号，并根据模拟预编码矩阵对处理后信号进行移相处理，获得移相后信号，以通过天线阵列发送移相后信号。也就是说，在本申请的实施例中，能够基于忆阻器阵列来实现将计算和存储融合的混合预编码处理。其中，基于忆阻器的存算单元可以被用来加速混合预编码中模拟预编码矩阵的计算过程，可以提供高能效算力，且基于忆阻器的存算单元、数字基带单元以及移相器阵列被集成到如基带芯片中，减少数据搬运延迟。可见，基于忆阻器的存算单元的混合预编码处理方案可以降低功耗，减小延迟，从而能够提升通信效率和通信性能。
基于上述实施例，本申请的再一实施例提出一种终端设备，该终端设备可以包括天线阵列和基带芯片。其中，基带芯片，可以配置为对待传输信号进行混合预编码处理，获得移相后信号；相应的，天线阵列，可以配置为发送移相后信号。
图16为终端设备的组成结构示意图，如图16所示，终端设备20可以包括天线阵列21和基带芯片10。其中，基带芯片10可以包括基于忆阻器的存算单元11，数字基带单元12，移相器阵列13以及射频链单元14。
基于忆阻器的存算单元11，配置为根据信道状态信息矩阵确定模拟预编码矩阵，并将模拟预编码矩阵分别传输至数字基带单元12和移相器阵列13；
数字基带单元12，配置为根据模拟预编码矩阵确定数字预编码矩阵，并基于数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；
移相器阵列13，配置为获取转换后信号对应的处理后信号，并根据模拟预编码矩阵对处理后信号进行移相处理，获得移相后信号，以通过天线阵列发送移相后信号。
进一步，在本申请的实施例中，基于忆阻器的存算单元11包括忆阻器阵列111，其中，忆阻器阵列111由多个忆阻器单元构成，多个忆阻器单元均为1T1R结构，或者，多个忆阻器单元均为2T2R结构。
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为根据信道状态信息矩阵确定信道状态信息矩阵对应的注意力矩阵；确定注意力矩阵与信道状态信息矩阵的和值矩阵，将和值矩阵输入至卷积层，输出模拟预编码矩阵。
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为对信道状态信息矩阵进行并行线性处理，分别获得第一矩阵、第二矩阵以及第三矩阵；根据第一矩阵、第二矩阵以及第三矩阵生成注意力矩阵。
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为根据第一全连接层、第二全连接层以及第三全连接层的权重值分别配置忆阻器阵列的电导值，以获得第一矩阵、第二矩阵以及第三矩阵。
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为将第一矩阵与第二矩阵的转置矩阵进行矩阵乘法运算，获得乘法结果矩阵；使用softmax激活函数处理乘法结果矩阵，获得处理后矩阵；将处理后矩阵与第三矩阵进行矩阵乘法运算，获得注意力矩阵。
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为根据卷积层的权重值配置忆阻器阵列的电导值，以获得模拟预编码矩阵。
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为对信道状态信息矩阵进行预处理。
进一步，在本申请的实施例中，数字基带单元12，还配置为根据模拟预编码矩阵和天线阵列对应的信道矩阵确定等效信道矩阵，并将等效信道矩阵传输至基于忆阻器的存算单元；
进一步，在本申请的实施例中，基于忆阻器的存算单元11，还配置为基于等效信道矩阵进行矩阵求逆处理，获得通道逆矩阵，并将通道逆矩阵传输至数字基带单元；
数字基带单元12，还配置为根据通道逆矩阵确定数字预编码矩阵。
进一步，在本申请的实施例中，数字基带单元12，还配置为将转换后信号传输至射频链单元；
射频链单元14，配置为对转换后信号进行处理，获得处理后信号。
进一步，在本申请的实施例中，移相器阵列13包括多个移相器131，
移相器阵列13，还配置为根据模拟预编码矩阵确定多个移相器131中的每个移相器的相位。
本申请实施例提供了一种终端设备，该终端设备包括天线阵列和基带芯片，基带芯片包括基于忆阻器的存算单元，数字基带单元以及移相器阵列，其中，基于忆阻器的存算单元，配置为根据信道状态信息矩阵确定模拟预编码矩阵，并将模拟预编码矩阵分别传输至数字基带单元和移相器阵列；数字基带单元，配置为根据模拟预编码矩阵确定数字预编码矩阵，并基于数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；移相器阵列，配置为获取转换后信号对应的处理后信号，并根据模拟预编码矩阵对处理后信号进行移相处理，获得移相后信号，以通过天线阵列发送移相后信号。也就是说，在本申请 的实施例中，能够基于忆阻器阵列来实现将计算和存储融合的混合预编码处理。其中，基于忆阻器的存算单元可以被用来加速混合预编码中模拟预编码矩阵的计算过程，可以提供高能效算力，且基于忆阻器的存算单元、数字基带单元以及移相器阵列被集成到如基带芯片中，减少数据搬运延迟。可见，基于忆阻器的存算单元的混合预编码处理方案可以降低功耗，减小延迟，从而能够提升通信效率和通信性能。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的实现流程示意图和/或方框图来描述的。应理解可由计算机程序指令实现流程示意图和/或方框图中的每一流程和/或方框、以及实现流程示意图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在实现流程示意图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在实现流程示意图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在实现流程示意图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本申请的较佳实施例而已，并非用于限定本申请的保护范围。
工业实用性
本申请实施例中，能够基于忆阻器阵列来实现将计算和存储融合的混合预编码处理。其中，基于忆阻器的存算单元可以被用来加速混合预编码中模拟预编码矩阵的计算过程，可以提供高能效算力，且基于忆阻器的存算单元、数字基带单元以及移相器阵列被集成到如基带芯片中，减少数据搬运延迟。可见，基于忆阻器的存算单元的混合预编码处理方案可以降低功耗，减小延迟，从而能够提升通信效率和通信性能。

Claims (20)

  1. 一种基带芯片，所述基带芯片包括基于忆阻器的存算单元，数字基带单元以及移相器阵列，其中，
    所述基于忆阻器的存算单元，配置为根据信道状态信息矩阵确定模拟预编码矩阵，并将所述模拟预编码矩阵分别传输至所述数字基带单元和所述移相器阵列；
    所述数字基带单元，配置为根据所述模拟预编码矩阵确定数字预编码矩阵，并基于所述数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；
    所述移相器阵列，配置为获取所述转换后信号对应的处理后信号，并根据所述模拟预编码矩阵对所述处理后信号进行移相处理，获得移相后信号，以通过天线阵列发送所述移相后信号。
  2. 根据权利要求1所述的基带芯片，其中，所述基于忆阻器的存算单元包括忆阻器阵列，所述忆阻器阵列由多个忆阻器单元构成，所述多个忆阻器单元均为1T1R结构，或者，所述多个忆阻器单元均为2T2R结构。
  3. 根据权利要求2所述的基带芯片，其中，
    所述基于忆阻器的存算单元，还配置为根据所述信道状态信息矩阵确定所述信道状态信息矩阵对应的注意力矩阵；确定所述注意力矩阵与所述信道状态信息矩阵的和值矩阵，将所述和值矩阵输入至卷积层，输出所述模拟预编码矩阵。
  4. 根据权利要求3所述的基带芯片，其中，
    所述基于忆阻器的存算单元，还配置为对所述信道状态信息矩阵进行并行线性处理，分别获得第一矩阵、第二矩阵以及第三矩阵；根据所述第一矩阵、所述第二矩阵以及所述第三矩阵生成所述注意力矩阵。
  5. 根据权利要求4所述的基带芯片，其中，
    所述基于忆阻器的存算单元，还配置为根据第一全连接层、第二全连接层以及第三全连接层的权重值分别配置所述忆阻器阵列的电导值，以获得所述第一矩阵、所述第二矩阵以及所述第三矩阵。
  6. 根据权利要求4所述的基带芯片，其中，
    所述基于忆阻器的存算单元，还配置为将所述第一矩阵与所述第二矩阵的转置矩阵进行矩阵乘法运算，获得乘法结果矩阵；使用softmax激活函数处理所述乘法结果矩阵，获得处理后矩阵；将所述处理后矩阵与所述第三矩阵进行矩阵乘法运算，获得所述注意力矩阵。
  7. 根据权利要求3所述的基带芯片，其中，
    所述基于忆阻器的存算单元，还配置为根据所述卷积层的权重值配置所述忆阻器阵列的电导值，以获得所述模拟预编码矩阵。
  8. 根据权利要求1所述的基带芯片，其中，
    所述数字基带单元，还配置为根据所述模拟预编码矩阵和天线阵列对应的信道矩阵确定等效信道矩阵，并将所述等效信道矩阵传输至所述基于忆阻器的存算单元；
    所述基于忆阻器的存算单元，还配置为基于所述等效信道矩阵进行矩阵求逆处理，获得通道逆矩阵，并将所述通道逆矩阵传输至所述数字基带单元；
    所述数字基带单元，还配置为根据所述通道逆矩阵确定所述数字预编码矩阵。
  9. 根据权利要求1-8任一项所述的基带芯片，其中，所述基带芯片还包括射频链单元，
    所述数字基带单元，还配置为将所述转换后信号传输至所述射频链单元；
    所述射频链单元，配置为对所述转换后信号进行处理，获得所述处理后信号。
  10. 根据权利要求1-8任一项所述的基带芯片，其中，所述移相器阵列包括多个移相器，
    所述移相器阵列，还配置为根据所述模拟预编码矩阵确定所述多个移相器中的每个移相器的相位。
  11. 一种混合预编码方法，所述混合预编码方法应用于终端设备，所述终端设备配置如权利要求1-10任一项所述的基带芯片和天线阵列，所述方法包括：
    所述基带芯片根据信道状态信息矩阵确定模拟预编码矩阵，根据所述模拟预编码矩阵确定数字预编码矩阵，并基于所述数字预编码矩阵对待传输信号进行转换处理，获得转换后信号；获取所述转换后信号对应的处理后信号，并根据所述模拟预编码矩阵对所述处理后信号进行移相处理，获得移相后信号；
    所述天线阵列发送所述移相后信号。
  12. 根据权利要求11所述的方法，其中，所述方法还包括：
    所述基带芯片根据所述信道状态信息矩阵确定所述信道状态信息矩阵对应的注意力矩阵；确定所述注意力矩阵与所述信道状态信息矩阵的和值矩阵，将所述和值矩阵输入至卷积层，输出所述模拟预编码矩阵。
  13. 根据权利要求12所述的方法，其中，所述方法还包括：
    所述基带芯片对所述信道状态信息矩阵进行并行线性处理，分别获得第一矩阵、第二矩阵以及第三矩阵；根据所述第一矩阵、所述第二矩阵以及所述第三矩阵生成所述注意力矩阵。
  14. 根据权利要求13所述的方法，其中，所述方法还包括：
    所述基带芯片根据第一全连接层、第二全连接层以及第三全连接层的权重值分别配置忆阻器阵列的电导值，以获得所述第一矩阵、所述第二矩阵以及所述第三矩阵。
  15. 根据权利要求13所述的方法，其中，所述方法还包括：
    所述基带芯片将所述第一矩阵与所述第二矩阵的转置矩阵进行矩阵乘法运算，获得乘法结果矩阵；使用softmax激活函数处理所述乘法结果矩阵，获得处理后矩阵；将所述处理后矩阵与所述第三矩阵进行矩阵乘法运算，获得所述注意力矩阵。
  16. 根据权利要求14所述的方法，其中，所述方法还包括：
    所述基带芯片根据所述卷积层的权重值配置所述忆阻器阵列的电导值，以获得所述模拟预编码矩阵。
  17. 根据权利要求11所述的方法，其中，所述方法还包括：
    所述基带芯片根据所述模拟预编码矩阵和天线阵列对应的信道矩阵确定等效信道矩阵；基于所述等效信道矩阵进行矩阵求逆处理，获得通道逆矩阵；根据所述通道逆矩阵确定所述数字预编码矩阵。
  18. 根据权利要求11-17任一项所述的方法，其中，所述方法还包括：
    所述基带芯片对所述转换后信号进行处理，获得所述处理后信号。
  19. 根据权利要求11-17任一项所述的方法，其中，所述方法还包括：
    所述基带芯片根据所述模拟预编码矩阵确定多个移相器中的每个移相器的相位。
  20. 一种终端设备，所述终端设备包括天线阵列和如权利要求1至10任一项所述的基带芯片，其中，
    所述基带芯片，用于对待传输信号进行混合预编码处理，获得移相后信号；
    所述天线阵列，用于发送所述移相后信号。
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