WO2024045416A1 - 一种扩展图块边界的分块渲染模式图形处理方法及系统 - Google Patents

一种扩展图块边界的分块渲染模式图形处理方法及系统 Download PDF

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WO2024045416A1
WO2024045416A1 PCT/CN2022/139346 CN2022139346W WO2024045416A1 WO 2024045416 A1 WO2024045416 A1 WO 2024045416A1 CN 2022139346 W CN2022139346 W CN 2022139346W WO 2024045416 A1 WO2024045416 A1 WO 2024045416A1
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tile
extended
block
tiles
module
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PCT/CN2022/139346
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English (en)
French (fr)
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杨喜乐
敖海
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芯动微电子科技(珠海)有限公司
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Priority to US18/191,010 priority Critical patent/US20240078634A1/en
Publication of WO2024045416A1 publication Critical patent/WO2024045416A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T19/00—Manipulating 3D models or images for computer graphics
    • G06T19/20—Editing of 3D images, e.g. changing shapes or colours, aligning objects or positioning parts
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/00—2D [Two Dimensional] image generation
    • G06T11/001—Texturing; Colouring; Generation of texture or colour
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00—Geometric image transformations in the plane of the image
    • G06T3/06—Topological mapping of higher dimensional structures onto lower dimensional surfaces
    • G06T3/067—Reshaping or unfolding 3D tree structures onto 2D planes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/90—Determination of colour characteristics
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/20—Special algorithmic details
    • G06T2207/20021—Dividing image into blocks, subimages or windows

Definitions

  • the present disclosure belongs to the field of image processing technology, and more specifically, relates to a block rendering mode graphics processing method and system that extends tile boundaries.
  • Computer graphics processing systems are used to process graphics data (including primitive data and vertex data) for various computer graphics applications (such as computer games), and output rendered images generated through the rendering pipeline.
  • Three-dimensional models in graphics applications are established by segmenting objects in the scene using primitives (including but not limited to triangles, lines, and points). These primitives consist of vertices and their positions in three-dimensional space. Lighting effects and shading properties defined.
  • the geometric data of primitives and vertices in the three-dimensional model is sent to the computer graphics processing system as the input data stream of the geometry processing stage in the rendering process, and the input primitives are geometrically processed, including converting the primitives to screen space. , and delete primitives that are not visible in screen space.
  • the geometry data of primitives and vertices is sent to the fragment processing pipeline for rendering in a computer graphics processing system.
  • the computer graphics processing system generates an output image of the 3D model and displays it on a display unit (eg, a display screen).
  • Existing computer graphics processing systems include tile-based tile rendering modes.
  • the tile rendering mode the screen is divided into multiple rectangular tiles. After geometric processing, the primitives are classified into different tiles on the screen. Then, fragment processing is performed on each tile on the screen to generate renderings. image. Since the rendered image of the computer graphics processing system in the tiled rendering mode is generated separately in each tile, the filtering of pixels on the boundary of each tile will involve pixels in adjacent tiles, which results in Filtering of pixels cannot be completed during tile processing. Therefore, after the entire rendering is completed, additional pixel processing using surrounding pixel information needs to be performed. In other words, two stages are required to complete the filtering of pixels, and the processing performance needs to be improved.
  • the present disclosure provides a block rendering mode graphics processing method and system that extends the tile boundary, so that the pixel filtering process can be completed after each tile is rendered, effectively improving the pixel Filter processing efficiency.
  • a graphics processing system including a geometry processing system and a fragment processing system; the geometry processing system is used to perform geometric processing on graphics primitives and divide the visible graphics primitives into blocks. Multiple extended tiles M' in the screen visual space; the fragment processing system is used to render each extended tile M' to obtain rendering images of multiple extended tiles M', and according to each extended tile M'
  • the filter kernel is enabled in the rendered image for pixel filtering; among them, multiple extended tiles M' are obtained by dividing the screen visual space into multiple tiles M, and then respectively extending the boundaries of the multiple tiles M.
  • the block M is a rectangular block of N ⁇ N pixels. Each boundary of the block M is extended outward by k pixels to obtain an extended block M'.
  • the extended block M' is (N +2k) ⁇ (N+2k) pixel rectangular block; the filter kernel is (2k+1) ⁇ (2k+1) filter kernel.
  • the geometry processing system includes a geometry processing pipeline and a blocking module; the geometry processing pipeline is used to delete invisible primitives in the screen visual space and retain only visible primitives in the screen visual space; and the blocking module is used to Divide the visible primitives into the multiple extended tiles M' of the screen visual space, and generate a tiled display list for each extended tile M'; the fragment processing system is used to divide the tiles generated according to the tiles module Display the list, render each extended tile M', and obtain rendering images of multiple extended tiles M'.
  • the tiling module tiles the visible primitive into multiple extended tiles M' in the screen visual space by checking whether there is an overlapping area between the primitive and each extended tile M'.
  • the blocking module is used to partition all primitives that overlap with the extended tile M' into the extended tile M', and include them in the extended tile M'.
  • the blocking module is used to block the primitive into all extended blocks M' that overlap with the primitive, and include them in the extended diagram Block M' is displayed in the block list.
  • the geometry processing system also includes an input assembly module, which is used to construct primitives according to the input geometric data, and the geometry processing pipeline is used to process the primitives constructed by the input assembly module, and delete the elements in the screen visual space. Invisible primitives.
  • the geometry processing pipeline further includes a geometry conversion module, a clipping and culling module, and a data receiving module; the geometry conversion module is used to convert the vertex data of primitives into screen visual space; the clipping and culling module is used to delete screen vision For the invisible primitives in the space, only the visible primitives in the screen visual space are retained; the data receiving module is used to receive and store the primitive data and converted vertex data of the visible primitives in the screen visual space.
  • the fragment processing system includes a tile processing module, a rasterization module, a hidden surface removal module and a pixel shading module;
  • the tile processing module is used to obtain the tile display list generated by the tile module, and display the tiles
  • the primitives required to render the tiles in the list are sent to the rasterization module;
  • the rasterization module is used to obtain the primitive data and converted vertex data required to display the primitives referenced in the list in blocks, and rasterize the primitives into Visible pixels;
  • the hidden surface removal module is used to perform depth testing on the visible pixels output by the rasterization module, and remove pixels behind other primitives at the same pixel position;
  • the pixel shading module is used to remove the visible pixels output by the hidden surface removal module. Visible pixels are shaded.
  • the fragment processing system includes a post-processing module, which is configured to enable a filter kernel on the rendered image of the block M within the extended block M' according to the rendered image of each extended block M'. Pixel filtering is performed to obtain a filtered image of the block M within the extended block M'.
  • the pixel (x, y) in the block M undergoes a (2k+1) ⁇ (2k+1) filter kernel to obtain the filtered color
  • f(x+u,y+v) represents the original pixel color at pixel (x+u,y+v) in the (2k+1) ⁇ (2k+1) filter kernel
  • h(u,v) represents The weight factor of F(x+u,y+v).
  • the multiple tiles are multiple tiles M obtained by dividing the screen visual space.
  • a graphics processing system including a geometry processing system and a fragment processing system; the geometry processing system is used to perform geometric processing on graphics primitives and divide the visible graphics primitives into blocks in the screen visual space. Multiple extended tiles M'; the fragment processing system is used to render each extended tile M' to obtain rendering images of multiple extended tiles M'; where multiple extended tiles M' are passed through the screen visual space Divide to obtain multiple tiles M, and then extend the boundaries of the multiple tiles M respectively; the fragment processing system is also used to enable filtering of the extended tile after the rendering image of each extended tile M' is generated.
  • the patch M within M' undergoes pixel filtering.
  • the filter kernel is enabled to perform pixel filtering on the tile M within the extended tile M'; the pixels of the tile M within each extended tile M'
  • the filtering process has nothing to do with whether the rendering images of other extended tiles M' are generated.
  • a graphics processing method which is characterized in that it includes: after performing geometric processing on the graphics elements, dividing the visible graphics elements into multiple extended graphics blocks M' in the screen visual space; Each extended tile M' is rendered to obtain rendering images of multiple extended tiles M'; among them, multiple extended tiles M' are obtained by dividing the screen visual space into multiple tiles M, and then the multiple extended tiles M' are obtained respectively.
  • the boundaries of each tile M are expanded; the filter kernel is enabled for pixel filtering according to the rendered image of each extended tile M'.
  • the block M is a rectangular block of N ⁇ N pixels, and each boundary of the block M is extended outward by k pixels to obtain the extended block M'.
  • Block M' is a rectangular block of (N+2k) ⁇ (N+2k) pixels; the filter kernel is a (2k+1) ⁇ (2k+1) filter kernel.
  • geometric processing of primitives includes: deleting invisible primitives in the screen visual space and retaining only visible primitives in the screen visual space; and dividing the visible primitives into multiple blocks in the screen visual space.
  • the visible primitive is tiled into multiple extended tiles M' in the screen visual space by checking whether there is an overlapping area between the primitive and each extended tile M'.
  • the blocking module is used to block all primitives that overlap with the extended block M' into the extended block M', and include them in In the block display list of the extended block M'; for each block, the block module is used to block the block into all extended blocks M' that overlap with the block, and include In the tile display list of the extended tile M'.
  • the method further includes: constructing a primitive according to the input geometric data; performing geometric processing on the primitive further includes: converting the vertex data of the primitive into screen visual space.
  • rendering each extended tile M' according to the tiled display list includes: obtaining the primitive data and converted vertex data required for the primitives referenced in the tiled display list, and converting the primitives Rasterize into visible pixels; perform a depth test on the visible pixels output by the rasterization module, and remove pixels behind other primitives at the same pixel position; shade the remaining visible pixels after removing the pixels.
  • enabling the filter kernel to perform pixel filtering according to the rendered image of each extended tile M' includes: according to the rendered image of each extended tile M', Render the image and enable the filter kernel to perform pixel filtering to obtain the filtered image.
  • all pixels required for filtering the rendered image of each tile M are included in the extended tile M' in which the tile M is located.
  • the pixel (x, y) in the block M undergoes a (2k+1) ⁇ (2k+1) filter kernel to obtain the filtered color
  • f(x+u,y+v) represents the original pixel color at pixel (x+u,y+v) in the (2k+1) ⁇ (2k+1) filter kernel
  • h(u,v) represents The weight factor of F(x+u,y+v).
  • a graphics processing method which includes: after performing geometric processing on the graphic elements, dividing the visible graphic elements into multiple extended tiles M' in the screen visual space; The tile M' is rendered to obtain rendering images of multiple extended tiles M'; among them, the multiple extended tiles M' are obtained by dividing the screen visual space into multiple tiles M, and then the multiple tiles M are obtained by extending the boundary of each extended tile M'; after the rendering image of each extended tile M' is generated, the filter kernel is enabled to perform pixel filtering on the tile M within the extended tile M'.
  • the filter kernel is enabled to perform pixel filtering on the tile M within the extended tile M'; the pixels of the tile M within each extended tile M'
  • the filtering process has nothing to do with whether the rendering images of other extended tiles M' are generated.
  • an electronic device including the above graphics processing system; alternatively, the electronic device includes: a processor; a memory communicatively connected to the processor; the memory stores instructions that can be executed by the processor. Executed by the processor to enable the processor to execute the above method.
  • a computer-readable storage medium stores computer instructions. When the computer instructions are executed by a processor, the above method is implemented.
  • the above technical solution conceived through the present disclosure has the following beneficial effects: when applying a filter kernel to a rendering tile for pixel processing, each boundary of the rendering tile is expanded outward in pixels. , so that all pixels required for pixel processing are included in the expanded tiles. Therefore, the pixel filtering process can be completed after each tile is rendered, without the need to enable a separate stage after all tiles are rendered. processing, effectively improving the processing efficiency of pixel filtering.
  • Figure 1 is a schematic diagram of pixel filtering using a 3 ⁇ 3 pixel filter kernel
  • Figure 2 is a schematic diagram of extending the block boundary according to an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a block rendering mode graphics processing system according to an embodiment of the present disclosure
  • Figure 4 is a schematic flow chart of a graphics processing method in block rendering mode according to an embodiment of the present disclosure
  • FIG. 5 is a structural block diagram of an electronic device according to an embodiment of the present disclosure.
  • image processing techniques can be applied to rendered images, such as bloom, depth of field, and super-resolution amplification, to enhance the visual effects of the rendering.
  • This image processing algorithm typically involves sampling the pixel color in the area surrounding the pixel.
  • the filtered color G(x, y) obtained by passing the (2k+1) ⁇ (2k+1) filter kernel on pixel (x, y) can be:
  • f(x+u,y+v) represents the original pixel color at pixel (x+u,y+v) in the (2k+1) ⁇ (2k+1) filter kernel
  • h(u,v) represents The weight factor of F(x+u,y+v).
  • the filtering of pixels on the boundary of each tile will involve pixels in adjacent tiles, which results in Filtering of pixels cannot be completed during tile processing.
  • the filtering calculation of the original pixel color f(x, y) in the block M1 requires the original pixel colors f(x+1, y+1), f(x+1, y) in the adjacent block M2 ) and f (x+1, y-1) information, therefore, the filtering at the boundary pixel (x, y) of the block M1 cannot be completed during the processing of the block M1.
  • each boundary of the rendering tile is pixel-extended outward, so that all pixels required for pixel processing are included in the extension.
  • the pixel filtering process can be completed after each tile is rendered, without the need to enable a separate stage for processing after all tiles are rendered, which effectively improves the processing efficiency of pixel filtering.
  • k pixels are additionally extended outward on each boundary of the N ⁇ N pixel patch.
  • each boundary of the patch M of size N ⁇ N pixels extends outward by k pixels.
  • the original block M with a size of N ⁇ N pixels is expanded into an extended block M' with (N+2k) ⁇ (N+2k) pixels (that is, by the corner points C 0 ', C 1 ', C 2 ' and C 3 ' define the rectangular area formed).
  • the (2k+1) ⁇ (2k+1) filter kernel is enabled on the rendered output image for pixel processing.
  • the embodiment of the present disclosure uses the (2k+1) ⁇ (2k+1) filter kernel to perform pixel processing on the pixels in the N ⁇ N block, all the required pixels are included in the expanded (N+2k) ⁇ (N+ 2k) in the tile. Therefore, the pixel filtering process can be completed after each tile is rendered, without waiting for all tiles to be rendered before starting a separate stage for processing, which effectively improves the processing efficiency of pixel filtering.
  • the tiled rendering mode graphics processing system for extending tile boundaries includes a geometry processing system and a fragment processing system.
  • the geometry processing system is used to construct primitives according to input geometric data (such as vertex data). , after performing geometric processing on the primitives, divide the visible primitives into multiple tiles in the screen visual space, and generate a tile display list for each tile.
  • the geometry processing system further includes an input assembly module, a geometry processing pipeline, and a binning module.
  • the input assembly module is used to construct primitives based on input geometric data.
  • the geometry processing pipeline is used to process the constructed primitives, delete the primitives that are invisible in the screen visual space, and retain only the visible primitives in the screen visual space.
  • the blocking module is used to divide the visible primitives into multiple tiles in the screen visual space and generate a tile display list for each tile.
  • the tiled display list contains all primitives that at least partially overlap with the tile and need to be rendered in the tile; when a primitive is located in multiple tiles, the primitive will be included in Screen visual space The tile display list for each tile in which this primitive is located.
  • the screen visual space is divided into multiple tiles M, visible primitives are tiled into multiple tiles M in the screen visual space, and a tiled display list is generated for each tile M.
  • a tiled display list is generated for each tile M.
  • the graphic element T0 partially overlaps with the rectangular area, and the graphic element T1 is located within the rectangular area. Therefore, both the graphic element T0 and the graphic element T1 are included in the block display list of the tile M.
  • neither the graphic element T2 nor the graphic element T3 overlaps with the rectangular area. Therefore, neither the graphic element T2 nor the graphic element T3 is included in the block display list of the block M.
  • the screen visual space is divided into multiple tiles M (i.e., original tiles), the boundary of each tile M is expanded to obtain an extended tile M', and the visible primitives are divided into Multiple tiles M' in the screen visual space, and generate a tile display list for each tile M'.
  • the original block M with a size of N ⁇ N pixels is expanded into an extended block M' with (N+2k) ⁇ (N+2k) pixels, by checking whether the picture element is located at the corner point.
  • Blocking can be completed within the rectangular area defined by C 0 ', C 1 ', C 2 ' and C 3 ' or at least partially within this rectangular area.
  • primitives T0 and T2 partially overlap with the rectangular area, and primitive T1 is located in the rectangular area. Therefore, primitives T0, T1, and T2 are all included in the block display list of block M'. middle.
  • the graphic element T3 does not overlap with the rectangular area. Therefore, the graphic element T3 is not included in the block display list of the graphic block M'.
  • the geometry processing pipeline further includes a geometry conversion module, a clipping and culling module, and a data receiving module.
  • the geometry conversion module is used to convert the vertex data of primitives constructed by the input assembly module into screen visual space.
  • the cropping and culling module is used to delete invisible primitives in the screen visual space and retain only the visible primitives in the screen visual space. These primitives are the primitives required to render the scene.
  • the data receiving module is used to receive and store the primitive data and converted vertex data of primitives visible in the screen visual space.
  • the geometry processing system includes a geometry processing pipeline, and primitives constructed by the input assembly module are sent to the geometry processing pipeline for processing by the geometry processing pipeline.
  • the geometry processing system includes multiple geometry processing pipelines, and primitives constructed by the input assembly module are distributed to multiple downstream geometry processing pipelines, and are processed separately by the multiple geometry processing pipelines.
  • the primitive data and converted vertex data in the data receiving module are written into the first memory of the storage module, and the block display list generated by the blocking module is written into the second memory of the storage module.
  • the fragment processing system is used to render the tiles according to the tile display list generated by the geometry processing system to obtain a rendered image.
  • the fragment processing system includes a block processing module, a rasterization module, a hidden surface removal module, a pixel shading module and a post-processing module.
  • the tile processing module is configured to read the tile display list generated by the geometry processing system from the second memory, and send the primitives required for rendering tiles in the tile display list to the rasterization module.
  • the rasterization module is used to read the primitive data and converted vertex data required for the primitives referenced in the block display list from the first memory, and rasterize the primitives into visible pixels.
  • the primitives are rasterized into visible pixels within the tile M.
  • primitives are rasterized into visible pixels within tile M'.
  • the hidden surface removal module is used to perform a depth test on the visible pixels output by the rasterization module. Specifically, the depth value of the visible pixel output by the rasterization module is compared with the depth value of the previous primitive pixel stored in the depth buffer. When the primitive pixels output by the rasterization module are blocked by the previous primitive pixels, the depth test is considered to have failed, and the primitive pixels output by the rasterization module are removed. Otherwise, the primitive pixels output by the rasterization module are sent to the pixel shading module. . That is to say, the pixels behind other primitives at the same pixel position are removed through the hidden surface removal module.
  • the depth value of the previous primitive pixel is a preset value. In some implementations, the depth value of the previous primitive pixel is the depth value of the previous primitive pixel that passed the depth test.
  • the current depth value of each pixel is stored in the on-chip depth buffer.
  • the current depth value of each pixel in the tile M having N ⁇ N pixels is stored in an on-chip depth buffer, that is, an on-chip depth buffer for storing the current depth value.
  • the size of the depth buffer is N ⁇ N pixels.
  • the current depth value of each pixel in the tile M' having (N+2k) ⁇ (N+2k) pixels is stored in the on-chip depth buffer, That is, the size of the on-chip depth buffer used to store the current depth value is (N+2k) ⁇ (N+2k) pixels.
  • the pixel coloring module is used to color the visible pixels output by the hidden surface removal module to obtain the final color of the primitive pixels.
  • the color information of the pixels in the tile is stored in an on-chip color buffer in a computer graphics processing system in tiled rendering mode to avoid frequent data exchange with external memory, which affects processing efficiency.
  • the pixel shading module performs shading on the pixels in the original tile M.
  • the pixel shading module performs shading processing on pixels in the extended tile M', and at this time, additional pixel shading work is completed on additional pixels in the extended tile M'.
  • the filter kernel When the filter kernel is enabled for pixel processing on the rendered output image, since the pixel color in the extended tile M' is generated at the same time as the pixel color in the original tile M, the pixel color from the original tile M can be directly used after the pixel color is generated in the original tile M'. Instead of waiting for all tiles to generate pixel colors before processing boundary pixels in a separate stage, processing that originally required two steps can be completed in one step. Effectively improves the efficiency of pixel processing.
  • the pixel filtering operation on the pixel (x, y) on the edge of the block M1 requires the pixel (x+1, y) from the adjacent block M2 +1), (x+1, y) and (x+1, y-1) original color information. If the previous rendering process is limited to the original tiles, you need to separately filter the pixels near the tile boundaries (such as pixels (x, y), (x, y-1)) after all tiles are rendered. .
  • the pixels in the extended boundary area around the original tile can be processed simultaneously with other pixels in the original tile, that is, the filtering operation on pixels near the boundary of the original tile can be completed directly after the pixel color is generated in the extended tile. Due to the additional acquisition of information about the extended boundary pixels, a separate processing stage is no longer required when using filter kernels for pixel processing.
  • the efficiency of pixel processing is improved by using information from extended boundary pixels around the original tile.
  • the pixel processing workload will also increase accordingly at the expanded tile boundary.
  • the size of the tile after extending the boundary increases from N ⁇ N to (N+2k) ⁇ (N+2k) pixels.
  • the number of extra pixels in the extended boundary tile area i.e. extended tile M’ is:
  • the post-processing module is used to enable the filter kernel to perform pixel filtering on the rendered image of the original block M to obtain a filtered image.
  • the pixel (x, y) in the original block M undergoes a (2k+1) ⁇ (2k+1) filter kernel to obtain the filtered color
  • k is a positive integer
  • x and y respectively represent the abscissa and ordinate of the pixel in the pixel coordinate system
  • u and v respectively represent the offset relative to the abscissa x and ordinate y in the image coordinate system
  • u and v are both integers
  • f(x+u,y+v) represents the original pixel color at pixel (x+u,y+v) in the (2k+1) ⁇ (2k+1) filter kernel
  • h(u ,v) represents the weight factor of F(x+u,y+v).
  • extending the tile boundary can be enabled only in selected renderings, and for other unselected renderings, the default tile processing method is still used. That is to say, when no additional pixel filtering is required, the pixel filtering function of the post-processing module is not enabled, and pixel shading and its previous processes can be performed only on the original tiles without additional pixel shading workload; when required When performing additional pixel filtering processing, the pixel filtering function of the post-processing module is enabled, and the pixel shading and its previous processes are performed on the extended tile, which can significantly improve the processing efficiency of pixel filtering.
  • configuration settings may be used to determine whether pixel post-processing using surrounding pixel information should be applied to rendering. That is, extended tile boundaries may be applied to rendering according to configuration settings in embodiments of the present disclosure.
  • the tiled rendering mode graphics processing method for extending tile boundaries includes:
  • Step 401 Perform geometric processing on primitives.
  • performing geometric processing on primitives includes deleting invisible primitives in the screen visual space and retaining only visible primitives in the screen visual space.
  • performing geometric processing on the primitive further includes: converting the vertex data of the primitive into screen visual space.
  • Step 403 Divide the visible primitives into multiple tiles in the screen visual space.
  • the tile size is determined through configuration settings.
  • the multiple tiles are multiple tiles M; when the configuration is set to the second mode (that is, pixel filtering is enabled), the multiple tiles are The tiles are multiple extended tiles M'; wherein the multiple tiles M are obtained by dividing the screen visual space, and the multiple extended tiles M' are obtained by extending the boundaries of the multiple tiles M.
  • the visible primitives are divided into multiple tiles in the screen visual space by checking whether there is an overlapping area between the primitives and the tiles.
  • Step 405 Generate a tile display list for each tile.
  • the blocking module is used to divide all primitives that overlap with the tile into the tile, and include them in the tile display list of the tile. ;
  • the blocking module is used to segment the graphic element into all tiles that overlap with the graphic element, and include them in the tile display list of the tile. Therefore, when an element is in more than one tile, the element will be included in the tiled display list for that multiple tiles.
  • Step 407 Render each tile according to the tile display list to obtain a rendered image of the tile.
  • rendering each tile according to the tiled display list includes: obtaining the primitive data and converted vertex data required for the primitives referenced in the tiled display list, rasterizing the primitives into visible pixels; perform a depth test on the visible pixels output by the rasterization module, and remove pixels behind other primitives at the same pixel position; the remaining visible pixels after removing the pixels are shaded.
  • removing pixels that are behind other primitives at the same pixel location includes comparing the depth value of the rasterized primitive pixel to the depth value of the previous primitive pixel stored in the depth buffer, at When a rasterized primitive pixel is obscured by a previous primitive pixel, the depth test is considered to have failed and the rasterized primitive pixel is removed.
  • the depth value of the previous primitive pixel is a preset value. In some implementations, the depth value of the previous primitive pixel is the depth value of the previous primitive pixel that passed the depth test.
  • Step 409 Enable the filter kernel to perform pixel filtering according to the rendered image of the tile.
  • this step 409 is performed when the configuration is set to the second mode.
  • enabling the filter kernel to perform pixel filtering based on the rendered image of the tile includes: based on the rendered image of the extended tile M', enabling the filter kernel to perform pixel filtering on the rendered image of the tile M to obtain a filtered image.
  • all pixels required for filtering the rendered image of tile M are included in the extended tile M'.
  • the block M is a rectangular block of N ⁇ N pixels. Each boundary of the block M is extended outward by k pixels to obtain an extended block M'.
  • the extended block M' is (N +2k) ⁇ (N+2k) pixel rectangular block; the filter kernel is (2k+1) ⁇ (2k+1) filter kernel.
  • the pixel (x, y) in the block M undergoes a (2k+1) ⁇ (2k+1) filter kernel to obtain the filtered color
  • k is a positive integer
  • x and y are respectively the abscissa and ordinate of the pixel in the pixel coordinate system
  • u and v are the offsets relative to the abscissa x and ordinate y in the image coordinate system
  • u and v are both integers
  • f(x+u,y+v) represents the original pixel color at pixel (x+u,y+v) in the (2k+1) ⁇ (2k+1) filter kernel
  • h(u ,v) represents the weight factor of F(x+u,y+v).
  • the k value is set appropriately by taking into account the processing efficiency of pixel filtering and the workload of additional pixel shading in rendering.
  • the above graphics processing method further includes: constructing primitives according to the input geometric data.
  • FIG. 5 is a structural block diagram of an electronic device according to an embodiment of the present disclosure.
  • An embodiment of the present disclosure also provides an electronic device.
  • the electronic device includes: at least one processor 501 and a memory 503 communicatively connected to the at least one processor 501 .
  • the memory 503 stores instructions that can be executed by at least one processor 501 .
  • the instructions are executed by at least one processor 501.
  • the processor 501 executes this instruction, it implements the graphics processing method in the above embodiment.
  • the number of memory 503 and processor 501 may be one or more.
  • This electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers.
  • Electronic devices may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices.
  • mobile devices such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices.
  • the components shown herein, their connections and relationships, and their functions are examples only and are not intended to limit implementations of the disclosure described and/or claimed herein.
  • the electronic device may also include a communication interface 505 for communicating with external devices for interactive data transmission.
  • the individual devices are connected to each other using different buses and can be installed on a common motherboard or otherwise installed as needed.
  • the processor 501 may process instructions for execution within the electronic device, including storage in or on memory to display a graphical user interface (Graphical User Interface) on an external input/output device, such as a display device coupled to the interface. GUI) graphics information instructions.
  • graphical user interface Graphic User Interface
  • GUI graphical user interface
  • multiple processors and/or multiple buses may be used with multiple memories and multiple memories, if desired.
  • multiple electronic devices can be connected, each device providing part of the necessary operation (eg, as a server array, a set of blade servers, or a multi-processor system).
  • the bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, only one thick line is used in Figure 5, but it does not mean that there is only one bus or one type of bus.
  • the memory 503, the processor 501 and the communication interface 505 are integrated on one chip, the memory 503, the processor 501 and the communication interface 505 can communicate with each other through the internal interface.
  • processor can be a central processing unit (Central Processing Unit, CPU), or other general-purpose processor, digital signal processor (Digital Signal Processing, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), Field Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • CPU Central Processing Unit
  • DSP Digital Signal Processing
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • a general-purpose processor can be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor that supports Advanced RISC Machines (ARM) architecture.
  • ARM Advanced RISC Machines
  • Embodiments of the present disclosure provide a computer-readable storage medium (such as the above-mentioned memory 503), which stores computer instructions. When the program is executed by a processor, the method provided in the embodiment of the present disclosure is implemented.
  • the memory 503 may include a storage program area and a storage data area, wherein the storage program area may store an operating system and an application program required for at least one function; the storage data area may store data required for use of the electronic device according to the graphics processing method. Created data, etc.
  • the memory 503 may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device.
  • the memory 503 optionally includes memory located remotely relative to the processor 501, and these remote memories may be connected to electronic devices of the graphics processing method through a network. Examples of the above-mentioned networks include but are not limited to the Internet, intranets, local area networks, mobile communication networks and combinations thereof.
  • references to the terms “one embodiment,” “some embodiments,” “an example,” “specific examples,” or “some examples” or the like means that specific features are described in connection with the embodiment or example.
  • structures, materials, or features are included in at least one embodiment or example of the present disclosure.
  • the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
  • those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, features defined as “first” and “second” may explicitly or implicitly include at least one of these features.
  • “plurality” means two or more than two, unless otherwise expressly and specifically limited.
  • Any process or method description in a flowchart or otherwise described herein may be understood to represent a representation that includes one or more (two or more) executable instructions for implementing the specified logical functions or steps of the process.
  • a module, fragment, or portion of code may be understood to represent a representation that includes one or more (two or more) executable instructions for implementing the specified logical functions or steps of the process.
  • a module, fragment, or portion of code may be understood to represent a representation that includes one or more (two or more) executable instructions for implementing the specified logical functions or steps of the process.
  • a module, fragment, or portion of code A module, fragment, or portion of code.
  • the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may be performed out of the order shown or discussed, including in a substantially concurrent manner or in the reverse order, depending on the functionality involved.
  • logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered a sequenced list of executable instructions for implementing the logical functions, and may be embodied in any computer-readable medium, For use by, or in combination with, instruction execution systems, devices or devices (such as computer-based systems, systems including processors or other systems that can fetch instructions from and execute instructions from the instruction execution system, device or device) or equipment.
  • various parts of the present disclosure may be implemented in hardware, software, firmware, or combinations thereof.
  • various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the method in the above embodiment can be completed by instructing relevant hardware through a program.
  • the program can be stored in a computer-readable storage medium. When executed, the program includes one of the steps of the method embodiment or other steps. combination.
  • each functional unit in various embodiments of the present disclosure may be integrated into one processing module, each unit may exist physically alone, or two or more units may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or software function modules. If the above integrated modules are implemented in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium.
  • the storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

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Abstract

本公开公开了一种扩展图块边界的分块渲染模式图形处理方法及系统。该系统包括几何处理系统和片段处理系统；几何处理系统用于对图元进行几何处理后，将可见的图元分块到屏幕视觉空间的多个扩展图块M'；片段处理系统用于对每个扩展图块M'进行渲染，得到多个扩展图块M'的渲染图像，以及根据每个扩展图块M'的渲染图像启用滤波核进行像素滤波；其中，多个扩展图块M'通过将屏幕视觉空间进行划分得到多个图块M，再分别将多个图块M的边界进行扩展得到。本公开使得像素滤波过程可以在每个图块渲染后完成，有效提升了像素滤波的处理效率。

Description

一种扩展图块边界的分块渲染模式图形处理方法及系统 技术领域
本公开属于图像处理技术领域，更具体地，涉及一种扩展图块边界的分块渲染模式图形处理方法及系统。
背景技术
计算机图形处理系统用于处理各种计算机图形应用(例如计算机游戏)的图形数据(包括图元数据和顶点数据)，输出通过渲染管道产生的渲染图像。
图形应用程序中的三维模型是使用图元(primitives)(例如包括但不限于三角形、线、点)对场景中物体的剖分建立的，这些图元由顶点为其在三维空间中的位置以及光线效果和着色特性定义。三维模型中图元和顶点的几何数据作为渲染过程中几何处理阶段(geometry processing)的输入数据流，被发送到计算机图形处理系统，对输入图元做几何处理，包括将图元转换到屏幕空间，并删除屏幕空间中不可见的图元。经过几何处理后，图元和顶点的几何数据被发送到片段处理管道(fragment processing pipeline)，以便在计算机图形处理系统中进行渲染。作为渲染处理的结果，计算机图形处理系统生成3D模型的输出图像，并在显示单元(例如显示屏幕)上进行显示。
现有的计算机图形处理系统包括基于图块(tile-based)的分块渲染模式。在分块渲染模式下，屏幕被划分为多个矩形图块，图元经过几何处理后在屏幕上被分类至不同图块，然后在屏幕上的每个图块中分别进行片段处理，生成渲染图像。由于分块渲染模式的计算机图形处理系统的渲染图像是在每个图块中单独生成的，而每个图块边界上像素的滤波将涉及相邻图块中的像素，这导致图块边界上像素的滤波在图块处理过程中无法完成。因此，需要在整个渲染完成后，另外进行使用周围像素信息的像素处理，也就是说，需要两个阶段来完成对像素的滤波，处理性能有待提升。
发明内容
针对现有技术的以上缺陷或改进需求，本公开提供了一种扩展图块边界的分块渲染模式图形处理方法及系统，使得像素滤波过程可以在每个图块渲染后完成，有效提升了像素滤波的处理效率。
为实现上述目的，按照本公开的一个方面，提供了一种图形处理系统，包括几何处理系统和片段处理系统；几何处理系统用于对图元进行几何处理后，将可见的图元分块到屏幕视觉空间的多个扩展图块M’；片段处理系统用于对每个扩展图块M’进行渲染，得到多个扩展图块M’的渲染图像，以及根据每个扩展图块M’的渲染图像启用滤波核进行像素滤波；其中，多个扩展图块M’通过将屏幕视觉空间进行划分得到多个图块M，再分别将多个图块M的边界进行扩展得到。
在一些实施方式中，图块M为N×N像素的矩形图块，将图块M的每条边界均向外扩展k个像素，得到扩展图块M’，扩展图块M’为(N+2k)×(N+2k)像素的矩形图块；滤波核为(2k+1)×(2k+1)滤波核。
在一些实施方式中，几何处理系统包括几何处理管道和分块模块；几何处理管道用于删除屏幕视觉空间中不可见的图元，仅保留屏幕视觉空间中可见的图元；分块模块用于将可见的图元分块到屏幕视觉空间的所述多个扩展图块M’，并为每个扩展图块M’生成分块显示列表；片段处理系统用于根据分块模块生成的分块显示列表，对每个扩展图块M’进行渲染，得到多个扩展图块M’的渲染图像。
在一些实施方式中，分块模块通过检查图元与每个扩展图块M’是否存在重叠区域，将可见的图元分块到屏幕视觉空间的多个扩展图块M’。
在一些实施方式中，对每个扩展图块M’，分块模块用于将所有与该扩展图块M’存在重叠区域的图元分块到该扩展图块M’，并包含在该扩展图块M’的分块显示列表中；对每个图元，分块模块用于将该图元分块到所有与该图元存在重叠区域的扩展图块M’，并包含在该扩展图块M’的分块显示列表中。
在一些实施方式中，几何处理系统还包括输入汇编模块，输入汇编模块用于根据输入的几何数据构造图元，几何处理管道用于对输入汇编模块构造的图元 进行处理，删除屏幕视觉空间中不可见的图元。
在一些实施方式中，几何处理管道进一步包括几何转换模块、裁剪和剔除模块以及数据接收模块；几何转换模块用于将图元的顶点数据转换到屏幕视觉空间；裁剪和剔除模块用于删除屏幕视觉空间中不可见的图元，仅保留屏幕视觉空间中可见的图元；数据接收模块用于接收和存储屏幕视觉空间中可见的图元的图元数据和转换后的顶点数据。
在一些实施方式中，片段处理系统包括分块处理模块、光栅化模块、隐藏面移除模块和像素着色模块；分块处理模块用于获取分块模块生成的分块显示列表，将分块显示列表中渲染图块所需的图元发送到光栅化模块；光栅化模块用于获取分块显示列表中引用的图元所需的图元数据和转换后的顶点数据，将图元光栅化为可见像素；隐藏面移除模块用于对光栅化模块输出的可见像素进行深度测试，将同一像素位置上位于其他图元后面的像素移除；像素着色模块用于将隐藏面移除模块输出的可见像素进行着色处理。
在一些实施方式中，片段处理系统包括后处理模块，后处理模块用于根据每个扩展图块M’的渲染图像，对该扩展图块M’内的图块M的渲染图像启用滤波核进行像素滤波处理，得到该扩展图块M’内的图块M的滤波后的图像。
在一些实施方式中，图块M中的像素(x，y)经过(2k+1)×(2k+1)滤波核得到滤波后的颜色
Figure PCTCN2022139346-appb-000001
其中，f(x+u,y+v)表示(2k+1)×(2k+1)滤波核中像素(x+u,y+v)处的原始像素颜色，h(u,v)表示F(x+u,y+v)的权重因子。
在一些实施方式中，在后处理模块被配置为不启用像素滤波处理时，多个图块为将屏幕视觉空间进行划分得到的多个图块M。
根据本公开的另一方面，提供了一种图形处理系统，包括几何处理系统和片段处理系统；几何处理系统用于对图元进行几何处理后，将可见的图元分块到屏幕视觉空间的多个扩展图块M’；片段处理系统用于对每个扩展图块M’进行渲染，得到多个扩展图块M’的渲染图像；其中，多个扩展图块M’通过将屏幕视觉空间进行划分得到多个图块M，再分别将多个图块M的边界进行扩展得到；片 段处理系统还用于在每个扩展图块M’的渲染图像生成后，启用滤波核对该扩展图块M’内的图块M进行像素滤波。
在一些实施方式中，根据每个扩展图块M’的渲染图像，启用滤波核对该扩展图块M’内的图块M进行像素滤波；每个扩展图块M’内的图块M的像素滤波过程与其它扩展图块M’的渲染图像是否生成无关。
根据本公开的又一方面，提供了一种图形处理方法，其特征在于，包括：对图元进行几何处理后，将可见的图元分块到屏幕视觉空间的多个扩展图块M’；对每个扩展图块M’进行渲染，得到多个扩展图块M’的渲染图像；其中，多个扩展图块M’通过将屏幕视觉空间进行划分得到多个图块M，再分别将多个图块M的边界进行扩展得到；根据每个扩展图块M’的渲染图像启用滤波核进行像素滤波。
在一些实施方式中，图块M为N×N像素的矩形图块，将所述图块M的每条边界均向外扩展k个像素，得到所述扩展图块M’，所述扩展图块M’为(N+2k)×(N+2k)像素的矩形图块；所述滤波核为(2k+1)×(2k+1)滤波核。
在一些实施方式中，对图元进行几何处理包括：删除屏幕视觉空间中不可见的图元，仅保留屏幕视觉空间中可见的图元；在将可见的图元分块到屏幕视觉空间的多个扩展图块M’后，为每个扩展图块M’生成分块显示列表；根据分块显示列表，对每个扩展图块M’进行渲染。
在一些实施方式中，通过检查图元与每个扩展图块M’是否存在重叠区域，将可见的图元分块到屏幕视觉空间的多个扩展图块M’。
在一些实施方式中，对每个扩展图块M’，所述分块模块用于将所有与该扩展图块M’存在重叠区域的图元分块到该扩展图块M’，并包含在该扩展图块M’的分块显示列表中；对每个图元，所述分块模块用于将该图元分块到所有与该图元存在重叠区域的扩展图块M’，并包含在该扩展图块M’的分块显示列表中。
在一些实施方式中，该方法还包括：根据输入的几何数据构造图元；对图元进行几何处理还包括：将图元的顶点数据转换到屏幕视觉空间。
在一些实施方式中，根据分块显示列表，对每个扩展图块M’进行渲染包括： 获取分块显示列表中引用的图元所需的图元数据和转换后的顶点数据，将图元光栅化为可见像素；对光栅化模块输出的可见像素进行深度测试，将同一像素位置上位于其他图元后面的像素移除；将像素移除后剩余的可见像素进行着色处理。
在一些实施方式中，根据每个扩展图块M’的渲染图像启用滤波核进行像素滤波包括：根据每个扩展图块M’的渲染图像，对该扩展图块M’内的图块M的渲染图像启用滤波核进行像素滤波处理，得到滤波后的图像。
在一些实施方式中，对每个图块M的渲染图像进行滤波处理所需的所有像素都包含在该图块M所在的扩展图块M’中。
在一些实施方式中，图块M中的像素(x，y)经过(2k+1)×(2k+1)滤波核得到滤波后的颜色
Figure PCTCN2022139346-appb-000002
其中，f(x+u,y+v)表示(2k+1)×(2k+1)滤波核中像素(x+u,y+v)处的原始像素颜色，h(u,v)表示F(x+u,y+v)的权重因子。
按照本公开的又一方面，提供了一种图形处理方法，包括：对图元进行几何处理后，将可见的图元分块到屏幕视觉空间的多个扩展图块M’；对每个扩展图块M’进行渲染，得到多个扩展图块M’的渲染图像；其中，多个扩展图块M’通过将屏幕视觉空间进行划分得到多个图块M，再分别将多个图块M的边界进行扩展得到；在每个扩展图块M’的渲染图像生成后，启用滤波核对该扩展图块M’内的图块M进行像素滤波。
在一些实施方式中，根据每个扩展图块M’的渲染图像，启用滤波核对该扩展图块M’内的图块M进行像素滤波；每个扩展图块M’内的图块M的像素滤波过程与其它扩展图块M’的渲染图像是否生成无关。
按照本公开的又一方面，提供了一种电子设备，包括上述图形处理系统；或者，电子设备包括：处理器；与处理器通信连接的存储器；存储器存储有可被处理器执行的指令，指令被处理器执行，以使处理器能够执行上述方法。
按照本公开的又一方面，提供了一种计算机可读存储介质，计算机可读存储介质存储有计算机指令，计算机指令被处理器执行时实现上述方法。
总体而言，通过本公开所构思的以上技术方案与现有技术相比，具有以下有益效果：对渲染图块应用滤波核进行像素处理时，将渲染图块的每条边界向外进行像素扩展，使得像素处理所需的所有像素都包含在扩展后的图块中，因此，像素滤波过程可以在每个图块渲染后完成，而不需要在所有图块渲染完成后再启用单独的阶段进行处理，有效提升了像素滤波的处理效率。
附图说明
图1是3×3的像素滤波核进行像素滤波的示意图；
图2是本公开实施例的对图块边界进行扩展的示意图；
图3是本公开实施例的分块渲染模式图形处理系统的结构示意图；
图4是本公开实施例的分块渲染模式图形处理方法流程示意图；
图5是本公开实施例的电子设备的结构框图。
具体实施方式
为了使本公开的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本公开进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本公开，并不用于限定本公开。正如本领域技术人员可以认识到的那样，在不脱离本公开的精神或范围的情况下，可通过各种不同方式修改所描述的实施例。因此，附图和描述被认为本质上是示例性的而非限制性的。
在计算机图形学中，图像处理技术可以应用于渲染图像，例如光华(bloom)、景深和超分辨率放大，以增强渲染的视觉效果。这种图像处理算法通常涉及采样像素周围区域的像素颜色。
例如，像素(x，y)经过(2k+1)×(2k+1)滤波核得到滤波后的颜色G(x，y)可以是：
Figure PCTCN2022139346-appb-000003
其中，f(x+u,y+v)表示(2k+1)×(2k+1)滤波核中像素(x+u,y+v)处 的原始像素颜色，h(u,v)表示F(x+u,y+v)的权重因子。
图1为k＝1时，3×3的像素滤波核进行像素滤波的示意图，像素(x，y)经过3×3滤波核得到滤波后的颜色可以是
Figure PCTCN2022139346-appb-000004
Figure PCTCN2022139346-appb-000005
可以看到，对于像素(x，y)进行滤波需要用到其周围8个像素的信息，也就是说，当k＝1时，滤波核还需要对位于像素周围的3×3–1个像素进行处理。类似地，当k＝2时，滤波核还需要对位于像素周围的5×5–1个像素进行处理。
由于分块渲染模式的计算机图形处理系统的渲染图像是在每个图块中单独生成的，而每个图块边界上像素的滤波将涉及相邻图块中的像素，这导致图块边界上像素的滤波在图块处理过程中无法完成。如图1所示，图块M1中原始像素颜色f(x，y)的滤波计算需要相邻图块M2中原始像素颜色f(x+1，y+1)、f(x+1，y)和f(x+1，y-1)的信息，因此，图块M1的边界像素(x，y)处的滤波在图块M1的处理过程中无法完成。
为此，在本公开的实施例中，在对渲染图块应用滤波核进行像素处理时，将渲染图块的每条边界向外进行像素扩展，使得像素处理所需的所有像素都包含在扩展后的图块中，进而使得像素滤波过程可以在每个图块渲染后完成，而不需要在所有图块渲染完成后再启用单独的阶段进行处理，有效提升了像素滤波的处理效率。
在一些实施方式中，当对渲染图像应用(2k+1)×(2k+1)滤波核进行像素处理时，在N×N像素的图块的每条边界上向外额外扩展出k个像素。
如图2所示，在大小为N×N像素的图块M(即由角点C 0、C 1、C 2和C 3定义构成的矩形区域)的每条边界均向外扩展k个像素，即将大小为N×N像素的原始图块M扩展为具有(N+2k)×(N+2k)个像素的扩展图块M’(即由角点C 0’、C 1’、C 2’和C 3’定义构成的矩形区域)。
在一些实施方式中，在扩展图块M’中的渲染完成后，再对渲染的输出图像启用(2k+1)×(2k+1)滤波核进行像素处理。
本公开实施例使用(2k+1)×(2k+1)滤波核对N×N块中的像素进行像素处理时，所需的所有像素都包含在扩展后的(N+2k)×(N+2k)的图块中。因此，像素滤波过程可以在每个图块渲染后完成，而不需要等待所有图块渲染完成后再开启单独的阶段进行处理，有效提升了像素滤波的处理效率。
如图3所示，本公开实施例的扩展图块边界的分块渲染模式图形处理系统包括几何处理系统和片段处理系统，几何处理系统用于根据输入的几何数据(例如顶点数据)构造图元，对图元进行几何处理后，将可见的图元分块到屏幕视觉空间的多个图块，并为每个图块生成分块显示列表。
几何处理系统进一步包括输入汇编模块、几何处理管道和分块模块。输入汇编模块用于根据输入的几何数据构造图元。几何处理管道用于对构造的图元进行处理，删除屏幕视觉空间中不可见的图元，仅保留屏幕视觉空间中可见的图元。分块模块用于将可见的图元分块到屏幕视觉空间的多个图块，并为每个图块生成分块显示列表。
在一些实施方式中，分块显示列表包含与图块至少部分重叠从而需要在图块中进行渲染的所有图元；当某个图元位于多个图块中时，该图元将被包含在屏幕视觉空间该图元所在的每个图块的分块显示列表中。
在一些实施方式中，将屏幕视觉空间划分为多个图块M，将可见的图元分块到屏幕视觉空间的多个图块M，并为每个图块M生成分块显示列表。如图2所示，对屏幕视觉空间的N×N像素的图块M，通过检查图元是否在由角点C 0、C 1、C 2和C 3定义组成的矩形区域内或至少部分在该矩形区域内，可以完成分块。例如，图元T0与该矩形区域部分重叠，图元T1位于该矩形区域内，因此，图元T0和图元T1均包含在图块M的分块显示列表中。而图元T2和图元T3均与该矩形区域不重叠，因此，图元T2和图元T3均不包含在图块M的分块显示列表中。
在一些实施方式中，将屏幕视觉空间划分为多个图块M(即原始图块)，对每个图块M的边界进行扩展，得到扩展图块M’，将可见的图元分块到屏幕视觉空间的多个图块M’，并为每个图块M’生成分块显示列表。如图2所示，将大小 为N×N像素的原始图块M扩展为具有(N+2k)×(N+2k)个像素的扩展图块M’，通过检查图元是否在由角点C 0’、C 1’、C 2’和C 3’定义构成的矩形区域内或至少部分在该矩形区域内，可以完成分块。例如，图元T0和图元T2与该矩形区域部分重叠，图元T1位于该矩形区域内，因此，图元T0、图元T1和图元T2均包含在图块M’的分块显示列表中。而图元T3与该矩形区域不重叠，因此，图元T3不包含在图块M’的分块显示列表中。
几何处理管道进一步包括几何转换模块、裁剪和剔除模块以及数据接收模块。几何转换模块用于将输入汇编模块构造的图元的顶点数据转换到屏幕视觉空间。裁剪和剔除模块用于删除屏幕视觉空间中不可见的图元，仅保留屏幕视觉空间中可见的图元，这部分图元即为渲染场景所需的图元。数据接收模块用于接收和存储屏幕视觉空间中可见的图元的图元数据和转换后的顶点数据。
在一些实施方式中，几何处理系统包括一个几何处理管道，输入汇编模块构造的图元下发至该几何处理管道，由该几何处理管道进行处理。在一些实施方式中，几何处理系统包括多个几何处理管道，输入汇编模块构造的图元分发至下游的多个几何处理管道，由该多个几何处理管道分别处理。
数据接收模块中的图元数据和转换后的顶点数据写入存储模块的第一存储器，分块模块生成的分块显示列表写入存储模块的第二存储器。
片段处理系统用于根据几何处理系统生成的分块显示列表，对图块进行渲染，得到渲染图像。如图3所示，片段处理系统包括分块处理模块、光栅化模块、隐藏面移除模块、像素着色模块和后处理模块。分块处理模块用于从第二存储器读取几何处理系统生成的分块显示列表，将分块显示列表中渲染图块所需的图元发送到光栅化模块。
光栅化模块用于从第一存储器读取分块显示列表中引用的图元所需的图元数据和转换后的顶点数据，将图元光栅化为可见像素。在一些实施方式中，对原始图块M，将图元光栅化为图块M内的可见像素。在一些实施方式中，对扩展图块M’，将图元光栅化为图块M’内的可见像素。
隐藏面移除模块用于对光栅化模块输出的可见像素进行深度测试，具体地， 将光栅化模块输出的可见像素的深度值与存储在深度缓冲区的之前图元像素的深度值进行比较，在光栅化模块输出的图元像素被之前图元像素遮挡时，认为深度测试没有通过，将光栅化模块输出的图元像素移除，否则将光栅化模块输出的图元像素发送至像素着色模块。也就是说，通过隐藏面移除模块，将同一像素位置上位于其他图元后面的像素移除。在一些实施方式中，之前图元像素的深度值为预设值。在一些实施方式中，之前图元像素的深度值为之前通过深度测试的图元像素的深度值。
为了避免与外部存储器频繁交换数据，在分块渲染模式的计算机图形处理系统中，每个像素的当前深度值都存储在片上深度缓冲区中。在一些实施方式中，对原始图块M，具有N×N个像素的图块M中的每个像素的当前深度值都存储在片上深度缓冲区中，即，用于存储当前深度值的片上深度缓冲区的大小为N×N像素。在一些实施方式中，对扩展图块M’，具有(N+2k)×(N+2k)个像素的图块M’中的每个像素的当前深度值都存储在片上深度缓冲区中，即，用于存储当前深度值的片上深度缓冲区的大小为(N+2k)×(N+2k)像素。
像素着色模块用于将隐藏面移除模块输出的可见像素进行着色处理，以获得图元像素的最终颜色。在一些实施方式中，图块中像素的颜色信息存储在分块渲染模式的计算机图形处理系统中的片上颜色缓冲区中，以避免与外部存储器进行频繁的数据交换，影响处理效率。
在一些实施方式中，像素着色模块在原始图块M中的像素上进行着色处理。
在一些实施方式中，像素着色模块在扩展图块M’中的像素上进行着色处理，此时，额外的像素着色工作在扩展图块M’中的额外的像素上完成。
在对渲染的输出图像启用滤波核进行像素处理时，由于扩展图块M’中的像素颜色与原始图块M中的像素颜色同时生成，可以在原始图块M中生成像素颜色后直接使用来自周围像素颜色的信息进行像素处理，而无需再等待所有图块生成像素颜色后才能在另一单独阶段进行边界像素处理，因此，将原本需要分两步完成的处理变成一步即可处理完成，有效提高了像素处理的效率。
以图1所示的3×3滤波核的像素滤波为例，对图块M1边缘的像素(x， y)进行像素滤波操作，需要来自相邻图块M2中的像素(x+1，y+1)、(x+1，y)和(x+1，y-1)的原始颜色信息。如果前面的渲染过程仅限于原始图块，则需要在所有图块渲染完成后，再对图块边界附近的像素(例如像素(x，y)、(x，y-1))进行单独的滤波。而如果前面的渲染过程是针对扩展图块，原始图块周围扩展边界区域中的像素(例如像素(x+1，y+1)、(x+1，y)和(x+1，y-1))能与该原始图块中的其他像素同时处理，即，对原始图块边界附近的像素的滤波操作能够在扩展图块中生成像素颜色后直接完成。由于额外获取了扩展边界像素的信息，使用滤波核进行像素处理时不再需要单独的处理阶段。
在本公开实施例提出的用于分块渲染模式的计算机图形处理系统的方案中，使用来自原始图块周围的扩展边界像素的信息使得像素处理的效率得到了提高。同时像素处理工作量在扩展的分块边界中也会相应增加。
以图2所示的图块为例，扩展边界后的图块大小从N×N增加到(N+2k)×(N+2k)像素。扩展边界图块区域(即扩展图块M’)中的额外像素数为：
uPexp＝2k×(N+2k)+2k×N
对于k＝1时的3x3内核，对于32x32像素的图块，扩展边界图块区域中的额外像素数为：
uPexp＝2×(32+2)+2×32＝132
在32x32像素的图块中占总像素的12.89％。
而对于k＝2时的5x5内核，对于32x32像素的图块，扩展边界图块区域中的额外像素数为：
uPexp＝4×(32+4)+4×32＝272
在32x32像素的图块中占总像素的26.56％。
可以看出，对于更大的滤波核，扩展图块中额外像素的百分比变得非常重要。因此，在本公开实施例中，可在高效像素滤波处理和渲染中额外像素着色的工作负载之间取得平衡，即，根据实际需求，综合考虑像素滤波的处理效率和渲染中额外像素着色的工作量，合理设置k值，本公开对此不作限制。
后处理模块用于对原始图块M的渲染图像启用滤波核进行像素滤波处理， 得到滤波后的图像。在一些实施方式中，原始图块M中的像素(x，y)经过(2k+1)×(2k+1)滤波核得到滤波后的颜色
Figure PCTCN2022139346-appb-000006
Figure PCTCN2022139346-appb-000007
其中，k为正整数，x和y分别表示该像素在像素坐标系中的横坐标和纵坐标，u和v分别表示图像坐标系中相对于横坐标x和纵坐标y的偏移量，u和v均为整数，f(x+u,y+v)表示(2k+1)×(2k+1)滤波核中像素(x+u,y+v)处的原始像素颜色，h(u,v)表示F(x+u,y+v)的权重因子。
为了避免额外的像素着色工作量，在本公开实施例中，扩展图块边界可以仅在选中的渲染中启用，对于其他未进行选择的渲染，仍使用默认的图块处理方式进行处理。也就是说，在不需要进行额外的像素滤波处理时，后处理模块的像素滤波功能不启用，像素着色及其之前的过程可以仅针对原始图块进行，无需额外的像素着色工作量；在需要进行额外的像素滤波处理时，后处理模块的像素滤波功能启用，像素着色及其之前的过程针对扩展图块进行，能显著提高像素滤波的处理效率。
在本公开实施例的分块渲染模式的计算机图形处理系统中，可使用配置设置以确定使用周围像素信息的像素后处理是否应用于渲染。也就是说，可以根据本公开实施例中的配置设置，将扩展图块边界应用于渲染。
如图4所示，本公开实施例的扩展图块边界的分块渲染模式图形处理方法包括：
步骤401：对图元进行几何处理。
在一些实施方式中，对图元进行几何处理包括：删除屏幕视觉空间中不可见的图元，仅保留屏幕视觉空间中可见的图元。
在一些实施方式中，对图元进行几何处理还包括：将图元的顶点数据转换到屏幕视觉空间。
步骤403：将可见的图元分块到屏幕视觉空间的多个图块。
在一些实施方式中，通过配置设置确定图块大小。
在一些实施方式中，在配置设置为第一模式(即不启用像素滤波)时，多个 图块为多个图块M；在配置设置为第二模式(即启用像素滤波)时，多个图块为多个扩展图块M’；其中，多个图块M通过将屏幕视觉空间进行划分得到，多个扩展图块M’通过将多个图块M的边界进行扩展得到。
在一些实施方式中，通过检查图元与图块是否存在重叠区域，将可见的图元分块到屏幕视觉空间的多个图块。
步骤405：为每个图块生成分块显示列表。
在一些实施方式中，对每个图块，所述分块模块用于将所有与该图块存在重叠区域的图元分块到该图块，并包含在该图块的分块显示列表中；对每个图元，所述分块模块用于将该图元分块到所有与该图元存在重叠区域的图块，并包含在该图块的分块显示列表中。因此，当某个图元位于多个图块中时，该图元将被包含在该多个图块的分块显示列表中。
步骤407：根据分块显示列表，对每个图块进行渲染，得到图块的渲染图像。
在一些实施方式中，所述根据分块显示列表，对每个图块进行渲染包括：获取分块显示列表中引用的图元所需的图元数据和转换后的顶点数据，将图元光栅化为可见像素；对光栅化模块输出的可见像素进行深度测试，将同一像素位置上位于其他图元后面的像素移除；将像素移除后剩余的可见像素进行着色处理。
在一些实施方式中，将同一像素位置上位于其他图元后面的像素移除包括：将光栅化的图元像素的深度值与存储在深度缓冲区的之前图元像素的深度值进行比较，在光栅化的图元像素被之前图元像素遮挡时，认为深度测试没有通过，将光栅化的图元像素移除。
在一些实施方式中，之前图元像素的深度值为预设值。在一些实施方式中，之前图元像素的深度值为之前通过深度测试的图元像素的深度值。
步骤409：根据图块的渲染图像启用滤波核进行像素滤波。
在一些实施方式中，在配置设置为第二模式时，执行该步骤409。
在一些实施方式中，根据图块的渲染图像启用滤波核进行像素滤波包括：根据扩展图块M’的渲染图像，对图块M的渲染图像启用滤波核进行像素滤波处理，得到滤波后的图像。
在一些实施方式中，对图块M的渲染图像进行滤波处理所需的所有像素都包含在扩展图块M’中。
在一些实施方式中，图块M为N×N像素的矩形图块，将图块M的每条边界均向外扩展k个像素，得到扩展图块M’，扩展图块M’为(N+2k)×(N+2k)像素的矩形图块；滤波核为(2k+1)×(2k+1)滤波核。
在一些实施方式中，使用(2k+1)×(2k+1)滤波核对N×N块中的像素进行像素处理时，所需的所有像素都包含在扩展后的(N+2k)×(N+2k)的图块中。
在一些实施方式中，图块M中的像素(x，y)经过(2k+1)×(2k+1)滤波核得到滤波后的颜色
Figure PCTCN2022139346-appb-000008
其中，k为正整数，x和y分别为该像素在像素坐标系中的横坐标和纵坐标，u和v分别为图像坐标系中相对于横坐标x和纵坐标y的偏移量，u和v均为整数，f(x+u,y+v)表示(2k+1)×(2k+1)滤波核中像素(x+u,y+v)处的原始像素颜色，h(u,v)表示F(x+u,y+v)的权重因子。
在一些实施方式中，综合考虑像素滤波的处理效率和渲染中额外像素着色的工作量，合理设置k值。
在一些实施方式中，在步骤401之前，上述图形处理方法还包括：根据输入的几何数据构造图元。
本公开实施例的扩展图块边界的分块渲染模式图形处理方法在进一步实现时，可参考前述实施例中对扩展图块边界的分块渲染模式图形处理系统的描述，且具备相同的有益效果，本公开在此不再赘述。
图5为根据本公开一实施例的电子设备的结构框图。本公开实施例还提供了一种电子设备，如图5所示，该电子设备包括：至少一个处理器501，以及与至少一个处理器501通信连接的存储器503。存储器503内存储有可被至少一个处理器501执行的指令。指令被至少一个处理器501执行。处理器501执行该指令时实现上述实施例中的图形处理方法。存储器503和处理器501的数量可以为一个或多个。该电子设备旨在表示各种形式的数字计算机，诸如，膝上型计 算机、台式计算机、工作台、个人数字助理、服务器、刀片式服务器、大型计算机、和其它适合的计算机。电子设备还可以表示各种形式的移动装置，诸如，个人数字处理、蜂窝电话、智能电话、可穿戴设备和其它类似的计算装置。本文所示的部件、它们的连接和关系、以及它们的功能仅仅作为示例，并且不意在限制本文中描述的和/或者要求的本公开的实现。
该电子设备还可以包括通信接口505，用于与外界设备进行通信，进行数据交互传输。各个设备利用不同的总线互相连接，并且可以被安装在公共主板上或者根据需要以其它方式安装。处理器501可以对在电子设备内执行的指令进行处理，包括存储在存储器中或者存储器上以在外部输入/输出装置(诸如，耦合至接口的显示设备)上显示图形用户界面(Graphical User Interface，GUI)的图形信息的指令。在其它实施方式中，若需要，可以将多个处理器和/或多条总线与多个存储器和多个存储器一起使用。同样，可以连接多个电子设备，各个设备提供部分必要的操作(例如，作为服务器阵列、一组刀片式服务器、或者多处理器系统)。该总线可以分为地址总线、数据总线、控制总线等。为便于表示，图5中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
可选的，在具体实现上，如果存储器503、处理器501及通信接口505集成在一块芯片上，则存储器503、处理器501及通信接口505可以通过内部接口完成相互间的通信。
应理解的是，上述处理器可以是中央处理器(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(Digital Signal Processing，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。值得说明的是，处理器可以是支持进阶精简指令集机器(Advanced RISC Machines，ARM)架构的处理器。
本公开实施例提供了一种计算机可读存储介质(如上述的存储器503)，其存储有计算机指令，该程序被处理器执行时实现本公开实施例中提供的方法。
可选的，存储器503可以包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需要的应用程序；存储数据区可存储根据图形处理方法的电子设备的使用所创建的数据等。此外，存储器503可以包括高速随机存取存储器，还可以包括非瞬时存储器，例如至少一个磁盘存储器件、闪存器件、或其他非瞬时固态存储器件。在一些实施例中，存储器503可选包括相对于处理器501远程设置的存储器，这些远程存储器可以通过网络连接至图形处理方法的电子设备。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包括于本公开的至少一个实施例或示例中。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或隐含地包括至少一个该特征。在本公开的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
流程图中或在此以其他方式描述的任何过程或方法描述可以被理解为，表示包括一个或多个(两个或两个以上)用于实现特定逻辑功能或过程的步骤的可执行指令的代码的模块、片段或部分。并且本公开的优选实施方式的范围包括另外的实现，其中可以不按所示出或讨论的顺序，包括根据所涉及的功能按基本同时的方式或按相反的顺序，来执行功能。
在流程图中表示或在此以其他方式描述的逻辑和/或步骤，例如，可以被认为是用于实现逻辑功能的可执行指令的定序列表，可以具体实现在任何计算机可读介质中，以供指令执行系统、装置或设备(如基于计算机的系统、包括处理器的系统或其他可以从指令执行系统、装置或设备取指令并执行指令的系统)使 用，或结合这些指令执行系统、装置或设备而使用。
应理解的是，本公开的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。上述实施例方法的全部或部分步骤是可以通过程序来指令相关的硬件完成，该程序可以存储于一种计算机可读存储介质中，该程序在执行时，包括方法实施例的步骤之一或其组合。
此外，在本公开各个实施例中的各功能单元可以集成在一个处理模块中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。上述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读存储介质中。该存储介质可以是只读存储器，磁盘或光盘等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到其各种变化或替换，这些都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (26)

  1. 一种图形处理系统，其特征在于，包括几何处理系统和片段处理系统；
    所述几何处理系统用于对图元进行几何处理后，将可见的图元分块到屏幕视觉空间的多个扩展图块M’；
    所述片段处理系统用于对每个扩展图块M’进行渲染，得到所述多个扩展图块M’的渲染图像，以及根据每个扩展图块M’的渲染图像启用滤波核进行像素滤波；
    其中，所述多个扩展图块M’通过将屏幕视觉空间进行划分得到多个图块M，再分别将所述多个图块M的边界进行扩展得到。
  2. 如权利要求1所述的图形处理系统，其特征在于，所述图块M为N×N像素的矩形图块，将所述图块M的每条边界均向外扩展k个像素，得到所述扩展图块M’，所述扩展图块M’为(N+2k)×(N+2k)像素的矩形图块；所述滤波核为(2k+1)×(2k+1)滤波核。
  3. 如权利要求2所述的图形处理系统，其特征在于，所述几何处理系统包括几何处理管道和分块模块；所述几何处理管道用于删除屏幕视觉空间中不可见的图元，仅保留屏幕视觉空间中可见的图元；所述分块模块用于将可见的图元分块到屏幕视觉空间的所述多个扩展图块M’，并为每个扩展图块M’生成分块显示列表；所述片段处理系统用于根据所述分块模块生成的分块显示列表，对每个扩展图块M’进行渲染，得到所述多个扩展图块M’的渲染图像。
  4. 如权利要求3所述的图形处理系统，其特征在于，所述分块模块通过检查图元与每个扩展图块M’是否存在重叠区域，将可见的图元分块到屏幕视觉空间的所述多个扩展图块M’。
  5. 如权利要求4所述的图形处理系统，其特征在于，对每个扩展图块M’，所述分块模块用于将所有与该扩展图块M’存在重叠区域的图元分块到该扩展图块M’，并包含在该扩展图块M’的分块显示列表中；对每个图元，所述分块模块用于将该图元分块到所有与该图元存在重叠区域的扩展图块M’，并包含在该扩 展图块M’的分块显示列表中。
  6. 如权利要求3所述的图形处理系统，其特征在于，所述几何处理系统还包括输入汇编模块，所述输入汇编模块用于根据输入的几何数据构造图元，所述几何处理管道用于对所述输入汇编模块构造的图元进行处理，删除屏幕视觉空间中不可见的图元。
  7. 如权利要求3所述的图形处理系统，其特征在于，所述几何处理管道进一步包括几何转换模块、裁剪和剔除模块以及数据接收模块；所述几何转换模块用于将图元的顶点数据转换到屏幕视觉空间；所述裁剪和剔除模块用于删除屏幕视觉空间中不可见的图元，仅保留屏幕视觉空间中可见的图元；所述数据接收模块用于接收和存储屏幕视觉空间中可见的图元的图元数据和转换后的顶点数据。
  8. 如权利要求7所述的图形处理系统，其特征在于，所述片段处理系统包括分块处理模块、光栅化模块、隐藏面移除模块和像素着色模块；所述分块处理模块用于获取所述分块模块生成的分块显示列表，将分块显示列表中渲染图块所需的图元发送到所述光栅化模块；所述光栅化模块用于获取分块显示列表中引用的图元所需的图元数据和转换后的顶点数据，将图元光栅化为可见像素；所述隐藏面移除模块用于对光栅化模块输出的可见像素进行深度测试，将同一像素位置上位于其他图元后面的像素移除；所述像素着色模块用于将所述隐藏面移除模块输出的可见像素进行着色处理。
  9. 如权利要求1至8中任一项所述的图形处理系统，其特征在于，所述片段处理系统包括后处理模块，所述后处理模块用于根据每个扩展图块M’的渲染图像，对该扩展图块M’内的图块M的渲染图像启用滤波核进行像素滤波处理，得到该扩展图块M’内的图块M的滤波后的图像。
  10. 如权利要求2至8中任一项所述的图形处理系统，其特征在于，所述图块M中的像素(x，y)经过(2k+1)×(2k+1)滤波核得到滤波后的颜色
    Figure PCTCN2022139346-appb-100001
    Figure PCTCN2022139346-appb-100002
    其中，f(x+u,y+v)表示(2k+1)×(2k+1)滤波核中像素(x+u,y+v)处的原始像素颜色，h(u,v)表示F(x+u,y+v)的权 重因子。
  11. 一种图形处理系统，其特征在于，包括几何处理系统和片段处理系统；
    所述几何处理系统用于对图元进行几何处理后，将可见的图元分块到屏幕视觉空间的多个扩展图块M’；
    所述片段处理系统用于对每个扩展图块M’进行渲染，得到所述多个扩展图块M’的渲染图像；其中，所述多个扩展图块M’通过将屏幕视觉空间进行划分得到多个图块M，再分别将所述多个图块M的边界进行扩展得到；
    所述片段处理系统还用于在每个扩展图块M’的渲染图像生成后，启用滤波核对该扩展图块M’内的图块M进行像素滤波。
  12. 如权利要求11所述的图形处理系统，其特征在于，根据每个扩展图块M’的渲染图像，启用滤波核对该扩展图块M’内的图块M进行像素滤波；每个扩展图块M’内的图块M的像素滤波过程与其它扩展图块M’的渲染图像是否生成无关。
  13. 一种图形处理方法，其特征在于，包括：
    对图元进行几何处理后，将可见的图元分块到屏幕视觉空间的多个扩展图块M’；
    对每个扩展图块M’进行渲染，得到多个扩展图块M’的渲染图像；其中，所述多个扩展图块M’通过将屏幕视觉空间进行划分得到多个图块M，再分别将所述多个图块M的边界进行扩展得到；
    根据每个扩展图块M’的渲染图像启用滤波核进行像素滤波。
  14. 如权利要求13所述的图形处理系统，其特征在于，所述图块M为N×N像素的矩形图块，将所述图块M的每条边界均向外扩展k个像素，得到所述扩展图块M’，所述扩展图块M’为(N+2k)×(N+2k)像素的矩形图块；所述滤波核为(2k+1)×(2k+1)滤波核。
  15. 如权利要求14所述的图形处理方法，其特征在于，所述对图元进行几何处理包括：删除屏幕视觉空间中不可见的图元，仅保留屏幕视觉空间中可见的图元；在所述将可见的图元分块到屏幕视觉空间的多个扩展图块M’后，为每个 扩展图块M’生成分块显示列表；根据分块显示列表，对每个扩展图块M’进行渲染。
  16. 如权利要求15所述的图形处理方法，其特征在于，通过检查图元与每个扩展图块M’是否存在重叠区域，将可见的图元分块到屏幕视觉空间的多个扩展图块M’。
  17. 如权利要求16所述的图形处理方法，其特征在于，对每个扩展图块M’，所述分块模块用于将所有与该扩展图块M’存在重叠区域的图元分块到该扩展图块M’，并包含在该扩展图块M’的分块显示列表中；对每个图元，所述分块模块用于将该图元分块到所有与该图元存在重叠区域的扩展图块M’，并包含在该扩展图块M’的分块显示列表中。
  18. 如权利要求15所述的图形处理方法，其特征在于，还包括：根据输入的几何数据构造图元；所述对图元进行几何处理还包括：将图元的顶点数据转换到屏幕视觉空间。
  19. 如权利要求18所述的图形处理方法，其特征在于，所述根据分块显示列表，对每个扩展图块M’进行渲染包括：获取分块显示列表中引用的图元所需的图元数据和转换后的顶点数据，将图元光栅化为可见像素；对光栅化模块输出的可见像素进行深度测试，将同一像素位置上位于其他图元后面的像素移除；将像素移除后剩余的可见像素进行着色处理。
  20. 如权利要求13至19中任一项所述的图形处理方法，其特征在于，所述根据每个扩展图块M’的渲染图像启用滤波核进行像素滤波包括：根据每个扩展图块M’的渲染图像，对该扩展图块M’内的图块M的渲染图像启用滤波核进行像素滤波处理，得到滤波后的图像。
  21. 如权利要求13至19中任一项所述的图形处理方法，其特征在于，对每个图块M的渲染图像进行滤波处理所需的所有像素都包含在该图块M所在的扩展图块M’中。
  22. 如权利要求14至19中任一项所述的图形处理方法，其特征在于，所述图块M中的像素(x，y)经过(2k+1)×(2k+1)滤波核得到滤波后的颜色
    Figure PCTCN2022139346-appb-100003
    其中，f(x+u,y+v)表示(2k+1)×(2k+1)滤波核中像素(x+u,y+v)处的原始像素颜色，h(u,v)表示F(x+u,y+v)的权重因子。
  23. 一种图形处理方法，其特征在于，包括：
    对图元进行几何处理后，将可见的图元分块到屏幕视觉空间的多个扩展图块M’；
    对每个扩展图块M’进行渲染，得到多个扩展图块M’的渲染图像；其中，所述多个扩展图块M’通过将屏幕视觉空间进行划分得到多个图块M，再分别将所述多个图块M的边界进行扩展得到；
    在每个扩展图块M’的渲染图像生成后，启用滤波核对该扩展图块M’内的图块M进行像素滤波。
  24. 如权利要求23所述的图形处理方法，其特征在于，根据每个扩展图块M’的渲染图像，启用滤波核对该扩展图块M’内的图块M进行像素滤波；每个扩展图块M’内的图块M的像素滤波过程与其它扩展图块M’的渲染图像是否生成无关。
  25. 一种电子设备，其特征在于，包括权利要求1至12中任一项所述的图形处理系统；
    或者，所述电子设备包括：
    处理器；
    与所述处理器通信连接的存储器；
    所述存储器存储有可被所述处理器执行的指令，所述指令被所述处理器执行，以使所述处理器能够执行权利要求13至24中任一项所述的方法。
  26. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机指令，所述计算机指令被处理器执行时实现如权利要求13至24中任一项所述的方法。
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