WO2024045217A1

WO2024045217A1 - Layout of word line driver, and memory

Info

Publication number: WO2024045217A1
Application number: PCT/CN2022/118565
Authority: WO
Inventors: 李明浩; 尚为兵; 武贤君
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-08-31
Filing date: 2022-09-13
Publication date: 2024-03-07
Also published as: CN117690923A

Abstract

The present disclosure relates to the field of semiconductor layout design, and particularly to a layout of a word line driver, and a memory. The layout of a word line driver comprises: a word line driver, which comprises a drive NMOS, a control PMOS and a drive PMOS. The layout comprises: a plurality of word line drive layouts, which are arranged in a first direction, the first direction being the extension direction of word lines, wherein each word line drive layout comprises: a drive NMOS layout, a control PMOS layout and a drive PMOS layout, which are sequentially arranged in a second direction, the second direction being the arrangement direction of the word lines. In the first direction, drive NMOS layouts in every two adjacent word line drive layouts share a source layer or a drain layer, control PMOS layouts therein share a source layer or a drain layer, and drive PMOS layouts therein share a source layer or a drain layer, wherein gate layers in the drive NMOS layouts and gate layers in the control PMOS layouts are connected by means of a gate connection layer, so as to prevent the layout size, in particular the gate length, of the word line driver from being limited by the sizes of the word line layouts in the arrangement direction of the word lines.

Description

Word line driver layout and memory

cross reference

This disclosure claims priority to the Chinese patent application titled "Layout and Memory of Word Line Driver" and application number 202211056560.X, which was submitted on August 31, 2022, which is fully incorporated into this disclosure by reference.

Technical field

The present disclosure relates to the field of semiconductor layout design, and in particular to a word line driver layout and memory.

Background technique

Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density and fast transmission speed. With the development of semiconductor technology, DRAM technology has become more and more advanced, and the integration of memory cells has become higher and higher. As the integration of memory cells increases, the integration of word lines that need to control the memory cells also increases accordingly.

The integration level of the word line determines the size of the word line layout, and the size of the word line layout will affect the layout settings of the corresponding word line driver; therefore, it is urgent to design a new word line driver layout method to avoid the problem of word line layout. In the arrangement direction, the layout size of the word line driver, especially the gate length, is limited by the word line layout size.

Contents of the invention

An embodiment of the present disclosure provides a word line driver layout, including: the word line driver includes a driving NMOS, a control PMOS, and a driving PMOS, and includes: a plurality of word line driving layouts arranged along a first direction, and the first direction is a word line driver layout. The extension direction of the line; each word line driving layout includes: a driving NMOS layout, a control PMOS layout and a driving PMOS layout arranged in sequence along the second direction. The second direction is the arrangement direction of the word line; and in the first direction, two The driving NMOS layouts in two adjacent word line driving layouts share a source or drain layer, the control PMOS layouts share a source or drain layer, and the driving PMOS layouts share a source or drain layer, where the driving NMOS The gate layer in the layout and the gate layer in the control PMOS layout are connected through a gate connection layer.

In addition, adjacent gate connection layers are staggered.

In addition, the edge size of the gate layer in the driving NMOS layout, the gate layer in the control PMOS layout, and the gate layer in the driving PMOS layout is larger than the middle size.

In addition, the layout of the word line driver also includes: a first interconnection layer, which is provided on the top of the gate layer in the driving NMOS layout, the control PMOS layout and the driving PMOS layout, and is provided with a first connection pattern, and the first connection pattern is The second direction extends and is used for interconnection between the terminals of driving NMOS, controlling PMOS and driving PMOS; the second interconnection layer is provided on the top of the first interconnection layer, and is provided with a second connection pattern. The second connection pattern Extending in the first direction and connected to the first connection pattern, it is used for inputting/outputting control signals corresponding to the driving NMOS, controlling PMOS and driving PMOS terminals.

In addition, the first connection pattern includes: an output contact pattern, extending along the second direction, and is arranged on the top of the drain pattern in the driving NMOS layout, the top of the drain pattern in the control PMOS layout, and the top of the drain pattern in the driving PMOS layout The top of the NMOS is used to connect the drain of the driving NMOS, the drain of the control PMOS and the drain of the driving PMOS; the first contact pattern extends along the second direction and is set on the top of the source pattern in the driving NMOS layout for Connect the source of the driving NMOS; the second contact pattern is set in the gap between the driving NMOS layout and the control PMOS layout, and is used to connect the gate of the driving NMOS and the gate of the control PMOS; the third contact pattern is along the second The direction extends and is arranged on the top of the source pattern in the driving PMOS layout and the control PMOS layout, and is used to connect the source electrode of the control PMOS and the source electrode of the driving PMOS; the fourth contact pattern is arranged on the top of the gate pattern in the driving PMOS layout. The top is used to connect the gate that drives the PMOS.

In addition, the second connection pattern includes: an output transmission pattern, which is arranged in the first direction and is used to connect the output contact pattern and the word line input pattern. The word line input pattern is used to provide a driving signal to the connected word line; the first transmission pattern , disposed on the top of the first contact pattern, used to connect the first contact pattern and the first input pattern, the first input pattern is used to receive the source control signal for driving NMOS; the second transmission pattern, disposed on the top of the second contact pattern, used to connect the second contact pattern and the second input pattern, the second input pattern is used to receive the gate control signal for driving the NMOS and controlling the PMOS; the third transmission pattern is arranged on the top of the third contact pattern and is used to connect the third contact graphics and a third input pattern, the third input pattern is used to receive the source control signal for controlling the PMOS and driving the PMOS; the fourth transmission pattern is arranged on top of the fourth contact pattern and is used to connect the fourth contact pattern and the fourth input pattern , the fourth input pattern is used to receive the gate control signal for driving the PMOS.

In addition, in the first direction, the projections of the third transmission patterns corresponding to different word line driving layouts in the first direction overlap with each other; the second connection pattern also includes: a third interconnection pattern arranged in the first direction, It is used to connect all third transmission patterns arranged in the first direction; and at least one third input pattern is arranged on the third interconnection pattern.

In addition, two third input patterns are disposed on the third interconnection pattern, and the third input patterns are disposed on both sides of the third interconnection pattern in the first direction.

In addition, a plurality of third transmission patterns corresponding to the word line driving layout are provided in the second direction.

In addition, in the first direction, the projections of the first transmission patterns corresponding to different word line driving layouts in the first direction partially overlap; the second connection pattern also includes: a plurality of first interconnection patterns, in the second direction They are arranged at intervals and extend in the first direction, and are used to connect all the first transmission patterns that overlap in projection in the first direction; and at least one first input pattern is provided on each first interconnection pattern.

In addition, in the first direction, the projections of the first transmission patterns corresponding to different word line driving layouts in the first direction completely overlap; the second connection pattern also includes: a first interconnection pattern arranged in the first direction, It is used to connect all the first transmission patterns arranged in the first direction; and at least one first input pattern is arranged on the first interconnection pattern.

In addition, two first input patterns are disposed on the first interconnection pattern, and the first input patterns are disposed on both sides of the first interconnection pattern in the first direction.

In addition, in the first direction, the second transmission patterns connect a plurality of second contact patterns; in the second direction, a plurality of second transmission patterns are arranged at intervals, and the adjacent second transmission patterns are projected in the second direction different.

In addition, in the first direction, a plurality of second transmission patterns are provided, and the projections of the plurality of second transmission patterns overlap with each other.

In addition, at least one second input pattern is provided on the second transmission pattern, and the projection positions of all the second input patterns in the second direction are different from each other.

In addition, the projections of the second contact patterns corresponding to two adjacent word line driving patterns in the first direction in the second direction overlap with each other; the overlapping projections of the second contact patterns correspond to the connected second transmission patterns. The projections in the directions coincide with each other.

Another embodiment of the present disclosure also provides a memory. The word line driver performs layout layout based on the layout of the word line driver provided in the above embodiment.

Description of drawings

One or more embodiments are exemplified by the pictures in the corresponding drawings. These illustrative illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a limitation on proportions; in order to To more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic circuit diagram of a word line driver provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of the layout of a word line driver and the arrangement of word lines according to an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a word line driving layout provided by an embodiment of the present disclosure;

FIG. 4 is a schematic structural diagram of the layout arrangement of multiple word line drivers provided by an embodiment of the present disclosure;

Figure 5 is a schematic structural diagram of the arrangement of the first interconnection layer provided by an embodiment of the present disclosure;

6 to 10 are schematic structural diagrams of the arrangement of the second interconnection layer according to an embodiment of the present disclosure.

Detailed ways

It can be known from the background art that as the integration level of memory cells increases, the integration level of word lines that need to be controlled by the memory cells also increases accordingly. The integration level of the word line determines the size of the word line layout, and the size of the word line layout affects the layout settings of the corresponding word line driver.

An embodiment of the present disclosure provides a word line driver layout that avoids the word line driver layout size, especially the gate length, being limited by the word line layout size in the arrangement direction of the word lines.

Persons of ordinary skill in the art can appreciate that in each embodiment of the present disclosure, many technical details are provided to enable readers to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present disclosure can also be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined with each other and referenced to each other on the premise that there is no contradiction.

FIG. 1 is a schematic circuit diagram of the word line driver provided by this embodiment. FIG. 2 is a schematic diagram of the layout of the word line driver and the arrangement of word lines provided by this embodiment. FIG. 3 is the structure of the word line driver layout provided by this embodiment. Schematic diagram. Figure 4 is a schematic structural diagram of the layout arrangement of multiple word line drivers provided by this embodiment. Figure 5 is a schematic structural diagram of the layout of the first interconnection layer provided by this embodiment. Figures 6 to 10 are schematic diagrams of the layout of the first interconnection layer provided by this embodiment. The structural schematic diagram of the arrangement of the second interconnection layer is provided. The layout of the word line driver provided in this embodiment is described in detail below with reference to the accompanying drawings, as follows:

Referring to Figure 1, for the word line driver provided in this embodiment, the word line driver includes: driving NMOS<N>, controlling PMOS<K> and driving PMOS, where the source of controlling PMOS<K> and driving PMOS The source of is connected to receive the first control signal. The gate of driving PMOS is used to receive the second control signal. The gate of controlling PMOS <K> is connected to the gate of driving NMOS <N>. , used to receive the third control signal, drive the source of NMOS<N> to receive the fourth control signal, drive the drain of NMOS<N>, control the drain of PMOS<K> and drive the drain of PMOS poles connected for outputting driving signals; specifically, driving NMOS<N>, controlling PMOS<K> and driving PMOS are generated based on the first control signal, the second control signal, the third control signal and the fourth control signal. Driving signal, the driving signal is used to drive the word line connected to the word line driver.

Referring to Figures 2 to 4, the layout of the word line driver includes:

A plurality of word line driving layouts 100 arranged along the first direction X, where the first direction , control PMOS layout 120 and drive PMOS layout 130, the second direction Y is the arrangement direction of the word lines.

Specifically, referring to Figure 2, the layout of the word line driver is set on one side of the extension direction of the word lines. The arrangement direction of the word lines is the connection direction of the arrangement of multiple word lines. The extension direction of the word lines is the layout of each word line. Direction; the layout of the word line driver is set based on the first direction X and the second direction Y, where the first direction X is the same as the extension direction of the word lines, and the second direction Y is the same as the arrangement direction of the word lines.

It should be noted that in the drawings of this embodiment, the first direction X and the second direction Y are vertical as an example for specific illustration, which is only for those skilled in the art to understand the layout of the word line driver in this solution. It does not constitute a limitation to this embodiment.

For the word line driving layout 100, the driving NMOS layout 110 is used to form the driving NMOS<N> shown in FIG. 1, the driving PMOS layout 130 is used to form the driving PMOS shown in FIG. 1, and the control PMOS layout 120 is used to form Control PMOS<K> shown in Figure 1.

For the layout of the word line driver, refer to FIG. 4. Multiple word line driver layouts are arranged along the first direction X. For each word line driver layout 100, refer to FIG. 3, the driving NMOS layout 110 includes: a first gate layer. 101. The first source contact layer 102 and the first drain contact layer 103 share a source layer or a drain between two adjacent driving NMOS layouts 110 in the word line driving layout 100 in the first direction X. layer, in the example of FIG. 3 , the first source contact layer 102 is shared between the driving NMOS layouts 110 in two adjacent word line driving layouts 100 . Specifically, the example of FIG. 3 does not reflect the source layer and the drain layer in the driving NMOS layout 110, where the source layer is disposed at the bottom of the first source contact layer 102, and the first source contact layer 102 and the source layer connection, thereby realizing data interaction with the source of the driving NMOS<N> through the first source contact layer 102; the drain layer is provided at the bottom of the first drain contact layer 103, and the first drain contact layer 103 is connected to the drain layer , thereby realizing data interaction through the first drain contact layer 103 and the drain of the driving NMOS<N>. The control PMOS layout 120 includes: a second gate layer 104, a second source contact layer 105 and a second drain contact layer 106. In the first direction X, two adjacent word lines drive the control PMOS in the layout 100 The source layer or the drain layer is shared between the layouts 120 . In the example of FIG. 3 , the second source contact layer 105 is shared between the control PMOS layouts 120 in two adjacent word line driving layouts 100 . Specifically, the example of FIG. 3 does not reflect the control of the source layer and the drain layer in the PMOS layout 120, where the source layer is disposed at the bottom of the second source contact layer 105, and the second source contact layer 105 and the source layer connection, thereby realizing data interaction with the source of the control PMOS<K> through the second source contact layer 105; the drain layer is provided at the bottom of the second drain contact layer 106, and the second drain contact layer 106 is connected to the drain layer , thereby realizing data interaction with the drain of the control PMOS<K> through the second drain contact layer 106. The driving PMOS layout 130 includes: a third gate layer 107, a third source contact layer 108 and a third drain contact layer 109; in the first direction X, two adjacent word lines in the driving PMOS driving layout 100 The source layer or the drain layer is shared between the layouts 130 . In the example of FIG. 3 , the third source contact layer 108 is shared between the driving PMOS layouts 130 in two adjacent word line driving layouts 100 . Specifically, the example of FIG. 3 does not reflect the source and drain layers in the driving PMOS layout 130. The source layer is disposed at the bottom of the third source contact layer 108, and the third source contact layer 108 and the source layer connection, thereby realizing data interaction with the source of the driving PMOS through the third source contact layer 108; the drain layer is provided at the bottom of the third drain contact layer 109, and the third drain contact layer 109 is connected to the drain layer , thereby realizing data interaction with the drain of the driving PMOS through the third drain contact layer 109.

It should be noted that for the example of FIG. 3 , the source electrode is shared between the driving NMOS layouts 110 , that is, the source electrode layer in the driving NMOS layout 110 is disposed between the first gate electrode layers 101 in adjacent driving NMOS layouts 110 . The driving NMOS layout 110 shares the first source contact layer 102 to implement data interaction with the source of the driving NMOS <N>; the control PMOS layout 120 shares the source, that is, the source layer in the PMOS layout 120 is controlled to be arranged adjacent to Between the second gate layers 104 in the control PMOS layout 120, the adjacent control PMOS layouts 120 share the second source contact layer 105 to implement data interaction with the source of the control PMOS<K>; the driving PMOS layouts 130 share The source, that is, the source layer in the driving PMOS layout 130 is disposed between the third gate layer 107 in the adjacent driving PMOS layout 130. The adjacent driving PMOS layouts 130 share the third source contact layer 108 to implement and drive PMOS. 's source of data interaction. In addition, in some embodiments, the drains can be shared between the driving NMOS layouts 110, that is, the drain layer in the driving NMOS layout 110 is disposed between the first gate layers 101 in the adjacent driving NMOS layouts 110. The adjacent drive NMOS layouts 110 share the first source contact layer to realize data interaction with the drain of the drive NMOS <N>; the drains are shared between the control PMOS layouts 120, that is, the drain layers in the PMOS layout 120 are controlled to be arranged adjacent to each other. Between the second gate layers 104 in the control PMOS layout 120, the adjacent control PMOS layouts 120 share the second drain contact layer to realize data interaction with the drain of the control PMOS<K>; the driving PMOS layouts 130 share a drain contact layer. pole, that is, the drain layer in the driving PMOS layout 130 is disposed between the third gate layer 107 in the adjacent driving PMOS layout 130, and the adjacent driving PMOS layouts 130 share the third drain contact layer to realize and drive PMOSDrain data interaction.

It should be noted that for the source layer and drain layer in the driving NMOS layout 110, the control PMOS layout 120 and the driving PMOS layout 130, as well as the corresponding source contact layer and drain contact layer, the source layer and the drain layer Based on the symmetrical arrangement of the gate layer, the drawings of this embodiment are only for those skilled in the art to understand the layout arrangement of the word line driver provided in this embodiment; in other embodiments, driving the NMOS layout, controlling the PMOS layout and The source layer and drain layer in the driving PMOS layout can be exchanged. At this time, the adjacent driving NMOS<N> shares the drain, the adjacent controlling PMOS<K> shares the drain, and the adjacent driving PMOS shares the drain. .

In addition, in the drawing shown in FIG. 3 , the number of patterns of the first source contact layer 102 and the first drain contact layer 103 in the driving NMOS layout 110 is two to reduce the number of subsequent interconnect layers and the driving NMOS. The contact resistance of the source layer and the drain layer in the layout 110 does not constitute a limit on the number of the first source contact layer 102 and the first drain contact layer 103 in this embodiment; in specific applications, it can be determined according to the driving NMOS The accuracy of <N> requires setting the number of the corresponding first source contact layer 102 and the first drain contact layer 103; accordingly, the number of the third source contact layer 108 and the third drain contact layer 109 in the driving PMOS layout 130 The number of patterns is four to reduce the contact resistance between the subsequently provided interconnect layer and the source layer and drain layer in the driving PMOS layout 130. This embodiment does not constitute a connection between the third source contact layer 108 and the third drain layer. The number of contact layers 109 is limited; in specific applications, the number of corresponding third source contact layers 108 and third drain contact layers 109 can be set according to the accuracy requirements for driving PMOS.

In addition, referring to FIG. 3 , the gate layer in the driving NMOS layout 110 and the gate layer in the control PMOS layout 120 are connected through the gate connection layer 203 . The gate connection layer 203 is used to connect the first gate in the driving NMOS layout 110 The electrode layer 101 and the second gate layer 104 in the control PMOS layout 120. Specifically, the gate connection layer 203 performs signal transmission through the first pattern 201 to receive the third control signal, and the third gate layer 107 performs signal transmission through the second pattern 202 to receive the second control signal.

In some embodiments, a first redundant gate pattern 204 is also provided on the side of the first drain contact layer 103 away from the first gate layer 101 , and the third drain contact layer 109 is away from the third gate layer. A second redundant gate pattern 205, a first redundant gate pattern 204 and a second redundant gate pattern 205 are also provided on one side of 103 to ensure that the gate structures in different word line drivers are in the same state. The layout environment of the line driver is consistent to ensure the uniformity of photolithography. If the first redundant gate pattern 204 and the second redundant gate pattern 205 are set, during the photolithography process of the layout of the word line driver , the gate pattern in the word line driving layout 100 may be broken.

It should be noted that since the doping types of the control PMOS<K> and the driving PMOS are the same, they can be set in the same type of active area, while the doping types of the controlling PMOS and the driving NMOS<N> Different, they cannot be arranged in the same type of active area; therefore, the distance between the control PMOS layout 120 and the driving PMOS layout 130 is smaller than the distance between the control PMOS layout 120 and the driving NMOS layout 110 . Correspondingly, in other embodiments, the control PMOS can be replaced by the control NMOS, and the control NMOS is formed based on the control NMOS layout. At this time, since the control NMOS and the driving NMOS have the same doping type, they can be arranged in the same type of active area. , the doping types of the control NMOS and the driving PMOS are different and cannot be set in the same type of active area. Therefore, the distance between the control NMOS layout and the driving PMOS layout is smaller than the distance between the control NMOS layout and the driving NMOS layout. .

For memory cells with gradually increasing integration, the layout size of the same number of memory cells decreases. Correspondingly, the spacing between word lines decreases, and the size of the word line layout in the direction of the word line arrangement decreases; while the word lines The layout size of the layout in the direction of the word line arrangement is reduced, and the layout size of the word line driver that adapts to it also needs to be reduced accordingly (refer to Figure 2). In this embodiment, multiple word line driver layouts 100 are arranged in the extension direction of the word lines, and each word line driver layout 100 is arranged in the arrangement direction of the word lines, so that the layout size of the word line driver can be reduced correspondingly. Adjust the size of the word line driver layout 100; for each word line driver layout 100, the layout size in the arrangement direction of the word lines is much larger than the layout size in the extension direction of the word lines (refer to Figure 3), making it easier to achieve size reduction. , thereby avoiding that the layout size of the word line driver, especially the gate length, is limited by the word line layout size in the direction of the word line arrangement.

In some embodiments, the edge size of the gate layer in the driving NMOS layout 110, the gate layer in the control PMOS layout 120, and the gate layer in the driving PMOS layout 130 is larger than the middle size; with specific reference to FIG. 3, for the first In the gate layer 101, the second gate layer 104 and the third gate layer 107, the edge size of the gate layer is larger than the middle size of the gate layer to increase the contact area of the gate layer, thereby reducing the signal transmission time of the gate layer. of parasitic capacitance.

Regarding the gate connection layers 203 provided in this embodiment, referring to FIG. 4 , adjacent gate connection layers 203 are staggered, and the projections of the first patterns 201 corresponding to the gate connection layers 203 on the second reverse direction Y overlap.

For the word line driver layout 100, refer to Figures 5 to 10. The word line driver layout 100 also includes: a first interconnection layer, which is provided on the top of the gate layer in the drive NMOS layout 110, the control PMOS layout 120 and the drive PMOS layout 130. , and a first connection pattern is provided. The first connection pattern extends in the second direction Y and is used for interconnection between the terminals of driving NMOS<N>, controlling PMOS<K> and driving PMOS; the second interconnection pattern A connection layer is provided on the top of the first interconnection layer and is provided with a second connection pattern. The second connection pattern extends in the first direction X and is connected to the first connection pattern for input/output driving NMOS<N> and control. Control signals corresponding to each terminal of PMOS<K> and drive PMOS, such as the first control signal, the second control signal, the third control signal, the fourth control signal and the drive signal shown in Figure 1.

For the first connection pattern, referring to Figure 5, the first connection pattern includes:

The output contact pattern 304 extends along the second direction Y and is disposed on the top of the drain pattern in the driving NMOS layout 110, the top of the drain pattern in the control PMOS layout 120, and the top of the drain pattern in the driving PMOS layout 130, for Connect the drain of driving NMOS<N>, the drain of controlling PMOS<K> and the drain of driving PMOS. Specifically, the output contact pattern 304 is disposed on the top of the first drain contact layer 103, the second drain contact layer 106, and the third drain contact layer 109, and is in contact with the first drain contact layer 103, the second drain contact layer 103, and the third drain contact layer 109. Layer 106 and third drain contact layer 109 are electrically connected, thereby connecting the drain of the driven NMOS<N>, the drain of the controlled PMOS<K>, and the drain of the driven PMOS.

The first contact pattern 301 extends along the second direction Y and is disposed on the top of the source pattern in the driving NMOS layout 110 for connecting the source of the driving NMOS<N>. Specifically, the first contact pattern 301 is disposed on the top of the first source contact layer 102 and is electrically connected to the first source contact layer 102, thereby connecting the source of the driving NMOS<N>.

The second contact pattern 302 extends along the second direction Y and is disposed in the gap between the driving NMOS layout 110 and the control PMOS layout 120 for connecting the gate of the driving NMOS<N> and the gate of the control PMOS<K>. pole. Specifically, the second contact pattern 302 is disposed on the top of the gate connection layer 203 and is electrically connected to the first pattern 201, thereby connecting the gate of driving NMOS<N> and the gate of controlling PMOS<K>.

The third contact pattern 303 extends along the second direction Y and is disposed on the top of the source pattern in the driving PMOS layout 130 and the control PMOS layout 120 for connecting the source of the control PMOS<K> and the source of the driving PMOS. Source. Specifically, the third contact pattern 303 is disposed on top of the second source contact layer 105 and the second source contact layer 108, and is electrically connected to the second source contact layer 105 and the second source contact layer 108, thereby connecting Control the source of PMOS<K> and drive the source of PMOS;

The fourth contact pattern 305 is disposed on the top of the gate pattern in the driving PMOS layout 130 and is used to connect the gate of the driving PMOS . Specifically, the fourth contact pattern 305 is disposed on the top of the third gate layer 107 and is electrically connected to the second pattern 202, thereby connecting the gate of the driving PMOS.

It should be noted that the fourth contact pattern 305 can be configured to extend in the first direction Graph 305 provides control signals for multiple driver PMOS simultaneously.

For the second connection pattern, referring to Figure 6, the second connection pattern includes:

The output transmission pattern 405 is arranged in the first direction X and is used to connect the output contact pattern 304 and the word line input pattern 415. The word line input pattern 405 is used to provide a driving signal to the connected word line. Specifically, the output transfer pattern 405 is connected to the output contact pattern 304 through the third pattern 425, thereby connecting the drain electrode of the driving NMOS<N>, the drain electrode of the control PMOS<K>, and the drain electrode of the driving PMOS, and by connecting The word line input pattern 415 outputs the driving signal.

The first transmission pattern 401 is disposed on the top of the first contact pattern 301 and is used to connect the first contact pattern 301 and the first input pattern 411. The first input pattern 411 is used to receive the source control signal for driving NMOS<N>. Specifically, the first transmission pattern 401 is disposed on top of the first contact pattern 301 for connecting the first contact pattern 301, thereby connecting the source of the driving NMOS<N>, and receiving the fourth control through the connected first input node 411 signal to transmit the fourth control signal to the source of the driver NMOS<N>.

The second transmission pattern 402 is disposed on the top of the second contact pattern 302 and is used to connect the second contact pattern 302 and the second input pattern 412. The second input pattern 412 is used to receive signals for driving NMOS<N> and controlling PMOS<K>. Gate control signal. Specifically, the second transmission pattern 402 is disposed on the top of the second contact pattern 302 for connecting the second contact pattern 302, thereby connecting the gate of driving NMOS<N> and the gate of controlling PMOS<K>, and through the connected The second input pattern 412 receives the third control signal to transmit the third control signal to the gate that drives the NMOS<N> and the gate that controls the PMOS<K>.

The third transmission pattern 403 is disposed on the top of the third contact pattern 303 and is used to connect the third contact pattern 303 and the third input pattern 413. The third input pattern 413 is used to receive control PMOS<K> and drive PMOS. Source control signal. Specifically, the third transmission pattern 403 is disposed on the top of the third contact pattern 303 for connecting the third contact pattern 303, thereby connecting the source of the control PMOS<K> and the source of the drive PMOS, and through the connection The third input pattern 413 receives the first control signal to transmit the first control signal to the source of the control PMOS<K> and the source of the driving PMOS.

The fourth transmission pattern 404 is disposed on the top of the fourth contact pattern 305 and is used to connect the fourth contact pattern 305 and the fourth input pattern 414. The fourth input pattern 414 is used to receive the gate control signal for driving the PMOS. Specifically, the fourth transmission pattern 404 is disposed on a side of the driving PMOS layout 130 away from the driving NMOS layout 110, and receives the second control signal through the connected fourth input pattern 414 to transmit the second control signal to the driving PMOSGate.

It should be noted that since the first transmission pattern 401 in FIG. 6 does not intersect with other first contact patterns 301, the position of the corresponding contact pattern is not shown, and the second transmission pattern 402 does not intersect with other second contact patterns. 302 has a pattern intersection, so the position of the corresponding contact pattern is not shown. The third transmission pattern 403 does not have a pattern intersection with other third contact patterns 303, so the position of the corresponding contact pattern is not shown. Those skilled in the art understand that A transmission pattern 401 also needs to be electrically connected to the first contact pattern 301 through a corresponding contact pattern. The second transmission pattern 402 also needs to be electrically connected to the second contact pattern 302 through a corresponding contact pattern. The third transmission pattern 403 also needs to be electrically connected to the corresponding contact pattern. Electrically connected to the third contact pattern 303.

Referring to Figure 7, in some embodiments, in the first direction X, the projections of the third transmission patterns 403 corresponding to different word line driving layouts 100 in the first direction The three interconnection patterns 423 are arranged in the first direction X and are used to connect all the third transmission patterns 403 arranged in the first direction X, and at least one third input pattern 413 is arranged on the third interconnection pattern. Multiple third transmission patterns 403 are connected through the third interconnection pattern 423 to simultaneously provide first control signals to multiple word line driving layouts 100 based on the same input pattern, and to avoid setting multiple signal receiving patterns to reduce the number of word lines. The overall parasitic capacitance of the driver layout.

In some embodiments, two third input patterns 413 are disposed on the third interconnection pattern 423, and the third input patterns 413 are disposed on both sides of the third interconnection pattern 423 in the first direction X.

In some embodiments, multiple third transmission patterns 403 corresponding to the word line driving layout 100 are provided in the second direction Y. The plurality of third transmission patterns 403 are segmented to provide control signals for the third contact pattern 303, which increases the contact area between the third transmission pattern 403 and the third contact pattern 303 to a certain extent, thereby reducing the control PMOS<K> The source voltage drop of and the source voltage drop of driving PMOS.

Referring to Figure 8, in some embodiments, the projections of the first transmission patterns 401 corresponding to different word line driving layouts 100 in the first direction X partially overlap, and the second connection pattern also includes: a plurality of first interconnection patterns 421 , arranged at intervals in the second direction Y and extending in the first direction First input pattern 411. Referring to Figure 9, in some embodiments, the projections of the first transmission patterns 401 corresponding to different word line driving layouts 100 in the first direction completely overlap, and the second connection pattern also includes: a first interconnection pattern 421, The direction X is set for connecting all first transmission patterns 401 set in the first direction X, and at least one first input pattern is set on the first interconnection pattern 421. Multiple first transmission patterns 401 are connected through the first interconnection pattern 421 to simultaneously provide fourth control signals to multiple word line driving layouts 100 based on the same input pattern, and to avoid setting multiple signal receiving patterns to reduce the number of word lines. The overall parasitic capacitance of the driver layout.

Continuing to refer to FIG. 9 , in some embodiments, two first input patterns 411 are provided on the first interconnection pattern 421 , and the first input patterns 411 are provided on both sides of the first interconnection pattern 421 in the first direction X. side.

Based on the foregoing discussion, it can be known that adjacent gate connection layers 203 are staggered, and the projections of the first patterns 201 corresponding to the gate connection layers 203 on the second reverse direction Y coincide.

In some embodiments, in the first direction The positions of the projections of the graphics 402 in the second direction Y are different. A plurality of second contact patterns 302 are connected through the second transmission pattern 402 .

Specifically referring to Figure 10 and combined with Figure 4, from top to bottom in the first direction The layout and the fifth word line driving layout are connected to the second word line driving layout and the sixth word line driving layout through a second transmission pattern 402, and the gate connection layer 203 in the first word line driving layout and the second word line driving layout Staggered arrangement: the gate connection layers 203 in the fifth word line driving layout and the sixth word line driving layout are arranged in an staggered manner, and the projections of the corresponding two second transmission patterns 402 in the second direction Y overlap; in addition, through a second The transmission pattern 402 connects the third word line driving layout and the seventh word line driving layout. A second transmission pattern 402 connects the fourth word line driving layout and the eighth word line driving layout. The third word line driving layout and the fourth word line driving layout are connected. The gate connection layers 203 in the line drive layout are staggered, the gate connection layers 203 in the seventh word line drive layout and the eighth word line drive layout are staggered, and the corresponding two second transmission patterns 402 are in the second direction Y. The projections overlap, and the second transmission patterns 402 corresponding to the word line driving layout 100 of adjacent groups, that is, the projection positions of the adjacent second transmission patterns 402 in the second direction Y are different, so as to realize multiple output patterns based on the same output pattern at the same time. The word line driver layout provides a third control signal and avoids setting multiple signal receiving patterns to reduce the overall parasitic capacitance of the word line driver layout. In some embodiments, in the first direction X, multiple second transmission graphics 402 are provided, and the projections of the multiple second transmission graphics 402 coincide with each other.

For the second transmission pattern 402 shown in FIG. 10 , since the second transmission pattern 402 spans multiple second contact patterns 302 , in order to clearly reflect the corresponding relationship between the second transmission pattern 402 and the second contact pattern 302 , the second transmission pattern 402 spans multiple second contact patterns 302 . Graphic 402 is connected to second contact graphic 302 through fourth pattern 422 .

In some embodiments, the projections of the second contact patterns 402 corresponding to two adjacent word line driving layouts 100 in the first direction X coincide with each other in the second direction Y, and the second contact patterns 304 with overlapping projections are connected correspondingly. The projections of the second transmission pattern 402 in the second direction Y coincide with each other.

In some embodiments, at least one second input pattern 412 is provided on the second transmission pattern 402, and the projection positions of all the second input patterns 412 in the second direction Y are complementary and the same. By staggering the positions of the second input patterns 412 to increase the spacing between adjacent second input patterns 412, the parasitic capacitance of the entire layout of the word line driver is reduced.

It should be noted that, in the drawings of this embodiment, a word line driver layout consisting of eight word line driver layouts 100 is used as an example for explanation, which does not constitute a limitation on the number of word line drive layouts 100 in the word line driver layout. In specific applications, specific settings can be made based on the actual number of sub-line driver layouts 100 that need to be set in the word line driver layout.

In this embodiment, multiple word line driver layouts 100 are arranged in the extension direction of the word lines, and each word line driver layout 100 is arranged in the arrangement direction of the word lines, so that the layout size of the word line driver can be reduced correspondingly. Adjust the size of the word line driver layout 100; for each word line driver layout 100, the layout size in the arrangement direction of the word lines is much larger than the layout size in the extension direction of the word lines (refer to Figure 3), making it easier to achieve size reduction. , thereby avoiding that the layout size of the word line driver, especially the gate length, is limited by the word line layout size in the direction of the word line arrangement. It should be noted that the number of word lines connected to a word line driver can be set to one or more, that is, the driving signal provided by the word line driver can drive one or more word lines at the same time. For the number of word lines connected to the word line driver, , this embodiment is not limited, that is, any number of word lines connected to the word line driver falls within the protection scope of the present disclosure.

It should also be noted that the features disclosed in the word line driver layout provided in the above embodiments can be combined arbitrarily without conflict, and a new word line driver layout embodiment can be obtained.

Another embodiment of the present disclosure provides a memory. The word line driver performs layout based on the layout of the word line driver provided in the above embodiment to avoid the layout size of the word line driver, especially the gate length, in the arrangement direction of the word lines. Limited by word line layout size.

Specifically, for memory cells with gradually increasing integration levels, the layout size of the same number of memory cells decreases. Correspondingly, the spacing between word lines decreases, and the layout size of the word line layout in the arrangement direction of the word lines decreases; The layout size of the word line layout in the word line arrangement direction is reduced, and the layout size of the word line driver adapted to it also needs to be reduced accordingly.

By arranging multiple word line driver layouts in the extension direction of the word lines, each word line driver layout is arranged in the arrangement direction of the word lines, so that the layout size of the word line driver can be reduced correspondingly by adjusting the size of the word line driver accordingly. Layout size; for each word line driver layout, the layout size in the arrangement direction of the word lines is much larger than the layout size in the extension direction of the word lines, making it easier to achieve size reduction, thereby avoiding word lines in the arrangement direction. The layout size of the line driver, especially the gate length, is limited by the word line layout size.

In some embodiments, the memory may be a memory unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory such as dynamic random access memory DRAM, synchronous dynamic random access memory SDRAM, double data rate synchronous dynamic random access memory DDR SDRAM, low power double data rate synchronous dynamic random access memory Access memory LPDDR SDRAM, graphics double data rate synchronous dynamic random access memory GDDR SDRAM, double data rate type dual synchronous dynamic random access memory DDR2SDRAM, double data rate type triple synchronous dynamic random access memory DDR3SDRAM, double data Rate fourth generation synchronous dynamic random access memory DDR4SDRAM, thyristor random access memory TRAM, etc.; or it can be non-volatile memory, such as phase change random access memory PRAM, magnetic random access memory MRAM, resistive random access memory RRAM etc.

Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and spirit of the present disclosure. scope.

Claims

A layout of a word line driver, the word line driver includes driving NMOS, controlling PMOS and driving PMOS, including:

A plurality of word line drive layouts arranged along a first direction, where the first direction is the extension direction of the word lines;

Each of the word line driving layouts includes: a driving NMOS layout, a control PMOS layout and a driving PMOS layout arranged sequentially along a second direction, where the second direction is the arrangement direction of the word lines;

And in the first direction, the driving NMOS layouts in two adjacent word line driving layouts share a source layer or a drain layer, and the control PMOS layouts share a source layer or a drain layer. The driving PMOS layout shares a source layer or a drain layer;

Wherein, the gate layer in the driving NMOS layout and the gate layer in the control PMOS layout are connected through a gate connection layer.
The layout of the word line driver according to claim 1, wherein adjacent gate connection layers are arranged in a staggered manner.
The layout of the word line driver according to claim 1, wherein the gate layer in the driving NMOS layout, the gate layer in the control PMOS layout and the gate layer in the driving PMOS layout have an edge size. Larger than center size.
The word line driver layout according to claim 1, further comprising:

A first interconnection layer is provided on the top of the gate layer in the driving NMOS layout, the control PMOS layout and the driving PMOS layout, and is provided with a first connection pattern, the first connection pattern extending in the second direction, For interconnection between the terminals of the driving NMOS, the control PMOS and the driving PMOS;

A second interconnection layer is provided on top of the first interconnection layer and is provided with a second connection pattern. The second connection pattern extends in the first direction and is connected to the first connection pattern for Input/output control signals corresponding to the terminals of the driving NMOS, the controlling PMOS and the driving PMOS.
The layout of a word line driver according to claim 4, wherein the first connection pattern includes:

The output contact pattern extends along the second direction and is disposed on the top of the drain pattern in the driving NMOS layout, the top of the drain pattern in the control PMOS layout, and the top of the drain pattern in the driving PMOS layout. , used to connect the drain of the driving NMOS, the drain of the controlling PMOS and the drain of the driving PMOS;

A first contact pattern extends along the second direction and is disposed on the top of the source pattern in the driving NMOS layout for connecting the source of the driving NMOS;

A second contact pattern is provided in the gap between the driving NMOS layout and the control PMOS layout, and is used to connect the gate of the driving NMOS and the gate of the control PMOS;

A third contact pattern extends along the second direction and is provided on top of the source pattern in the driving PMOS layout and the control PMOS layout, for connecting the source of the control PMOS and the driving PMOS. source;

The fourth contact pattern is arranged on the top of the gate pattern in the driving PMOS layout and is used to connect the gate electrode of the driving PMOS.
The layout of the word line driver according to claim 5, wherein the second connection pattern includes:

An output transmission pattern is provided in the first direction and is used to connect the output contact pattern and a word line input pattern, and the word line input pattern is used to provide a driving signal to the connected word line;

A first transmission pattern, arranged on the top of the first contact pattern, is used to connect the first contact pattern and a first input pattern, and the first input pattern is used to receive the source control signal of the driving NMOS;

A second transmission pattern is provided on top of the second contact pattern and is used to connect the second contact pattern and a second input pattern. The second input pattern is used to receive the gate of the driving NMOS and the control PMOS. Extreme control signal;

A third transmission pattern is provided on top of the third contact pattern and is used to connect the third contact pattern and a third input pattern. The third input pattern is used to receive the source of the control PMOS and the driving PMOS. Extreme control signal;

The fourth transmission pattern is disposed on the top of the fourth contact pattern and is used to connect the fourth contact pattern and the fourth input pattern. The fourth input pattern is used to receive the gate control signal of the driving PMOS.
The word line driver layout according to claim 6, comprising:

In the first direction, the projections of the third transmission patterns corresponding to different word line driving layouts in the first direction overlap with each other;

The second connection pattern further includes: a third interconnection pattern arranged in the first direction for connecting all the third transmission patterns arranged in the first direction;

And at least one third input pattern is provided on the third interconnection pattern.
The layout of the word line driver according to claim 7, wherein two third input patterns are provided on the third interconnection pattern, and the third input pattern is provided in the first direction. Both sides of the third interconnect pattern.
The word line driver layout according to claim 7 or 8, wherein a plurality of third transmission patterns corresponding to the word line driver layout are provided in the second direction.
The word line driver layout according to claim 6, comprising:

In the first direction, the projections of the first transmission patterns corresponding to different word line driving layouts in the first direction partially overlap;

The second connection pattern also includes: a plurality of first interconnection patterns, spaced apart in the second direction and extending in the first direction, for connecting the overlapping projections in the first direction. all said first transmission graphics;

And at least one first input pattern is provided on each of the first interconnection patterns.
The word line driver layout according to claim 6, comprising:

In the first direction, the projections of the first transmission patterns corresponding to different word line driving layouts in the first direction completely overlap;

The second connection pattern further includes: a first interconnection pattern arranged in the first direction for connecting all the first transmission patterns arranged in the first direction;

And at least one first input pattern is provided on the first interconnection pattern.
The layout of a word line driver according to claim 11, wherein two first input patterns are provided on the first interconnection pattern, and the first input patterns are provided in the first direction. both sides of the first interconnect pattern.
The word line driver layout according to claim 6, comprising:

In the first direction, the second transmission pattern connects a plurality of second contact patterns;

In the second direction, a plurality of the second transmission patterns are arranged at intervals, and adjacent second transmission patterns project at different positions in the second direction.
The layout of a word line driver according to claim 13, wherein a plurality of second transmission patterns are provided in the first direction, and projections of the plurality of second transmission patterns overlap with each other.
The layout of the word line driver according to claim 13 or 14, wherein at least one second input pattern is provided on the second transmission pattern, and the projection of all the second input patterns in the second direction The locations are different from each other.
The layout of the word line driver according to claim 15, comprising:

The projections of the second contact patterns corresponding to the word line driving layouts that are adjacent in the first direction in the second direction coincide with each other;

The overlapping second contact patterns correspond to the connected second transmission patterns, and the projections in the second direction overlap with each other.
A memory in which a word line driver performs layout layout based on the layout of the word line driver according to any one of claims 1 to 15.