CN111755048A - Lower word line driving read auxiliary circuit and layout design - Google Patents
Lower word line driving read auxiliary circuit and layout design Download PDFInfo
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- CN111755048A CN111755048A CN202010577071.3A CN202010577071A CN111755048A CN 111755048 A CN111755048 A CN 111755048A CN 202010577071 A CN202010577071 A CN 202010577071A CN 111755048 A CN111755048 A CN 111755048A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
Abstract
The invention discloses a lower word line driving and reading auxiliary circuit and layout design, which are used for pulling down the voltage of a word line selected by a memory. By sharing one word line voltage division submodule by two word lines, the function of driving the read auxiliary circuit by the lower word line can be realized, and meanwhile, the number of devices is saved, the layout area is saved, and the layout wiring is simplified.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a lower word line driving read auxiliary circuit and layout design.
Background
The Memory is divided into a Flash Memory (Flash), a Dynamic Random Access Memory (DRAM), and a Static Random Access Memory (SRAM), wherein the SRAM is the first choice for a critical system Memory module, such as a cache between a CPU and a main Memory, because the SRAM can be quickly read and written without periodic refreshing. At present, a memory cell of a commonly used static random access memory mainly adopts a six-transistor type, and is composed of a transmission transistor and a pull-down transistor, wherein a gate and a source of the transmission transistor are respectively and electrically connected to a word line and a bit line, so that the on/off of the transmission transistor is controlled by the word line, and stored data is written in or read out by the bit line. For a 6-transistor memory cell of a static random access memory, when the memory cell is read, the current capacities of a pass transistor and a pull-down transistor of the memory cell are unbalanced (the current capacity of the pull-down transistor is obviously weaker than that of the pass transistor) due to process deviation, so that data stored in an internal node of the memory cell is subjected to read upset during a read operation or a pseudo read operation. In the industry, the read flip is solved by increasing a Word Line Under Drive (WLUD) read assist circuit to lower the voltage when the Word Line is turned on.
As shown in fig. 1, a lower word line driving read assist circuit structure disclosed in the prior art performs word line voltage division by adding a grounded PMOS transistor (PMOS), and controls a gate of the PMOS transistor by using read assist enable signals RA _0 and RA _1 to realize a function of pulling down a word line voltage. The defect is that, referring to fig. 2, as the storage capacity of the memory increases, the total number of word lines in the memory also increases, if each word line needs to drive the read auxiliary circuit by the lower word line, the number of PMOS transistors needed is large, and the layout size is large; in addition, since the PMOS substrate and the source electrode have different potentials, the power tap and the source electrode trace cannot be shared, and the layout size and the wiring complexity are increased.
Therefore, a solution that can reduce the number of devices, save layout area, and simplify layout wiring is needed.
Disclosure of Invention
The invention aims to provide a lower word line driving read auxiliary circuit and a layout design, which are used for solving the problems of numerous devices, large layout size and complex wiring in the prior art.
In order to solve the above technical problem, the present invention provides a lower word line driving read assist circuit for pulling down a voltage of a word line selected by a memory, the lower word line driving read assist circuit including:
a word line drive control submodule configured to generate a corresponding word line signal based on a word line of the memory;
a word line voltage divider submodule configured to pull down a voltage of a first word line signal;
the first word line signal is a word line signal corresponding to a word line selected by the memory, the number of the word line signals is the same as that of the word lines, at least one word line voltage division submodule is connected between every two word lines, and the on-off of each word line voltage division submodule is controlled by a first control signal.
Optionally, the word line voltage divider sub-module includes:
the first group of voltage division transistors and the second group of voltage division transistors are respectively provided with a voltage division input end, a voltage division output end and a voltage division control end;
the voltage division input end of the first group of voltage division transistors is connected with one word line;
the voltage division input end of the second group of voltage division transistors is connected with the other word line;
the voltage division output end of the first group of voltage division transistors is connected with the output end of the second group of voltage division transistors;
the voltage division control ends of the first group of voltage division transistors and the second group of voltage division transistors are connected with the first control signal;
the first control signal is used for controlling the first group of voltage division transistors and the second group of voltage division transistors to be turned on and off.
Optionally, the first group of voltage division transistors includes a first PMOS transistor, and the second group of voltage division transistors includes a second PMOS transistor;
the source electrode of the first PMOS tube is connected with one word line;
the source electrode of the second PMOS tube is connected with the other word line;
the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube;
and the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are both connected with the first control signal.
Optionally, the first group of voltage division transistors includes two first PMOS transistors, and the second group of voltage division transistors includes two second PMOS transistors;
the two first PMOS tubes are connected in series, and the source electrode of one first PMOS tube is connected with one word line;
the two second PMOS tubes are connected in series, and the source electrode of one second PMOS tube is connected with the other word line;
the drain electrode of the other first PMOS tube is connected with the drain electrode of the other second PMOS tube;
the grid electrodes of the two first PMOS tubes and the grid electrodes of the two second PMOS tubes are connected with the first control signal.
Optionally, the first group of voltage division transistors includes a plurality of first PMOS transistors, and the second group of voltage division transistors includes a plurality of second PMOS transistors;
the plurality of first PMOS tubes are connected in series to form a first series circuit, and the source electrode of one first PMOS tube at one end of the first series circuit is connected with one word line;
the plurality of second PMOS tubes are connected in series to form a second series circuit, and the source electrode of one second PMOS tube positioned at one end of the second series circuit is connected with the other word line;
the drain electrode of one first PMOS tube positioned at the other end of the first series circuit is connected with the drain electrode of one second PMOS tube positioned at the other end of the second series circuit;
the grid electrodes of the first PMOS tubes and the grid electrodes of the second PMOS tubes are connected with the first control signal.
Optionally, the first group of voltage division transistors includes a first NMOS transistor, and the second group of voltage division transistors includes a second NMOS transistor;
the drain electrode of the first NMOS tube is connected with one word line;
the drain electrode of the second NMOS tube is connected with the other word line;
the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube;
and the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube are both connected with the first control signal.
Optionally, the first group of voltage division transistors includes two first NMOS transistors, and the second group of voltage division transistors includes two second NMOS transistors;
the two first NMOS tubes are connected in series, and the drain electrode of one first NMOS tube is connected with one word line;
the two second NMOS tubes are connected in series, and the drain electrode of one second NMOS tube is connected with the other word line;
the source electrode of the other first NMOS transistor is connected with the source electrode of the other second NMOS transistor;
the grid electrodes of the two first NMOS tubes and the grid electrodes of the two second NMOS tubes are connected with the first control signal.
Optionally, the first group of voltage division transistors includes a plurality of first NMOS transistors, and the second group of voltage division transistors includes a plurality of second NMOS transistors;
the plurality of first NMOS tubes are connected in series to form a third series circuit, and the drain electrode of one first NMOS tube positioned at one end of the third series circuit is connected with one word line;
the plurality of second NMOS tubes are connected in series to form a fourth series circuit, and the drain electrode of one second NMOS tube at one end of the fourth series circuit is connected with the other word line;
the source electrode of one first NMOS tube positioned at the other end of the first series circuit is connected with the source electrode of one second NMOS tube positioned at the other end of the second series circuit;
the grid electrodes of the first NMOS tubes and the grid electrodes of the second NMOS tubes are connected with the first control signal.
Optionally, the word line drive control sub-module comprises a decoder.
Optionally, at least two word line voltage division submodules are connected between every two word lines, and the at least two sub-line voltage division submodules are connected in parallel.
Based on the same inventive concept, the invention also provides a layout design of the lower word line driving reading auxiliary circuit, and the lower word line driving reading auxiliary circuit is driven by any one of the characteristic descriptions.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention provides a lower word line driving and reading auxiliary circuit which is used for reducing the voltage of a word line selected by a memory, and comprises a word line driving control submodule and a word line voltage division submodule, wherein at least one word line voltage division submodule is connected between every two word lines, and the on-off of each word line voltage division submodule is controlled by a first control signal. Compared with the prior art of the lower word line driving read-assist circuit, the technical scheme provided by the invention utilizes the principle that only one word line in a storage array is effective (high level) and the potentials of other word lines are low when the read-write operation is carried out on a storage unit of a certain memory, and the function of pulling down the corresponding word line is realized by directly connecting the two ends of the word line voltage division submodule to the two word lines in a crossing manner, so that the design that each word line needs the ground potential is omitted. By sharing one word line voltage division submodule by two word lines, the function of driving the read auxiliary circuit by the lower word line can be realized, and meanwhile, the number of devices is saved, the layout area is saved, and the layout wiring is simplified.
2. By adjusting the number of the word line voltage division submodule and/or the first group of voltage division transistors and the second group of voltage division transistors, the requirement of the lower word line driving reading auxiliary circuit with more gears is met, and the universality of the lower word line driving reading auxiliary circuit provided by the invention can be improved.
The invention also provides a layout design of the lower word line driving reading auxiliary circuit, which belongs to the same inventive concept with the lower word line driving reading auxiliary circuit, so that the lower word line driving reading auxiliary circuit has the same beneficial effects.
Drawings
FIG. 1 is a schematic diagram of a lower word line driving read assist circuit according to the prior art;
fig. 2 is a schematic diagram of a design structure of a layout of a lower word line driving read assist circuit provided in the prior art;
FIG. 3 is a schematic diagram of a lower word line driving read assist circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a lower word line driving read assist circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a lower word line driving read assist circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a layout design structure implemented by using the lower word line driving read assist circuit provided in the embodiment of the present invention;
FIG. 7 is a waveform diagram of a simulation implemented by the lower word line driving read assist circuit according to an embodiment of the present invention.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Referring to fig. 3 to 7, the present invention provides a lower word line driving read assist circuit for pulling down a voltage of a selected word line of a memory, the lower word line driving read assist circuit comprising:
a word line drive control submodule configured to generate a corresponding word line signal based on a word line of the memory;
a word line voltage divider submodule configured to pull down a voltage of a first word line signal;
the first word line signal is a word line signal corresponding to a word line selected by the memory, the number of the word line signals is the same as that of the word lines, at least one word line voltage division submodule is connected between every two word lines, and the on-off of each word line voltage division submodule is controlled by a first control signal.
The invention provides a lower word line driving and reading auxiliary circuit which is used for reducing the voltage of a word line selected by a memory, and comprises a word line driving control submodule and a word line voltage division submodule, wherein at least one word line voltage division submodule is connected between every two word lines, and the on-off of each word line voltage division submodule is controlled by a first control signal. Compared with the prior art of the lower word line driving read-assist circuit, the technical scheme provided by the invention utilizes the principle that only one word line in a storage array is effective (high level) and the potentials of other word lines are low when the read-write operation is carried out on a storage unit of a certain memory, and the function of pulling down the corresponding word line is realized by directly connecting the two ends of the word line voltage division submodule to the two word lines in a crossing manner, so that the design that each word line needs the ground potential is omitted. By sharing one word line voltage division submodule by two word lines, the function of driving the read auxiliary circuit by the lower word line can be realized, and meanwhile, the number of devices is saved, the layout area is saved, and the layout wiring is simplified.
Preferably, the word line voltage divider sub-module includes: the first group of voltage division transistors and the second group of voltage division transistors are provided with voltage division input ends, voltage division output ends and voltage division control ends. The voltage division input end of the first group of voltage division transistors is connected with one word line, and the voltage division input end of the second group of voltage division transistors is connected with the other word line. The voltage division output end of the first group of voltage division transistors is connected with the output end of the second group of voltage division transistors, and the voltage division control end of the first group of voltage division transistors and the voltage division control end of the second group of voltage division transistors are connected with the first control signal. The first control signal is used for controlling the first group of voltage division transistors and the second group of voltage division transistors to be turned on and off.
It can be understood that, in the embodiment of the present invention, the word line voltage division submodule is formed by using a transistor, and mainly utilizes the characteristic that the transistor has a characteristic of controlling on and off according to the control terminal, and since the transistor has an on resistance after being turned on, the transistor is equivalent to a circuit with a resistance value which can be changed by the control terminal, and further has a voltage division function. In other embodiments of the present invention, the result with similar characteristics may also be used to implement the word line voltage-dividing sub-module, for example, a variable resistor or a capacitor may also be used, and many other types of electronic devices may also be used to implement the function of the word line voltage-dividing sub-module, which is not described herein. When the lower word line driving read-assist circuit provided by the invention is applied to a memory, the transistor is selected to ensure that the volume of the circuit is small enough to meet the requirement of the memory. Therefore, the word line voltage division submodule can be preferably implemented by selecting a transistor. For convenience of explanation, the technical solution of the present invention will be described below by taking transistors as an example.
Specifically, the word line driving control sub-module includes, but is not limited to, a decoder. Referring to fig. 3, a wordline driver control sub-module (Controller) composed of digital logic circuits such as a decoder, etc. includes a selection Signal (SEL) and a clock signal (CLK), and further includes inverters, nand gates, nor gates, transmission gates, etc. for generating a wordline signal (WL).
Furthermore, at least two word line voltage division submodules are connected between every two word lines, and the at least two sub-line voltage division submodules are connected in parallel. Referring to fig. 3, in the embodiment of the present invention, two word line voltage dividing sub-modules are connected between every two word lines, and it should be understood that in other embodiments of the present invention, three or four or more word line voltage dividing sub-modules may be connected between every two word lines, which may be specifically selected according to actual needs and is not limited herein. By adjusting the number of the word line voltage division submodules, the requirements of lower word line driving reading auxiliary circuits with more gears are met, and the universality of the lower word line driving reading auxiliary circuit provided by the invention can be improved. In addition, as can be seen from fig. 3 to 5, in the embodiment of the present invention, the word line voltage dividing submodule is respectively connected to two adjacent word lines, such as WL _2n and WL _2n +1 in fig. 3 to 5, where n is a positive integer starting from 0, and the size of n is related to the capacity of the memory. It should be understood that such a connection is merely for convenience of illustrating the technical solutions of the present invention, and should not be construed as limiting the present application in any way. In other embodiments of the present invention, the word line voltage divider sub-module may further connect two word lines that are not adjacent to each other, for example, WL _0 and WL _3, which is not limited herein.
Further, the first group of voltage division transistors comprises a first PMOS transistor, and the second group of voltage division transistors comprises a second PMOS transistor. The source electrode of the first PMOS tube is connected with one word line, the source electrode of the second PMOS tube is connected with the other word line, the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, and the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are both connected with the first control signal.
Referring to fig. 4, when the first group of voltage division transistors includes only one first PMOS transistor and the second group of voltage division transistors includes only one second PMOS transistor, the source of the first PMOS transistor is connected to WL _2n and the source of the second PMOS transistor is connected to WL _2n + 1. If the content of the word line corresponding to WL _2n in the memory needs to be read, where WL _2n is high level and WL _2n +1 is low level, the first control signal, i.e. RA _0 in fig. 4, may be set to low level, and the first PMOS transistor and the second PMOS transistor are in a conducting state, because the first PMOS transistor has an on-resistance in the conducting state, a voltage division effect may be performed on WL _2n, and WL _2n +1 at this time is equivalent to the ground potential of the first PMOS transistor. Similarly, if the content of the word line corresponding to WL _2n +1 in the memory needs to be read, WL _2n +1 is at a high level and WL _2n is at a low level, the first control signal, i.e. RA _0 in fig. 4, may be set to be at a low level, the first PMOS transistor and the second PMOS transistor are in a conducting state, and since the second PMOS transistor has an on-resistance in the conducting state, the voltage division function may be performed on WL _2n +1, and WL _2n at this time is equivalent to the ground potential of the second PMOS transistor. Through the analysis, the technical scheme provided by the invention can enable two adjacent word lines to share one sub-line voltage division submodule and mutually become mutual ground potentials under the control of the first control signal, so that the function of driving the read auxiliary circuit by the word lines can be realized under the condition of greatly saving the number of the PMOSs and not additionally using a grounding power line, and the layout size and the wiring can be simplified.
Furthermore, the first group of voltage division transistors comprises two first PMOS tubes, and the second group of voltage division transistors comprises two second PMOS tubes. The two first PMOS tubes are connected in series, and the source electrode of one first PMOS tube is connected with one word line. The two second PMOS tubes are connected in series, and the source electrode of one second PMOS tube is connected with the other word line. The drain electrode of the other first PMOS tube is connected with the drain electrode of the other second PMOS tube, and the grid electrodes of the two first PMOS tubes and the grid electrodes of the two second PMOS tubes are connected with the first control signal.
Also taking the connection between WL _2n and WL _2n +1 as an example, when two first PMOS transistors are included in the first group of voltage-dividing transistors and two second PMOS transistors are included in the second group of voltage-dividing transistors, the source of one first PMOS transistor is connected to WL _2n, and the source of one second PMOS transistor is connected to WL _2n + 1. The two first PMOS tubes and the two second PMOS tubes are connected in series, namely the drain electrode of one PMOS tube is connected with the source electrode of the other PMOS tube. If the content of the word line corresponding to WL _2n in the memory needs to be read, where WL _2n is a high level and WL _2n +1 is a low level, the first control signal may be set to a low level, and both the first PMOS transistors and the two second PMOS transistors are in a conducting state, since there is an on-resistance in the conducting state of the two first PMOS transistors, a voltage division effect may be performed on WL _2n, and WL _2n +1 at this time is equivalent to the ground potential of the two first PMOS transistors. Similarly, if the content of the word line corresponding to WL _2n +1 in the memory needs to be read, at this time, WL _2n +1 is high level, WL _2n is low level, the first control signal may be set to low level, and both the first PMOS transistor and the second PMOS transistor are in a conducting state, because there is an on-resistance in the conducting state of the two second PMOS transistors, a voltage division effect may be performed on WL _2n +1, and WL _2n at this time is equivalent to the ground potential of the two second PMOS transistors.
Furthermore, the first group of voltage division transistors comprises a plurality of first PMOS tubes, and the second group of voltage division transistors comprises a plurality of second PMOS tubes. The plurality of first PMOS tubes are connected in series to form a first series circuit, and the source electrode of one first PMOS tube at one end of the first series circuit is connected with one word line. The plurality of second PMOS tubes are connected in series to form a second series circuit, and the source electrode of one second PMOS tube at one end of the second series circuit is connected with the other word line. And the drain electrode of one first PMOS tube positioned at the other end of the first series circuit is connected with the drain electrode of one second PMOS tube positioned at the other end of the second series circuit. The grid electrodes of the first PMOS tubes and the grid electrodes of the second PMOS tubes are connected with the first control signal. It should be noted that the number of the first PMOS transistors and the second PMOS transistors may be three, four, or even more, and is not limited herein, and may be selected according to actual needs.
Also taking the connection between WL _2n and WL _2n +1 as an example, when a plurality of the first PMOS transistors are included in the first group of voltage-dividing transistors and a plurality of the second PMOS transistors are included in the second group of voltage-dividing transistors, the source of one of the first PMOS transistors is connected to WL _2n, and the source of one of the second PMOS transistors is connected to WL _2n + 1. The plurality of first PMOS tubes and the plurality of second PMOS tubes are connected in series, namely the drain electrode of one PMOS tube in two adjacent PMOS tubes is connected with the source electrode of the other PMOS tube. If the content of the word line corresponding to WL _2n in the memory needs to be read, where WL _2n is high level and WL _2n +1 is low level, the first control signal may be set to low level, and the plurality of first PMOS transistors and the plurality of second PMOS transistors are all in a conducting state, and since the plurality of first PMOS transistors have on-resistance in the conducting state, a voltage division effect may be performed on WL _2n, and WL _2n +1 at this time is equivalent to the ground potential of the plurality of first PMOS transistors. Similarly, if the content of the word line corresponding to WL _2n +1 in the memory needs to be read, WL _2n +1 is at a high level and WL _2n is at a low level, the first control signal may be set to be at the low level, the plurality of first PMOS transistors and the plurality of second PMOS transistors are all in a conducting state, since the plurality of second PMOS transistors have an on-resistance in the conducting state, a voltage division effect can be performed on WL _2n +1, and WL _2n at this time is equivalent to the ground potential of the plurality of second PMOS transistors.
Further, referring to fig. 5, the first group of voltage-dividing transistors and the second group of voltage-dividing transistors may be other types of transistors besides PMOS transistors, for example, the first group of voltage-dividing transistors includes a first NMOS transistor, and the second group of voltage-dividing transistors includes a second NMOS transistor. The drain electrode of the first NMOS tube is connected with one word line, the drain electrode of the second NMOS tube is connected with the other word line, the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, and the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube are both connected with the first control signal.
Referring to fig. 5, when the first group of voltage division transistors includes only one first NMOS transistor and the second group of voltage division transistors includes only one second NMOS transistor, the drain of the first NMOS transistor is connected to WL _2n and the drain of the second NMOS transistor is connected to WL _2n + 1. If the content of the word line corresponding to WL _2n in the memory needs to be read, where WL _2n is high level and WL _2n +1 is low level, the first control signal, i.e. RA _0 in fig. 4, may be set to high level, and the first NMOS transistor and the second NMOS transistor are in a conducting state, because the first NMOS transistor has an on-resistance in the conducting state, a voltage division effect may be performed on WL _2n, and WL _2n +1 at this time is equivalent to the ground potential of the first NMOS transistor. Similarly, if the content of the word line corresponding to WL _2n +1 in the memory needs to be read, WL _2n +1 is at a high level and WL _2n is at a low level, the first control signal, i.e. RA _0 in fig. 4, may be set to be at a high level, the first NMOS transistor and the second NMOS transistor are in a conducting state, and since the second NMOS transistor has an on-resistance in the conducting state, the voltage division function may be performed on WL _2n +1, and WL _2n at this time is equivalent to the ground potential of the second NMOS transistor. Through the analysis, the technical scheme provided by the invention can enable two adjacent word lines to share one sub-line voltage division submodule and mutually become mutual ground potentials under the control of the first control signal, so that the function of driving the read auxiliary circuit by the lower word line can be realized under the condition of greatly saving the number of the NMOS and not additionally using a grounding power line, and the layout size and the wiring can be simplified.
Further, the first group of voltage division transistors comprises two first NMOS transistors, and the second group of voltage division transistors comprises two second NMOS transistors. The two first NMOS tubes are connected in series, and the drain electrode of one first NMOS tube is connected with one word line. The two second NMOS tubes are connected in series, and the drain electrode of one second NMOS tube is connected with the other word line. The source electrode of the other first NMOS tube is connected with the source electrode of the other second NMOS tube, and the grid electrodes of the two first NMOS tubes and the grid electrodes of the two second NMOS tubes are connected with the first control signal.
Also taking the connection between WL _2n and WL _2n +1 as an example, when two first NMOS transistors are included in the first group of voltage-dividing transistors and two second NMOS transistors are included in the second group of voltage-dividing transistors, the drain of one first NMOS transistor is connected to WL _2n, and the drain of one second NMOS transistor is connected to WL _2n + 1. The two first NMOS tubes and the two second NMOS tubes are connected in series, namely the drain electrode of one NMOS tube is connected with the source electrode of the other NMOS tube. If the content of the word line corresponding to WL _2n in the memory needs to be read, where WL _2n is a high level and WL _2n +1 is a low level, the first control signal may be set to a high level, and the two first NMOS transistors and the two second NMOS transistors are in a conducting state, because the first NMOS transistor has an on-resistance in the conducting state, a voltage division effect may be performed on WL _2n, and WL _2n +1 at this time is equivalent to the ground potential of the two first NMOS transistors. Similarly, if the content of the word line corresponding to WL _2n +1 in the memory needs to be read, at this time, WL _2n +1 is high level, WL _2n is low level, the first control signal may be set to high level, the two first NMOS transistors and the two second NMOS transistors are in a conducting state, since there is an on-resistance in the conducting state of the two second NMOS transistors, a voltage division effect may be performed on WL _2n +1, and WL _2n at this time is equivalent to the ground potential of the two second NMOS transistors.
Furthermore, the first group of voltage division transistors comprises a plurality of first NMOS transistors, and the second group of voltage division transistors comprises a plurality of second NMOS transistors. The plurality of first NMOS tubes are connected in series to form a third series circuit, and the drain electrode of one first NMOS tube at one end of the third series circuit is connected with one word line. The plurality of second NMOS tubes are connected in series to form a fourth series circuit, and the drain electrode of one second NMOS tube at one end of the fourth series circuit is connected with the other word line. The source electrode of one first NMOS tube positioned at the other end of the first series circuit is connected with the source electrode of one second NMOS tube positioned at the other end of the second series circuit. The grid electrodes of the first NMOS tubes and the grid electrodes of the second NMOS tubes are connected with the first control signal. It should be noted that the number of the first NMOS transistors and the second NMOS transistors may be three, four, or even more, which is not limited herein and may be selected according to actual needs.
Also taking the connection between WL _2n and WL _2n +1 as an example, when the first group of voltage division transistors includes a plurality of the first NMOS transistors and the second group of voltage division transistors includes a plurality of the second NMOS transistors, the drain of one of the first NMOS transistors is connected to WL _2n, and the drain of one of the second NMOS transistors is connected to WL _2n + 1. The plurality of first NMOS tubes and the plurality of second NMOS tubes are connected in series, namely the drain electrode of one NMOS tube in two adjacent PMOS tubes is connected with the source electrode of the other NMOS tube. If the content of the word line corresponding to WL _2n in the memory needs to be read, where WL _2n is a high level and WL _2n +1 is a low level, the first control signal may be set to a high level, and the plurality of first NMOS transistors and the plurality of second NMOS transistors are in a conducting state, and since the plurality of first NMOS transistors have an on-resistance in the conducting state, a voltage division function may be performed on WL _2n, where WL _2n +1 is equivalent to a ground potential of the plurality of first NMOS transistors. Similarly, if the content of the word line corresponding to WL _2n +1 in the memory needs to be read, WL _2n +1 is at a high level and WL _2n is at a low level, the first control signal may be set to be at the high level, the plurality of first NMOS transistors and the plurality of second NMOS transistors are in a conducting state, and since the plurality of second NMOS transistors have an on-resistance in the conducting state, the voltage division function may be performed on WL _2n +1, and WL _2n at this time is equivalent to the ground potential of the plurality of second NMOS transistors.
In order to facilitate understanding of the technical solution of the present invention, several more specific embodiments are provided as follows:
referring to fig. 3, a lower word line driving read assist circuit according to an embodiment of the present invention includes: a word line driving control submodule (Controller) composed of a decoder and other digital logic circuits contains a selection Signal (SEL) and a clock signal (CLK), includes a plurality of inverters, NAND gates, NOR gates, transmission gates and the like, and is used for generating a word line signal (WL). And a plurality of groups of word line voltage division submodules (Under Drive) comprising a plurality of gear word line voltage division transistors, wherein the gear of the voltage division can be selected by adjusting the grid control signals (RA _0, RA _1) of the word line voltage division transistors, and the gear word line voltage division submodules are used for pulling down the potential of the appointed word line. If the total number of rows of the word lines is 2n (n is a natural number), n groups are required for the word line voltage-dividing sub-module, and two adjacent word lines can share one group of word line voltage-dividing sub-module. The connection method comprises the following steps: the word line voltage division submodule (Under Drive _0) containing the first control signal (RA _0) and the word line voltage division submodule (Under Drive _1) containing the first control signal (RA _1) have voltage division input ends and voltage division output ends which are connected to two adjacent word lines WL _2n and WL _2n + 1.
Referring to fig. 4, an application example of the word line voltage divider sub-module using PMOS transistors is shown. The source of the PMOS transistor PM _1 is connected to the lower word line (WL _2n) in the adjacent word line, the drain of the PMOS transistor PM _1 is connected to the drain of the PMOS transistor PM _2, and the source of the PMOS transistor PM _2 is connected to the upper word line (WL _2n +1) in the adjacent word line. The gates of the PMOS transistors PM _1 and PM _2 are connected to the first control signal (RA _ 0). The source of the PMOS transistor PM _3 is connected with the high-order word line (WL _2n +1) in the adjacent word line, the drain of the PMOS transistor PM _3 is connected with the drain of the PMOS transistor PM _4, and the source of the PMOS transistor PM _4 is connected with the low-order word line (WL _2n) in the adjacent word line. The gates of the PMOS transistors PM _3 and PM _4 are connected to the first control signal (RA _ 1). In practical application, the number of the PMOS tubes can be continuously increased according to circuit requirements so as to pull down the specified word line voltage to a greater extent.
Referring to fig. 5, an example of an application in which an NMOS transistor is selected for the word line voltage divider sub-module is shown. The drain of the NMOS transistor NM _1 is connected to a lower word line (WL _2n) of adjacent word lines, the source of the NMOS transistor NM _1 is connected to the source of the NMOS transistor NM _2, and the drain of the NMOS transistor NM _2 is connected to a higher word line (WL _2n +1) of the adjacent word lines. The gates of the NMOS transistor NM _1 and NM _2 are connected to a first control signal RA _ 0. The drain of the NMOS transistor NM _3 is connected to a higher word line (WL _2n +1) of the adjacent word lines, the source of the NMOS transistor NM _3 is connected to the source of the NMOS transistor NM _4, and the drain of the NMOS transistor NM _4 is connected to a lower word line (WL _2n) of the adjacent word lines. The gates of the NMOS transistor NM _3 and NM _4 are connected to the first control signal RA _ 1. In practical application, the number of the NMOS transistors can be continuously increased according to circuit requirements so as to pull down the specified word line voltage to a greater extent.
Referring to FIG. 6, assuming that an SRAM memory ARRAY (ARRAY) has 512 rows, the SRAM word lines are also 512. The implementation is performed by using an application example as shown in fig. 4, and the word line voltage division submodule Under Drive _0/1 is composed of two PMOS transistors. And the word line voltage division submodule is connected to two adjacent word lines in a cross mode, and when one word line is selected, the other word line is required to be at a low voltage. Taking a basic block including only two adjacent word lines (WL _0, WL _1) as an example, when the lower word line driving read assist circuit structure composed of PMOS transistors as shown in fig. 4 is used, the layout thereof is shown in fig. 6. When WL _0 is selected, WL _0 is high, and its adjacent WL _1 is in the low state not selected, and at this time, one end of the lower word line driving read auxiliary circuit for pulling down WL _0 voltage is connected to WL _1, similar to the design of ground potential; similarly, when WL _1 is selected, WL _1 is active and its adjacent WL _0 is low, the previous lower word line driving read assist circuit for pulling down the active WL _0 voltage may be used to pull down the active WL _1 voltage in reverse, and WL _0 is equivalent to the ground voltage. Simulation waveform diagram as shown in fig. 7, when only the first control signal (RA _0) is active, WL _0 is pulled down from 1.05V to 0.95V; when both first control signals RA _0, RA _1 are active, WL _0 is pulled low from 1.05V to 0.893V. Therefore, the function of the lower word line driving read-assist circuit is realized, and gear adjustment of the lower word line driving read-assist circuit is realized by controlling RA _0 and RA _ 1.
Based on the same inventive concept, the embodiment of the invention also provides a layout design of the lower word line driving reading auxiliary circuit, and the lower word line driving reading auxiliary circuit is driven by using any one of the above characteristic descriptions.
Based on the same inventive concept, the embodiment of the present invention further provides a memory chip, wherein the read assist circuit is driven by using any one of the lower word lines described in the above feature description.
In conclusion, the invention has the following beneficial effects:
1. the invention provides a lower word line driving and reading auxiliary circuit which is used for reducing the voltage of a word line selected by a memory, and comprises a word line driving control submodule and a word line voltage division submodule, wherein at least one word line voltage division submodule is connected between every two word lines, and the on-off of each word line voltage division submodule is controlled by a first control signal. Compared with the prior art of the lower word line driving read-assist circuit, the technical scheme provided by the invention utilizes the principle that only one word line in a storage array is effective (high level) and the potentials of other word lines are low when the read-write operation is carried out on a storage unit of a certain memory, and the function of pulling down the corresponding word line is realized by directly connecting the two ends of the word line voltage division submodule to the two word lines in a crossing manner, so that the design that each word line needs the ground potential is omitted. By sharing one word line voltage division submodule by two word lines, the function of driving the read auxiliary circuit by the lower word line can be realized, and meanwhile, the number of devices is saved, the layout area is saved, and the layout wiring is simplified.
2. By adjusting the number of the word line voltage division submodule and/or the first group of voltage division transistors and the second group of voltage division transistors, the requirement of the lower word line driving reading auxiliary circuit with more gears is met, and the universality of the lower word line driving reading auxiliary circuit provided by the invention can be improved.
The invention also provides a layout design of the lower word line driving reading auxiliary circuit, which belongs to the same inventive concept with the lower word line driving reading auxiliary circuit, so that the lower word line driving reading auxiliary circuit has the same beneficial effects.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example" or "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. And the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (11)
1. A lower wordline driver read assist circuit for pulling a voltage of a selected wordline of a memory down, the lower wordline driver read assist circuit comprising:
a word line drive control submodule configured to generate a corresponding word line signal based on a word line of the memory;
a word line voltage divider submodule configured to pull down a voltage of a first word line signal;
the first word line signal is a word line signal corresponding to a word line selected by the memory, the number of the word line signals is the same as that of the word lines, at least one word line voltage division submodule is connected between every two word lines, and the on-off of each word line voltage division submodule is controlled by a first control signal.
2. The lower wordline driver read assist circuit of claim 1, wherein the wordline voltage divider submodule includes:
the first group of voltage division transistors and the second group of voltage division transistors are respectively provided with a voltage division input end, a voltage division output end and a voltage division control end;
the voltage division input end of the first group of voltage division transistors is connected with one word line;
the voltage division input end of the second group of voltage division transistors is connected with the other word line;
the voltage division output end of the first group of voltage division transistors is connected with the output end of the second group of voltage division transistors;
the voltage division control ends of the first group of voltage division transistors and the second group of voltage division transistors are connected with the first control signal;
the first control signal is used for controlling the first group of voltage division transistors and the second group of voltage division transistors to be turned on and off.
3. The lower wordline driver read assist circuit of claim 2, wherein the first set of voltage divider transistors includes a first PMOS transistor and the second set of voltage divider transistors includes a second PMOS transistor;
the source electrode of the first PMOS tube is connected with one word line;
the source electrode of the second PMOS tube is connected with the other word line;
the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube;
and the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are both connected with the first control signal.
4. The lower word line driving read assist circuit of claim 2 wherein the first set of voltage divider transistors comprises two first PMOS transistors and the second set of voltage divider transistors comprises two second PMOS transistors;
the two first PMOS tubes are connected in series, and the source electrode of one first PMOS tube is connected with one word line;
the two second PMOS tubes are connected in series, and the source electrode of one second PMOS tube is connected with the other word line;
the drain electrode of the other first PMOS tube is connected with the drain electrode of the other second PMOS tube;
the grid electrodes of the two first PMOS tubes and the grid electrodes of the two second PMOS tubes are connected with the first control signal.
5. The lower word line driving read assist circuit of claim 2 wherein the first set of voltage divider transistors comprises a plurality of first PMOS transistors and the second set of voltage divider transistors comprises a plurality of second PMOS transistors;
the plurality of first PMOS tubes are connected in series to form a first series circuit, and the source electrode of one first PMOS tube at one end of the first series circuit is connected with one word line;
the plurality of second PMOS tubes are connected in series to form a second series circuit, and the source electrode of one second PMOS tube positioned at one end of the second series circuit is connected with the other word line;
the drain electrode of one first PMOS tube positioned at the other end of the first series circuit is connected with the drain electrode of one second PMOS tube positioned at the other end of the second series circuit;
the grid electrodes of the first PMOS tubes and the grid electrodes of the second PMOS tubes are connected with the first control signal.
6. The lower wordline driver read assist circuit of claim 2, wherein the first set of voltage divider transistors includes a first NMOS transistor and the second set of voltage divider transistors includes a second NMOS transistor;
the drain electrode of the first NMOS tube is connected with one word line;
the drain electrode of the second NMOS tube is connected with the other word line;
the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube;
and the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube are both connected with the first control signal.
7. The lower wordline driver read assist circuit of claim 2, wherein the first set of voltage divider transistors includes two first NMOS transistors and the second set of voltage divider transistors includes two second NMOS transistors;
the two first NMOS tubes are connected in series, and the drain electrode of one first NMOS tube is connected with one word line;
the two second NMOS tubes are connected in series, and the drain electrode of one second NMOS tube is connected with the other word line;
the source electrode of the other first NMOS transistor is connected with the source electrode of the other second NMOS transistor;
the grid electrodes of the two first NMOS tubes and the grid electrodes of the two second NMOS tubes are connected with the first control signal.
8. The lower wordline driver read assist circuit of claim 2, wherein the first set of voltage divider transistors includes a first plurality of NMOS transistors and the second set of voltage divider transistors includes a second plurality of NMOS transistors;
the plurality of first NMOS tubes are connected in series to form a third series circuit, and the drain electrode of one first NMOS tube positioned at one end of the third series circuit is connected with one word line;
the plurality of second NMOS tubes are connected in series to form a fourth series circuit, and the drain electrode of one second NMOS tube at one end of the fourth series circuit is connected with the other word line;
the source electrode of one first NMOS tube positioned at the other end of the first series circuit is connected with the source electrode of one second NMOS tube positioned at the other end of the second series circuit;
the grid electrodes of the first NMOS tubes and the grid electrodes of the second NMOS tubes are connected with the first control signal.
9. The lower wordline driver read assist circuit of claim 1, wherein the wordline driver control submodule includes a decoder.
10. The lower wordline driver read assist circuit of any one of claims 1 to 9, wherein at least two wordline voltage divider submodules are connected between every two wordlines and the at least two sub-wordline voltage divider submodules are connected in parallel.
11. Layout design of a lower word line driving read assist circuit, characterized in that the lower word line driving read assist circuit according to any of claims 1-10 is used.
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| CN202010577071.3A CN111755048A (en) | 2020-06-22 | 2020-06-22 | Lower word line driving read auxiliary circuit and layout design |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112967741A (en) * | 2021-02-06 | 2021-06-15 | 江南大学 | High-speed high-voltage word line driving circuit facing storage array |
| US11804262B2 (en) | 2021-06-17 | 2023-10-31 | Nvidia Corp. | Area efficient memory cell read disturb mitigation |
| WO2024045217A1 (en) * | 2022-08-31 | 2024-03-07 | 长鑫存储技术有限公司 | Layout of word line driver, and memory |
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2020
- 2020-06-22 CN CN202010577071.3A patent/CN111755048A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112967741A (en) * | 2021-02-06 | 2021-06-15 | 江南大学 | High-speed high-voltage word line driving circuit facing storage array |
| CN112967741B (en) * | 2021-02-06 | 2023-09-08 | 江南大学 | High-speed high-voltage word line driving circuit for memory array |
| US11804262B2 (en) | 2021-06-17 | 2023-10-31 | Nvidia Corp. | Area efficient memory cell read disturb mitigation |
| WO2024045217A1 (en) * | 2022-08-31 | 2024-03-07 | 长鑫存储技术有限公司 | Layout of word line driver, and memory |
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