WO2024040644A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

Info

Publication number
WO2024040644A1
WO2024040644A1 PCT/CN2022/118570 CN2022118570W WO2024040644A1 WO 2024040644 A1 WO2024040644 A1 WO 2024040644A1 CN 2022118570 W CN2022118570 W CN 2022118570W WO 2024040644 A1 WO2024040644 A1 WO 2024040644A1
Authority
WO
WIPO (PCT)
Prior art keywords
doped region
doping
region
epitaxial layer
doping concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/118570
Other languages
English (en)
French (fr)
Inventor
刘志拯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Publication of WO2024040644A1 publication Critical patent/WO2024040644A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H10F39/8023—Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
    • H10F30/22—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
    • H10F30/221—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PN homojunction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • CMOS image sensors have made the market share of CMOS image sensors surpass CCD image sensors, especially in the mid-to-low-end consumer electronics industry.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which are at least conducive to improving the photogenerated carrier retention problem when the photodiode performs photogenerated carrier transmission, and utilizes a second doped region surrounding the first doped region. Reduce the leakage current of the photodiode, which is beneficial to improving the performance of the photodiode and optimizing the low-light imaging performance of the semiconductor structure.
  • embodiments of the present disclosure provide a semiconductor structure, including: a substrate, the substrate includes a first doped region and a second doped region surrounding the first doped region, so The doping type of the first doping region and the doping type of the second doping region are different, and the first doping region and the second doping region together constitute a photodiode; wherein, the second doping region
  • the doping region includes a bottom, a middle and a top, and the doping concentration of the middle is smaller than the doping concentration of the bottom and the top.
  • the doping concentration of the bottom is greater than the doping concentration of the top.
  • the doping concentration in the first doping region ranges from 5 ⁇ 10 16 atoms/cm 3 to 3 ⁇ 10 17 atoms/cm 3 .
  • the doping concentration of the bottom part is 1 ⁇ 10 16 atoms/cm 3 ⁇ 5 ⁇ 10 16 atoms/cm 3 ; the doping concentration of the middle part is 5 ⁇ 10 15 atoms/cm 3 ⁇ 1 ⁇ 10 16 atoms/cm 3 ; the doping concentration of the top is 8 ⁇ 10 15 atoms/cm 3 to 2 ⁇ 10 16 atoms/cm 3 .
  • the thickness of the middle portion is greater than the thickness of the bottom and the top in a direction from the bottom to the top.
  • the thickness of the top is less than the thickness of the bottom in a direction from the bottom to the top.
  • the thickness of the first doped region in the direction from the bottom to the top, is 3.9 ⁇ m to 4.1 ⁇ m, the thickness of the bottom is 0.45 ⁇ m to 0.55 ⁇ m, and the thickness of the middle region is 0.45 ⁇ m to 0.55 ⁇ m.
  • the thickness is 3.2 ⁇ m ⁇ 3.4 ⁇ m, and the thickness of the top is 0.15 ⁇ m ⁇ 0.25 ⁇ m.
  • the semiconductor structure further includes: a third doping region and a transmission gate structure, the third doping region is spaced above the first doping region, and the transmission gate structure is connected to the transmission gate structure.
  • the first doped region and the third doped region are adjacent.
  • the doping type of the third doping region is the same as the doping type of the first doping region, and the doping concentration of the third doping region is greater than or equal to the first doping region.
  • the doping concentration of the impurity region is the same as the doping type of the first doping region, and the doping concentration of the third doping region is greater than or equal to the first doping region. The doping concentration of the impurity region.
  • another aspect of the present disclosure further provides a method for manufacturing a semiconductor structure, including: forming a substrate, the substrate including a first doped region and a third region surrounding the first doped region. Two doping regions, the doping type of the first doping region is different from the doping type of the second doping region, the first doping region and the second doping region together constitute a photodiode; Wherein, the second doped region includes a bottom, a middle and a top, and the doping concentration of the middle is smaller than the doping concentration of the bottom and the top.
  • the step of forming the substrate includes: providing a substrate; using an epitaxial growth process to respectively form a first epitaxial layer, a second epitaxial layer and a third epitaxial layer on the substrate.
  • the epitaxial layer, the second epitaxial layer and the third epitaxial layer are respectively doped with different concentrations of the second type to form an initial second doped region; the central area of the initial second doped region is A first type of doping is performed to form the first doped region, and the remaining initial second doped region serves as the second doped region.
  • the second epitaxial layer in the step of doping the first epitaxial layer, the second epitaxial layer and the third epitaxial layer with different concentrations of the second type, the second epitaxial layer The doping concentration is lower than the doping concentration of the first epitaxial layer and the third epitaxial layer, and the doping concentration of the third epitaxial layer is lower than the doping concentration of the first epitaxial layer.
  • the thickness of the second epitaxial layer is greater than that of the third epitaxial layer in a direction from the first epitaxial layer to the third epitaxial layer. The thickness of an epitaxial layer and the thickness of the third epitaxial layer.
  • the manufacturing method of the semiconductor structure further includes: forming a third doped region, the third doped region is located in the second doped region and is spaced apart from the first doped region. ; Form a transmission gate structure adjacent to both the first doping region and the third doping region.
  • the step of forming the third doped region includes: performing the first type doping on a portion of the surface of the third epitaxial layer away from the first doped region to partially The second doped region is transformed into the third doped region.
  • the step of forming the transmission gate structure includes: forming a through hole on a side of the third epitaxial layer away from the second epitaxial layer, the bottom of the through hole exposing the first doped Doping region, the top sidewall of the through hole exposes the third doping region, and a dielectric layer and a conductive layer are formed on the inner wall of the through hole in sequence.
  • the doping type of the first doping region and the doping type of the second doping region are different, thereby forming a PN junction for collecting photogenerated carriers, and the doping of different areas in the second doping region
  • Different impurity concentrations have different effects on the bandgap width of the PN junction.
  • the doping concentration at the bottom is larger, and the more impurity energy levels introduced, the smaller the bandgap width is, and it is easier for electrons in the valence band to jump in.
  • the conduction band makes it easier to generate photogenerated carriers; on the other hand, the doping concentration in the middle is the smallest, which is conducive to storing the collected photogenerated carriers; moreover, when transmitting photogenerated carriers, the doping concentration at the bottom is used to match the The difference in doping concentration in the middle part, that is, the difference between the potential at the bottom and the potential in the middle part is used to increase the transfer speed of photogenerated carriers and reduce the probability of photogenerated carriers staying in the first doped region to improve the semiconductor Image lag issues in structures.
  • using the second doped region to surround the first doped region is beneficial to utilizing the potential energy difference between the second doped region and the first doped region to reduce the probability of photogenerated carriers leaking from the second doped region. , thus helping to reduce the leakage current of the photodiode.
  • the first doped region and the second doped region in the embodiments of the present disclosure are beneficial to improving the performance of the photodiode and optimizing the low-light imaging performance of the semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of a photodiode carrying out photogenerated carrier transmission in a semiconductor structure according to an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of a photodiode storing photogenerated carriers in a semiconductor structure according to an embodiment of the present disclosure
  • 4 to 7 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
  • the pixel part of the CMOS image sensor usually consists of a photodiode, a transmission tube, a floating diffusion node, a reset tube, a source follower, and a selector tube.
  • a photodiode When light is incident on the surface of a semiconductor, part of the incident light is reflected while the remainder is absorbed by the semiconductor.
  • the photon energy entering the semiconductor is not lower than the forbidden band width of the semiconductor material, the semiconductor material will have a certain probability to absorb this energy, thereby generating electron-hole pairs, that is, photogenerated carriers.
  • the transmission tube is turned on, and the photogenerated carriers are transferred from the photodiode area to the floating diffusion node under the action of the electric field, which completes the conversion process of charge-voltage information, and finally passes through the row gate tube and column level.
  • the readout circuit reads out the optical signals stored in the floating diffusion nodes line by line.
  • the present disclosure provides a semiconductor structure and a manufacturing method thereof.
  • the semiconductor structure can be applied to a CMOS image sensor.
  • the doping type of the first doping region and the doping type of the second doping region are different, which is beneficial to A PN junction is formed to collect photogenerated carriers.
  • the doping concentration at the bottom is larger, and the more impurity energy levels are introduced, the smaller the forbidden band width of the PN junction is, and the electrons in the valence band It is easier to transition into the conduction band and generate photo-generated carriers.
  • the doping concentration in the middle is the smallest, which is conducive to storing the collected photo-generated carriers; moreover, when transmitting photo-generated carriers, the doping concentration at the bottom is used to match the
  • the difference in doping concentration in the middle that is, using the difference between the potential at the bottom and the potential in the middle, increases the transfer speed of photogenerated carriers, which is beneficial to reducing the probability of photogenerated carriers staying in the photodiode, that is, improving photogenerated carrier retention problem, thereby improving the image hysteresis problem in semiconductor structures.
  • using the second doped region to surround the first doped region is beneficial to utilizing the potential energy difference between the second doped region and the first doped region to reduce the probability of photogenerated carriers leaking from the second doped region. , thus helping to reduce the leakage current of the photodiode.
  • the first doped region and the second doped region in the embodiments of the present disclosure are beneficial to improving the performance of the photodiode and optimizing the low-light imaging performance of the semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a photodiode carrying out photogenerated carrier transmission in the semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of the semiconductor structure provided by an embodiment of the present disclosure.
  • a brief schematic diagram of a photodiode storing photogenerated carriers in a semiconductor structure according to an embodiment is disclosed.
  • the semiconductor structure includes: a substrate 100.
  • the substrate 100 includes a first doped region 101 and a second doped region 102 surrounding the first doped region 101.
  • the doping type of the first doped region 101 Different from the doping type of the second doped region 102, the first doped region 101 and the second doped region 102 together constitute the photodiode 103; wherein the second doped region 102 includes a bottom 112, a middle 122 and a top 132.
  • the doping concentration of the middle portion 122 is smaller than the doping concentration of the bottom portion 112 and the doping concentration of the top portion 132 .
  • the more impurity energy levels introduced, the smaller the forbidden band width of the PN junction, and the electrons in the valence band are more likely to transition into the conduction band, making it easier to generate photogenerated carriers.
  • the doping concentration of the middle part 122 is the smallest, which is beneficial to the first doping region 101 surrounded by the middle part 122 to store the collected photo-generated carriers; moreover, during the transmission of photo-generated carriers, the doping concentration of the bottom part 112 and the middle part 122 are used
  • the difference in doping concentration that is, the difference between the potential at the bottom 112 and the potential at the middle 122 is used to increase the transfer speed of photo-generated carriers and reduce the probability of photo-generated carriers staying in the photodiode 103 to improve the semiconductor structure Image lag problem in .
  • the potential between the bottom 112 and the doping concentration of the middle 122 is A large difference is conducive to the formation of a potential energy gradient as shown in Figure 2, which promotes the transfer of photogenerated carriers from places with high potential energy to places with low potential energy like water flow, and the height difference in potential energy is conducive to improving the transfer of photogenerated carriers.
  • speed that is, increasing the probability of photo-generated carriers rushing out of the first doped region 101, making it easier for photo-generated carriers to transport out of the first doped region 101, which is beneficial to reducing photo-generated carriers staying in the first doped region 101.
  • the probability in the doping region 101 is to improve the image lag problem in the semiconductor structure and optimize the low-light imaging performance of the semiconductor structure.
  • the second doped region 102 is used to surround the first doped region 101, and the potential energy difference between the second doped region 102 and the first doped region 101 is used to reduce the flow of photogenerated carriers from the second doped region 102.
  • the probability of leakage is thus beneficial to reducing the leakage current of the photodiode 103 to improve the photoelectric conversion performance of the photodiode 103 .
  • the doping type of the first doping region 101 and the doping type of the second doping region 102 are different, which means: the first doping region 101 is doped with first type ions, and the second doping region 102 is doped with ions of the first type.
  • the impurity region 102 is doped with second type ions, where the first type ions are one of N-type ions and P-type ions, and the second type ions are the other one of N-type ions and P-type ions.
  • the N-type ions may include at least one of arsenic ions, phosphorus ions or antimony ions
  • the P-type ions may include at least one of boron ions, indium ions or gallium ions.
  • the first doped region 101 is doped with N-type, that is, the first doped region 101 is doped with N-type ions
  • the second doped region 102 is doped with P-type, that is, the second doped region 101 is doped with N-type ions.
  • the doped region 102 is doped with P-type ions as an example.
  • the first doped region may be P-type doped
  • the second doped region may be N-type doped.
  • the doping concentration of the middle part 122 is less than the doping concentration of the bottom 112 and the doping concentration of the top 132 means: the doping concentration of the first type ions in the middle part 122 is less than the doping concentration of the bottom 112 concentration, and the doping concentration of the first type ions in the middle portion 122 is smaller than the doping concentration in the top portion 132 .
  • the doping concentration of bottom 112 is greater than the doping concentration of top 132 .
  • the doping concentration at the bottom is the highest.
  • the doping concentration of the top 132 is centered, which is beneficial to reducing the defect density in the top 132 caused by the doping process, which is beneficial to reducing the amount of photogenerated carriers passing through the top 132.
  • the probability of being captured and consumed by the defects in the top 132 is beneficial to further improving the collection efficiency of photogenerated carriers, thereby improving the photoelectric conversion efficiency of the photodiode.
  • the doping concentration of the bottom 112 is greater than the doping concentration of the top 132 means that the doping concentration of the second type ions in the bottom 112 is greater than the doping concentration of the top 132 .
  • the doping concentration of the bottom 112 may be 1 ⁇ 10 16 atoms/cm 3 ⁇ 5 ⁇ 10 16 atoms/cm 3 ; the doping concentration of the middle 122 may be 5 ⁇ 10 15 atoms/cm 3 ⁇ 1 ⁇ 10 16 atoms/cm 3 ; the doping concentration of the top 132 can be 8 ⁇ 10 15 atoms/cm 3 to 2 ⁇ 10 16 atoms/cm 3 .
  • the doping concentration of the bottom 112 refers to the doping concentration of the second type ions in the bottom 112; the doping concentration of the middle 122 refers to the doping concentration of the second type ions in the middle 122; the top The doping concentration of 132 refers to the doping concentration of the second type ions in the top 132 .
  • the doping concentration of the bottom 112, that is, the doping concentration of P-type ions in the bottom 112, may be 1 ⁇ 10 16 atom/cm 3 ⁇ 5 ⁇ 10 16 atom/cm 3 ;
  • the doping concentration of the middle 122 that is, the doping concentration of P-type ions in the middle 122 can be 5 ⁇ 10 15 atom/cm 3 ⁇ 1 ⁇ 10 16 atom/cm 3 ;
  • the doping concentration of the top 132 that is, the doping concentration of P-type ions in the top 132
  • the impurity concentration can be 8 ⁇ 10 15 atoms/cm 3 to 2 ⁇ 10 16 atoms/cm 3 .
  • the first doping region 101 is doped with second type ions in addition to the first type ions, and the second type ions are doped in the first doping region.
  • the doping concentration in region 101 is less than or equal to the doping concentration in second doped region 102 .
  • the doping concentration in the first doped region 101 may range from 5 ⁇ 10 16 atoms/cm 3 to 3 ⁇ 10 17 atoms/cm 3 . In this way, it is beneficial to form a required PN junction between the first doped region 101 and the second doped region 102 as a whole, thereby promoting the generation of photogenerated carriers. In practical applications, the doping concentration of the first doping region 101 can be reasonably set according to the number of photogenerated carriers that the photodiode 103 needs to generate.
  • the doping concentration in the first doping region 101 refers to the doping concentration of the first type ions in the first doping region 101 .
  • the doping concentration in the first doping region 101 that is, the doping concentration of N-type ions in the first doping region 101, may be 5 ⁇ 10 16 atoms/cm 3 to 3 ⁇ 10 17 atoms/ cm 3 .
  • the thickness of the middle portion 122 is greater than the thickness of the bottom portion 112 and the top portion 132 in the direction X in which the bottom portion 112 points toward the top portion 132 .
  • the first doped region 101 surrounded by the middle part 122 is mainly used to store photogenerated carriers, that is, most of the effective charges are stored in the first doped region 101 surrounded by the middle part 122. Therefore, at the bottom 112 , the middle part 122 and the top part 132, with reference to Figure 3, the thickness of the middle part 122 is the largest, which is conducive to increasing the space occupied by the first doped region 101 surrounded by the middle part 122 in the photodiode 103, that is, increasing the effective charge storage space. , to improve the charge storage capability of the first doped region 101 surrounded by the middle portion 122 , thereby helping to increase the full well capacity of the photodiode 103 . In addition, the bottom 112 and the top 132 are mainly used to form a higher potential and a larger potential difference with the middle 122 , which helps the first doped region 101 surrounded by the middle 122 to store photogenerated carriers.
  • the thickness of top 132 is less than the thickness of bottom 112 in the direction X in which bottom 112 points toward top 132 .
  • the bottom 112 and the top 132 are mainly used to form a higher potential, and the first doping region 101 surrounded by the middle 122 is mainly used to store photogenerated carriers, so the thickness of the bottom 112 and the top 132 do not need to be If it is too high, only a higher doping concentration is required. In this way, it is helpful to prevent the first doped region 101 surrounded by the bottom 112 and the first doped region 101 surrounded by the top 132 from occupying too much area in the photodiode 103, reducing the Full well capacity of photodiode 103.
  • making the thickness of the top 132 smaller than the thickness of the bottom 112 is beneficial to achieving a higher doping concentration of the bottom 112 than that of the top 132, and when photogenerated carrier transmission is required, that is, when the transmission gate structure 105 is turned on. , the photogenerated carriers stored in the first doped region 101 surrounded by the middle portion 122 are more likely to pass through the first doped region 101 surrounded by the top portion 132 .
  • the thickness of the top 132 can be 3.2 ⁇ m to 3.4 ⁇ m, and the thickness of the top 132 can be 0.15 ⁇ m to 0.25 ⁇ m.
  • the thickness can be 0.2 ⁇ m.
  • the semiconductor structure may further include: a third doping region 104 and a transmission gate structure 105 .
  • the third doping region 104 is spaced above the first doping region 101 , and the transmission gate structure 105 and The first doped region 101 and the third doped region 104 are both adjacent.
  • the second doping region 102 may also include: an accommodation region 142 located above the top 132 , and the third doping region 104 and the transmission gate structure 105 are located in the accommodation region 142 .
  • the doping concentration of the second type ions in the accommodation region 142 may be the same as the doping concentration in the top 132 .
  • the transmission gate structure 105 and the first doping region 101 are arranged along the direction X, and the transmission gate structure 105 and the third doping region 104 are arranged along the direction perpendicular to the direction X.
  • the third doped region 104, the transmission gate structure 105, the top of the first doped region 101 and part of the second doped region 102 constitute a transistor structure, and the third doped region 104 and the first doped region 101 The top two correspond to the source and drain regions of the transistor structure.
  • the transmission gate structure 105 is configured to: refer to Figure 2, when photogenerated carrier transmission is required, conduct a charge transmission path between the third doping region 104 and the top 132; refer to Figure 3, when the first When the doped region 101 stores photogenerated carriers, the charge transmission path between the third doped region 104 and the top 132 is turned off.
  • the doping type of the third doping region 104 is the same as the doping type of the first doping region 101 , and the doping concentration of the third doping region 104 is greater than or equal to that of the first doping region 101 . impurity concentration.
  • the doping type of the third doping region 104 and the doping type of the first doping region 101 are both N-type doping.
  • the transmission gate structure 105 includes a dielectric layer 115 and a conductive layer 125 , and the dielectric layer 115 is located between the first doped region 101 and the conductive layer 125 .
  • the dielectric layer 115 may be in contact with the top 132 , and the dielectric layer 115 may be in contact with the third doped region 104 .
  • the gap may be filled by the second doped region 102; there may be a part of the gap between the dielectric layer 115 and the third doped region 104, This space is filled by the second doped region 102 .
  • the number of photodiodes 103 may be multiple, the transmission gate structure 105 corresponds to the photodiode 103 one-to-one, and the third doped region 104 corresponds to the photodiode 103 one-to-one; the semiconductor structure also It may include: a deep trench isolation structure 107 located between adjacent photodiodes 103 , between adjacent transmission gate structures 105 , and between adjacent third doped regions 104 .
  • the photodiode 103, the transmission gate structure 105 and the third doped region 104 constitute a pixel unit, and the deep trench isolation structure 107 can be used to achieve isolation between adjacent pixel units to reduce the interference between adjacent pixel units.
  • the optical crosstalk and electrical crosstalk between the semiconductor structures are beneficial to further improving the optoelectronic performance of the semiconductor structure.
  • the semiconductor structure may further include a substrate 110 for supporting the aforementioned plurality of pixel units and the deep trench isolation structure 107 .
  • the semiconductor structure provided by an embodiment of the present disclosure can be applied to a CMOS image sensor, in which the doping type of the first doping region 101 and the doping type of the second doping region 102 are different, which is beneficial to the formation of collection The PN junction of photogenerated carriers.
  • the potential energy difference between the bottom 112 and the second doped region 102 is larger, which is conducive to utilizing the larger
  • the potential energy difference collects photo-generated carriers
  • the doping concentration of the middle part 122 is the smallest, which is conducive to the first doping region 101 surrounded by the middle part 122 to store the collected photo-generated carriers; moreover, when carrying out photo-generated carrier transmission, the bottom part is used
  • the difference between the doping concentration of 112 and the doping concentration of the middle 122 that is, the difference between the potential at the bottom 112 and the potential at the middle 122 is used to increase the transfer speed of photogenerated carriers, thereby helping to reduce the retention of photogenerated carriers.
  • the probability in the photodiode 103 is to improve the retention problem of photogenerated carriers, thereby improving the image lag problem in the semiconductor structure.
  • using the second doped region 102 to surround the first doped region 101 is beneficial to utilizing the potential energy difference between the second doped region 102 and the first doped region 101 to reduce the flow of photogenerated carriers from the second doped region. 102, thus helping to reduce the leakage current of the photodiode.
  • Another embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, which is used to prepare the semiconductor structure provided in the previous embodiment.
  • a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to FIGS. 1 to 7 .
  • 4 to 7 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure. It should be noted that the parts that are the same as or corresponding to the previous embodiments will not be described again here.
  • the manufacturing method of a semiconductor structure includes: forming a substrate 100 , which includes a first doped region 101 and a second doped region 102 surrounding the first doped region 101 .
  • the first doped region 101 The doping type is different from the doping type of the second doped region 102.
  • the first doped region 101 and the second doped region 102 together constitute the photodiode 103; wherein the second doped region 102 includes a bottom 112 and a middle 122 and the top 132 , the doping concentration of the middle 122 is smaller than the doping concentration of the bottom 112 and the doping concentration of the top 132 .
  • the doping concentration of the middle part 122 is smaller than the doping concentration of the bottom 112 and the doping concentration of the top 132, which is beneficial to utilizing the doping concentration of the bottom 112 and the doping concentration of the middle part 122 when performing photogenerated carrier transmission.
  • the difference in concentration that is, the difference between the potential at the bottom 112 and the potential at the middle 122 is used to increase the transfer speed of photogenerated carriers and reduce the probability of photogenerated carriers staying in the photodiode 103 to improve the image in the semiconductor structure Lag issues.
  • the doping type of the first doped region 101 is different from the doping type of the second doped region 102.
  • the use of the second doped region 102 to surround the first doped region 101 is beneficial to the use of the second doped region 102 and
  • the potential energy difference between the first doped regions 101 reduces the probability of photogenerated carriers leaking from the second doped region 102 , thereby helping to reduce the leakage current of the photodiode 103 .
  • forming the substrate 100 may include the following steps:
  • a substrate 110 is provided; an epitaxial growth process is used to form a first epitaxial layer 120 , a second epitaxial layer 130 and a third epitaxial layer 140 respectively on the substrate 110 .
  • the third epitaxial layer 140 includes a first portion 141 and an accommodation region 142 .
  • the first part 141 is used to subsequently form the top of the second doped region
  • the accommodation region 142 is used to subsequently form the third doped region
  • the entire third epitaxial layer 140 is used to subsequently form the transmission gate structure.
  • the number of photodiodes 103 finally formed may be multiple, the transmission gate structure 105 corresponds to the photodiode 103 one-to-one, and the third doped region 104 corresponds to the photodiode 103 one-to-one.
  • the manufacturing method of the semiconductor structure may also include the following steps:
  • the first epitaxial layer 120 , the second epitaxial layer 130 and the third epitaxial layer 140 are patterned to form trenches; continuing to refer to FIG. 5 , a deep trench isolation structure 107 filled with the trenches is formed.
  • a deep trench isolation structure 107 filled with the trenches is formed.
  • a deep trench is formed to isolate the plurality of photodiodes, the transmission gate structure 105 and the third doping region 104. Isolation structures107.
  • the first epitaxial layer 120 , the second epitaxial layer 130 and the third epitaxial layer 140 are respectively doped with different concentrations of the second type to form an initial second doped region 152 .
  • the doping concentration of the second epitaxial layer 130 is low.
  • the doping concentration of the third epitaxial layer 140 is lower than the doping concentration of the first epitaxial layer 120 .
  • the bottom 112 (refer to FIG. 6 ) of the second doped region 102 (refer to FIG. 6 ) is subsequently formed based on the first epitaxial layer 120 , and the middle portion 122 (refer to FIG.
  • the second doped region 102 is formed based on the second epitaxial layer 130 .
  • the top 132 of the second doped region 102 is formed based on the third epitaxial layer 140 (refer to FIG. 6 )
  • performing doping of the second type with different concentrations on the first epitaxial layer 120 , the second epitaxial layer 130 and the third epitaxial layer 140 means: 130 and the third epitaxial layer 140 are respectively doped with different concentrations of P-type ions.
  • the thickness of the second epitaxial layer 130 is greater than that of the first epitaxial layer 120 .
  • thickness and the thickness of the third epitaxial layer 140 are compared in the step of forming the initial second doped region 152 , along the direction X in which the first epitaxial layer 120 points to the third epitaxial layer 140 .
  • the middle portion 122 is beneficial to subsequently form the middle portion 122 with a thickness greater than the thickness of the bottom portion 112 and the thickness of the top portion 132 , which is beneficial to increasing the space occupied by the first doped region 101 surrounded by the middle portion 122 in the photodiode 103 , that is, increasing the effective
  • the charge storage space is provided to improve the charge storage capacity of the first doped region 101 surrounded by the middle portion 122, thereby conducive to improving the full well capacity of the photodiode 103.
  • the thickness of the first portion 141 of the top portion 132 of the second doped region 102 in the direction X from the first epitaxial layer 120 toward the third epitaxial layer 140 is smaller than the thickness of the first epitaxial layer 120, In this way, it is beneficial to subsequently form the top 132 with a thickness smaller than that of the bottom 112 .
  • the first type of doping is performed on the central region of the initial second doped region 152 to form the first doped region 101 , and the remaining initial second doped region 152 serves as the second doped region 102 .
  • the formed second doped region 102 includes a bottom 112, a middle 122 and a top 132.
  • the doping concentration of the middle 122 is smaller than the doping concentration of the bottom 112 and the doping concentration of the top 132, and the doping concentration of the bottom 112 The concentration is greater than the doping concentration of top 132 .
  • the potential difference between the bottom 112 and the middle 122 is large, which is conducive to the formation of Prompting photogenerated carriers to transfer from places with high potential energy to places with low potential energy like water flow, and the height difference in potential energy is conducive to increasing the transfer speed of photogenerated carriers, that is, increasing the transfer speed of photogenerated carriers from the first doping region 101
  • the probability of rushing out makes it easier for photo-generated carriers to transport out of the first doped region 101, which is beneficial to reducing the probability of photo-generated carriers staying in the first doped region 101, thereby improving the image lag in the semiconductor structure.
  • the doping concentration of the top 132 is in the middle, which is beneficial to reducing the defect density in the top 132 caused by the doping process, and is beneficial to reducing the probability that the photogenerated carriers are captured and consumed by the defects in the top 132 when passing through the top 132. In this way, it is conducive to further improving the collection efficiency of photogenerated carriers, thereby being conducive to improving the photoelectric conversion efficiency of the photodiode.
  • doping the central region of the initial second doped region 152 with the first type means doping the central region of the initial second doped region 152 with N-type ions.
  • the manufacturing method of the semiconductor structure may further include: forming a third doped region 104 , the third doped region 104 is located in the second doped region 102 and is connected with the first doped region 104 .
  • the impurity regions 101 are spaced apart; a transmission gate structure 105 is formed, and the transmission gate structure 105 is adjacent to both the first doping region 101 and the third doping region 104 .
  • the third doped region 104 located in the second doped region 102 means that the third doped region 104 is located in the accommodating region 142; the transmission gate structure 105 is also located in the accommodating region 142.
  • the third doped region 104, the transmission gate structure 105, the top of the first doped region 101 and part of the second doped region 102 constitute a transistor structure, and the third doped region 104 and the first doped region 101 The top two correspond to the source and drain regions of the transistor structure.
  • the step of forming the third doped region 104 may include: referring to FIG. 7 , performing a first type doping on a portion of the surface of the third epitaxial layer 140 away from the first doped region 101 to partially The first doped region 101 is converted into a third doped region 104.
  • performing the first type doping on a portion of the surface of the third epitaxial layer 140 away from the first doping region 101 means performing the first type doping on a portion of the accommodation region 142 to form The third doped region 104.
  • the doping concentration of the third doped region 104 is greater than or equal to the doping concentration of the first doped region 101 .
  • the step of forming the transmission gate structure 105 may include: referring to FIG. 7 , forming a through hole 106 on a side of the third epitaxial layer 140 away from the second epitaxial layer 130 , with the bottom of the through hole 106 exposing the first doped layer. In the impurity region 101, the top sidewall of the through hole 106 exposes the third doping region 104; referring to FIG. 1, a dielectric layer 115 and a conductive layer 125 are formed on the inner wall of the through hole 106 in sequence.
  • the bottom of the through hole 106 may not expose the first doped region 101, and the top sidewall of the through hole 106 may not expose the third doped region 104, that is, the dielectric layer 115 may be There may be a part of the gap between the tops 132, and the gap is filled by the second doped region 102; there may be a part of the gap between the dielectric layer 115 and the third doped region 104, and the gap is filled by the second doped region 102. .
  • the formed semiconductor structure can be applied to a CMOS image sensor.
  • the doping concentration of the bottom 112 and the middle part 122 are used.
  • the difference in doping concentration that is, the difference between the potential at the bottom 112 and the potential at the middle 122 is used to increase the transfer speed of photogenerated carriers, which is beneficial to reducing the probability of photogenerated carriers staying in the photodiode 103, that is, Improve the retention problem of photogenerated carriers, thereby improving the image lag problem in semiconductor structures.
  • using the second doped region 102 to surround the first doped region 101 is beneficial to utilizing the potential energy difference between the second doped region 102 and the first doped region 101 to reduce the flow of photogenerated carriers from the second doped region. 102, thus helping to reduce the leakage current of the photodiode.

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

本公开实施例涉及半导体技术领域，提供一种半导体结构及其制造方法，半导体结构包括：基底，所述基底中包括第一掺杂区和包围所述第一掺杂区的第二掺杂区，所述第一掺杂区的掺杂类型和所述第二掺杂区的掺杂类型不同，所述第一掺杂区和所述第二掺杂区共同构成光电二极管；其中，所述第二掺杂区包括底部、中部和顶部，所述中部的掺杂浓度小于所述底部的掺杂浓度和所述顶部的掺杂浓度。本公开实施例至少有利于改善光电二极管进行光生载流子传输时的光生载流子滞留的问题，以及利用包围第一掺杂区的第二掺杂区降低光电二极管的漏电电流，从而有利于提高光电二极管的性能，以及优化半导体结构的微光成像性能。

Description

半导体结构及其制造方法
交叉引用
本申请要求于2022年08月23日递交的名称为“半导体结构及其制造方法”、申请号为202211013671.2的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构及其制造方法。
背景技术
CMOS图像传感器的低功耗、低成本、高集成以及高灵活度等特点，使得CMOS图像传感器的市场份额已经超越CCD图像传感器，尤其是在中低端的消费类电子行业。
在消费类电子产品中，便携性是产品不断升级的目标之一，故为了缩小产品的体积，同时保证产品的性能，图像传感器的像素尺寸越来越小，但是大感光面积的像素在特定领域也有着尤为重要的应用。在微弱光照下的夜晚、深海区域，为了增加图像传感器的感光量，则多采用具有大像素的图像传感器，可以增加满阱容量，从而提高灵敏度和信噪比。但是随着感光面积的增加，会导致光生载流子的滞留问题以及降低光生载流子的传输速度，容易导致最终形成的图像出现滞后。
发明内容
本公开实施例提供一种半导体结构及其制造方法，至少有利于改善光电二极管进行光生载流子传输时的光生载流子滞留的问题，以及利用包围第一掺杂区的第二掺杂区降低光电二极管的漏电电流，从而有利于提高光电二极管的性能，以及优化半导体结构的微光成像性能。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：基底，所述基底中包括第一掺杂区和包围所述第一掺杂区的第二掺杂区，所述第一掺杂区的掺杂类型和所述第二掺杂区的掺杂类型不同，所述第一掺杂区和所述第二掺杂区共同构成光电二极管；其中，所述第二掺杂区包括底部、中部和顶部，所述中部的掺杂浓度小于所述底部的掺杂浓度和所述顶部的掺杂浓度。
在一些实施例中，所述底部的掺杂浓度大于所述顶部的掺杂浓度。
在一些实施例中，所述第一掺杂区中的掺杂浓度为5×10 16atom/cm 3～3× 10 17atom/cm 3。
在一些实施例中，所述底部的掺杂浓度为1×10 16atom/cm 3～5×10 16atom/cm 3；所述中部的掺杂浓度为5×10 15atom/cm 3～1×10 16atom/cm 3；所述顶部的掺杂浓度为8×10 15atom/cm 3～2×10 16atom/cm 3。
在一些实施例中，沿所述底部指向所述顶部的方向上，所述中部的厚度大于所述底部和所述顶部的厚度。
在一些实施例中，沿所述底部指向所述顶部的方向上，所述顶部的厚度小于所述底部的厚度。
在一些实施例中，沿所述底部指向所述顶部的方向上，所述第一掺杂区的厚度为3.9μm～4.1μm，所述底部的厚度为0.45μm～0.55μm，所述中部的厚度为3.2μm～3.4μm，所述顶部的厚度为0.15μm～0.25μm。
在一些实施例中，所述半导体结构还包括：第三掺杂区和传输门结构，所述第三掺杂区间隔设置在所述第一掺杂区上方，所述传输门结构与所述第一掺杂区和所述第三掺杂区均相邻。
在一些实施例中，所述第三掺杂区的掺杂类型与所述第一掺杂区的掺杂类型相同，所述第三掺杂区的掺杂浓度大于或等于所述第一掺杂区的掺杂浓度。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制造方法，包括：形成基底，所述基底中包括第一掺杂区和包围所述第一掺杂区的第二掺杂区，所述第一掺杂区的掺杂类型与所述第二掺杂区的掺杂类型不同，所述第一掺杂区和所述第二掺杂区共同构成光电二极管；其中，所述第二掺杂区包括底部、中部和顶部，所述中部的掺杂浓度小于所述底部的掺杂浓度和所述顶部的掺杂浓度。
在一些实施例中，形成所述基底的步骤包括：提供衬底；采用外延生长工艺分别在所述衬底上形成第一外延层、第二外延层和第三外延层，对所述第一外延层、所述第二外延层和所述第三外延层分别进行不同浓度的第二类型的掺杂，以形成初始第二掺杂区；对所述初始第二掺杂区的中心区域进行第一类型的掺杂，以形成所述第一掺杂区，剩余所述初始第二掺杂区作为所述第二掺杂区。
在一些实施例中，在对所述第一外延层、所述第二外延层和所述第三外延层分别进行不同浓度的第二类型的掺杂的步骤中，所述第二外延层的掺杂浓度低于所述第一外延层和所 述第三外延层的掺杂浓度，所述第三外延层的掺杂浓度低于所述第一外延层的掺杂浓度。
在一些实施例中，在形成所述初始第二掺杂区的步骤中，沿所述第一外延层指向所述第三外延层的方向上，所述第二外延层的厚度大于所述第一外延层的厚度以及所述第三外延层的厚度。
在一些实施例中，所述半导体结构的制造方法还包括：形成第三掺杂区，所述第三掺杂区位于所述第二掺杂区中且与所述第一掺杂区相间隔；形成传输门结构，所述传输门结构与所述第一掺杂区和所述第三掺杂区均相邻。
在一些实施例中，形成所述第三掺杂区的步骤包括：对远离所述第一掺杂区的所述第三外延层的部分表面进行所述第一类型的掺杂，以将部分所述第二掺杂区转化为所述第三掺杂区。
在一些实施例中，形成所述传输门结构的步骤包括：在所述第三外延层远离所述第二外延层的一侧形成通孔，所述通孔的底部暴露出所述第一掺杂区，所述通孔的顶部侧壁暴露出所述第三掺杂区，依次在所述通孔的内壁形成介质层和导电层。
本公开实施例提供的技术方案至少具有以下优点：
光电二极管中，第一掺杂区的掺杂类型和第二掺杂区的掺杂类型不同，从而形成PN结，用于收集光生载流子，而且，第二掺杂区中不同区域的掺杂浓度不同，对PN结的禁带宽度的影响不同，一方面，底部的掺杂浓度较大，引入的杂质能级越多，导致禁带宽度越小，价带中的电子更容易跃迁进入导带，更容易产生光生载流子；另一方面，中部的掺杂浓度最小，有利于存储收集的光生载流子；而且，在进行光生载流子传输时，利用底部的掺杂浓度与中部的掺杂浓度的差，即利用底部处的电势与中部处的电势之差，提高光生载流子的转移速度，降低光生载流子滞留在第一掺杂区中的概率，以改善半导体结构中的图像滞后问题。此外，利用第二掺杂区包围第一掺杂区，有利于利用第二掺杂区和第一掺杂区之间的势能差，降低光生载流子从第二掺杂区中泄露的概率，从而有利于降低光电二极管的漏电电流。
由上述分析可知，本公开实施例中的第一掺杂区和第二掺杂区有利于提高光电二极管的性能，以及优化半导体结构的微光成像性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。一个或多个实施例 通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的半导体结构的一种结构示意图；
图2为本公开一实施例提供的半导体结构中光电二极管进行光生载流子传输时的一种简要示意图；
图3为本公开一实施例提供的半导体结构中光电二极管存储光生载流子时的一种简要示意图；
图4至图7为本公开另一实施例提供的半导体结构的制造方法各步骤对应的结构示意图。
具体实施方式
经分析发现，CMOS图像传感器的像素部分通常由光电二极管、传输管、浮空扩散节点、复位管、源级跟随器以及选择管等组成。当光入射到半导体表面时，其中一部分入射光被反射，而其余则被半导体吸收。当进入半导体内部的光子能量不低于半导体材料禁带宽度时，那么半导体材料便有一定概率吸收这份能量，从而产生电子-空穴对，即光生载流子。光照积分完成后，传输管传输导通，光生载流子在电场的作用下由光电二极管区域转移至浮空扩散节点，即完成电荷-电压信息的转换过程，最后通过行选通管以及列级读出电路，逐行读出存储在浮空扩散节点的光信号。
然而，随着图像传感器的像素尺寸越来越小，在微弱光照下的夜晚、深海区域，为了增加图像传感器的感光量，多采用具有大像素的图像传感器，可以增加满阱容量，但是随着感光面积的增加，会降低光生载流子的传输速度以及导致光生载流子的滞留问题，容易导致最终形成的图像出现滞后，降低形成的图像的质量。
本公开实施提供一种半导体结构及其制造方法，半导体结构可以应用于CMOS图像传感器中，半导体结构中，第一掺杂区的掺杂类型和第二掺杂区的掺杂类型不同，有利于形成收集光生载流子的PN结，而且，第二掺杂区中，底部的掺杂浓度较大，引入的杂质能级越多，导致PN结的禁带宽度越小，价带中的电子更容易跃迁进入导带，更容易产生光生载流子，中部的掺杂浓度最小，有利于存储收集的光生载流子；而且，在进行光生载流子传输 时，利用底部的掺杂浓度与中部的掺杂浓度的差，即利用底部处的电势与中部处的电势之差，提高光生载流子的转移速度，从而有利于降低光生载流子滞留在光电二极管中的概率，即改善光生载流子的滞留问题，从而改善半导体结构中的图像滞后问题。此外，利用第二掺杂区包围第一掺杂区，有利于利用第二掺杂区和第一掺杂区之间的势能差，降低光生载流子从第二掺杂区中泄露的概率，从而有利于降低光电二极管的漏电电流。
由上述分析可知，本公开实施例中的第一掺杂区和第二掺杂区有利于提高光电二极管的性能，以及优化半导体结构的微光成像性能。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
本公开一实施例提供一种半导体结构，以下将结合附图对本公开一实施例提供的半导体结构进行详细说明。图1为本公开一实施例提供的半导体结构的一种结构示意图；图2为本公开一实施例提供的半导体结构中光电二极管进行光生载流子传输时的一种简要示意图；图3为本公开一实施例提供的半导体结构中光电二极管存储光生载流子时的一种简要示意图。
参考图1和图2，半导体结构包括：基底100，基底100中包括第一掺杂区101和包围第一掺杂区101的第二掺杂区102，第一掺杂区101的掺杂类型和第二掺杂区102的掺杂类型不同，第一掺杂区101和第二掺杂区102共同构成光电二极管103；其中，第二掺杂区102包括底部112、中部122和顶部132，中部122的掺杂浓度小于底部112的掺杂浓度和顶部132的掺杂浓度。
可以理解的是，第二掺杂区102中不同区域的掺杂浓度不同，光生载流子的产生能力也不同。
具体的，由于底部112的掺杂浓度较大，引入的杂质能级越多，导致PN结的禁带宽度越小，价带中的电子更容易跃迁进入导带，更容易产生光生载流子，中部122的掺杂浓度最小，有利于中部122包围的第一掺杂区101存储收集的光生载流子；而且，在进行光生载流子传输时，利用底部112的掺杂浓度与中部122的掺杂浓度的差，即利用底部112处的电势与中部122处的电势之差，提高光生载流子的转移速度，降低光生载流子滞留在光电二极管103中的概率，以改善半导体结构中的图像滞后问题。
可以理解的是，参考图2，在进行光生载流子传输时，由于底部112的掺杂浓度与中部122的掺杂浓度之差较大，则底部112处的电势与中部122处的电势之差较大，有利于形成如图2所示的势能梯度，促使光生载流子如水流一般从势能高之处向势能低之处转移，且势能的高度差有利于提高光生载流子的转移速度，即提高光生载流子从第一掺杂区101中冲出去的概率，使得光生载流子更容易从第一掺杂区101中传输出去，有利于降低光生载流子滞留在第一掺杂区101中的概率，以改善半导体结构中的图像滞后问题，以及优化半导体结构的微光成像性能。
此外，利用第二掺杂区102包围第一掺杂区101，利用第二掺杂区102和第一掺杂区101之间的势能差，降低光生载流子从第二掺杂区102中泄露的概率，从而有利于降低光电二极管103的漏电电流，以提高光电二极管103的光电转换性能。
在一些实施例中，第一掺杂区101的掺杂类型和第二掺杂区102的掺杂类型不同指的是：第一掺杂区101中掺杂有第一类型离子，第二掺杂区102中掺杂有第二类型离子，其中，第一类型离子为N型离子和P型离子中的一者，第二类型离子为N型离子和P型离子中的另一者。具体地，N型离子可以包括砷离子、磷离子或者锑离子中的至少一种；P型离子可以包括硼离子、铟离子或者镓离子中的至少一种。
需要说明的是，后续以第一掺杂区101为N型掺杂，即第一掺杂区101中掺杂有N型离子，第二掺杂区102为P型掺杂，即，第二掺杂区102中掺杂有P型离子为示例。在实际应用中，第一掺杂区可以为P型掺杂，第二掺杂区可以为N型掺杂。
在一些实施例中，中部122的掺杂浓度小于底部112的掺杂浓度和顶部132的掺杂浓度指的是：第一类型离子在中部122中的掺杂浓度小于在底部112中的掺杂浓度，且第一类型离子在中部122中的掺杂浓度小于在顶部132中的掺杂浓度。
以下将结合附图对本公开一实施例提供的半导体结构进行更为详细的说明。
在一些实施例中，底部112的掺杂浓度大于顶部132的掺杂浓度。
可以理解的是，参考图2和图3，在底部112、中部122以及顶部132中，底部的掺杂浓度最高，一方面，有利于使得底部112处具有足够的电荷来产生较高的电势，从而在进行光生载流子传输时，有利于形成如图2所示的势能梯度，以提高光生载流子的转移速度，从而降低光生载流子滞留在第一掺杂区101中的概率，以改善半导体结构中的图像滞后问题；另一方面，参考图3，在需要第一掺杂区101存储光生载流子时，有利于使得底部112处的电势与中部122处的电势之差较大，从而有利于提高中部122包围的第一掺杂区101的电荷 存储能力，即提高光电二极管103的全阱容量。
此外，在底部112、中部122以及顶部132中，顶部132的掺杂浓度居中，有利于降低由于掺杂工艺造成的顶部132中的缺陷密度，则有利于降低光生载流子在经过顶部132时被顶部132中的缺陷捕获消耗的概率，如此，有利于进一步提高光生载流子的收集效率，从而有利于提高光电二极管的光电转换效率。
在一些实施例中，底部112的掺杂浓度大于顶部132的掺杂浓度指的是：第二类型离子在底部112中的掺杂浓度大于在顶部132中的掺杂浓度。
在一些实施例中，底部112的掺杂浓度可以为1×10 16atom/cm 3～5×10 16atom/cm 3；中部122的掺杂浓度可以为5×10 15atom/cm 3～1×10 16atom/cm 3；顶部132的掺杂浓度可以为8×10 15atom/cm 3～2×10 16atom/cm 3。
可以理解的是，底部112的掺杂浓度指的是第二类型离子在底部112中的掺杂浓度；中部122的掺杂浓度指的是第二类型离子在中部122中的掺杂浓度；顶部132的掺杂浓度指的是第二类型离子在顶部132中的掺杂浓度。在一个例子中，底部112的掺杂浓度，即P型离子在底部112中的掺杂浓度可以为1×10 16atom/cm 3～5×10 16atom/cm 3；中部122的掺杂浓度，即P型离子在中部122中的掺杂浓度可以为5×10 15atom/cm 3～1×10 16atom/cm 3；顶部132的掺杂浓度，即P型离子在顶部132中的掺杂浓度可以为8×10 15atom/cm 3～2×10 16atom/cm 3。
需要说明的是，在实际应用中，由于半导体结构的制造方法，第一掺杂区101除了掺杂第一类型离子，还掺杂有第二类型离子，且第二类型离子在第一掺杂区101中的掺杂浓度小于或等于在第二掺杂区102中的掺杂浓度。
在一些实施例中，第一掺杂区101中的掺杂浓度可以为5×10 16atom/cm 3～3×10 17atom/cm 3。如此，有利于使得第一掺杂区101与第二掺杂区102整体之间形成符合要求的PN结，促进光生载流子的产生。在实际应用中，可根据光电二极管103所需产生的光生载流子的数量，合理设置第一掺杂区101的掺杂浓度。
可以理解的是，第一掺杂区101中的掺杂浓度指的是第一类型离子在第一掺杂区101中的掺杂浓度。在一个例子中，第一掺杂区101中的掺杂浓度，即N型离子在第一掺杂区101中的掺杂浓度可以为5×10 16atom/cm 3～3×10 17atom/cm 3。
在一些实施例中，沿底部112指向顶部132的方向X上，中部122的厚度大于底部112和顶部132的厚度。
可以理解的是，中部122包围的第一掺杂区101主要用于存储光生载流子，即大部分有效的电荷均存储在中部122包围的第一掺杂区101中，因此，在底部112、中部122以及顶部132中，参考图3，中部122的厚度最大，有利于增大中部122包围的第一掺杂区101在光电二极管103中所占的空间，即增大有效的电荷存储空间，以提高中部122包围的第一掺杂区101的电荷存储能力，从而有利于提高光电二极管103的全阱容量。此外，底部112和顶部132主要是用于形成较高的电势，与中部122之间形成较大的电势差，有助于中部122包围的第一掺杂区101存储光生载流子。
在一些实施例中，沿底部112指向顶部132的方向X上，顶部132的厚度小于底部112的厚度。
可以理解的是，底部112和顶部132主要是用于形成较高的电势，中部122包围的第一掺杂区101主要用于存储光生载流子，则底部112的厚度和顶部132的厚度无需过高，只需掺杂浓度较高即可，如此，有利于避免底部112包围的第一掺杂区101和顶部132包围的第一掺杂区101占用光电二极管103中过多的区域，降低光电二极管103的全阱容量。而且，使得顶部132的厚度小于底部112的厚度，有利于实现底部112的掺杂浓度高于顶部132的掺杂浓度，且在需要进行光生载流子传输时，即传输门结构105导通时，中部122包围的第一掺杂区101中存储的光生载流子更容易通过顶部132包围的第一掺杂区101。
在一些实施例中，沿底部112指向顶部132的方向X上，第一掺杂区101的厚度可以为3.9μm～4.1μm，底部112的厚度可以为0.45μm～0.55μm，中部122的厚度可以为3.2μm～3.4μm，顶部132的厚度可以为0.15μm～0.25μm。
在一个例子中，沿底部112指向顶部132的方向X上，第一掺杂区101的厚度可以为4.0μm，底部112的厚度可以为0.5μm，中部122的厚度可以为3.3μm，顶部132的厚度可以为0.2μm。
在一些实施例中，参考图1，半导体结构可以还包括：第三掺杂区104和传输门结构105，第三掺杂区104间隔设置在第一掺杂区101上方，传输门结构105与第一掺杂区101和第三掺杂区104均相邻。
需要说明的是，在一些实施例中，第二掺杂区102还可以包括：容纳区142，容纳区142位于顶部132之上，第三掺杂区104和传输门结构105位于容纳区142中。在一个例子中，第二类型离子在容纳区142中的掺杂浓度可以与在顶部132中的掺杂浓度一样。
在一些实施例中，继续参考图1，传输门结构105与第一掺杂区101沿方向X排布， 传输门结构105与第三掺杂区104沿垂直于方向X的方向排布。
可以理解的是，第三掺杂区104、传输门结构105、第一掺杂区101的顶部以及部分第二掺杂区102构成晶体管结构，第三掺杂区104和第一掺杂区101的顶部两者相当于晶体管结构的源区和漏区。其中，传输门结构105被配置为：参考图2，在需要进行光生载流子传输时，导通第三掺杂区104和顶部132之间电荷的传输路径；参考图3，在需要第一掺杂区101存储光生载流子时，关断第三掺杂区104和顶部132之间电荷的传输路径。
在一些实施例中，第三掺杂区104的掺杂类型与第一掺杂区101的掺杂类型相同，第三掺杂区104的掺杂浓度大于或等于第一掺杂区101的掺杂浓度。
在一个例子中，第三掺杂区104的掺杂类型与第一掺杂区101的掺杂类型均为N型掺杂。
在一些实施例中，参考图1，传输门结构105包括介质层115和导电层125，介质层115位于第一掺杂区101和导电层125之间。
在一个例子中，继续参考图1，介质层115可以和顶部132接触连接，且介质层115可以和第三掺杂区104接触连接。在实际应用中，介质层115可以和顶部132之间可以具有一部分的间隔，该间隔由第二掺杂区102填充；介质层115可以和第三掺杂区104之间可以具有一部分的间隔，该间隔由第二掺杂区102填充。
在一些实施例中，参考图1，光电二极管103的数量可以为多个，传输门结构105与光电二极管103一一对应，且第三掺杂区104与光电二极管103一一对应；半导体结构还可以包括：深沟槽隔离结构107，位于相邻光电二极管103之间，且位于相邻传输门结构105之间，以及位于相邻第三掺杂区104之间。
可以理解的是，光电二极管103、传输门结构105以及第三掺杂区104构成一个像素单元，可以利用深沟槽隔离结构107实现相邻像素单元之间的隔离，以降低相邻像素单元之间的光学串扰和电学串扰，从而有利于进一步提高半导体结构的光电性能。
在一些实施例中，半导体结构还可以包括：衬底110，用于对前述多个像素单元以及深沟槽隔离结构107起支撑作用。
综上所述，本公开一实施例提供的半导体结构可以应用于CMOS图像传感器，其中，第一掺杂区101的掺杂类型和第二掺杂区102的掺杂类型不同，有利于形成收集光生载流子的PN结，而且，第二掺杂区102中，底部112的掺杂浓度较大，则底部112与第二掺杂区 102之间的势能差较大，有利于利用较大的势能差收集光生载流子，中部122的掺杂浓度最小，有利于中部122包围的第一掺杂区101存储收集的光生载流子；而且，在进行光生载流子传输时，利用底部112的掺杂浓度与中部122的掺杂浓度的差，即利用底部112处的电势与中部122处的电势之差，提高光生载流子的转移速度，从而有利于降低光生载流子滞留在光电二极管103中的概率，即改善光生载流子的滞留问题，从而改善半导体结构中的图像滞后问题。此外，利用第二掺杂区102包围第一掺杂区101，有利于利用第二掺杂区102和第一掺杂区101之间的势能差，降低光生载流子从第二掺杂区102中泄露的概率，从而有利于降低光电二极管的漏电电流。
本公开另一实施例还提供一种半导体结构的制造方法，用于制备前述实施例提供的半导体结构。以下将结合图1至图7对本公开另一实施例提供的半导体结构的制造方法进行详细说明。图4至图7为本公开另一实施例提供的半导体结构的制造方法各步骤对应的结构示意图。需要说明的是，与前述实施例相同或相应的部分在此不再赘述。
参考图4至图7，半导体结构的制造方法包括：形成基底100，基底100中包括第一掺杂区101和包围第一掺杂区101的第二掺杂区102，第一掺杂区101的掺杂类型与第二掺杂区102的掺杂类型不同，第一掺杂区101和第二掺杂区102共同构成光电二极管103；其中，第二掺杂区102包括底部112、中部122和顶部132，中部122的掺杂浓度小于底部112的掺杂浓度和顶部132的掺杂浓度。
可以理解的是，中部122的掺杂浓度小于底部112的掺杂浓度和顶部132的掺杂浓度，在进行光生载流子传输时，有利于利用底部112的掺杂浓度与中部122的掺杂浓度的差，即利用底部112处的电势与中部122处的电势之差，提高光生载流子的转移速度，降低光生载流子滞留在光电二极管103中的概率，以改善半导体结构中的图像滞后问题。此外，第一掺杂区101的掺杂类型与第二掺杂区102的掺杂类型不同，利用第二掺杂区102包围第一掺杂区101，有利于利用第二掺杂区102和第一掺杂区101之间的势能差，降低光生载流子从第二掺杂区102中泄露的概率，从而有利于降低光电二极管103的漏电电流。
在一些实施例中，形成基底100可以包括如下步骤：
参考图4，提供衬底110；采用外延生长工艺分别在衬底110上形成第一外延层120、第二外延层130和第三外延层140。
在一些实施例中，继续参考图4，沿第一外延层120指向第三外延层140的方向X上，第三外延层140包括第一部分141和容纳区142。其中，第一部分141用于后续形成第二掺 杂区的顶部，容纳区142用于后续形成第三掺杂区，第三外延层140整体用于后续形成传输门结构。
在一些实施例中，继续参考图1，最终形成的光电二极管103的数量可以为多个，传输门结构105与光电二极管103一一对应，且第三掺杂区104与光电二极管103一一对应；半导体结构的制造方法还可以包括如下步骤：
参考图5，对第一外延层120、第二外延层130和第三外延层140进行图形化处理，以形成沟槽；继续参考图5，形成填充满沟槽的深沟槽隔离结构107。如此，有利于厚度基于第一外延层120、第二外延层130和第三外延层140形成多个光电二极管、传输门结构105以及第三掺杂区104。在实际应用中，也可以在形成多个光电二极管、传输门结构105以及第三掺杂区104之后，再形成隔离多个光电二极管、传输门结构105以及第三掺杂区104的深沟槽隔离结构107。
继续参考图5，对第一外延层120、第二外延层130和第三外延层140分别进行不同浓度的第二类型的掺杂，以形成初始第二掺杂区152。
在一些实施例中，在对第一外延层120、第二外延层130和第三外延层140分别进行不同浓度的第二类型的掺杂的步骤中，第二外延层130的掺杂浓度低于第一外延层120和第三外延层140的掺杂浓度，第三外延层140的掺杂浓度低于第一外延层120的掺杂浓度。如此，后续基于第一外延层120形成第二掺杂区102(参考图6)的底部112(参考图6)，基于第二外延层130形成第二掺杂区102的中部122(参考图6)，以及基于第三外延层140形成第二掺杂区102的顶部132(参考图6)时，有利于形成使得中部122的掺杂浓度小于底部112的掺杂浓度和顶部132的掺杂浓度，且使得底部112的掺杂浓度大于顶部132的掺杂浓度。
在一些实施例中，对第一外延层120、第二外延层130和第三外延层140分别进行不同浓度的第二类型的掺杂指的是：在第一外延层120、第二外延层130和第三外延层140分别掺杂不同浓度的P型离子。
在一些实施例中，在形成初始第二掺杂区152的步骤中，沿第一外延层120指向第三外延层140的方向X上，第二外延层130的厚度大于第一外延层120的厚度以及第三外延层140的厚度。如此，有利于后续形成厚度大于底部112的厚度和顶部132的厚度的中部122，从而有利于增大中部122包围的第一掺杂区101在光电二极管103中所占的空间，即增大有效的电荷存储空间，以提高中部122包围的第一掺杂区101的电荷存储能力，从而有利于提 高光电二极管103的全阱容量。
在一些实施例中，沿第一外延层120指向第三外延层140的方向X上用于后续形成第二掺杂区102的顶部132的第一部分141的厚度小于第一外延层120的厚度，如此，有利于后续形成厚度小于底部112的顶部132。
参考图6，对初始第二掺杂区152的中心区域进行第一类型的掺杂，以形成第一掺杂区101，剩余初始第二掺杂区152作为第二掺杂区102。
可以理解的是，形成的第二掺杂区102包括底部112、中部122和顶部132，中部122的掺杂浓度小于底部112的掺杂浓度和顶部132的掺杂浓度，且底部112的掺杂浓度大于顶部132的掺杂浓度。如此，在进行光生载流子传输时，由于底部112的掺杂浓度与中部122的掺杂浓度之差较大，则底部112处的电势与中部122处的电势之差较大，有利于形成促使光生载流子如水流一般从势能高之处向势能低之处转移，且势能的高度差有利于提高光生载流子的转移速度，即提高光生载流子从第一掺杂区101中冲出去的概率，使得光生载流子更容易从第一掺杂区101中传输出去，有利于降低光生载流子滞留在第一掺杂区101中的概率，以改善半导体结构中的图像滞后问题，以及优化半导体结构的微光成像性能。此外，顶部132的掺杂浓度居中，有利于降低由于掺杂工艺造成的顶部132中的缺陷密度，则有利于降低光生载流子在经过顶部132时被顶部132中的缺陷捕获消耗的概率，如此，有利于进一步提高光生载流子的收集效率，从而有利于提高光电二极管的光电转换效率。
在一些实施例中，对初始第二掺杂区152的中心区域进行第一类型的掺杂指的是：在初始第二掺杂区152的中心区域掺杂N型离子。
在一些实施例中，结合参考图7和图1，半导体结构的制造方法还可以包括：形成第三掺杂区104，第三掺杂区104位于第二掺杂区102中且与第一掺杂区101相间隔；形成传输门结构105，传输门结构105与第一掺杂区101和第三掺杂区104均相邻。
在一些实施例中，第三掺杂区104位于第二掺杂区102中指的是第三掺杂区104位于容纳区142中；传输门结构105也位于容纳区142中。
可以理解的是，第三掺杂区104、传输门结构105、第一掺杂区101的顶部以及部分第二掺杂区102构成晶体管结构，第三掺杂区104和第一掺杂区101的顶部两者相当于晶体管结构的源区和漏区。
在一些实施例中，形成第三掺杂区104的步骤可以包括：参考图7，对远离第一掺杂 区101的第三外延层140的部分表面进行第一类型的掺杂，以将部分第一掺杂区101转化为第三掺杂区104。
在一些实施例中，对远离第一掺杂区101的第三外延层140的部分表面进行第一类型的掺杂指的是，对容纳区142的部分区域进行第一类型的掺杂以形成第三掺杂区104。其中，第三掺杂区104的掺杂浓度大于或等于第一掺杂区101的掺杂浓度。
在一些实施例中，形成传输门结构105的步骤可以包括：参考图7，在第三外延层140远离第二外延层130的一侧形成通孔106，通孔106的底部暴露出第一掺杂区101，通孔106的顶部侧壁暴露出第三掺杂区104；参考图1，依次在通孔106的内壁形成介质层115和导电层125。
需要说明的是，再实际应用中，通孔106的底部可以不暴露出第一掺杂区101，通孔106的顶部侧壁可以不暴露出第三掺杂区104，即介质层115可以和顶部132之间可以具有一部分的间隔，该间隔由第二掺杂区102填充；介质层115可以和第三掺杂区104之间可以具有一部分的间隔，该间隔由第二掺杂区102填充。
综上所述，本公开另一实施例提供的半导体结构的制造方法中，形成的半导体结构可以应用于CMOS图像传感器，在进行光生载流子传输时，利用底部112的掺杂浓度与中部122的掺杂浓度的差，即利用底部112处的电势与中部122处的电势之差，提高光生载流子的转移速度，从而有利于降低光生载流子滞留在光电二极管103中的概率，即改善光生载流子的滞留问题，从而改善半导体结构中的图像滞后问题。此外，利用第二掺杂区102包围第一掺杂区101，有利于利用第二掺杂区102和第一掺杂区101之间的势能差，降低光生载流子从第二掺杂区102中泄露的概率，从而有利于降低光电二极管的漏电电流。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (16)

  1. 一种半导体结构，包括：
    基底，所述基底中包括第一掺杂区和包围所述第一掺杂区的第二掺杂区，所述第一掺杂区的掺杂类型和所述第二掺杂区的掺杂类型不同，所述第一掺杂区和所述第二掺杂区共同构成光电二极管；
    其中，所述第二掺杂区包括底部、中部和顶部，所述中部的掺杂浓度小于所述底部的掺杂浓度和所述顶部的掺杂浓度。
  2. 如权利要求1所述的半导体结构，其中，所述底部的掺杂浓度大于所述顶部的掺杂浓度。
  3. 如权利要求1或2所述的半导体结构，其中，所述第一掺杂区的掺杂浓度为5×10 16atom/cm 3～3×10 17atom/cm 3。
  4. 如权利要求1或2所述的半导体结构，其中，所述底部的掺杂浓度为1×10 16atom/cm 3～5×10 16atom/cm 3；所述中部的掺杂浓度为5×10 15atom/cm 3～1×10 16atom/cm 3；所述顶部的掺杂浓度为8×10 15atom/cm 3～2×10 16atom/cm 3。
  5. 如权利要求2所述的半导体结构，其中，沿所述底部指向所述顶部的方向上，所述中部的厚度大于所述底部和所述顶部的厚度。
  6. 如权利要求5所述的半导体结构，其中，沿所述底部指向所述顶部的方向上，所述顶部的厚度小于所述底部的厚度。
  7. 如权利要求6所述的半导体结构，其中，沿所述底部指向所述顶部的方向上，所述第一掺杂区的厚度为3.9μm～4.1μm，所述底部的厚度为0.45μm～0.55μm，所述中部的厚度为3.2μm～3.4μm，所述顶部的厚度为0.15μm～0.25μm。
  8. 如权利要求1或2所述的半导体结构，其中，所述半导体结构还包括：第三掺杂区和传输门结构，所述第三掺杂区间隔设置在所述第一掺杂区上方，所述传输门结构与所述第一掺杂区和所述第三掺杂区均相邻。
  9. 如权利要求8所述的半导体结构，其中，所述第三掺杂区的掺杂类型与所述第一掺杂区的掺杂类型相同，所述第三掺杂区的掺杂浓度大于或等于所述第一掺杂区的掺杂浓度。
  10. 一种半导体结构的制造方法，包括：
    形成基底，所述基底中包括第一掺杂区和包围所述第一掺杂区的第二掺杂区，所述第一掺杂区的掺杂类型与所述第二掺杂区的掺杂类型不同，所述第一掺杂区和所述第二掺杂区共同构成光电二极管；
    其中，所述第一掺杂区包括底部、中部和顶部，所述中部的掺杂浓度小于所述底部的掺杂浓度和所述顶部的掺杂浓度。
  11. 如权利要求10所述的制造方法，其中，形成所述基底的步骤包括：
    提供衬底；
    采用外延生长工艺分别在所述衬底上形成第一外延层、第二外延层和第三外延层；
    对所述第一外延层、所述第二外延层和所述第三外延层分别进行不同浓度的第二类型的掺杂，以形成初始第二掺杂区；
    对所述初始第二掺杂区的中心区域进行第一类型的掺杂，以形成所述第一掺杂区，剩余所述初始第二掺杂区作为所述第二掺杂区。
  12. 如权利要求11所述的制造方法，其中，在对所述第一外延层、所述第二外延层和所述第三外延层分别进行不同浓度的第二类型的掺杂的步骤中，所述第二外延层的掺杂浓度低于所述第一外延层和所述第三外延层的掺杂浓度，所述第三外延层的掺杂浓度低于所述第一外延层的掺杂浓度。
  13. 如权利要求11所述的制造方法，其中，在形成所述初始第二掺杂区的步骤中，沿所述第一外延层指向所述第三外延层的方向上，所述第二外延层的厚度大于所述第一外延层的厚度以及所述第三外延层的厚度。
  14. 如权利要求11所述的制造方法，还包括：
    形成第三掺杂区，所述第三掺杂区位于所述第二掺杂区中且与所述第一掺杂区相间隔；
    形成传输门结构，所述传输门结构与所述第一掺杂区和所述第三掺杂区均相邻。
  15. 如权利要求14所述的制造方法，其中，形成所述第三掺杂区的步骤包括：对远离所述第一掺杂区的所述第三外延层的部分表面进行所述第一类型的掺杂，以将部分所述第二掺杂区转化为所述第三掺杂区。
  16. 如权利要求14所述的制造方法，其中，形成所述传输门结构的步骤包括：在所述第三外延层远离所述第二外延层的一侧形成通孔，所述通孔的底部暴露出所述第一掺杂区，所述通孔的顶部侧壁暴露出所述第三掺杂区，依次在所述通孔的内壁形成介质层和导电层。
PCT/CN2022/118570 2022-08-23 2022-09-13 半导体结构及其制造方法 Ceased WO2024040644A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211013671.2A CN117673094A (zh) 2022-08-23 2022-08-23 半导体结构及其制造方法
CN202211013671.2 2022-08-23

Publications (1)

Publication Number Publication Date
WO2024040644A1 true WO2024040644A1 (zh) 2024-02-29

Family

ID=90012213

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/118570 Ceased WO2024040644A1 (zh) 2022-08-23 2022-09-13 半导体结构及其制造方法

Country Status (2)

Country Link
CN (1) CN117673094A (zh)
WO (1) WO2024040644A1 (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101720510A (zh) * 2007-06-19 2010-06-02 桑迪士克3D公司 具有减少的反向电流的结型二极管
CN103000645A (zh) * 2011-09-14 2013-03-27 英飞凌科技股份有限公司 具有可控制的光谱响应的光电探测器
CN103022069A (zh) * 2013-01-10 2013-04-03 上海中科高等研究院 图像传感器
CN204391115U (zh) * 2015-02-15 2015-06-10 格科微电子（上海）有限公司 背照式图像传感器
CN107004709A (zh) * 2014-12-22 2017-08-01 英特尔公司 防止子沟道漏电流
CN108110039A (zh) * 2016-11-25 2018-06-01 深圳尚阳通科技有限公司 超结器件及其制造方法
CN111509074A (zh) * 2020-04-29 2020-08-07 武汉新芯集成电路制造有限公司 半导体器件及其制造方法
US20210098524A1 (en) * 2019-09-30 2021-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an image sensor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101720510A (zh) * 2007-06-19 2010-06-02 桑迪士克3D公司 具有减少的反向电流的结型二极管
CN103000645A (zh) * 2011-09-14 2013-03-27 英飞凌科技股份有限公司 具有可控制的光谱响应的光电探测器
CN103022069A (zh) * 2013-01-10 2013-04-03 上海中科高等研究院 图像传感器
CN107004709A (zh) * 2014-12-22 2017-08-01 英特尔公司 防止子沟道漏电流
CN204391115U (zh) * 2015-02-15 2015-06-10 格科微电子（上海）有限公司 背照式图像传感器
CN108110039A (zh) * 2016-11-25 2018-06-01 深圳尚阳通科技有限公司 超结器件及其制造方法
US20210098524A1 (en) * 2019-09-30 2021-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an image sensor
CN111509074A (zh) * 2020-04-29 2020-08-07 武汉新芯集成电路制造有限公司 半导体器件及其制造方法

Also Published As

Publication number Publication date
CN117673094A (zh) 2024-03-08

Similar Documents

Publication Publication Date Title
US10861989B2 (en) Image sensor with an absorption enhancement semiconductor layer
US7492027B2 (en) Reduced crosstalk sensor and method of formation
US10438980B2 (en) Image sensor with a high absorption layer
CN103227183B (zh) 一种抑制背照式cmos图像传感器电学互扰的方法
US20090179293A1 (en) Image sensor and method for manufacturing the same
JP3727639B2 (ja) 固体撮像装置
US7880196B2 (en) Image sensor and method for manufacturing the same
JP7597381B2 (ja) Ｕｔｂｂ光検出器ピクセルユニット、アレイ及び方法
US7432121B2 (en) Isolation process and structure for CMOS imagers
CN103855177B (zh) 图像传感器
CN104916655B (zh) 图像传感器及制备方法、减少电学互扰的方法
US20230107371A1 (en) Global Shutter CMOS Image Sensor and Method for Making the Same
CN214152901U (zh) 一种垂直电荷转移型光子解调器
KR101002122B1 (ko) 이미지센서 및 그 제조방법
WO2024040644A1 (zh) 半导体结构及其制造方法
KR100997328B1 (ko) 이미지센서 및 그 제조방법
US20230369378A1 (en) Photodiode and manufacturing method thereof
US20090166789A1 (en) Image sensor and method for manufacturing the same
CN110034146A (zh) 图像传感器及其形成方法
KR20040065332A (ko) 이온주입영역을 소자분리막으로 사용한 시모스 이미지센서및 그 제조방법
US12439719B2 (en) CMOS image sensor
CN120344002A (zh) 短波红外图像传感器及其制造方法
CN103280451A (zh) 改善cmos图像传感器性能的方法
KR20000041454A (ko) 볼록한 형상의 포토다이오드를 갖는 이미지센서 및 그 제조방법
CN118263263A (zh) 光电传感器及其形成方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22956188

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22956188

Country of ref document: EP

Kind code of ref document: A1