WO2024040514A1 - Dispositif électronique à base de nitrure - Google Patents

Dispositif électronique à base de nitrure Download PDF

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Publication number
WO2024040514A1
WO2024040514A1 PCT/CN2022/114807 CN2022114807W WO2024040514A1 WO 2024040514 A1 WO2024040514 A1 WO 2024040514A1 CN 2022114807 W CN2022114807 W CN 2022114807W WO 2024040514 A1 WO2024040514 A1 WO 2024040514A1
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Prior art keywords
nitride
node
clamping
circuit
conduction
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PCT/CN2022/114807
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English (en)
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WO2024040514A9 (fr
Inventor
Weipeng Li
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Innoscience (Shenzhen) Semiconductor Co., Ltd.
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Application filed by Innoscience (Shenzhen) Semiconductor Co., Ltd. filed Critical Innoscience (Shenzhen) Semiconductor Co., Ltd.
Priority to CN202280004847.XA priority Critical patent/CN116134689A/zh
Priority to PCT/CN2022/114807 priority patent/WO2024040514A1/fr
Publication of WO2024040514A1 publication Critical patent/WO2024040514A1/fr
Publication of WO2024040514A9 publication Critical patent/WO2024040514A9/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches

Definitions

  • the present invention generally relates to an electronic device with clamping circuit. More specifically, the present invention relates to a nitride-based compound electronic device with clamping circuit.
  • Direct bandgap materials such as III-V compound materials have been widely used for high-power and high-frequency devices because of their low power losses and fast switching transition in comparison with silicon (Si) metal oxide semiconductor (MOS) materials.
  • silicon Si
  • MOS metal oxide semiconductor
  • GaN gallium nitride
  • FET field effect transistor
  • FIG. 1 a clamping circuit as shown in FIG. 1 can be used to address such issue.
  • the clamping circuit may include a Si Zener diode D1 and resistor Rg connected in series with a gate of a GaN transistor Q1.
  • the clamping circuit of FIG. 1 may induce a significant gate leakage current.
  • the gate-source voltage of the transistor can only be clamped to a fixed value when a driving voltage is higher than the breakdown voltage of the Zener diode.
  • the driving voltage is lower than the breakdown voltage of the Zener diode, a portion of the gate-source voltage will be lost, causing increase of conduction loss. Therefore, the conventional clamping circuit cannot be compatible with a wide range of driving voltages such as from 5V to 10V or above.
  • One objective of the present invention is to address above shortcomings of conventional clamping circuits and provide a clamping circuit design tailor-made for nitride-based transistor.
  • a nitride-based electronic device having a control terminal, a first conduction terminal and a second conduction terminal.
  • the nitride-based electronic device comprises: a main switching element having a first conduction node connected to the first conduction terminal and a second conduction node connected to the second conduction terminal; an auxiliary switching circuit having a first conduction node connected to the control terminal and a second conduction node connected to a control node of the main switching element; a clamping circuit having a first node connected to a control node of the auxiliary switching circuit and a second node connected to the second conduction node of the main switching element; a capacitor having a first electrode connected to the first node of the clamping circuit and a second electrode connected to the second node of the clamping circuit; a first resistor having a first electrode connected to the first conduction node of the auxiliary switching circuit and a second electrode connected to the first node of the clamping circuit; and a second
  • the clamping circuit By implementing the clamping circuit provided by the present invention, it is no need to connect a large value resistor in series with the transistor gate directly, the impact on driving speed of the transistor can be minimized. Moreover, the gate-source voltage of transistor can be clamped to a fixed value over a wide range of driving voltages, allowing the electronic device to have high compatibility and low conduction loss.
  • FIG. 1 shows a circuit diagram for a conventional clamping circuit
  • FIG. 2 shows a circuit block diagram for a nitride-based electronic device according to some embodiments of the present invention
  • FIG. 3 shows an exemplary main switching element in the nitride-based electronic device of FIG. 2;
  • FIG. 4 shows an exemplary auxiliary switching element in the nitride-based electronic device of FIG. 2;
  • FIG. 5 shows another exemplary auxiliary switching element in the nitride-based electronic device of FIG. 2;
  • FIG. 6 shows an exemplary clamping circuit in the nitride-based electronic device of FIG. 2;
  • FIG. 7 shows another exemplary auxiliary switching element in the nitride-based electronic device of FIG. 2;
  • FIG. 8 shows a cross sectional view of various functional components in an IC chip 50 for forming the electronic device according to the present invention.
  • FIG. 9 shows a flowchart of a method for manufacturing a nitride-based electronic device according to one embodiment of the present invention.
  • FIG. 2 is a circuit block diagram for an electronic device 100 according to some embodiments of the present invention. As shown in FIG. 2, the electronic device 100 may have a control terminal Ctrl, a conduction terminal Cdct1 and a conduction terminal Cdct2.
  • the electronic device 100 may comprise a main switching element 120.
  • the main switching element 120 may have a control node 121.
  • the main switching element 120 may have a first conduction node 122 connected to the first conduction terminal Cdct1.
  • the main switching element 120 may have a second conduction node 123 connected to the second conduction terminal Cdct2.
  • the electronic device 100 may further comprise an auxiliary switching circuit 140.
  • the auxiliary switching circuit 140 may have a control node 141.
  • the auxiliary switching circuit 140 may have a first conduction node 142 connected to the control terminal Ctrl.
  • the auxiliary switching circuit 140 may have a second conduction node 143 connected to the control node 121 of the main switching element 120.
  • the electronic device 100 may further comprise a clamping circuit 160 having a first node 161 and a second node 162.
  • the clamping circuit 160 may have a first node 161 connected to the control node 141 of the auxiliary switching circuit 140.
  • the clamping circuit 160 may have a second node 162 connected to the second conduction node 123 of main switching element 120 and the second conduction terminal Cdct2.
  • the electronic device 100 may further comprise a capacitor C1.
  • the capacitor C1 may have a first electrode connected to the first node 161 of the clamping circuit 160 and the control node 141 of the auxiliary switching circuit 140.
  • the capacitor C1 may have a second electrode connected to the second node 162 of the clamping circuit 160, the second conduction node 123 of the main switching element 120 and the second conduction terminal Cdct2.
  • the electronic device 100 may further comprise a first resistor R1.
  • the first resistor R1 may have a first electrode connected to the first conduction node 142 of the auxiliary switching circuit 140 and the control terminal Ctrl.
  • the first resistor R1 may have a second electrode connected to the control node 141 of the auxiliary switching circuit 140 and the first node 161 of the clamping circuit 160.
  • the electronic device 100 may further comprise a second resistor R2.
  • the second resistor R2 may have a first electrode connected to the control node 121 of the main switching element 120 and the second conduction node 143 of the auxiliary switching circuit.
  • the second resistor R2 may have a second electrode connected to the second node 162 of the clamping circuit 160, the second conduction node 123 of the main switching element 120, the second electrode of the capacitor C1 and the second conduction terminal Cdct2.
  • the main switching element 120 may be a main nitride-based transistor Qm having a gate G acting as the control node 121 of the main switching element, a drain D acting as the first conduction node 122 of the main switching element and a source S acting as the second conduction node 123 of the main switching element.
  • the main nitride-based transistor Qm is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT) .
  • the auxiliary switching circuit 140 may comprise an auxiliary nitride-based depletion-mode (D-mode) transistor Qa having a gate G connected to the control node 141 of the auxiliary switching circuit, a drain D connected to the first conduction node 142 of the auxiliary switching circuit and a source S connected to the second conduction node 143 of the auxiliary switching circuit.
  • the auxiliary nitride-based D-mode transistor Qa may be a AlGaN/GaN D-mode HEMT.
  • the auxiliary switching circuit 140 may comprise an auxiliary nitride-based enhance-mode E-mode transistor Qa having a gate G connected to the control node 141 of the auxiliary switching circuit, a drain D connected to the first conduction node 142 of the auxiliary switching circuit and a source S connected to the second conduction node 143 of the auxiliary switching circuit.
  • the auxiliary switching circuit may further comprise a diode D1 having an anode connected to the source of the auxiliary nitride-based E-mode transistor Qa and a cathode connected to the drain of the auxiliary nitride-based E-mode transistor Qa.
  • the auxiliary nitride-based E-mode transistor Qa may be a AlGaN/GaN E-mode HEMT
  • the clamping circuit 160 may comprise a clamping rectifier Dc having an anode connected to the first node 161 of the clamping circuit 160 and a cathode connected to the second node 162 of the clamping circuit 160.
  • the clamping rectifier Dc may be a clamping diode or a clamping nitride-based transistor having a source and a gate electrically shorted together to act as the anode of the clamping rectifier and a drain to act as the cathode of the clamping rectifier.
  • the clamping nitride-based transistor may be a AlGaN/GaN enhancement-mode (E-mode) HEMT.
  • the clamping circuit 160 may comprise a plurality of clamping rectifiers Dc1, Dc2, ..., DcN connected in series, where N is the number of clamping rectifiers.
  • the clamping circuit 160 may include a first clamping rectifier Dc1 having an anode connected to the first node 161 of the clamping circuit 160.
  • the clamping circuit 160 may include a last clamping rectifier DcN having a cathode connected to the second node 162 of the clamping circuit 160.
  • each of the plurality of clamping rectifiers Dc1, Dc2, ..., DcN may be a clamping diode or a clamping nitride-based transistor having a source and a gate electrically shorted together to act as an anode of the clamping rectifier and a drain to act as a cathode of the clamping rectifier.
  • the clamping nitride-based transistor Qc may be a AlGaN/GaN enhancement-mode (E-mode) HEMT.
  • the electronic device 100 may be integrated into a nitride-based integrated circuit (IC) chip.
  • the main switching element 120, the auxiliary switching circuit 140 and the clamping circuit 160 may be integrated into the IC chip 50.
  • the main switching element 120, the auxiliary switching circuit 140, the clamping circuit 160, the first resistor R1, the second resistor R2 and the capacitor C1 may be integrated into a nitride-based integrated circuit IC chip.
  • FIG. 8 shows a cross sectional view of various functional components in an IC chip 50 for forming the electronic device 100 according to the present invention.
  • the functional components may include one or more transistor structure 50Q, one or more rectifier structure 50D, one or more resistor structure 50R and one or more capacitor structure 50C.
  • the IC chip 50 may comprise a substrate 502, one or more nitride-based semiconductor layers 504, 506, gate structures 510, source/drain (S/D) electrodes 516, one or more second passivation layers 524, 526 and 528, one or more conductive vias 532, 536, one or more conductive layers 542, 546, a protection layer 554, conductive pads 570 and one or more isolation regions 580.
  • a substrate 502 one or more nitride-based semiconductor layers 504, 506, gate structures 510, source/drain (S/D) electrodes 516, one or more second passivation layers 524, 526 and 528, one or more conductive vias 532, 536, one or more conductive layers 542, 546, a protection layer 554, conductive pads 570 and one or more isolation regions 580.
  • the substrate 502 may be a semiconductor substrate.
  • the exemplary materials of the substrate 502 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable semiconductor materials.
  • the substrate 502 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) .
  • the substrate 502 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
  • the nitride-based semiconductor layer 504 is disposed over the substrate 502.
  • the exemplary materials of the nitride-based semiconductor layer 504 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
  • the exemplary structures of the nitride-based semiconductor layer 504 can include, for example but are not limited to, multilayered structure, superlattice structure and composition-gradient structures.
  • the nitride-based semiconductor layer 506 is disposed on the nitride-based semiconductor layer 504.
  • the exemplary materials of the nitride-based semiconductor layer 506 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layers 504 and 506 are selected such that the nitride-based semiconductor layer 506 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 504, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.
  • the nitride-based semiconductor layer 504 is an undoped GaN layer having a bandgap of approximately 3.4 eV
  • the nitride-based semiconductor layer 506 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV.
  • the nitride-based semiconductor layers 504 and 506 can serve as a channel layer and a barrier layer, respectively.
  • a triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
  • the nitride-based IC chip is available to include one or more GaN-based high-electron-mobility transistors (HEMT) .
  • HEMT high-electron-mobility transistors
  • the nitride-based IC chip may further include a buffer layer, a nucleation layer, or a combination thereof (not illustrated) .
  • the buffer layer can be disposed between the substrate 502 and the nitride-based semiconductor layer 504.
  • the buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 502 and the nitride-based semiconductor layer 504, thereby curing defects due to the mismatches/difference.
  • the buffer layer may include a III-V compound.
  • the III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof.
  • the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
  • the nucleation layer may be formed between the substrate 502 and the buffer layer.
  • the nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 502 and a III-nitride layer of the buffer layer.
  • the exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
  • the gate structures 510 are disposed on/over/above the second nitride-based semiconductor layer 506.
  • Each of the gate structures 510 may include an optional gate semiconductor layer 512 and a gate metal layer 514.
  • the gate semiconductor layer 512 and the gate metal layer 514 are stacked on the nitride-based semiconductor layer 506.
  • the gate semiconductor layer 512 are between the nitride-based semiconductor layer 506 and the gate metal layer 514.
  • the gate semiconductor layer 512 and the gate metal layer 514 may form a Schottky barrier.
  • the nitride-based IC chip may further include an optional dielectric layer (not shown) between the gate semiconductor layer 512 and the gate metal layer 514.
  • the exemplary materials of the gate semiconductor layer 512 can include, for example but are not limited to, group III-V nitride semiconductor materials, such as GaN, AlGaN, InN, AlInN, InGaN, AlInGaN, or combinations thereof.
  • group III-V nitride semiconductor materials such as GaN, AlGaN, InN, AlInN, InGaN, AlInGaN, or combinations thereof.
  • the p-doped materials are achieved by using a impurity, such as Be, Mg, Zn, Cd, and Mg.
  • the nitride-based semiconductor layer 504 includes undoped GaN and the nitride-based semiconductor layer 506 includes AlGaN, and the doped III-V compound semiconductor layers 512 are GaN layers which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the bidirectional switching device 51 into an off-state condition.
  • the gate metal layer 514 may include metals or metal compounds.
  • the gate metal layer 514 may be formed as a single layer, or plural layers of the same or different compositions.
  • the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metallic compounds.
  • the exemplary materials of the gate metal layer 514 may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof.
  • the optional dielectric layer can be formed by a single layer or more layers of dielectric materials.
  • the exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO x layer, a SiN x layer, a high-k dielectric material (e.g., HfO 2 , Al 2 O 3 , TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , etc) , or combinations thereof.
  • a high-k dielectric material e.g., HfO 2 , Al 2 O 3 , TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , etc
  • the S/D electrodes 516 are disposed on the nitride-based semiconductor layer 506.
  • the “S/D” electrode means each of the S/D electrodes 516 can serve as a source electrode or a drain electrode, depending on the device design.
  • the S/D electrodes 516 can be located at two opposite sides of the corresponding gate structure 510 although other configurations may be used, particularly when plural source, drain, or gate electrodes are employed in the device.
  • Each of the gate structure 510 can be arranged such that each of the gate structure 510 is located between the at least two of the S/D electrodes 516.
  • the gate structures 510 and the S/D electrodes 516 can collectively act as at least one nitride-based/GaN-based HEMT with the 2DEG region.
  • the adjacent S/D electrodes 516 are symmetrical about the gate structure 510 therebetween. In some embodiments, the adjacent S/D electrodes 516 can be optionally asymmetrical about the gate structure 510 therebetween. That is, one of the S/D electrodes 516 may be closer to the gate structure 510 than another one of the S/D electrodes 516.
  • the S/D electrodes 516 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof.
  • the exemplary materials of the S/D electrodes 516 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof.
  • the S/D electrodes 516 may be a single layer, or plural layers of the same or different composition.
  • the S/D electrodes 516 may form ohmic contacts with the nitride-based semiconductor layer 506. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the S/D electrodes 516.
  • each of the S/D electrodes 516 is formed by at least one conformal layer and a conductive filling.
  • the conformal layer can wrap the conductive filling.
  • the exemplary materials of the conformal layer for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof.
  • the exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.
  • the passivation layer 524 is disposed over the nitride-based semiconductor layer 506.
  • the passivation layer 524 can be formed for a protection purpose or for enhancing the electrical properties of the device (e.g., by providing an electrically isolation effect between/among different layers/elements) .
  • the passivation layer 524 covers a top surface of the nitride-based semiconductor layer 506.
  • the passivation layer 524 may cover the gate structures 510.
  • the passivation layer 524 can at least cover opposite two sidewalls of the gate structures 510.
  • the S/D electrodes 516 can penetrate/pass through the passivation layer 524 to contact the nitride-based semiconductor layer 506.
  • the exemplary materials of the passivation layer 524 can include, for example but are not limited to, SiN x , SiO x , Si 3 N 4 , SiON, SiC, SiBN, SiCBN, oxides, nitrides, poly (2-ethyl-2-oxazoline) (PEOX) , or combinations thereof.
  • the passivation layer 524 can be a multi-layered structure, such as a composite dielectric layer of Al 2 O 3 /SiN, Al 2 O 3 /SiO 2 , AlN/SiN, AlN/SiO 2 , or combinations thereof.
  • the passivation layer 526 is disposed above the passivation layer 524 and the S/D electrodes 516.
  • the passivation layer 526 covers the passivation layer 524 and the S/D electrodes 516.
  • the passivation layer 526 can serve as a planarization layer which has a level top surface to support other layers/elements.
  • the exemplary materials of the passivation layer 526 can include, for example but are not limited to, SiN x , SiO x , Si 3 N 4 , SiON, SiC, SiBN, SiCBN, oxides, PEOX, or combinations thereof.
  • the passivation layer 526 is a multi-layered structure, such as a composite dielectric layer of Al 2 O 3 /SiN, Al 2 O 3 /SiO 2 , AlN/SiN, AlN/SiO 2 , or combinations thereof.
  • the conductive vias 532 are disposed within the passivation layer 526 and passivation layer 524.
  • the conductive vias 532 penetrate the passivation layer 526 and passivation layer 524.
  • the conductive vias 532 extend longitudinally to electrically couple with the gate structure 510 and the S/D electrodes 516, respectively.
  • the upper surfaces of the conductive vias 532 are free from coverage of the passivation layer 526.
  • the exemplary materials of the conductive vias 532 can include, for example but are not limited to, conductive materials, such as metals or alloys.
  • the conductive layer 542 are disposed on the passivation layer 526 and the conductive vias 532.
  • the conductive layer 542 are in contact with the conductive vias 532.
  • the exemplary materials of the conductive layer 542 can include, for example but are not limited to, conductive materials.
  • the conductive layer 542 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.
  • the passivation layer 528 is disposed above the passivation layer 526 and the conductive layer 542.
  • the passivation layer 528 covers the passivation layer 526 and the conductive layer 542.
  • the passivation layer 528 can serve as a planarization layer which has a level top surface to support other layers/elements.
  • the exemplary materials of the passivation layer 528 can include, for example but are not limited to, SiN x , SiO x , Si 3 N 4 , SiON, SiC, SiBN, SiCBN, oxides, PEOX, or combinations thereof.
  • the passivation layer 528 is a multi-layered structure, such as a composite dielectric layer of Al 2 O 3 /SiN, Al 2 O 3 /SiO 2 , AlN/SiN, AlN/SiO 2 , or combinations thereof.
  • the conductive vias 536 are disposed within the passivation layer 528.
  • the conductive vias 536 penetrate the passivation layer 528.
  • the conductive vias 536 extend longitudinally to electrically couple with the conductive layer 542.
  • the upper surfaces of the conductive vias 536 are free from coverage of the passivation layer 536.
  • the exemplary materials of the conductive vias 536 can include, for example, but are not limited to, conductive materials, such as metals or alloys.
  • the conductive layer 546 are disposed on the passivation layer 528 and the conductive vias 536.
  • the conductive layer 546 ss in contact with the conductive vias 536.
  • the exemplary materials of the conductive layer 546 can include, for example but are not limited to, conductive materials.
  • the conductive layer 546 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.
  • the protection layer 554 is disposed above the passivation layer 528 and the conductive layer 546.
  • the protection layer 554 covers the passivation layer 528 and the conductive layer 546.
  • the protection layer 554 can prevent the conductive layer 546 from oxidizing. Some portions of the conductive layer 546 can be exposed through openings in the protection layer 554 to form the conductive pads 570, which are configured to electrically connect to external elements (e.g., an external circuit) .
  • the conductive pads 570 may include one or more conductive pads to act as terminals of the IC chip.
  • Conductive layers 542 and 546 may also be configured to form conductor structures including, but not limited to transistor gate G, transistor source S, transistor drain D, rectifier anode A, rectifier cathode C, capacitor terminals C bottom and C top , resistor terminals R p and R N , or other conductor structures.
  • conductor structures and various functional components are described as being arranged at specific positions in FIG. 8, selection, configuration and quantity of the conductor structures and various functional components can vary depending on design specifications.
  • FIG. 9 shows a flowchart of a method for manufacturing a nitride-based electronic device having a control terminal, a first conduction terminal and a second conduction terminal according to one embodiment of the present invention.
  • the method may comprise the following steps:
  • S902 configuring a main switching element which has a control node, a first conduction node connected to the first conduction terminal and a second conduction node connected to the second conduction terminal;
  • S904 configuring an auxiliary switching circuit which has a control node, a first conduction node connected to the control terminal and a second conduction node connected to the control node of the main switching element;
  • S904 configuring a clamping circuit which has a first node connected to the control node of the auxiliary switching circuit and a second node connected to the second conduction terminal;
  • S906 forming a capacitor which has a first electrode connected to the first node of the clamping circuit and a second electrode connected to the second conduction terminal;
  • S910 forming a second resistor which has a first electrode connected to the control node of the main switching element and a second electrode connected to the second conduction terminal.
  • the main switching element is configured by forming a main nitride-based transistor having a gate acting as the control node of the main switching element, a drain acting as the first conduction node of the main switching element and a source acting as the second conduction node of the main switching element.
  • the auxiliary switching circuit is configured by forming an auxiliary nitride-based depletion-mode (D-mode) transistor having a gate connected to the control node of the auxiliary switching circuit, a drain connected to the first conduction node of the auxiliary switching circuit and a source connected to the second conduction node of the auxiliary switching circuit.
  • D-mode auxiliary nitride-based depletion-mode
  • the auxiliary switching circuit is configured by: forming an auxiliary nitride-based enhance-mode (E-mode) transistor which has a gate connected to the control node of the auxiliary switching circuit, a drain connected to the first conduction node of the auxiliary switching circuit and a source connected to the second conduction node of the auxiliary switching circuit; and forming a rectifier which has an anode connected to the source of the auxiliary nitride-based E-mode transistor and a cathode connected to the drain of the auxiliary nitride-based E-mode transistor.
  • E-mode auxiliary nitride-based enhance-mode
  • the clamping circuit is configured by forming a clamping rectifier which has an anode connected to the first node of the clamping circuit and a cathode connected to the second node of the clamping circuit.
  • the clamping rectifier is constituted with a clamping nitride-based transistor which has a source and a gate electrically shorted together to act as the anode of the clamping rectifier and a drain to act as the cathode of the clamping rectifier.
  • the clamping circuit is configured by forming a plurality of clamping rectifiers connected in series, the plurality of clamping rectifiers including a first clamping rectifier having an anode connected to the first node of the clamping circuit and a last clamping rectifier having a cathode connected to the second node of the clamping circuit.
  • each of the plurality of clamping rectifiers is constituted with a clamping nitride-based transistor having a source and a gate electrically shorted together to act as an anode of the clamping rectifier and a drain to act as a cathode of the clamping rectifier.
  • the method for manufacturing a nitride-based electronic device further comprise integrating the main switching element, the auxiliary switching circuit and the clamping circuit into a nitride-based integrated circuit (IC) chip.
  • IC integrated circuit
  • the method for manufacturing a nitride-based electronic device further comprise integrating the main switching element, the auxiliary switching circuit, the clamping circuit, the first resistor, the second resistor and the capacitor into a nitride-based IC chip.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Power Conversion In General (AREA)
  • Electronic Switches (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

L'invention concerne un dispositif électronique à base de nitrure ayant une borne de commande, une première borne de conduction et une seconde borne de conduction. Le dispositif électronique à base de nitrure comprend : un élément de commutation principal qui peut être un transistor, un circuit de commutation auxiliaire et un circuit de serrage. En mettant en œuvre le circuit de serrage fourni par la présente invention, il n'est pas nécessaire de connecter directement une résistance de grande valeur en série avec une grille du transistor, l'impact sur la vitesse d'entraînement du transistor peut être réduit au minimum. De plus, la tension grille-source du transistor peut être serrée à une valeur fixe sur une large plage de tensions d'attaque, ce qui permet au dispositif électronique d'avoir une compatibilité élevée et une faible perte de conduction.
PCT/CN2022/114807 2022-08-25 2022-08-25 Dispositif électronique à base de nitrure WO2024040514A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202280004847.XA CN116134689A (zh) 2022-08-25 2022-08-25 氮化物基电子装置
PCT/CN2022/114807 WO2024040514A1 (fr) 2022-08-25 2022-08-25 Dispositif électronique à base de nitrure

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2757688A1 (fr) * 2013-01-18 2014-07-23 HS Elektronik Systeme GmbH Circuit de transistor avec calage actif pour des conditions de fonctionnement à basse température
US20140327010A1 (en) * 2013-05-03 2014-11-06 Texas Instuments Incorporated Avalanche energy handling capable iii-nitride transistors
US20180181151A1 (en) * 2016-12-26 2018-06-28 Texas Instruments Incorporated Methods and apparatus for negative output voltage active clamping using a floating bandgap reference and temperature compensation
CN114793468A (zh) * 2022-01-18 2022-07-26 英诺赛科(苏州)半导体有限公司 用于电池管理的氮化物基双向开关装置及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2757688A1 (fr) * 2013-01-18 2014-07-23 HS Elektronik Systeme GmbH Circuit de transistor avec calage actif pour des conditions de fonctionnement à basse température
US20140327010A1 (en) * 2013-05-03 2014-11-06 Texas Instuments Incorporated Avalanche energy handling capable iii-nitride transistors
US20180181151A1 (en) * 2016-12-26 2018-06-28 Texas Instruments Incorporated Methods and apparatus for negative output voltage active clamping using a floating bandgap reference and temperature compensation
CN114793468A (zh) * 2022-01-18 2022-07-26 英诺赛科(苏州)半导体有限公司 用于电池管理的氮化物基双向开关装置及其制造方法

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