WO2024038897A1

WO2024038897A1 - Element, element manufacturing method, and photonic spin register

Info

Publication number: WO2024038897A1
Application number: PCT/JP2023/029737
Authority: WO
Inventors: 充竹中; 武壽中山; 信一高木; カシディットトープラサートポン
Original assignee: 国立大学法人東京大学
Priority date: 2022-08-18
Filing date: 2023-08-17
Publication date: 2024-02-22

Abstract

An element 100 according to the present disclosure comprises: a semiconductor portion 120 that is disposed on an insulating layer 110, extends in one direction, and is made of a Group III-V semiconductor; and a pair of metal-containing portions 130 that extend on the insulating layer 110 in a direction orthogonal to the one direction so as to sandwich the semiconductor portion 120, and that is made of a metal or an alloy.

Description

Device, device manufacturing method, and photonic spin register

The present invention relates to an element, a method for manufacturing the element, and a photonic spin register.

In recent years, the amount of data communication has continued to increase, and it is essential to improve the operating speed of photodetectors in optical communication systems. In order to achieve both broadband and high sensitivity at the same time, research is being conducted on plasmon waveguide photodetectors that use plasmon waveguides that strongly confine light in the gap between two metals. For example, Non-Patent Document 1 and Non-Patent Document 2 report a plasmon waveguide optical receiver using Si or Ge as a waveguide on a Si platform.

Furthermore, devices with minute optical waveguides are also used as optical modulators. For example, Patent Document 1 discloses a MOS optical modulator as an optical modulator using silicon photonics.

JP2018-028608A

As mentioned above, devices with various structures have been developed as devices having waveguides, but the optimal element structure has not yet been clarified. For example, there is a demand for a photoelectric conversion element, a light receiver, or an optical modulator that can realize a band of 200 GHz or more. Furthermore, there is a need for a photoelectric conversion element, a light receiver, or an optical modulator that can realize low parasitic capacitance.

The problem to be solved by the present invention is to provide an element that operates at high speed or has low parasitic capacitance.

One aspect of the present disclosure includes a semiconductor portion made of a III-V group semiconductor disposed on an insulating layer and extending in one direction; a pair of metal-containing portions extending along the metal-containing portion and made of a metal or an alloy.

In the device according to this embodiment, since the semiconductor portion is made of a III-V group semiconductor, a process in which thermal holes generated in the metal-containing portion are injected into the valence band of the semiconductor portion and/or a valence band of the semiconductor portion is performed. While suppressing the process in which electrons are excited from the electron band to the conduction band and generate electrons and holes, it is possible to generate a process in which thermoelectrons generated in the metal-containing part are injected into the conduction band of the semiconductor part. That is, the III-V group semiconductor can control the heights of the Schottky barriers for hot holes and hot electrons at the contact interface with a metal or an alloy by the effect of Fermi energy pinning. Further, since the semiconductor portion is made of a III-V group semiconductor, carrier mobility in the semiconductor portion is high. Therefore, the element according to this embodiment can realize an element with high operating speed and low parasitic capacitance.

In another aspect of the present disclosure, the energies of the top of the valence band and the bottom of the conduction band of the III-V group semiconductor are E _V and E _C , respectively, and the energy of the first metal-containing part of the pair of metal-containing parts is When the Fermi level is E _f1 , the Fermi level of the second metal-containing part of the pair of metal-containing parts is E _f2 , and the energy of light having a wavelength λ is E _λ , the semiconductor The present invention provides an element in which there is a wavelength λ at which optical confinement due to plasmon resonance occurs in the region, and the following equations (1) and (2) are satisfied.

In another aspect of the present disclosure, there is provided an element that further satisfies the following formula (3), where E _g is the band gap energy of the III-V semiconductor.

Another aspect of the present disclosure provides an element in which the metal-containing portion is an alloy of a III-V semiconductor and a metal. Because the metal-containing part is an alloy of a III-V semiconductor and a metal, the device of this embodiment can be manufactured without precise alignment of the semiconductor part and the metal-containing part.

In another aspect of the present disclosure, an element is provided that further includes voltage application means for applying a voltage between a pair of metal-containing parts.

In another aspect of the present disclosure, the III-V group semiconductor consists of at least one selected from the group consisting of Al, Ga, and In, and at least one selected from the group consisting of P and As. Provide an element.

Another aspect of the present disclosure provides an element in which the metal-containing portion includes Au, Ni, or Pt.

Another aspect of the present disclosure provides an element in which the III-V semiconductor includes InGaAs or InP, and the metal-containing portion includes an alloy of Au and InGaAs or InP, or an alloy of Ni and InGaAs or InP. do.

In another aspect of the present disclosure, an element is provided that further includes a waveguide for introducing light into the semiconductor portion.

In another aspect of the present disclosure, the waveguide and the semiconductor portion extend together in one direction, and the waveguide provides an element that is not adjacent to the pair of metal-containing portions. According to this aspect, the semiconductor part and the waveguide can be integrally formed, so manufacturing is easy.

Another aspect of the present disclosure provides an element in which the waveguide is disposed on the side opposite to the semiconductor portion with respect to the insulating layer. According to this aspect, the element according to this embodiment can be easily formed on a substrate having an existing waveguide.

Another aspect of the present disclosure provides an element that is a photoelectric conversion element, an optical modulator, or a light receiver.

Another aspect of the present disclosure provides an element that is a light receiver and generates a photocurrent when a semiconductor portion receives light.

Another aspect of the present disclosure provides a photonic spin resistor that includes an element and a spin Hall element that is electrically connected to the element and exhibits a spin Hall effect due to a photocurrent from the element.

In another aspect of the present disclosure, a method for manufacturing an element includes the steps of: forming a III-V group semiconductor layer on an insulating layer; and forming a pair of metal films facing each other on the III-V group semiconductor layer. A step of obtaining a laminate including an insulating layer, a III-V group semiconductor layer, and a metal film by forming a laminate, and firing the laminate to alloy the III-V group semiconductor and at least part of the metal film. a step of forming a pair of metal-containing parts by doing so. According to this method, the semiconductor part and the metal-containing part can be manufactured without precise alignment.

In another aspect of the present disclosure, the step of obtaining a laminate including an insulating layer, the III-V semiconductor layer, and a metal film includes forming a mask portion extending in one direction on the III-V semiconductor layer. and a step of forming a metal film on the III-V group semiconductor layer in which the mask portion is formed to form a pair of metal films facing each other with the mask portion in between, Provided is a method for manufacturing an element, which further includes a step of removing a metal film remaining without being alloyed after the step of forming a pair of metal-containing parts.

According to the present invention, it is possible to provide an element that operates at high speed or has low parasitic capacitance.

1 shows (A) a schematic perspective view and (B) a schematic cross-sectional view of an element according to an embodiment of the present invention. 2 shows a concept for realizing a single running carrier device using a device according to an embodiment of the present invention. FIG. 3 shows (A) a schematic plan view and (B) a schematic cross-sectional view of an element in another aspect according to an embodiment of the present invention. An example of a method for manufacturing an element according to an embodiment of the present invention is shown. Another example of a method for manufacturing an element according to an embodiment of the present invention is shown. An example of measurement results of optical properties of an alloy of a semiconductor and a metal is shown. An example of simulation results regarding an element according to an embodiment of the present invention is shown. Another example of simulation results regarding the element according to the embodiment of the present invention is shown. A modification of the element according to the embodiment of the present invention is shown. A modification of the method for manufacturing an element according to an embodiment of the present invention is shown.

Hereinafter, an embodiment (hereinafter referred to as "this embodiment") according to one aspect of the present invention will be described based on the drawings. In addition, in each figure, those with the same reference numerals have the same or similar configurations.

[First embodiment]
FIG. 1 is (A) a schematic perspective view and (B) a schematic cross-sectional view taken along the line XX of an element 100 according to the present embodiment. The element 100 includes a semiconductor section 120 made of a III-V semiconductor arranged on an insulating layer 110 and extending in one direction, and a semiconductor section 120 made of a III-V semiconductor arranged on the insulating layer 110 in a direction perpendicular to the one direction so as to sandwich the semiconductor section 120 therebetween. and a pair of metal-containing parts 130 that extend along the metal or alloy.

The insulating layer 110 is a layer having insulating properties. The insulating layer 110 is a layer made of, for example, aluminum oxide (Al ₂ O ₃ ), silicon oxide (SiO ₂ ), hafnium oxide (HfO ₂ ), etc., and is typically a layer made of aluminum oxide.

The semiconductor section 120 is arranged on the insulating layer 110, extends in one direction, and is made of a III-V group semiconductor. Further, the pair of metal-containing parts 130 are arranged on the surface of the insulating layer 110 on which the semiconductor part 120 is arranged (hereinafter also referred to as "first main surface") so as to sandwich the semiconductor part 120 therebetween. extends along a direction perpendicular to the direction. Therefore, the first metal-containing part 131 and the second metal-containing part 132 are arranged on both sides of the linear semiconductor part 120 in electrical and physical contact. This constitutes a plasmon waveguide. Note that the pair of metal-containing parts 130 may have other configurations as long as optical confinement occurs in the semiconductor part 120 due to plasmon resonance and electron exchange occurs between the metal-containing part 130 and the semiconductor part 120. It's okay to stay.

When light enters the semiconductor section 120, surface plasmon polariton is generated, and the incident light is confined within the semiconductor section 120. The element 100 is used as a photoelectric conversion element, a light receiver, etc. by detecting hot carriers generated by surface plasmon as photocurrent, for example.

In conventional plasmon waveguide light receivers such as those disclosed in Non-Patent Document 1 and Non-Patent Document 2, surface plasmons generate hot electrons and hot holes, thereby generating photocurrent. Generally, electrons move much faster than holes, so the movement of holes dominates the operating speed of a light receiver (the same applies to photoelectric conversion elements and optical modulators).

In the device 100 according to this embodiment, since the semiconductor portion 120 is made of a III-V group semiconductor, it is possible to control the energy barrier at the interface between the semiconductor portion 120 and the metal-containing portion 130. A single traveling carrier receiver may be provided in which a current is generated. This concept will be explained using FIG. 2.

FIG. 2 is a diagram illustrating three processes in which a photocurrent may occur when a driving voltage V _bias is applied to the first metal-containing portion 131 in the device 100. In FIG. 2, the energies at the top of the valence band and the bottom of the conduction band of the III-V group semiconductor (semiconductor portion 120) are E _V and E _C , respectively, and the Fermi level of the first metal-containing portion 131 is E _f1 . , the Fermi level of the second metal-containing portion 132 is shown as E _f2 , and the band gap energy of the III-V group semiconductor (semiconductor portion 120) is shown as E _g .

The three processes that can generate a photocurrent in the element 100 include a process in which hot holes generated in the first metal-containing portion 131 are injected into the valence band of the semiconductor portion 120, shown in (1) in FIG. A process in which thermionic electrons generated in the second metal-containing portion 132 are injected into the conduction band of the semiconductor portion 120, shown as (2) in FIG. Examples include processes in which electrons are excited from the band to the conduction band, producing electrons and holes.

In order to increase the operating speed of the element 100, it is preferable to suppress the generation of photocurrent due to holes, that is, it is preferable to suppress the process (1) and/or the process (3) in FIG. . When the wavelength of light that enters the semiconductor portion 120 and causes surface plasmon polaritons is λ, and the energy of the light is _Eλ , it is preferable that the following equations (1) and (2) hold true. The following formula (1) means that the process (1) in Figure 2 does not occur or does not substantially occur, and the following formula (2) means that the process (2) in Figure 2 does not occur. means.

Furthermore, it is more preferable that the following equation (3) holds true. Equation (3) below means that the process (3) in FIG. 2 does not occur or does not substantially occur.

Note that the wavelength λ of the light in the above equation is not particularly limited, but may be, for example, 1550 nm, and E _λ in this case is 0.80 eV. The wavelength λ of the light may be in the infrared region.

In the device 100 according to this embodiment, since the semiconductor portion 120 is made of a III-V group semiconductor, the process (2) in FIG. process can occur. In other words, at the contact interface with a metal or alloy, a III-V semiconductor can increase the values on the right-hand side of the above equations (1) and (2) (respectively, thermal holes and thermal electrons) due to the effect of Fermi energy pinning. (corresponding to the energy of the Schottky barrier) can be controlled. Therefore, the element 100 can realize an element with high operating speed and low parasitic capacitance.

The material constituting the semiconductor section 120 is not particularly limited as long as it is a III-V group semiconductor. The III-V group semiconductor means a semiconductor consisting of a III(13) group element and a V(15) group element. Examples of III-V group semiconductors include semiconductors made of at least one selected from the group consisting of Al, Ga, and In, and at least one selected from the group consisting of P and As. . Specific examples include InP, InGaAs, InGaAsP, AlInGaAsP, AlInGaAs, GaAs, and AlGaAs. Among these, InP and InGaAs are preferred. Note that the III-V semiconductor may be doped.

For example, when InP is used as the material constituting the semiconductor part 120, the values on the right side of the above equations (1) and (2) (thermal holes and (corresponding to the energy of the Schottky barrier for thermionic electrons) are approximately 0.9 eV and approximately 0.4 eV. This is due to the effect of Fermi level pinning on the interface defects of InP. Further, the value on the right side of the above equation (3) (corresponding to the energy of the band gap of InP) is about 1.3 eV. Therefore, when the wavelength λ is 1550 nm and InP is used for the semiconductor portion 120, ideally, the above equations (1) to (3) hold true.

The width of the semiconductor portion 120 (indicated by w in FIG. 1B) is not particularly limited as long as it is a size that allows surface plasmon to occur, and may be, for example, 300 nm or less, 250 nm or less, 200 nm or less, 150 nm or less, or 100 nm or less. It's fine. The width w may be, for example, 10 nm or more, 20 nm or more, 30 nm or more, or 50 nm or more. The smaller the width w, the higher the confinement effect by surface plasmons, and the higher the sensitivity of the element. Furthermore, the smaller the width w, the shorter the distance that carriers move in the semiconductor section 120, so the operating speed can be increased.

The material constituting the metal-containing portion 130 is not particularly limited as long as it is a metal or an alloy. The metal contained in the metal-containing portion 130 is not particularly limited as long as it can generate surface plasmon polariton, and examples thereof include Au, Ni, and Pt. The metal or alloy contained in the metal-containing portion 130 may have a negative dielectric constant at the wavelength of the light used, for example, may have a negative dielectric constant in the infrared region, such as 1550 nm. The dielectric constant may be negative.

From the viewpoint of ease of manufacture, the metal-containing portion 130 is preferably an alloy of a III-V group semiconductor that constitutes the semiconductor portion 120 and a metal. That is, according to this aspect, the element 100 can be manufactured without precise alignment of the semiconductor part and the metal-containing part. A method for manufacturing the element according to this embodiment will be described later.

The material constituting the first metal-containing portion 131 and the material constituting the second metal-containing portion 132 may be the same or different. For example, the first metal-containing portion 131 and the second metal-containing portion 132 may be an alloy of a III-V group semiconductor forming the semiconductor portion 120 and a metal. In this case, the metals forming the alloy in the first metal-containing portion 131 and the second metal-containing portion 132 may be the same or different.

In one embodiment, the III-V semiconductor of the semiconductor portion 120 may include InGaAs or InP, and the metal-containing portion 130 may include an alloy of Au and InGaAs or InP, or an alloy of Ni and InGaAs or InP. . In one embodiment, the III-V semiconductor of the semiconductor portion 120 may be InGaAs or InP, and the metal-containing portion 130 may be an alloy of Au and InGaAs or InP, or an alloy of Ni and InGaAs or InP. .

The element 100 further includes a waveguide 140 for introducing light into the semiconductor section 120. The waveguide 140 is connected to one end of the semiconductor section 120 on the first main surface of the insulating layer 110 in order to introduce light into the semiconductor section 120. In FIG. 1, the waveguide 140 and the semiconductor part 120 extend in one direction as one, and the waveguide 140 is not adjacent to the pair of metal-containing parts 130.

The width of the waveguide 140 may be larger than the width w of the semiconductor section 120, and the joint portion between the waveguide 140 and the semiconductor section 120 may have a tapered shape in which the width becomes smaller toward the semiconductor section 120 side.

The material constituting the waveguide 140 may be a material that can be used as a waveguide in the field of photonics. From the viewpoint of ease of manufacture, the waveguide 140 may be made of the same material as the semiconductor section 120.

The element 100 may further include voltage application means for applying a voltage between the pair of metal-containing parts 130. For example, a driving voltage that makes the first metal-containing part 131 have a positive potential with respect to the second metal-containing part 132 (electrons flow from the first metal-containing part 131 to the second metal-containing part 132) is applied. A configuration may also be adopted in which a photocurrent is generated in an external circuit connected to the second metal-containing portion 132 by applying a driving voltage such as that shown in FIG.

[Second embodiment]
FIG. 3 is (A) a schematic perspective view and (B) a schematic cross-sectional view taken along the line XX of the element 200 according to the present embodiment. The element 200 is arranged on an insulating layer 210 and includes a semiconductor portion 220 made of a III-V semiconductor that extends in one direction, and a semiconductor portion 220 made of a III-V semiconductor that is placed on the insulating layer 210 in a direction perpendicular to the one direction so as to sandwich the semiconductor portion 220 therebetween. a pair of metal-containing parts 230 extending along and made of metal or an alloy. The element 200 shown in FIG. 3 differs from the element 100 shown in FIG. 1 mainly in the arrangement position of the waveguide 240. Below, the configuration of the element 200 according to changes from the element 100 shown in FIG. 1 will be explained, and other explanations will be omitted. The omitted configurations may be the same as or similar to the corresponding configurations in the element 100 shown in FIG. 1.

The insulating layer 210 is a layer having insulating properties. The insulating layer 210 is, for example, a thin film of aluminum oxide (Al ₂ O ₃ ), silicon oxide (SiO ₂ ), hafnium oxide (HfO ₂ ), or the like, and is typically a thin film of aluminum oxide. The thickness of the insulating layer 210 is desirably made as thin as possible in order to improve the efficiency of the element (for example, sensitivity as a light receiver, modulation efficiency as a photoelectric conversion element or optical modulator, etc.). In order to suppress an increase in leakage current due to the quantum tunnel effect, the thickness may be, for example, 3 nm or more. The thickness of the insulating layer 210 may be, for example, about 5 nm to 10 nm.

The element 200 further includes a waveguide 240 for introducing light into the semiconductor section 220. The waveguide 240 is arranged on the surface of the insulating layer 210 opposite to the first main surface (hereinafter also referred to as "second main surface") in order to introduce light into the semiconductor section 220. In FIG. 3, the waveguide 240 extends in the same direction as the semiconductor section 220 and is arranged to overlap the semiconductor section 220 in plan view.

The width of the waveguide 240 may be larger than the width w of the semiconductor section 220. The metal-containing portion 230 may have a tapered portion 230T that is not adjacent to the semiconductor portion 220. In the tapered portion 230T, the distance between the pair of metal-containing portions 230 may be configured to become narrower from the waveguide 240 side to the semiconductor portion 220 side in a plan view of the element 200.

The material constituting the waveguide 240 may be a material that can be used as a waveguide in the field of photonics. In the embodiment shown in FIG. 3, the element 200 may be constructed of separate materials since the semiconductor portion 220 and the waveguide 240 are not in physical contact. The waveguide 240 may be made of, for example, a silicon-based material.

The element 200 includes, around the waveguide 240, a cladding portion 250 made of a material having a lower refractive index than the waveguide 240. The cladding portion 250 may be hollow, for example, or may be made of a material such as SiO ₂ .

The element 200 may further include voltage application means for applying a voltage between the pair of metal-containing parts 230. For example, a driving voltage that makes the first metal-containing part 231 have a positive potential with respect to the second metal-containing part 232 (electrons flow from the first metal-containing part 231 to the second metal-containing part 232 A configuration may also be adopted in which a photocurrent is generated in an external circuit connected to the second metal-containing portion 232 by applying a driving voltage such as that shown in FIG.

[Element manufacturing method]
A method for manufacturing an element according to this embodiment will be explained using FIGS. 4 and 5. However, it goes without saying that methods other than those described in detail below can be used as a method for manufacturing the element according to this embodiment.

The method for manufacturing the device according to this embodiment includes the steps of forming a III-V group semiconductor layer on the insulating layer, and forming a pair of metal films facing each other on the III-V group semiconductor layer. A step of obtaining a laminate including an insulating layer, a III-V semiconductor layer, and a metal film, and firing the laminate to alloy the III-V semiconductor and at least a portion of the metal film. forming a metal-containing portion.

FIG. 4 is a diagram showing an example of a method for manufacturing the element 100 shown in FIG. 1. First, as a first step, a III-V semiconductor layer 410 is formed on the insulating layer 110, as shown in FIG. 4(A). The method for forming the III-V semiconductor layer 410 is not particularly limited, and various semiconductor layer forming methods can be used. For example, wafer bonding, Metal-Organic Vapor Phase Epitaxy, MOCVD (Metal-Organic Chemical Vapor Deposition), or the like may be used.

For patterning the III-V group semiconductor layer 410, a lithography apparatus such as an electron beam lithography apparatus or an ultraviolet irradiation apparatus may be used, for example. After patterning, a III-V semiconductor layer 410 processed into a desired pattern can be obtained by dry etching or wet etching.

As a second step, as shown in FIG. 4B, a stacked layer including the insulating layer 110, the III-V semiconductor layer 410, and the metal film 420 is formed by forming a pair of metal films 420 facing each other. get. The method for forming the metal film 420 is not particularly limited, and various metal film forming methods can be used. For example, sputtering, vapor deposition, etc. may be used. The thickness of the metal film 420 is not particularly limited, but may be, for example, 50 nm to 500 nm.

For patterning the metal film 420, for example, a lithography apparatus such as an electron beam lithography apparatus or an ultraviolet exposure apparatus may be used. After patterning, a metal film 420 processed into a desired pattern can be obtained by dry etching or wet etching. In patterning the metal film 420, in the next step, when the III-V group semiconductor and the metal are alloyed, the metal diffuses in the plane direction and an alloy is formed in a wider area than the patterned area of the metal film. The pattern of the metal film 420 may be designed in consideration of the possibility that the metal film 420 may be

In the third step, as shown in FIG. 4(C), the laminate obtained in the second step is fired to alloy the III-V group semiconductor and at least a portion of the metal film, thereby forming a pair. A metal-containing portion 130 is formed. The entire metal film may be alloyed with the III-V group semiconductor, or a portion thereof may be alloyed with the III-V group semiconductor, and an unalloyed portion may remain after firing. The firing temperature and firing time may be appropriately selected depending on the type of III-V semiconductor and metal.

The method for manufacturing an element according to this embodiment may include steps other than the above-mentioned steps described using FIG. 4. For example, the method for manufacturing an element according to the present embodiment may include a step of surface treatment of the III-V semiconductor layer 410 after forming the III-V semiconductor layer 410 and before forming the metal film 420. . A surface treatment step may be performed to promote alloying of the III-V semiconductor and metal. Further, the method for manufacturing an element according to the present embodiment may include a step of removing the unalloyed metal film after alloying the III-V group semiconductor and the metal.

FIG. 5 is a diagram showing an example of a method for manufacturing the element 200 shown in FIG. 3. According to the manufacturing method shown in FIG. 5, the element according to this embodiment can be easily formed on a substrate having an existing waveguide.

First, as a first step, as shown in FIG. It is bonded to a substrate on which an insulating layer 521 is formed. As the bonding method, for example, wafer bonding or the like may be used. As a result, as shown in FIG. 5B, the III-V semiconductor layer 510 is provided on the first main surface of the insulating layer 210, and the waveguide 240 is provided on the second main surface opposite to the first main surface. A laminate having a cladding portion 250 and a cladding portion 250 is obtained.

As a second step, as shown in FIG. 5C, a mask layer 530 is formed to cover the III-V semiconductor layer 510. The mask layer 530 may be, for example, a SiO ₂ layer formed by plasma-enhanced chemical vapor deposition (PECVD) or the like.

As a third step, as shown in FIG. 5D, a stacked layer including the insulating layer 210, the III-V semiconductor layer 510, and the metal film 540 is formed by forming a pair of metal films 540 facing each other. get. The method for forming the metal film 540 is not particularly limited, and various metal film forming methods can be used. For example, sputtering, vapor deposition, and other methods used for pad formation may be used.

As the fourth step, as shown in FIG. 5(E), the laminate obtained in the third step is fired to alloy the III-V group semiconductor and at least a portion of the metal film, thereby forming a pair. A metal-containing portion 230 is formed. The entire metal film may be alloyed with the III-V group semiconductor, or a portion thereof may be alloyed with the III-V group semiconductor, and an unalloyed portion may remain after firing. The firing temperature and firing time may be appropriately selected depending on the type of III-V semiconductor and metal.

The method for manufacturing an element according to this embodiment may include steps other than the above-mentioned steps described using FIG. 5. For example, the method for manufacturing an element according to the present embodiment may include a surface treatment step of the III-V semiconductor layer 510 after forming the III-V semiconductor layer 510 and before forming the mask layer 530. . A surface treatment step may be performed to promote alloying of the III-V semiconductor and metal. Further, the method for manufacturing an element according to this embodiment may include a step of removing the mask layer 530 and the unalloyed metal film 540 after alloying the III-V semiconductor and the metal.

[Application]
The element according to this embodiment can be used as a photoelectric conversion element, an optical modulator, or a light receiver.
For example, in the device according to this embodiment, taking the device 100 shown in FIG. 1 as an example, the first metal-containing portion 131 It can be used as a light receiver by applying a driving voltage so that the potential of the second metal-containing portion 132 becomes positive and detecting the photocurrent from the second metal-containing portion 132.

Alternatively, the element according to the present embodiment may be explained using the element 100 shown in FIG. 1 as an example. When made incident, it can be used as an electro-absorption optical modulator. When used as an optical modulator, the semiconductor section 120 is preferably made of InGaAsP or has a multiple quantum well structure (MQS).

When the element according to this embodiment is used as a light receiver, it includes the element according to this embodiment and a spin Hall element that is electrically connected to the element and exhibits a spin Hall effect by photocurrent from the element. A photonic spin register may be provided. For the detailed structure of the photonic spin register including a plasmon waveguide light receiver, reference can be made to International Publication No. 2022/158545.

Such a photonic spin register consists of a shift register section having a magnetic layer extending in one direction, and a photoreceiver section (main unit) that receives a pulse amplitude modulated optical signal input in series and converts it into a photocurrent. an element according to an embodiment), and a spin Hall element that is electrically connected to a photoreceiver, is laminated on a part of the magnetic layer, and exhibits a spin Hall effect when a photocurrent from the photoreceptor flows. may be provided. When a photocurrent flows through the spin Hall element, spin information is written by the spin-orbit torque acting on the magnetic order of the magnetic domains of the magnetic layer. When a unidirectional shift current is applied to the shift register section, the domain wall moves within the magnetic layer, and spin information written in the magnetic domain moves and is buffered in the magnetic layer.

The operating speed of the element according to this embodiment may be, for example, 100 GHz or more, 200 GHz or more, 400 GHz or more, 500 GHz or more, or 1 THz or more. The upper limit of the operating speed is not particularly limited, but may be, for example, 10 THz or 5 THz.

In a photonic spin resistor, if a photodetector with a parasitic capacitance of about 1 fF and a load resistance of 100 Ω are used in combination, the operating speed determined by the RC time constant will be close to 1 THz. On the other hand, when the operating speed approaches 1 THz, the operating speed is determined by the time it takes the carrier to travel in the light receiver. The carrier travel time is dominated by the travel time in the semiconductor portion. The device according to this embodiment is preferable in that the semiconductor portion is made of a III-V group semiconductor, so that the carrier velocity in the semiconductor portion is high and the travel time in the semiconductor portion can be shortened.

[Optical property evaluation]
Hereinafter, the optical constants of an alloy of a III-V group semiconductor and a metal were measured, and the applicability of such an alloy to the device according to the present embodiment was verified through simulation.

After several types of metals were deposited on an InP bulk substrate or an InGaAs bulk substrate, alloying was performed by annealing. When using an InP substrate, it is immersed in BHF (buffered hydrofluoric acid for semiconductors) for 15 seconds to treat the natural oxide film on the surface; metal is deposited using an electron beam evaporator; RTA (rapid thermal annealing) is performed in a nitrogen atmosphere. ) was used for annealing. At this time, the RTA conditions were 250° C. and 1 minute.

When using InGaAs, an In _0.53 Ga _0.47 As layer with a thickness of 500 nm is formed on the InP substrate by metal organic vapor phase epitaxy; the surface of the InGaAs layer is cleaned with BHF; and RF (Radio Frequency) sputtering is performed. A metal layer with a thickness of 130 nm was formed using the following steps; thereafter, heat treatment was performed at 300° C. for 1 minute in a nitrogen atmosphere.

The optical constants of the prepared alloy sample and a sample with only metal deposited before annealing were measured by spectroscopic ellipsometry. Afterwards, cross-sectional mode analysis was performed based on the measurement results. As examples of measurement results, graphs in which the real part and imaginary part of the permittivity of Au-InGaAs and Au are plotted for each wavelength are shown in FIGS. 6(a) and 6(b), respectively. It was found that the real part of the complex dielectric constant of the Au-InGaAs alloy is almost the same as that of Au, and has a negative value of about -100 at a wavelength of 1550 nm. This suggests that the propagating surface plasmon polariton required in the plasmon waveguide exists at the Au-InGaAs alloy/semiconductor interface.

Similarly, it was found that the real part of the dielectric constant of the alloy of InP and metal is about -80 for Au-InP, about 0 for Pt-InP, and about -18 for Ni-InP. It has also been found that in Pt-InP, the real part of the dielectric constant is negative if the wavelength is in the range of about 200 nm to 1500 nm.

Based on the complex relative permittivity obtained in the measurement, the metal-containing part (alloy of III-V group semiconductor and metal) / semiconductor part (III-V group semiconductor) / metal-containing part (III-V group semiconductor) / metal-containing part (III-V group semiconductor) / metal-containing part (III-V group semiconductor - Cross-sectional mode analysis of the structure (alloy of group V semiconductor and metal) was performed. As an example of the measurement results, FIG. 7(a) shows the analysis results at a wavelength of 1550 nm in the Au-InGaAs alloy/InGaAs/Au-InGaAs alloy structure. FIG. 7(b) shows the analysis results at a wavelength of 1550 nm in the Au/InGaAs/Au structure. As shown in FIG. 7, it was found that a plasmonic optical confinement mode in which the optical electric field is concentrated in the InGaAs portion can be obtained even when the Au-InGaAs alloy is used, as in the case where Au is used. Similarly, cross-sectional mode analysis was performed for the case where Ni-InP or Au-InP alloy and InP were used, and it was confirmed that an optical confinement mode existed in the plasmon waveguide structure portion.

FIG. 8 shows the propagation of an optical electric field in a plasmonic waveguide having an Au-InGaAs/InGaAs/Au-InGaAs structure. The upper diagram in FIG. 8 is a plan view showing the arrangement of materials, and the lower diagram in FIG. 8 is a simulation result. It was found that due to strong optical confinement, input light is absorbed with a device length of about 1 μm.

From the above results, it was found that the alloy of III-V group semiconductor and metal is applicable to the element according to this embodiment.

[Modified example]
The present embodiment described above is an illustration for explaining the present invention, and the present invention is not intended to be limited to the present embodiment, and the present invention can be modified in various ways without departing from the gist thereof. be.

For example, the element according to this embodiment may have a semiconductor portion 920 protruding from a pair of metal-containing portions 930 and forming a rib structure, as in an element 900 whose schematic cross-sectional view is shown in FIG. good. According to this aspect, the thickness of the metal-containing portion can be made relatively thinner than that of the element 100 shown in FIG. 1, which may enable easier manufacturing. In the element 900 shown in FIG. 9, the thickness of the metal-containing portion 930 (931, 932) may be, for example, 100 nm or more and 200 nm or less. Similarly, in the element 200 shown in FIG. 3, the semiconductor portion 220 may protrude from the pair of metal-containing portions 230.

Furthermore, in the method for manufacturing an element according to the present embodiment, patterning of the metal-containing portion may be performed by patterning a mask portion. That is, as a modification of the method for manufacturing an element according to the present embodiment, the step of forming a pair of metal films includes the step of forming a mask portion extending in one direction on the III-V group semiconductor layer; The method may include a step of forming a pair of metal films facing each other with the mask part in between by forming a metal film on the III-V group semiconductor layer in which the mask part is formed.

A modification of this manufacturing method will be explained using FIG. 10. First, as a first step, a III-V semiconductor layer 1010 is formed on an insulating layer 110, as shown in FIG. 10(A). As a second step, a mask portion 1020 is formed as shown in FIG. 10(B). The depth and width of the mask portion 1020 in the paper direction of FIG. 10 may be approximately the same as the semiconductor portion to be formed. The mask portion 1020 may be made of an insulating material that does not form an alloy with the metal constituting the metal film 1030. The mask portion 1020 may be, for example, a SiO ₂ layer formed by plasma-enhanced chemical vapor deposition (PECVD) or the like.

Next, as a third step, a metal film 1030 is formed on the III-V semiconductor layer 1010 in which the mask portion 1020 is formed. Through these first to third steps, a pair of metal films facing each other with the mask portion in between can be formed. Note that, after that, in the same manner as the manufacturing method explained using FIGS. 4 and 5, the laminate is fired, the III-V group semiconductor and the metal are alloyed, and a pair of metal-containing parts is formed. .

To explain using FIGS. 10(D) and (E), in the fourth step, the laminate obtained in the third step is fired to alloy the III-V group semiconductor and the metal. A pair of metal-containing portions 130 are formed. The fifth step may include a step of removing the unalloyed metal film 1030 after alloying the III-V semiconductor and the metal (FIG. 10E). Further, the step of removing the mask portion 1020 may be included. Note that in FIG. 10, the semiconductor portion 120 may protrude from the pair of metal-containing portions 130, similar to the element 900 shown in FIG.

[Additional notes]
The present invention includes the following embodiments.
[1]
a semiconductor portion made of a III-V semiconductor disposed on the insulating layer and extending in one direction;
a pair of metal-containing parts made of a metal or an alloy and extending along a direction perpendicular to the one direction so as to sandwich the semiconductor part on the insulating layer;
element.
[2]
Let the energies of the upper valence band and the lower part of the conduction band of the III-V group semiconductor be E _V and E _C , respectively;
The Fermi level of the first metal-containing part of the pair of metal-containing parts is E _f1 ,
The Fermi level of the second metal-containing part of the pair of metal-containing parts is E _f2 ,
When the energy of light with wavelength λ is E _λ ,
There is a wavelength λ at which optical confinement occurs due to plasmon resonance in the semiconductor portion,
The following formulas (1) and (2) hold true,
The element according to [1].

[3]
When the band gap energy of the III-V group semiconductor is E _g ,
Furthermore, the following equation (3) holds true,
The element according to [2].

[4]
the metal-containing portion is an alloy of the III-V group semiconductor and a metal;
The device according to any one of [1] to [3].
[5]
further comprising voltage application means for applying a voltage between the pair of metal-containing parts;
The device according to any one of [1] to [4].
[6]
The III-V group semiconductor consists of at least one selected from the group consisting of Al, Ga, and In, and at least one selected from the group consisting of P and As,
The device according to any one of [1] to [5].
[7]
The metal-containing portion contains Au, Ni, or Pt.
The device according to any one of [1] to [6].
[8]
The III-V semiconductor includes InGaAs or InP,
The metal-containing portion includes an alloy of Au and InGaAs or InP, or an alloy of Ni and InGaAs or InP.
The device according to any one of [1] to [7].
[9]
further comprising a waveguide for introducing light into the semiconductor section,
The device according to any one of [1] to [8].
[10]
The waveguide and the semiconductor section extend as one in the one direction,
the waveguide is not adjacent to the pair of metal-containing parts;
The element according to [9].
[11]
the waveguide is arranged on a side opposite to the semiconductor section with respect to the insulating layer;
The element according to [9].
[12]
A photoelectric conversion element, a light modulator or a light receiver,
The device according to any one of [1] to [11].
[13]
It is a light receiver,
generating a photocurrent when the semiconductor section receives light;
The device according to any one of [1] to [11].
[14]
The element described in [13],
a spin Hall element that is electrically connected to the element and exhibits a spin Hall effect due to a photocurrent from the element;
Photonic spin register.
[15]
A method for manufacturing the device according to any one of [1] to [13],
forming a III-V semiconductor layer on the insulating layer;
forming a pair of metal films facing each other on the III-V group semiconductor layer to obtain a laminate including the insulating layer, the III-V group semiconductor layer, and a metal film;
forming the pair of metal-containing parts by firing the laminate and alloying the III-V group semiconductor and at least a portion of the metal film;
manufacturing method, including.
[16]
Obtaining the laminate including the insulating layer, the III-V semiconductor layer, and the metal film,
forming a mask portion extending in one direction on the III-V group semiconductor layer;
forming a pair of metal films facing each other with the mask part in between, by forming a metal film on the III-V semiconductor layer in which the mask part is formed;
including;
After the step of forming the pair of metal-containing parts, the method further includes a step of removing the remaining metal film without being alloyed.
The manufacturing method according to [15].

100,200,900...Element, 110,210,521,522...Insulating layer, 120,220,920...Semiconductor part, 130,131,132,230,231,232,930,931,932...Metal-containing part, 140, 240... Waveguide, 230T... Tapered part, 250... Clad part, 410, 510, 1010... III-V group semiconductor layer, 420, 540, 1030... Metal film, 530... Mask layer, 1020... Mask part.

Claims

a semiconductor portion made of a III-V semiconductor disposed on the insulating layer and extending in one direction;
a pair of metal-containing parts made of a metal or an alloy and extending along a direction perpendicular to the one direction so as to sandwich the semiconductor part on the insulating layer;
element.
Let the energies of the upper valence band and the lower part of the conduction band of the III-V group semiconductor be E V and E C , respectively;
The Fermi level of the first metal-containing part of the pair of metal-containing parts is E f1 ,
The Fermi level of the second metal-containing part of the pair of metal-containing parts is E f2 ,
When the energy of light with wavelength λ is E λ ,
There is a wavelength λ at which optical confinement occurs due to plasmon resonance in the semiconductor portion,
The following formulas (1) and (2) hold true,
The device according to claim 1.
When the band gap energy of the III-V group semiconductor is E g ,
Furthermore, the following equation (3) holds true,
The element according to claim 2.
the metal-containing portion is an alloy of the III-V group semiconductor and a metal;
The element according to any one of claims 1 to 3.
further comprising voltage application means for applying a voltage between the pair of metal-containing parts;
The element according to any one of claims 1 to 3.
The III-V group semiconductor consists of at least one selected from the group consisting of Al, Ga, and In, and at least one selected from the group consisting of P and As,
The element according to any one of claims 1 to 3.
The metal-containing portion contains Au, Ni, or Pt.
The element according to any one of claims 1 to 3.
The III-V semiconductor includes InGaAs or InP,
The metal-containing portion includes an alloy of Au and InGaAs or InP, or an alloy of Ni and InGaAs or InP.
The element according to any one of claims 1 to 3.
further comprising a waveguide for introducing light into the semiconductor section,
The element according to any one of claims 1 to 3.
The waveguide and the semiconductor section extend as one in the one direction,
the waveguide is not adjacent to the pair of metal-containing parts;
The element according to claim 9.
the waveguide is arranged on a side opposite to the semiconductor section with respect to the insulating layer;
The element according to claim 9.
A photoelectric conversion element, a light modulator or a light receiver,
The element according to any one of claims 1 to 3.
The element according to any one of claims 1 to 3,
a spin Hall element that is electrically connected to the element and exhibits a spin Hall effect due to a photocurrent from the element;
Photonic spin register.
A method for manufacturing an element according to any one of claims 1 to 3, comprising:
forming a III-V semiconductor layer on the insulating layer;
forming a pair of metal films facing each other on the III-V group semiconductor layer to obtain a laminate including the insulating layer, the III-V group semiconductor layer, and the metal film;
forming the pair of metal-containing parts by firing the laminate and alloying the III-V group semiconductor and at least a portion of the metal film;
manufacturing methods, including
Obtaining the laminate including the insulating layer, the III-V semiconductor layer, and the metal film,
forming a mask portion extending in one direction on the III-V group semiconductor layer;
forming a pair of metal films facing each other with the mask part in between, by forming a metal film on the III-V semiconductor layer in which the mask part is formed;
including;
After the step of forming the pair of metal-containing parts, the method further includes a step of removing the remaining metal film without being alloyed.
The manufacturing method according to claim 14.