WO2024037537A1 - 集成式封装 - Google Patents

集成式封装 Download PDF

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Publication number
WO2024037537A1
WO2024037537A1 PCT/CN2023/113107 CN2023113107W WO2024037537A1 WO 2024037537 A1 WO2024037537 A1 WO 2024037537A1 CN 2023113107 W CN2023113107 W CN 2023113107W WO 2024037537 A1 WO2024037537 A1 WO 2024037537A1
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WIPO (PCT)
Prior art keywords
unit
integrated package
light
driving transistor
emitting
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Application number
PCT/CN2023/113107
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English (en)
French (fr)
Inventor
郭家泰
傅乔
Original Assignee
嘉和半导体股份有限公司
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Publication of WO2024037537A1 publication Critical patent/WO2024037537A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission

Definitions

  • the present application relates to a semiconductor component, and in particular to an integrated package.
  • LEDs Light emitting diodes
  • micro-LED or mini-LED have become the light-emitting components of next-generation displays.
  • a conventional LED display includes a plurality of LED sub-pixels including at least one LED driven or controlled by a thin-film transistor (TFT) on a glass substrate, all of which are arranged together to Form a pixel array.
  • the driving system of the pixel array in the display includes passive matrix addressing (PM) addressing, active matrix addressing (active matrix (AM) addressing), semi-active matrix addressing (semi-AM addressing), etc. Drive System.
  • PM passive matrix addressing
  • AM active matrix
  • semi-active matrix addressing semi-active matrix addressing
  • the drive system uses amorphous silicon (Amorphous Silicon) and low temperature polysilicon (LTPS) technology to make thin film transistors on glass backplanes. Due to their low electron mobility, the efficiency of the system is even lower. Therefore, in the application of micro-LED/mini-LED displays, it is necessary to consider the integrated configuration between the LED and the drive system in the display in order to achieve high efficiency and integration.
  • Amorphous Silicon amorphous silicon
  • LTPS low temperature polysilicon
  • This application relates to an integrated package that is used to make a transistor and an energy storage unit into an integrated control component and package it on a carrier substrate for use in a driving system.
  • This application relates to an integrated package for packaging transistors and light-emitting elements on a carrier substrate for use in a driving system.
  • an integrated package including an integrated control component.
  • the integrated control element includes a switching transistor unit, a driving transistor unit and an energy storage unit.
  • the switching transistor unit includes a first source, a first drain and a first gate.
  • the driving transistor unit includes a second source, a second drain and a second gate, wherein the second gate is coupled to the first drain.
  • the energy storage unit is coupled between the second drain and the second gate.
  • the integrated package also includes a gate terminal, a drain terminal and a source terminal for external coupling.
  • an integrated package including an integrated control element and a light-emitting unit.
  • the integrated control element includes a drive transistor unit.
  • the driving transistor unit includes a source, a drain and a gate.
  • the light-emitting unit is coupled to the source.
  • the integrated package also includes a gate terminal, a drain terminal for external coupling, and a ground terminal coupled to the light-emitting unit.
  • FIG. 1 is a schematic diagram of an integrated package according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the integrated package shown in FIG. 1 being used in an active addressing system.
  • FIG. 3 is a schematic diagram of an integrated control element according to an embodiment of the present application.
  • 4A to 4C are schematic cross-sectional views of a HEMT according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the integrated package shown in FIG. 1 being used in an active addressing system.
  • FIG. 6 is a schematic diagram of an integrated package used in an active addressing system according to another embodiment of the present application.
  • FIG. 7 is a schematic diagram of the integrated package shown in FIG. 6 being used in an active addressing system.
  • FIG. 8 is a schematic diagram of an integrated package according to another embodiment of the present application.
  • FIG. 9 is a schematic diagram of the integrated package shown in FIG. 8 being used in an active addressing system.
  • FIG. 10 is a schematic diagram of an integrated package according to another embodiment of the present application.
  • FIG. 11 is a schematic diagram of the integrated package shown in FIG. 10 being used in a semi-active addressing system.
  • FIG. 12 is a schematic diagram of an integrated package according to another embodiment of the present application.
  • FIG. 13 is a schematic diagram of the integrated package shown in FIG. 12 being used in a semi-active addressing system.
  • Active addressing system 20 Semi-active addressing system 100 ⁇ 104: Integrated package 1000: Bearing unit 1001, 1001': Integrated control components 1100:Backplane 1100a: Front 1100b: Back 1101:Conductive via 111:Data cable 112:Scan line 113:Power cord 200, 200', 200": HEMT components 202:Base 204: First buffer layer 206: Second buffer layer 208: Channel layer 209: Two-dimensional electron gas 210:Barrier layer 211:Buffer structure 212: Doped layer 213: Groove 300:Package structure T1: switching transistor unit T2, T3: drive transistor unit C1: Energy storage unit S1: first source S2: second source D1: first drain D2: second drain G1: first gate G2: second gate P1: source extreme P2: Drain terminal P3: Gate terminal Vdata1 ⁇ VdataN: driving voltage SCAN1 ⁇ SCANM: scanning signal VDD: drain voltage P4: Control signal output terminal R1: red light emitting subunit
  • FIG. 1 is a schematic diagram of an integrated package 100 according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the integrated package 100 shown in FIG. 1 applied in the active addressing system 10 .
  • FIG. 3 shows a schematic diagram of an integrated control component 1001 according to an embodiment of the present application.
  • Integrated package 100 includes an integrated control component 1001 .
  • the integrated control element 1001 includes a switching transistor unit T1, a driving transistor unit T2 and an energy storage unit C1.
  • the switching transistor unit T1 includes a first source S1, a first drain D1 and a first gate G1.
  • the driving transistor unit T2 includes a second source S2, a second drain D2 and a second gate G2, wherein the second gate G2 is coupled to the first drain D1.
  • the energy storage unit C1 is coupled between the second drain D2 and the second gate G2.
  • the integrated package 100 may further include a carrying unit 1000 and an integrated control component 1001 formed on the carrying unit 1000.
  • the switching transistor unit T1 and the driving transistor unit T2 may include a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or a High Electron Mobility Transistor (HEMT).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • HEMT High Electron Mobility Transistor
  • the semiconductor material of MOSFET includes silicon (Si) or germanium (Ge).
  • the semiconductor materials of HEMT include III-V materials or SiC materials, where III-V materials include gallium nitride-based (GaN-based) or gallium arsenide-based (GaAs-based) III-V compound semiconductor materials.
  • the HEMT element itself has the characteristics of high mobility and high frequency, so it can be used in the field of switching elements (such as the switching transistor unit T1 and the driving transistor unit T2 of the present disclosure).
  • GaN-based HEMT devices have higher efficiency than traditional Si-based MOSFETs and are smaller in size, which facilitates integration with other electronic components to form an integrated die, or through die-level package to form an integrated package. Therefore, integrated die or integrated packages can replace TFTs routed on glass backplanes in traditional active, semi-active or passive addressing systems to provide higher power to the light-emitting units ED (e.g. LED components) To improve driver efficiency, users can also simplify wiring and increase performance through integrated chips or integrated packages.
  • ED light-emitting units
  • FIG. 4A to 4C are schematic cross-sectional views of HEMT devices 200, 200', and 200" according to an embodiment of the present application.
  • the HEMT devices 200, 200', and 200" are field effect transistors. It forms a heterogeneous interface by two materials with different energy gaps, forming a two-dimensional electron gas (2DEG) as a carrier channel, making the transistor suitable for high voltage, high frequency or low voltage. Noise applications.
  • 2DEG two-dimensional electron gas
  • the switching transistor unit T1 or the driving transistor unit T2 uses a gallium nitride-based depletion-mode HEMT element (Depletion-Mode HEMT, D-HEMT) 200 as an example, which is a normally open type HEMT components.
  • the HEMT device 200 includes a semiconductor stack including a buffer structure 211 , a channel layer 208 disposed on the buffer structure 211 , and a barrier layer 210 . There is a two-dimensional electron gas 209 in the channel layer 208 close to the interface with the barrier layer 210 .
  • the HEMT device 200 also includes a gate G, a drain D and a source S provided on the barrier layer 210, which are equivalent to the first source S1/second source S2 and the second source S2 of the switching transistor unit T1/driving transistor unit T2. a drain D1/second drain D2, and a first gate G1/second gate G2.
  • the HEMT device 200 may further include a substrate 202, which may be a growth substrate for semiconductor stacked epitaxial growth, and its material may include silicon or sapphire.
  • the buffer structure 211 may include AlGaN series materials, such as a first buffer layer 204 and a second buffer layer 206 sequentially stacked on the substrate 202.
  • the material of the first buffer layer 204 may be AlN, and the material of the second buffer layer 206 may be AlGaN Or GaN, but not limited to that.
  • the channel layer 208 and the barrier layer 210 are undoped layers or unintentionally doped layers.
  • the switching transistor unit T1 or the driving transistor unit T2 uses a gallium nitride-based enhancement-mode HEMT element (Enhancement-Mode HEMT, E-HEMT) 200' as an example, which is a normally-off type HEMT components.
  • the enhancement mode HEMT device 200' has a doped layer 212 between the gate G and the barrier layer 210, such as a GaN layer containing P-type doping.
  • the HEMT device 200" is also a normally-off HEMT device.
  • the normally-off HEMT device 200" has a recess in the barrier layer 210 below the gate G. slot 213. The two-dimensional electron gas 209 formed between the channel layer 208 and the barrier layer 210 is blocked by the doping layer 212 or the groove 213, thereby forming a normally-off E-HEMT device.
  • the energy storage unit C1 of the integrated control component 1001 may be a capacitor.
  • the switching transistor unit T1 and the driving transistor unit T2 are HEMT elements. One end of the energy storage unit C1 is connected to the node between the first drain D1 and the second gate G2 of the switching transistor unit T1, and the other end of the energy storage unit C1 is connected to the second drain D2. But it is not limited to this.
  • the switching transistor unit T1 and the driving transistor unit T2 are other forms of transistor elements, the other end of the energy storage unit C1 can also be connected to the second source S2.
  • the switching transistor unit T1 and the driving transistor unit T2 in the integrated control device 1001 are selected from any two of the HEMT devices 200', 200' and 200".
  • the switching transistor unit T1, the driving transistor unit T2 and The energy storage units C1 are each provided on the carrying unit 1000 in the form of a bare chip or a package covered with protective glue.
  • the integrated package 100 may include an encapsulation layer (not shown) covering the integrated control element 1001 and on the carrying unit 1000 to form an integrated package 100.
  • the energy storage unit C1 may also be the same chip or package as one of the switching transistor unit T1 and the driving transistor unit T2.
  • the switching transistor unit T1 and the driving transistor unit T2 of the integrated control element 1001 can be formed on a common substrate 202 in the form of a monolithic substrate.
  • the switching transistor unit T1, the driving transistor unit T2 and/or Or the energy storage unit C1 is integrated into one die.
  • the method of forming the co-substrate integrated control device 1001 includes: depositing a semiconductor stack on the substrate 202; selectively etching the semiconductor stack to expose a portion of the surface of the substrate 202 to separate the semiconductor stack into two active regions, respectively.
  • the gate G, the drain D and the source S are formed on the two active areas to form the switching transistor unit T1 and the driving transistor unit T2; and on the substrate 202, the switching transistor unit An energy storage unit C1 is formed on the transistor unit T1 or the driving transistor unit T2.
  • the switching transistor unit T1, the driving transistor unit T2, and the energy storage unit C1 of a common substrate can be disposed on the carrying unit 1000, and then covered with a packaging layer to form the integrated package 100.
  • the substrate 202 of the switching transistor unit T1, the driving transistor unit T2, and the energy storage unit C1 of a common substrate can replace the carrying unit 1000, that is, no additional carrying unit 1000 is needed, and the packaging layer covers the common substrate.
  • the switching transistor unit T1, the driving transistor unit T2, the energy storage unit C1 and the substrate 202 constitute an integrated control element 1001.
  • the transistors may also be bonded to the substrate 202 through wafer transfer to form the switching transistor unit T1 and/or the driving transistor unit T2 on a common substrate.
  • the surface of the substrate 202 may include a bonding layer (not shown).
  • the switching transistor unit T1 and/or the driving transistor unit T2 may be formed on the same or different growth substrates and then undergo one or more transfers and bonding processes. and the process of removing the growth substrate, transferring the semiconductor stack to the substrate 202, and then forming the switching transistor unit T1 and/or the driving transistor unit T2 through subsequent processes.
  • the process may also be performed before transferring and bonding to form the switching transistor unit T1 and/or the driving transistor unit T2, and then transfer and bonding to form the switching transistor unit T1 and/or the driving transistor unit T2 to the substrate 202.
  • the integrated package 100 also includes a gate terminal P3, a drain terminal P2 and a source terminal P1 for external coupling. Furthermore, as shown in FIGS. 1 and 2 , the integrated package 100 may also include a control signal output terminal P4. The control signal output terminal P4 is used to be coupled to the light emitting unit ED.
  • each light-emitting unit ED may be a light-emitting diode die or a light-emitting diode package component.
  • the semiconductor material of the light-emitting unit ED may be AlInGaN series material AlxInyGa(1-x-y)N or AlInGaP series material AlxInyGa(1-x-y)P, where 0 ⁇ x, y ⁇ 1; (x+y) ⁇ 1.
  • the integrated package 100 can be used in the active addressing system 10 of the display.
  • the active addressing system 10 includes a gate driver 120 , a source driver 110 , a power supply 130 and a plurality of integrated packages. 100.
  • the source terminal of each integrated package 100 is coupled to the source driver 110 through the data line 111 to receive the voltage data Vdata1 ⁇ VdataN.
  • the gate terminal P3 of each integrated package 100 is coupled to the gate driver 120 through the scan line 112 to receive the scan signals SCAN1 ⁇ SCANM, so that the gate driver 120 turns on or off the switching transistor unit T1 of each integrated package.
  • the drain terminal P2 of each integrated package 100 is coupled to the power supply 130 through the power line 113, which provides a current and a drain voltage VDD to each integrated package 100.
  • the integrated package 100 is arranged in an array, for example On the back plate 1100 (refer to Figures 14 and 15), the number thereof is not limited.
  • the switching transistor unit T1 of each integrated package 100 can determine the switching of the driving transistor unit T2, thereby controlling the switching of the integrated control element 1001.
  • the energy storage unit C1 can store voltage data (Vdata) to stabilize the voltage of the second gate G2 of the driving transistor unit T2 during the switching process.
  • the energy storage unit C1 can still keep the second gate G2 of the driving transistor unit T2 in the on-conducting state, thereby continuing to provide current to the corresponding light-emitting unit ED.
  • the light-emitting units ED corresponding to each integrated package 100 can emit different colors of light.
  • the light emitting unit ED may emit red light, green light or blue light.
  • the control signal output terminal P4 of each integrated package 100 is electrically coupled to the light emitting unit ED of different colors to generate red light, green light, blue light or a combination thereof.
  • the plurality of integrated packages 100 can introduce current through the drain terminal P2 respectively. Then the current can flow from the second drain D2 of the driving transistor unit T2 to the second source S2, and then flow to the corresponding light-emitting unit ED through the second source S2, so that the multiple light-emitting units ED generate corresponding red light and green light respectively. , blue light or a combination thereof.
  • TFT backplanes materials that can be used to manufacture TFT backplanes include amorphous silicon (a-Si), low temperature polysilicon (LTPS) and low temperature polycrystalline oxide (LTPO).
  • a-Si amorphous silicon
  • LTPS low temperature polysilicon
  • LTPO low temperature polycrystalline oxide
  • the electron mobility of LTPS TFT and LTPO TFT is higher than that of a-Si Si TFT, but lower than high electron mobility transistor (HEMT).
  • HEMT high electron mobility transistor
  • the electron mobility of the HEMT devices 200, 200', and 200" shown in Figures 4A to 4C is much higher than that of the silicon-based transistors mentioned above.
  • the above-mentioned switching transistor unit T1 and driving transistor unit T2 can be selected as two E-HEMT elements, two D-HEMT elements, or one E-HEMT element and one D-HEMT element.
  • the external IC controller can adjust signals, such as signals of the scan line 112 and the data line 111, according to the types of the switching transistor unit T1 and the driving transistor unit T2.
  • the drive transistor unit T2 for semi-active addressing may be an E-HEMT element.
  • FIG. 14 and FIG. 15 respectively illustrate a schematic diagram of a packaging structure according to an embodiment of the present application.
  • the package structure 300 includes a backplane 1100, the integrated package 100 and a light emitting unit ED.
  • the packaging structure 300 may be a partial specific structure of the active addressing system 10 of FIG. 2 .
  • Backplane 1100 available For circuit boards or glass substrates.
  • the integrated package 100 and the light-emitting unit ED are respectively disposed on opposite sides of the backplane 1100 .
  • the backplane 1100 includes a front side 1100a and a backside 1100b.
  • the integrated package 100 is disposed on the backside 1100b of the backplane 1100.
  • the light-emitting unit ED is disposed on the front side 1100a of the backplane 1100, and there is a throughput between the integrated package 100 and the light-emitting unit ED.
  • At least one conductive via 1101 of the backplane 1100 is electrically connected.
  • control signal output terminal P4 of the integrated package 100 in FIG. 1 can be electrically connected to the conductive via 1101 .
  • the integrated package 100 and the light-emitting unit ED are disposed on opposite sides of the backplane 1100 respectively, the number of light-emitting units ED that can be configured on the front of the backplane 1100 can be increased, and the area that cannot be displayed on the display can be reduced, thereby improving the display effect. .
  • the light-emitting unit ED can be a light-emitting diode package component, including at least one light-emitting diode die, or any number of parallel/series connected light-emitting diode die to form a light-emitting diode array light source.
  • the light-emitting diode packaging component of each light-emitting unit ED includes, for example, any number of parallel/series-connected light-emitting diode dies. However, the number may be the same or different, and each light-emitting unit ED may be controlled by an independent integrated component 100 .
  • FIG. 5 is a schematic diagram of the integrated package 100 shown in FIG. 1 being used in the active addressing system 10 .
  • each integrated package 100 includes a gate terminal P3, a drain terminal P2, a source terminal P1 and a control signal output terminal for external coupling.
  • P4 The light-emitting unit ED includes multiple light-emitting sub-unit strings.
  • the control signal output terminal P4 of each integrated package 100 is electrically connected to, for example, the positive electrode of a light-emitting sub-unit string.
  • Each light-emitting sub-unit string is connected in parallel with, for example, a common N pole. Form connection.
  • the corresponding connected light-emitting sub-unit string of each integrated package 100 includes three light-emitting sub-units, including a red light-emitting sub-unit R1, a green light-emitting sub-unit G1 and a blue light-emitting sub-unit B1, so that the light emitting The unit ED generates corresponding red light, green light, blue light or a combination thereof.
  • the detailed description of the internal structure of the integrated package 100 and the active addressing system 10 has been described in detail in the above-mentioned FIG. 2 and will not be described again here.
  • FIG. 6 shows a schematic diagram of the integrated package 101 applied in the active addressing system 10 according to another embodiment of the present application.
  • the integrated package 101 is in an all-in-one form and includes multiple integrated control components 1001. Similar to the above embodiment, each integrated control component 1001 includes a switch. Transistor unit T1, driving transistor unit T2 and energy storage unit C1.
  • the integrated package 101 can be in the form of a four-in-one, that is to say, four integrated control elements 1001 are provided on the same carrying unit 1000. In other words, there are four switching transistor units T1 and four driving transistor units T2. and four energy storage units C1.
  • This integrated package 101 includes A common gate terminal P3, a common drain terminal P2, four source terminals P1 and four control signal output terminals P4 are used for external coupling.
  • the common gate terminal P3 is connected to the first gate G1 of each switching transistor unit T1 through a wire
  • the common drain terminal P2 is connected to the second drain D2 of each driving transistor unit T2 through a wire
  • each source terminal P1 is used for coupling
  • To a data line 111 that provides a driving voltage, each control signal output terminal P4 is used to be coupled to a light-emitting unit ED.
  • the internal structure of the integrated package 101 and the detailed description of the active addressing system 10 are similar to FIG. 2 and will not be described again here.
  • FIG. 7 is a schematic diagram of another embodiment of the integrated package 101 shown in FIG. 6 being used in the active addressing system 10 .
  • the light-emitting unit ED is similar to Figure 5 and includes multiple light-emitting sub-unit strings.
  • the control signal output terminal P4 of each integrated package 100 is electrically connected to multiple light-emitting sub-unit strings, for example, four light-emitting sub-unit strings.
  • the light-emitting unit ED generates corresponding red light, green light, blue light or a combination thereof.
  • FIG. 2 is a schematic diagram of another embodiment of the integrated package 101 shown in FIG. 6 being used in the active addressing system 10 .
  • the light-emitting unit ED is similar to Figure 5 and includes multiple light-emitting sub-unit strings.
  • the control signal output terminal P4 of each integrated package 100 is electrically connected to multiple light-emitting sub-unit strings, for example, four light-emitting sub-unit strings.
  • the light-emitting unit ED generates
  • FIG. 8 is a schematic diagram of an integrated package 102 according to another embodiment of the present application.
  • the integrated package 102 also includes a light-emitting unit ED disposed on the carrier.
  • the light-emitting unit ED is coupled to the second source S2 of the driving transistor unit T2, and the integrated package 102 further includes a ground terminal GN coupled to the light-emitting element ED.
  • Other internal structures of the integrated package 102 are similar to FIG. 1 and will not be described again here.
  • the switching transistor unit T1 and the driving transistor unit T2 in the integrated control device 1001 are selected from any two of the HEMT devices 200', 200' and 200" in Figures 4A to 4C.
  • the switching transistor unit The manner in which T1, the driving transistor unit T2, the light-emitting unit ED and the energy storage unit C1 are integrated into the integrated package 102, for example, in the form of a bare chip, a package or a common substrate, is also similar to the previous embodiment.
  • FIG. 9 is a schematic diagram of an embodiment of the integrated package 102 shown in FIG. 8 being used in the active addressing system 10 .
  • the integrated package 102 may be used in the active addressing system 10 of the display.
  • the switching transistor unit T1 of each integrated package 102 can control the switching of the integrated control element 1001 .
  • the energy storage unit C1 can store voltage data to stabilize the voltage of the second gate G2 of the driving transistor unit T2 during the switching process and keep the second gate G2 of the driving transistor unit T2 in the on-conducting state, thereby available at the end of the scan signal pulse Afterwards, current is still continuously provided to the light emitting unit ED in the integrated package 102 .
  • the detailed description of the internal structure of the integrated package 102 and the active addressing system 10 has been described in detail in FIG. 8 and will not be described again here.
  • FIG. 10 shows a schematic diagram of an integrated package 103 according to another embodiment of the present application.
  • FIG. 11 shows that the integrated package 103 shown in FIG. 10 is applied to a semi-active addressing system.
  • the integrated package 103 includes an integrated control component 1001'.
  • the integrated control element 1001' includes a driving transistor unit T3.
  • the integrated package 103 may further include a carrying unit 1000, on which the integrated control element 1001' and the light-emitting unit ED are disposed.
  • the driving transistor unit T3 includes a source electrode S3, a drain electrode D3 and a gate electrode G3.
  • the light emitting unit ED is coupled to the source electrode S3.
  • the integrated package 103 also includes a gate terminal P3 for external coupling, a drain terminal P2 and a ground terminal GN coupled to the light-emitting unit ED.
  • each light-emitting unit ED may be a light-emitting diode die, including one or more light-emitting diode units.
  • the integrated package 103 can be used in a semi-active addressing system 20 including a gate driver 120 and a data bus 121 .
  • the drain terminal P2 of each integrated package 103 is coupled to the data bus 121 that provides voltage data Vdata1 ⁇ VdataN through the data line 111 .
  • the gate terminal P3 of each integrated package 103 is coupled to the gate driver 120 that provides the scan signals SCAN1 ⁇ SCANM through the scan line 112 .
  • the plurality of integrated packages 103 are arranged on a backplane (not shown) in an array, for example, and their number is not limited.
  • the gate driver 120 can turn on or off the driving transistor unit T3 of each integrated package through the gate terminal P3 to control the switching of the integrated control element 1001', thereby determining the switching of the light-emitting unit ED.
  • the light-emitting unit ED of each integrated package 103 is coupled to the ground terminal GN, so that current can flow to the light-emitting unit ED through the driving transistor unit T3.
  • the driving transistor unit T3 in the integrated control element 1001' is selected from any one of the HEMT elements 200', 200' and 200" in Figures 4A to 4C.
  • the driving transistor unit T3 and the light-emitting unit ED The method of integration into the integrated package 103, such as a die, a package or a common substrate, is also similar to the previous embodiment.
  • the driving transistor unit T3 and the light-emitting unit ED are respectively provided on the carrying unit 1000 .
  • the driving transistor unit T3 and the light emitting unit ED may be coupled in a one-to-one manner.
  • FIG. 12 is a schematic diagram of an integrated package 104 according to another embodiment of the present application
  • FIG. 13 is a diagram of the integrated package 104 shown in FIG. 12 Schematic diagram of application in semi-active site selection system 20.
  • the integrated package 104 is in an all-in-one form and includes multiple integrated control components 1001'. Similar to the above embodiment, each integrated control component 1001' includes a driving transistor unit T3.
  • the integrated package 104 may be in a three-in-one form, that is, three integrated control elements 1001', that is, three switching transistor units T3, are provided on the same carrying unit 1000.
  • the integrated package 104 includes a common drain terminal P2 for external coupling, a common ground terminal GN and three gate terminals P3.
  • the common drain terminal P2 is connected to the drain D3 of each driving transistor unit T3 through a wire
  • the common ground terminal GN is connected to the cathode N1 of each light-emitting unit ED through a wire
  • each gate terminal P3 is used to be coupled to the corresponding scan line 112. Used to turn on or off one of the three light-emitting units ED.
  • the plurality of light-emitting units ED may include a red light-emitting sub-unit R1, a green light-emitting sub-unit G1, and a blue light-emitting sub-unit B1, so that the light-emitting unit ED generates corresponding red light, green light, blue light, or a combination thereof. .
  • the integrated package of this application uses a new driver design to replace the traditional TFT glass backplane using LTPS switching technology to solve the above-mentioned problems of the traditional TFT backplane.
  • the integrated package of this application can be used in active (AM) matrix addressing or semi-active (semi-AM) addressing driving systems, becoming a new direction in display design.

Abstract

一种集成式封装，包括一集成式控制元件。集成式控制元件包括一开关晶体管单元、一驱动晶体管单元以及一储能单元。开关晶体管单元包括一第一源极、一第一漏极以及一第一栅极。驱动晶体管单元包括一第二源极、一第二漏极以及一第二栅极，其中第二栅极耦接至第一漏极。储能单元耦接在第二漏极和第二栅极之间。集成式封装还包括用于对外耦接的一栅极端、一漏极端以及一源极端。

Description

集成式封装 技术领域
本申请案涉及一种半导体元件，且特别涉及一种集成式封装。
背景技术
近年来，半导体元件的尺寸逐渐小型化，结构也逐渐复杂化。
此外，显示技术的应用在我们的日常生活中已经无处不在，其广泛的应用涵盖智能手机、平板计算机、桌上型显示器和电视。发光二极管(light emitting diode，LED)，例如micro-LED或mini-LED已成为下一代显示器的发光元件。
传统的LED显示器包括多个LED子像素，所述多个LED子像素包括至少一个由玻璃基板上的薄膜晶体管(thin-film transistor，TFT)驱动或控制的LED，所有LED子像素布置在一起以形成像素阵列。显示器中的像素阵列的驱动系统包括无源矩阵寻址(passive matrix(PM)addressing)、有源矩阵寻址(active matrix(AM)addressing)及半有源矩阵寻址(semi-AM addressing)等驱动系统。相较于有源寻址系统，无源寻址系统的响应时间相对较慢。而半有源寻址系统的响应时间介于无源寻址系统和有源寻址系统之间。此外，驱动系统中采用非晶硅(Amorphous Silicon)、低温多晶硅(Low temperature polysilicon，LTPS)技术来制作薄膜晶体管在玻璃背板上，因其电子迁移率较低造成系统的效率更加低下。因此在micro-LED/mini-LED显示器的应用中，需考虑LED与显示器中驱动系统之间的整合配置以期能达到高效率及集成化。
发明内容
本申请案涉及一种集成式封装，用以将晶体管及储能单元制作成一集成式控制元件并封装在一承载基板上，以供驱动系统使用。
本申请案涉及一种集成式封装，用以将晶体管及发光元件封装在一承载基板上，以供驱动系统使用。
根据本申请案的一方面，提出一种集成式封装，包括一集成式控制元件。 集成式控制元件包括一开关晶体管单元、一驱动晶体管单元以及一储能单元。开关晶体管单元包括一第一源极、一第一漏极以及一第一栅极。驱动晶体管单元包括一第二源极、一第二漏极以及一第二栅极，其中第二栅极耦接至第一漏极。储能单元耦接在第二漏极和第二栅极之间。集成式封装还包括用于对外耦接的一栅极端、一漏极端以及一源极端。
根据本申请案的另一方面，提出一种集成式封装，包括一集成式控制元件以及一发光单元。集成式控制元件包括一驱动晶体管单元。驱动晶体管单元包括一源极、一漏极以及一栅极。发光单元耦接在源极。集成式封装还包括用于对外耦接的一栅极端、一漏极端以及耦接在发光单元的一接地端。
为了对本申请案的上述及其他方面有更佳的了解，下文特举实施例，并配合附图详细说明如下：
附图说明
图1绘示依照本申请案一实施例的集成式封装的示意图。
图2绘示依照图1所示的集成式封装应用于有源寻址系统中的示意图。
图3绘示依照本申请案一实施例集成式控制元件的示意图。
图4A至4C绘示依照本申请案一实施例的HEMT的剖面示意图。
图5绘示依照图1所示的集成式封装应用于有源寻址系统中的示意图。
图6绘示依照本申请案另一实施例的集成式封装应用于有源寻址系统中的示意图。
图7绘示图6所示的集成式封装应用于有源寻址系统中的示意图。
图8绘示依照本申请案另一实施例的集成式封装的示意图。
图9绘示图8所示的集成式封装应用于有源寻址系统中的示意图。
图10绘示依照本申请案另一实施例的集成式封装的示意图。
图11绘示图10所示的集成式封装应用于半有源寻址系统中的示意图。
图12绘示依照本申请案另一实施例的集成式封装的示意图。
图13绘示图12所示的集成式封装应用于半有源选址系统中的示意图。
图14及图15分别绘示依照本申请案一实施例的封装结构的示意图。
【符号说明】
10:有源寻址系统
20:半有源寻址系统
100～104:集成式封装
1000:承载单元
1001、1001’:集成式控制元件
1100:背板
1100a:正面
1100b:背面
1101:导电通孔
111:数据线
112:扫描线
113:电源线
200、200’、200”:HEMT元件
202:基底
204:第一缓冲层
206:第二缓冲层
208:沟道层
209:二维电子气
210:阻障层
211:缓冲结构
212:掺杂层
213:凹槽
300:封装结构
T1:开关晶体管单元
T2，T3:驱动晶体管单元
C1:储能单元
S1:第一源极
S2:第二源极
D1:第一漏极
D2:第二漏极
G1:第一栅极
G2:第二栅极
P1:源极端
P2:漏极端
P3:栅极端
Vdata1～VdataN:驱动电压
SCAN1～SCANM:扫描信号
VDD:漏极电压
P4:控制信号输出端
R1:红光发光子单元
G1:绿光发光子单元
B1:蓝光发光子单元
S3，S:源极
D3，D:漏极
G3，G:栅极
GN:接地端
N1:阴极
具体实施方式
下面将结合本申请的实施例中的附图，对本申请的实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。以下是以相同/类似的符号表示相同/类似的元件做说明。
请参照图1至3，其中图1绘示依照本申请案一实施例的集成式封装100的示意图，图2绘示图1所示的集成式封装100应用于有源寻址系统10中的示意图，图3绘示依照本申请案一实施例的集成式控制元件1001的示意图。集成式封装100包括一集成式控制元件1001。集成式控制元件1001包括一开关晶体管单元T1、一驱动晶体管单元T2以及一储能单元C1。开关晶体管单元T1包括一第一源极S1、一第一漏极D1以及一第一栅极G1。驱动晶体管单元T2包括一第二源极S2、一第二漏极D2以及一第二栅极G2，其中第二栅极G2耦接至第一漏极D1。储能单元C1耦接在第二漏极D2和第二栅极G2之间。集成式封装100可还包括一承载单元1000，集成式控制元件1001 形成于承载单元1000上。
开关晶体管单元T1、驱动晶体管单元T2可包含金属-氧化物-半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)或高电子迁移速度晶体管(High Electron Mobility Transistor，HEMT)。其中MOSFET的半导体材料包含硅(Si)、或锗(Ge)。HEMT的半导体材料包含III-V族材料或SiC材料，其中III-V族材料包含氮化镓基(GaN based)或砷化镓基(GaAs based)的三五族化合物半导体材料。HEMT元件本身具有高迁移率和高频的特点，因此可用于开关元件领域(例如本公开的开关晶体管单元T1及驱动晶体管单元T2)。在一个实施例中，GaN基的HEMT元件的效率高于传统Si基的MOSFET，并且尺寸较小，从而有利于与其他电子元件进行整合以成为一集成式晶粒，或再藉由晶粒级封装而制成一集成式封装。因此，集成式晶粒或集成式封装可以取代传统的有源、半有源或无源寻址系统中在玻璃背板上布线的TFT，以提供发光单元ED(例如LED元件)较高的电源驱动器效率，使用者也可藉由集成式晶粒或集成式封装简化布线、增加效能。
请参照图4A至4C，图4A至4C绘示依照本申请案一实施例的HEMT元件200、200’、200”的剖面示意图。HEMT元件200、200’、200”是一种场效应晶体管，其藉由两种具有不同能隙的材料形成异质接口，在其中形成一二维电子气(two-dimensional electron gas，2DEG)做为载子沟道，使得晶体管适于高压、高频或低噪声的应用。参照图4A，在一实施例中，开关晶体管单元T1或驱动晶体管单元T2以选用氮化镓基的耗尽型HEMT元件(Depletion-Mode HEMT，D-HEMT)200为例，其为一常开型HEMT元件。在一实施例中，HEMT元件200包括半导体叠层，包含缓冲结构211、设缓冲结构211上的沟道层208，以及阻障层210。在沟道层208中靠近和阻障层210的界面处具有二维电子气209。HEMT元件200还包含设于阻障层210上的栅极G、漏极D和源极S，相当于开关晶体管单元T1/驱动晶体管单元T2的第一源极S1/第二源极S2、第一漏极D1/第二漏极D2、以及第一栅极G1/第二栅极G2。在一实施例中，HEMT元件200还可包含基底202，其可以是用于半导体叠层磊晶成长用的成长基底，其材料可包含硅或蓝宝石(sapphire)。缓冲结构211可包含AlGaN系列材料，例如在基底202上依序堆叠的第一缓冲层204及第二缓冲层206，第一缓冲层204的材料可为AlN，第二缓冲层206的材料可为AlGaN 或GaN，但不仅限于此。沟道层208及阻障层210为无掺杂层或非故意掺杂层。参照图4B，在一实施例中，开关晶体管单元T1或驱动晶体管单元T2以选用氮化镓基的增强型HEMT元件(Enhancement-Mode HEMT，E-HEMT)200’为例，其为一常关型HEMT元件。其与耗尽型HEMT元件200的差异在于增强型HEMT元件200’在栅极G与阻障层210之间具有一掺杂层212，例如为含有P型掺杂的GaN层。在图4C中，HEMT元件200”也是一种常关型HEMT元件，其与耗尽型HEMT元件200的差异在于常关型HEMT元件200”在栅极G下方的阻障层210中设有凹槽213。藉由掺杂层212或凹槽213以阻断形成在沟道层208和阻障层210之间的二维电子气209，从而形成常关形式的E-HEMT元件。
如图1及图3所示，在一实施例中，集成式控制元件1001的储能单元C1可为电容。开关晶体管单元T1和驱动晶体管单元T2为HEMT元件。储能单元C1的一端连接在开关晶体管单元T1的第一漏极D1与第二栅极G2之间的节点，储能单元C1的另一端连接在第二漏极D2。但不仅限于此，开关晶体管单元T1和驱动晶体管单元T2为其他形式的晶体管元件时，储能单元C1的另一端也可连接在第二源极S2。
在一实施例中，集成式控制元件1001中的开关晶体管单元T1及驱动晶体管单元T2选自HEMT元件200’、200’及200”中的任两者。开关晶体管单元T1、驱动晶体管单元T2及储能单元C1各自以裸晶(Bare chip)或以盖上保护胶的封装体形式设置在承载单元1000上。集成封装100可包含一封装层(图未示)覆盖于集成式控制元件1001及承载单元1000上，以构成集成式封装100。在另一实施例中，储能单元C1也可与开关晶体管单元T1及驱动晶体管单元T2的其中之一为同一晶粒或封装体。
在一实施例中，集成式控制元件1001的开关晶体管单元T1及驱动晶体管单元T2可以共基底(monolithic substrate)的形式形成于共同的基底202上，将开关晶体管单元T1、驱动晶体管单元T2和/或储能单元C1整合为一个晶粒。形成共基底集成式控制元件1001的方法包含：在基底202上沉积半导体叠层；选择性蚀刻半导体叠层至暴露基底202的一部分表面，以将半导体叠层区隔为两个主动区域，分别在两个主动区域上形成栅极G、漏极D和源极S形成开关晶体管单元T1和驱动晶体管单元T2；以及在基底202上、开关晶 体管单元T1、或驱动晶体管单元T2上形成储能单元C1。在本实施例中，可将共基底的开关晶体管单元T1、驱动晶体管单元T2、和储能单元C1设置在承载单元1000上，再覆盖封装层构成集成式封装100。在另一实施例中，共基底的开关晶体管单元T1、驱动晶体管单元T2、和储能单元C1的基底202可取代承载单元1000，亦即不需要另外的承载单元1000，封装层覆盖共基底的开关晶体管单元T1、驱动晶体管单元T2、储能单元C1和基底202构成集成式控制元件1001。然而，也可也可藉由晶圆转移方式将晶体管接合于基底202上，形成共基底的开关晶体管单元T1和/或驱动晶体管单元T2。例如基底202的表面可包含一接合层(未绘示)，开关晶体管单元T1和/或驱动晶体管单元T2可在相同或不同成长基板上形成半导体叠层后，再通过一或多次转移、接合及移除成长基板的工艺，将半导体叠层转移到基底202上，再经由后续工艺加工形成开关晶体管单元T1和/或驱动晶体管单元T2。在一实施例中，工艺加工也可在转移接合前实施形成开关晶体管单元T1和/或驱动晶体管单元T2后，再转移接合形成开关晶体管单元T1和/或驱动晶体管单元T2至基底202。
集成式封装100还包括用于对外耦接的一栅极端P3、一漏极端P2以及一源极端P1。再者，如图1及2所示，集成式封装100还可包括一控制信号输出端P4。控制信号输出端P4用以耦接至发光单元ED。在图2中，每一发光单元ED可为发光二极管晶粒或发光二极管封装元件。发光单元ED的半导体材料可为AlInGaN系列材料AlxInyGa(1-x-y)N或AlInGaP系列材料AlxInyGa(1-x-y)P，其中0≦x，y≦1；(x+y)≦1。
如图2所示，集成式封装100可用于显示器的有源寻址系统10中，有源寻址系统10包括一栅极驱动器120、一源极驱动器110、一电源130和多个集成式封装100。各个集成式封装100的源极端藉由数据线111耦接至源极驱动器110，以接收电压数据Vdata1～VdataN。各个集成式封装100的栅极端P3藉由扫描线112耦接至栅极驱动器120，以接收扫描信号SCAN1～SCANM，以供栅极驱动器120开启或关闭各集成式封装的开关晶体管单元T1。各个集成式封装100的漏极端P2藉由电源线113耦接至电源130其提供一电流与一漏极电压VDD给各个集成式封装100。集成式封装100例如以阵列排列在一 背板1100(参照图14、15)上，其数量不限。各集成式封装100的开关晶体管单元T1可决定驱动晶体管单元T2的开关，进而控制集成式控制元件1001的开关。另外，当驱动晶体管单元T2导通时，储能单元C1可存储电压数据(Vdata)，以在开关切换过程中稳定驱动晶体管单元T2的第二栅极G2的电压，另外，在扫描信号(SCAN)脉冲结束后，储能单元C1仍可保持驱动晶体管单元T2的第二栅极G2在开启导通状态，从而持续提供电流给所对应的发光单元ED。
在一实施例中，各集成式封装100所对应的发光单元ED可发出不同的色光。例如在图2中，发光单元ED可发出红光、绿光或蓝光。各个集成式封装100的控制信号输出端P4电性耦接至不同色光的发光单元ED，以产生红光、绿光、蓝光或其组合的色光。
具体而言，多个集成式封装100可分别藉由漏极端P2导入电流。接着电流可由驱动晶体管单元T2的第二漏极D2流向第二源极S2，再经由第二源极S2流向对应的发光单元ED，以使多个发光单元ED分别产生对应的红光、绿光、蓝光或其组合的色光。
一般而言，可用于制造TFT背板的材料包括非晶硅(amorphous silicon，a-Si)、低温多晶硅(Low temperature polysilicon，LTPS)和低温多晶氧化物(low temperature polycrystalline oxide，LTPO)，三者之间的主要区别在于a-Si材料的TFT背板允许在低温工艺中大面积制造，但其电子迁移率相对其他两者较低，LTPS TFT及LTPO TFT的电子迁移率虽高于a-Si TFT，但低于高电子迁移率晶体管(HEMT)。图4A至图4C所示的HEMT元件200、200’、200”的电子迁移率远高于上述的硅基晶体管。
上述的开关晶体管单元T1及驱动晶体管单元T2可以选择为两个E-HEMT元件、两个D-HEMT元件、或者一个E-HEMT元件及一个D-HEMT元件。在本实施例中，外部IC控制器可以根据开关晶体管单元T1及驱动晶体管单元T2的类型来调整信号，例如扫描线112和数据线111的信号。在一个实施例中，用于半有源寻址的驱动晶体管单元T2可以是E-HEMT元件。请参照图14及图15，其分别绘示依照本申请案一实施例的封装结构的示意图。封装结构300包括一背板1100、上述集成式封装100以及一发光单元ED。封装结构300可为图2的有源寻址系统10的局部的具体结构。背板1100可 为电路板或玻璃基板。在一实施例中，集成式封装100和发光单元ED分别设置在背板1100的相背两侧。背板1100包括一正面1100a以及一背面1100b，集成式封装100设置在背板1100的背面1100b，发光单元ED设置在背板1100的正面1100a，且集成式封装100与发光单元ED之间以穿过背板1100的至少一个导电通孔1101电性连接，例如可将图1中的集成式封装100的控制信号输出端P4电性连接于导电通孔1101。藉由将集成式封装100和发光单元ED分别设置在背板1100的相背两侧，可增加背板1100在正面可以配置发光单元ED的数量，及减少显示器无法显示的面积，从而提升显示效果。
如图14所示，发光单元ED可为一发光二极管封装元件，包含至少一个发光二极管晶粒，或任意数量并联/串联的发光二极管晶粒，以组成一发光二极管阵列光源。如图15所示，每个发光单元ED的发光二极管封装元件例如包含任意数量并联/串联的发光二极管晶粒，然而数量可以相同或不同，且每个发光单元ED可由独立的集成式元件100控制。
图5绘示依照图1所示的集成式封装100应用于有源寻址系统10中的示意图。请参照图5并配合参照图1，相同于前述实施例，在本实施例中，各个集成式封装100包括用于对外耦接的栅极端P3、漏极端P2、源极端P1以及控制信号输出端P4。发光单元ED包括多个发光子单元串，每一个集成式封装100的控制信号输出端P4对应电连接一个发光子单元串的例如正极，每一个发光子单元串之间以例如共N极并联的形式连接。在一实施例中，每个集成式封装100对应连接的发光子单元串包含三个发光子单元，包含红光发光子单元R1、绿光发光子单元G1及蓝光发光子单元B1，以使发光单元ED产生对应的红光、绿光、蓝光或其组合的色光。有关集成式封装100的内部结构与有源寻址系统10的细部说明，已详述于上述图2中，在此不再赘述。
图6绘示依照本申请案另一实施例的集成式封装101应用于有源寻址系统10中的示意图。请参照图6并配合参照图1，在本实施例中，集成式封装101为多合一的形式，包含多个集成式控制元件1001，类似上述实施例，每一个集成式控制元件1001包含开关晶体管单元T1、驱动晶体管单元T2以及储能单元C1。例如集成式封装101可为四合一的形式，也就是说，在同一承载单元1000上设有四个集成式控制元件1001，换句话说有四个开关晶体管单元T1、四个驱动晶体管单元T2以及四个储能单元C1。此集成式封装101包括 用于对外耦接的一个共用的栅极端P3、一个共用的漏极端P2、四个源极端P1以及四个控制信号输出端P4。共用的栅极端P3通过导线连接至各个开关晶体管单元T1的第一栅极G1，共用的漏极端P2通过导线连接至各个驱动晶体管单元T2的第二漏极D2，各个源极端P1用以耦接至提供一驱动电压的一数据线111，各个控制信号输出端P4用以耦接至一发光单元ED。集成式封装101的内部结构与有源寻址系统10的细部说明类似于图2，在此不再赘述。
请参照图7，其绘示图6所示的集成式封装101应用于有源寻址系统10中另一实施例的示意图。在本实施例中，多合一形式的集成式封装101的细部结构已详述于图6中，在此不再赘述。本实施例与图6的不同处在于发光单元ED是类似图5，包括多个发光子单元串。本实施例与图5的差异在于每一个集成式封装100的控制信号输出端P4对应电连接多个发光子单元串，例如四个发光子单元串。藉此使发光单元ED产生对应的红光、绿光、蓝光或其组合的色光。有关各个集成式封装101的内部结构与有源寻址系统10的细部说明相似于图2，在此不再赘述。
请参照图8，其绘示依照本申请案另一实施例的集成式封装102的示意图，与图1的集成式封装100不同之处在于，集成式封装102还包括一发光单元ED设置在承载单元1000上。发光单元ED耦接于驱动晶体管单元T2的第二源极S2，且集成式封装102还包括一接地端GN耦接于发光元件ED。有关集成式封装102的其他内部结构相似于图1，在此不再赘述。
相似于前述实施例，集成式控制元件1001中的开关晶体管单元T1及驱动晶体管单元T2选自图4A至图4C的HEMT元件200’、200’及200”中的任两者。另外开关晶体管单元T1、驱动晶体管单元T2、发光单元ED及储能单元C1整合为集成式封装102的方式，例如分别为裸晶、封装体或共基板的形式也相似于前述实施例。
图9绘示图8所示的集成式封装102应用于有源寻址系统10中一实施例的示意图。如图9所示并配合参照图8，集成式封装102可用于显示器的有源寻址系统10中。相似于图2，各集成式封装102的开关晶体管单元T1可控制集成式控制元件1001的开关。另外，储能单元C1可存储电压数据，以在开关切换过程中稳定驱动晶体管单元T2的第二栅极G2的电压，并保持驱动晶体管单元T2的第二栅极G2在开启导通状态，从而可在扫描信号脉冲结束 后，仍持续提供电流给集成式封装102中的发光单元ED。有关集成式封装102的内部结构与有源寻址系统10的细部说明，已详述于图8中，在此不再赘述。
请参照图10及图11，其中图10绘示依照本申请案另一实施例的集成式封装103的示意图，图11绘示图10所示的集成式封装103应用于半有源寻址系统20中一实施例的示意图。集成式封装103包括一集成式控制元件1001’。集成式控制元件1001’包括一驱动晶体管单元T3。集成式封装103可还包括一承载单元1000，集成式控制元件1001’和发光单元ED设置在承载单元1000上。驱动晶体管单元T3包括一源极S3、一漏极D3以及一栅极G3，发光单元ED耦接于源极S3。集成式封装103还包括用于对外耦接的一栅极端P3、一漏极端P2及耦接于发光单元ED的一接地端GN。在图11中，每一发光单元ED可为发光二极管晶粒，包括一个或多个发光二极管单元。
如图11所示，集成式封装103可用于半有源寻址系统20中，半有源寻址系统20包括栅极驱动器120和数据总线121。各个集成式封装103的漏极端P2通过数据线111耦接至提供电压数据Vdata1～VdataN的数据总线121。各个集成式封装103的栅极端P3通过扫描线112耦接至提供扫描信号SCAN1～SCANM的栅极驱动器120。多个集成式封装103例如以阵列排列在一背板(未绘示)上，其数量不限。栅极驱动器120可通过栅极端P3开启或关闭各集成式封装的驱动晶体管单元T3，以控制集成式控制元件1001’的开关，进而决定发光单元ED的开关。另外，各集成式封装103的发光单元ED耦接于接地端GN，以使电流可通过驱动晶体管单元T3流至发光单元ED。
相似于前述实施例，集成式控制元件1001’中的驱动晶体管单元T3选自图4A至图4C的HEMT元件200’、200’及200”中的任一个。另外驱动晶体管单元T3和发光单元ED整合为集成式封装103的方式，例如分别为裸晶、封装体或共基板的形式也相似于前述实施例。
如图11所示，在具有上述集成式封装103的半有源矩阵(semi-AM)寻址系统20中，驱动晶体管单元T3及发光单元ED分别设置在承载单元1000上。在图11中，驱动晶体管单元T3与发光单元ED可以一对一的方式耦接。
请参照图12及图13并配合参照图11，其中图12绘示依照本申请案另一实施例的集成式封装104的示意图，图13绘示图12所示的集成式封装104 应用于半有源选址系统20中的示意图。在本实施例中，集成式封装104为多合一的形式，包含多个集成式控制元件1001’，类似上述实施例，每一个集成式控制元件1001’包含驱动晶体管单元T3。例如集成式封装104可为三合一的形式，也就是说，在同一承载单元1000上设有三个集成式控制元件1001’，即三个开关晶体管单元T3。三个开关晶体管单元T3和三个发光单元ED一对一耦接。集成式封装104包括用于对外耦接的一共用的漏极端P2、一共用的接地端GN以及三个栅极端P3。共用漏极端P2通过导线连接至各个驱动晶体管单元T3的漏极D3，共用接地端GN通过导线连接至各个发光单元ED的阴极N1，各个栅极端P3用以耦接至相对应的扫描线112，用以开启或关闭三个发光单元ED其中之一。有关集成式封装104的内部结构与半有源寻址系统20的细部说明，已详述于上述图11中，在此不再赘述。
此外，多个发光单元ED可包括红光发光子单元R1、绿光发光子单元G1及蓝光发光子单元B1，以使发光单元ED产生对应的红光、绿光、蓝光，或其组合的色光。
由于目前的玻璃金属化技术仍面临技术瓶颈，导致良率低、成本高，加上采用LTPS切换技术的TFT玻璃背板价格昂贵，因此需要调整某些部分的工艺和参数，以精确控制和驱动LED电流。本申请案的集成式封装采用新的驱动设计取代传统的采用LTPS切换技术的TFT玻璃背板，以解决上述传统TFT背板的问题。本申请案的集成式封装可应用在有源(AM)矩阵选址或半有源(semi-AM)选址的驱动系统中，成为显示器设计的新方向。
综上所述，虽然本申请案已以实施例公开如上，然其并非用以限定本申请案。本申请案所属领域技术人员，在不脱离本申请案的精神和范围内，当可作各种的更动与润饰。因此，本申请案的保护范围当视所附权利要求书界定范围为准。

Claims (11)

  1. 一种集成式封装，包括：
    集成式控制元件，包括：
    开关晶体管单元，包括第一源极、第一漏极以及第一栅极；
    驱动晶体管单元，包括第二源极、第二漏极以及第二栅极，其中该第二栅极耦接至该第一漏极；以及
    储能单元，耦接在该第二漏极和该第二栅极之间；
    其中该集成式封装还包括用于对外耦接的栅极端、漏极端以及源极端。
  2. 如权利要求1所述的集成式封装，还包括承载单元，该开关晶体管单元、该驱动晶体管单元及该储能单元位于该承载单元上。
  3. 如权利要求2所述的集成式封装，还包括发光单元设置在该承载单元上且耦接于该驱动晶体管单元的该第二源极，该集成式封装还包括接地端耦接于该发光元件。
  4. 如权利要求1所述的集成式封装，还包括控制信号输出端，其中该控制信号输出端用以耦接至发光单元。
  5. 如权利要求4所述的集成式封装，其中该发光单元与该集成式封装分别设置在背板的相背两侧，以形成封装结构。
  6. 如权利要求4所述的集成式封装，其中该发光单元包括多个发光子单元。
  7. 如权利要求1所述的集成式封装，其中该源极端用以耦接至提供驱动电压的数据线，该栅极端用以耦接扫描线，该漏极端用以耦接至提供漏极电压的电源线，其中该开关晶体管单元、该驱动晶体管单元及该储能单元分别有多个，所述开关晶体管单元并联耦接至该扫描线，所述驱动晶体管单元耦接至该电源线，各该驱动晶体管单元还包括控制信号输出端用以耦接至发光单元。
  8. 一种集成式封装，包括：
    集成式控制元件，形成于该承载单元上，包括：
    驱动晶体管单元，包括源极、漏极以及栅极；以及
    发光单元，耦接于该源极；
    其中该集成式封装还包括用于对外耦接的栅极端、漏极端及耦接于该发 光单元的接地端。
  9. 如权利要求8所述的集成式封装，还包括承载单元，该驱动晶体管单元与该发光单元设置在该承载单元上。
  10. 如权利要求8所述的集成式封装，其中该驱动晶体管单元与该发光单元以一对一的方式耦接。
  11. 如权利要求8所述的集成式封装，其中该漏极端用以耦接至提供驱动电压的数据线，该栅极端用以耦接扫描线，该驱动晶体管单元及该发光单元分别有多个，所述驱动晶体管单元并联耦接到该数据线，所述驱动晶体管单元的该源极分别耦接至所述发光单元。
PCT/CN2023/113107 2022-08-15 2023-08-15 集成式封装 WO2024037537A1 (zh)

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CN113471250A (zh) * 2020-03-31 2021-10-01 华为技术有限公司 一种有机发光显示面板和显示装置
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